;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
+;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;; Z -- likewise, with special suffixes for x87 instructions.
;; * -- print a star (in certain assembler syntax)
;; A -- print an absolute memory reference.
+;; E -- print address with DImode register names if TARGET_64BIT.
;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
;; s -- print a shift double count, followed by the assemblers argument
;; delimiter.
;; ; -- print a semicolon (after prefixes due to bug in older gas).
;; @ -- print a segment register of thread base pointer load
-;; UNSPEC usage:
-
(define_c_enum "unspec" [
;; Relocation specifiers
UNSPEC_GOT
;; Prologue support
UNSPEC_STACK_ALLOC
UNSPEC_SET_GOT
- UNSPEC_REG_SAVE
- UNSPEC_DEF_CFA
UNSPEC_SET_RIP
UNSPEC_SET_GOT_OFFSET
UNSPEC_MEMORY_BLOCKAGE
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_TRUNC_NOOP
UNSPEC_DIV_ALREADY_SPLIT
+ UNSPEC_MS_TO_SYSV_CALL
UNSPEC_CALL_NEEDS_VZEROUPPER
UNSPEC_PAUSE
+ UNSPEC_LEA_ADDR
+ UNSPEC_STOS
;; For SSE/MMX support:
UNSPEC_FIX_NOTRUNC
UNSPEC_MASKMOV
UNSPEC_MOVMSK
- UNSPEC_MOVNT
- UNSPEC_MOVU
UNSPEC_RCP
UNSPEC_RSQRT
- UNSPEC_SFENCE
- UNSPEC_PFRCP
- UNSPEC_PFRCPIT1
- UNSPEC_PFRCPIT2
- UNSPEC_PFRSQRT
- UNSPEC_PFRSQIT1
- UNSPEC_MFENCE
- UNSPEC_LFENCE
UNSPEC_PSADBW
- UNSPEC_LDDQU
- UNSPEC_MS_TO_SYSV_CALL
;; Generic math support
UNSPEC_COPYSIGN
UNSPEC_SP_TLS_SET
UNSPEC_SP_TLS_TEST
- ;; SSSE3
- UNSPEC_PSHUFB
- UNSPEC_PSIGN
- UNSPEC_PALIGNR
-
- ;; For SSE4A support
- UNSPEC_EXTRQI
- UNSPEC_EXTRQ
- UNSPEC_INSERTQI
- UNSPEC_INSERTQ
-
- ;; For SSE4.1 support
- UNSPEC_BLENDV
- UNSPEC_INSERTPS
- UNSPEC_DP
- UNSPEC_MOVNTDQA
- UNSPEC_MPSADBW
- UNSPEC_PHMINPOSUW
- UNSPEC_PTEST
+ ;; For ROUND support
UNSPEC_ROUND
- ;; For SSE4.2 support
+ ;; For CRC32 support
UNSPEC_CRC32
- UNSPEC_PCMPESTR
- UNSPEC_PCMPISTR
-
- ;; For FMA4 support
- UNSPEC_FMADDSUB
- UNSPEC_XOP_UNSIGNED_CMP
- UNSPEC_XOP_TRUEFALSE
- UNSPEC_XOP_PERMUTE
- UNSPEC_FRCZ
-
- ;; For AES support
- UNSPEC_AESENC
- UNSPEC_AESENCLAST
- UNSPEC_AESDEC
- UNSPEC_AESDECLAST
- UNSPEC_AESIMC
- UNSPEC_AESKEYGENASSIST
-
- ;; For PCLMUL support
- UNSPEC_PCLMUL
-
- ;; For AVX support
- UNSPEC_PCMP
- UNSPEC_VPERMIL
- UNSPEC_VPERMIL2
- UNSPEC_VPERMIL2F128
- UNSPEC_CAST
- UNSPEC_VTESTP
- UNSPEC_VCVTPH2PS
- UNSPEC_VCVTPS2PH
-
- ;; For AVX2 support
- UNSPEC_VPERMSI
- UNSPEC_VPERMDF
- UNSPEC_VPERMSF
- UNSPEC_VPERMTI
- UNSPEC_GATHER
;; For BMI support
UNSPEC_BEXTR
- ;; For RDRAND support
- UNSPEC_RDRAND
-
;; For BMI2 support
UNSPEC_PDEP
UNSPEC_PEXT
UNSPECV_BLOCKAGE
UNSPECV_STACK_PROBE
UNSPECV_PROBE_STACK_RANGE
- UNSPECV_EMMS
- UNSPECV_LDMXCSR
- UNSPECV_STMXCSR
- UNSPECV_FEMMS
- UNSPECV_CLFLUSH
UNSPECV_ALIGN
- UNSPECV_MONITOR
- UNSPECV_MWAIT
- UNSPECV_CMPXCHG
- UNSPECV_XCHG
- UNSPECV_LOCK
UNSPECV_PROLOGUE_USE
+ UNSPECV_SPLIT_STACK_RETURN
UNSPECV_CLD
UNSPECV_NOPS
- UNSPECV_VZEROALL
- UNSPECV_VZEROUPPER
UNSPECV_RDTSC
UNSPECV_RDTSCP
UNSPECV_RDPMC
UNSPECV_RDGSBASE
UNSPECV_WRFSBASE
UNSPECV_WRGSBASE
- UNSPECV_SPLIT_STACK_RETURN
-])
+
+ ;; For RDRAND support
+ UNSPECV_RDRAND
+
+ ;; Non-local goto.
+ UNSPECV_NLGR
+ ])
;; Constants to represent rounding modes in the ROUND instruction
(define_constants
(define_attr "movu" "0,1" (const_string "0"))
;; Used to control the "enabled" attribute on a per-instruction basis.
-(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,bmi2"
+(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,
+ bmi2,fma4,fma"
(const_string "base"))
(define_attr "enabled" ""
(eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
+ (eq_attr "isa" "fma4") (symbol_ref "TARGET_FMA4")
+ (eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
]
(const_int 1)))
;; Base name for insn mnemonic.
(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
+;; Mapping of logic-shift operators
+(define_code_iterator any_lshift [ashift lshiftrt])
+
;; Mapping of shift-right operators
(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
;; Base name for define_insn
-(define_code_attr shiftrt_insn [(lshiftrt "lshr") (ashiftrt "ashr")])
+(define_code_attr shift_insn
+ [(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")])
;; Base name for insn mnemonic.
-(define_code_attr shiftrt [(lshiftrt "shr") (ashiftrt "sar")])
+(define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")])
+(define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")])
;; Mapping of rotate operators
(define_code_iterator any_rotate [rotate rotatert])
split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
operands[1] = gen_lowpart (DImode, operands[2]);
- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (4)));
})
split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
operands[1] = gen_lowpart (DImode, operands[2]);
- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (4)));
})
(set_attr "mode" "OI")])
(define_insn "*movti_internal_rex64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=!r,o,x,x,xm")
- (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=!r,o,x,x,m")
+ (match_operand:TI 1 "general_operand" "riFo,re,C,xm,x"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
[(set_attr "type" "*,*,sselog1,ssemov,ssemov")
(set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex")
(set (attr "mode")
- (cond [(eq_attr "alternative" "2,3")
- (if_then_else
- (match_test "optimize_function_for_size_p (cfun)")
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "4")
- (if_then_else
- (ior (match_test "TARGET_SSE_TYPELESS_STORES")
- (match_test "optimize_function_for_size_p (cfun)"))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "DI")))])
+ (cond [(eq_attr "alternative" "0,1")
+ (const_string "DI")
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ (and (eq_attr "alternative" "4")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "V4SF")
+ ]
+ (const_string "TI")))])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(define_insn "*movdi_internal_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=r,r ,r,m ,!o,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
+ "=r,r ,r,m ,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
(match_operand:DI 1 "general_operand"
- "Z ,rem,i,re,n ,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
+ "Z ,rem,i,re,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (get_attr_type (insn))
case TYPE_MMX:
return "pxor\t%0, %0";
- case TYPE_MULTI:
- return "#";
-
case TYPE_LEA:
- return "lea{q}\t{%a1, %0|%0, %a1}";
+ return "lea{q}\t{%E1, %0|%0, %E1}";
default:
gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
return "mov{l}\t{%k1, %k0|%k0, %k1}";
else if (which_alternative == 2)
return "movabs{q}\t{%1, %0|%0, %1}";
+ else if (ix86_use_lea_for_mov (insn, operands))
+ return "lea{q}\t{%E1, %0|%0, %E1}";
else
return "mov{q}\t{%1, %0|%0, %1}";
}
}
[(set (attr "type")
(cond [(eq_attr "alternative" "4")
- (const_string "multi")
- (eq_attr "alternative" "5")
(const_string "mmx")
- (eq_attr "alternative" "6,7,8,9")
+ (eq_attr "alternative" "5,6,7,8")
(const_string "mmxmov")
- (eq_attr "alternative" "10")
+ (eq_attr "alternative" "9")
(const_string "sselog1")
- (eq_attr "alternative" "11,12,13,14,15")
+ (eq_attr "alternative" "10,11,12,13,14")
(const_string "ssemov")
- (eq_attr "alternative" "16,17")
+ (eq_attr "alternative" "15,16")
(const_string "ssecvt")
(match_operand 1 "pic_32bit_operand" "")
(const_string "lea")
(const_string "8")
(const_string "*")))
(set (attr "prefix_rex")
- (if_then_else (eq_attr "alternative" "8,9")
+ (if_then_else (eq_attr "alternative" "7,8")
(const_string "1")
(const_string "*")))
(set (attr "prefix_data16")
- (if_then_else (eq_attr "alternative" "11")
+ (if_then_else (eq_attr "alternative" "10")
(const_string "1")
(const_string "*")))
(set (attr "prefix")
- (if_then_else (eq_attr "alternative" "10,11,12,13,14,15")
+ (if_then_else (eq_attr "alternative" "11,12,13,14,15")
(const_string "maybe_vex")
(const_string "orig")))
- (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,DI,TI,DI,TI,DI,DI,DI,DI,DI")])
+ (set_attr "mode" "SI,DI,DI,DI,DI,DI,DI,DI,DI,TI,DI,TI,DI,DI,DI,DI,DI")])
;; Reload patterns to support multi-word load/store
;; with non-offsetable address.
DONE;
})
-;; Convert impossible stores of immediate to existing instructions.
-;; First try to get scratch register and go through it. In case this
-;; fails, move by 32bit parts.
-(define_peephole2
- [(match_scratch:DI 2 "r")
- (set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
- "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
- && !x86_64_immediate_operand (operands[1], DImode)"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0) (match_dup 2))])
-
-;; We need to define this as both peepholer and splitter for case
-;; peephole2 pass is not run.
-;; "&& 1" is needed to keep it from matching the previous pattern.
-(define_peephole2
- [(set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
- "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
- && !x86_64_immediate_operand (operands[1], DImode) && 1"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 4) (match_dup 5))]
- "split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);")
-
-(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
- "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
- ? epilogue_completed : reload_completed)
- && !symbolic_operand (operands[1], DImode)
- && !x86_64_immediate_operand (operands[1], DImode)"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 4) (match_dup 5))]
- "split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);")
-
(define_insn "*movdi_internal"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=r ,o ,*y,m*y,*y,*x,m ,*x,*x,*x,m ,*x,*x,?*x,?*Ym")
return "movd\t{%1, %0|%0, %1}";
case TYPE_LEA:
- return "lea{l}\t{%a1, %0|%0, %a1}";
+ return "lea{l}\t{%E1, %0|%0, %E1}";
default:
gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
- return "mov{l}\t{%1, %0|%0, %1}";
+ if (ix86_use_lea_for_mov (insn, operands))
+ return "lea{l}\t{%E1, %0|%0, %E1}";
+ else
+ return "mov{l}\t{%1, %0|%0, %1}";
}
}
[(set (attr "type")
;; into register when rax is not available
(define_insn "*movabs<mode>_1"
[(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
- (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))]
- "TARGET_64BIT && ix86_check_movabs (insn, 0)"
+ (match_operand:SWI1248x 1 "nonmemory_operand" "a,r<i>"))]
+ "TARGET_LP64 && ix86_check_movabs (insn, 0)"
"@
- movabs{<imodesuffix>}\t{%1, %P0|%P0, %1}
- mov{<imodesuffix>}\t{%1, %a0|%a0, %1}"
+ movabs{<imodesuffix>}\t{%1, %P0|[%P0], %1}
+ mov{<imodesuffix>}\t{%1, %a0|<iptrsize> PTR %a0, %1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*")
(set_attr "length_address" "8,0")
(define_insn "*movabs<mode>_2"
[(set (match_operand:SWI1248x 0 "register_operand" "=a,r")
(mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
- "TARGET_64BIT && ix86_check_movabs (insn, 1)"
+ "TARGET_LP64 && ix86_check_movabs (insn, 1)"
"@
- movabs{<imodesuffix>}\t{%P1, %0|%0, %P1}
- mov{<imodesuffix>}\t{%a1, %0|%0, %a1}"
+ movabs{<imodesuffix>}\t{%P1, %0|%0, [%P1]}
+ mov{<imodesuffix>}\t{%a1, %0|%0, <iptrsize> PTR %a1}"
[(set_attr "type" "imov")
(set_attr "modrm" "0,*")
(set_attr "length_address" "8,0")
(const_int 8))
(match_operand:SWI48x 1 "nonmemory_operand" "Qn"))]
"TARGET_64BIT"
- "mov{b}\t{%b1, %h0|%h0, %b1}"
+{
+ if (CONST_INT_P (operands[1]))
+ operands[1] = simplify_gen_subreg (QImode, operands[1], <MODE>mode, 0);
+ return "mov{b}\t{%b1, %h0|%h0, %b1}";
+}
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(const_int 8))
(match_operand:SI 1 "general_operand" "Qmn"))]
"!TARGET_64BIT"
- "mov{b}\t{%b1, %h0|%h0, %b1}"
+{
+ if (CONST_INT_P (operands[1]))
+ operands[1] = simplify_gen_subreg (QImode, operands[1], SImode, 0);
+ return "mov{b}\t{%b1, %h0|%h0, %b1}";
+}
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "nonimmediate_operand" ""))]
- "TARGET_SSE2"
+ "TARGET_64BIT || TARGET_SSE2"
{
ix86_expand_move (TFmode, operands);
DONE;
""
"ix86_expand_move (<MODE>mode, operands); DONE;")
-(define_insn "*movtf_internal"
+(define_insn "*movtf_internal_rex64"
[(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?*r ,!o")
- (match_operand:TF 1 "general_operand" "xm,x,C,*roF,F*r"))]
- "TARGET_SSE2
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))
+ (match_operand:TF 1 "general_operand" "xm,x,C,*roF,*r"))]
+ "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| GET_CODE (operands[1]) != CONST_DOUBLE
(const_string "TI"))]
(const_string "DI")))])
+(define_insn "*movtf_internal_sse2"
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x")
+ (match_operand:TF 1 "general_operand" "xm,x,C"))]
+ "TARGET_SSE2 && !TARGET_64BIT
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))
+ && (!can_create_pseudo_p ()
+ || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
+ || GET_CODE (operands[1]) != CONST_DOUBLE
+ || (optimize_function_for_size_p (cfun)
+ && standard_sse_constant_p (operands[1])
+ && !memory_operand (operands[0], TFmode))
+ || (!TARGET_MEMORY_MISMATCH_STALL
+ && memory_operand (operands[0], TFmode)))"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ /* Handle misaligned load/store since we
+ don't have movmisaligntf pattern. */
+ if (misaligned_operand (operands[0], TFmode)
+ || misaligned_operand (operands[1], TFmode))
+ {
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "%vmovups\t{%1, %0|%0, %1}";
+ else
+ return "%vmovdqu\t{%1, %0|%0, %1}";
+ }
+ else
+ {
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "%vmovaps\t{%1, %0|%0, %1}";
+ else
+ return "%vmovdqa\t{%1, %0|%0, %1}";
+ }
+
+ case 2:
+ return standard_sse_constant_opcode (insn, operands[1]);
+
+ default:
+ gcc_unreachable ();
+ }
+}
+ [(set_attr "type" "ssemov,ssemov,sselog1")
+ (set_attr "prefix" "maybe_vex")
+ (set (attr "mode")
+ (cond [(eq_attr "alternative" "0,2")
+ (if_then_else
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ (const_string "TI"))
+ (eq_attr "alternative" "1")
+ (if_then_else
+ (ior (match_test "TARGET_SSE_TYPELESS_STORES")
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ (const_string "TI"))]
+ (const_string "DI")))])
+
+(define_insn "*movxf_internal_rex64"
+ [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
+ (match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,Yx*rC"))]
+ "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
+ && (!can_create_pseudo_p ()
+ || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
+ || GET_CODE (operands[1]) != CONST_DOUBLE
+ || (optimize_function_for_size_p (cfun)
+ && standard_80387_constant_p (operands[1]) > 0
+ && !memory_operand (operands[0], XFmode))
+ || (!TARGET_MEMORY_MISMATCH_STALL
+ && memory_operand (operands[0], XFmode)))"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ return output_387_reg_move (insn, operands);
+
+ case 2:
+ return standard_80387_constant_opcode (operands[1]);
+
+ case 3:
+ case 4:
+ return "#";
+
+ default:
+ gcc_unreachable ();
+ }
+}
+ [(set_attr "type" "fmov,fmov,fmov,multi,multi")
+ (set_attr "mode" "XF,XF,XF,SI,SI")])
+
;; Possible store forwarding (partial memory) stall in alternative 4.
(define_insn "*movxf_internal"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
- (match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,FYx*r"))]
- "!(MEM_P (operands[0]) && MEM_P (operands[1]))
+ (match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,Yx*rF"))]
+ "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| GET_CODE (operands[1]) != CONST_DOUBLE
(define_insn "*movdf_internal_rex64"
[(set (match_operand:DF 0 "nonimmediate_operand"
- "=f,m,f,?r,?m,?r,!o,x,x,x,m,Yi,r ")
+ "=?Yf*f,?m ,?Yf*f,?r,?m,?r,?r,x,x,x,m,Yi,r ")
(match_operand:DF 1 "general_operand"
- "fm,f,G,rm,r ,F ,F ,C,x,m,x,r ,Yi"))]
+ "Yf*fm ,Yf*f ,G ,rm,rC,C ,F ,C,x,m,x,r ,Yi"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
return "mov{q}\t{%1, %0|%0, %1}";
case 5:
- return "movabs{q}\t{%1, %0|%0, %1}";
+ return "mov{l}\t{%1, %k0|%k0, %1}";
case 6:
- return "#";
+ return "movabs{q}\t{%1, %0|%0, %1}";
case 7:
return standard_sse_constant_opcode (insn, operands[1]);
[(set (attr "type")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "fmov")
- (eq_attr "alternative" "3,4,5")
+ (eq_attr "alternative" "3,4,5,6")
(const_string "imov")
- (eq_attr "alternative" "6")
- (const_string "multi")
(eq_attr "alternative" "7")
(const_string "sselog1")
]
(const_string "ssemov")))
(set (attr "modrm")
(if_then_else
- (and (eq_attr "alternative" "5") (eq_attr "type" "imov"))
+ (and (eq_attr "alternative" "6") (eq_attr "type" "imov"))
(const_string "0")
(const_string "*")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "alternative" "5") (eq_attr "type" "imov"))
+ (and (eq_attr "alternative" "6") (eq_attr "type" "imov"))
(const_string "8")
(const_string "*")))
(set (attr "prefix")
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
- (eq_attr "alternative" "3,4,5,6,11,12")
+ (eq_attr "alternative" "3,4,6,11,12")
(const_string "DI")
+ (eq_attr "alternative" "5")
+ (const_string "SI")
/* xorps is one byte shorter. */
(eq_attr "alternative" "7")
;; Possible store forwarding (partial memory) stall in alternative 4.
(define_insn "*movdf_internal"
[(set (match_operand:DF 0 "nonimmediate_operand"
- "=f,m,f,?Yd*r ,!o ,x,x,x,m,*x,*x,*x,m")
+ "=Yf*f,m ,Yf*f,?Yd*r ,!o ,x,x,x,m,*x,*x,*x,m")
(match_operand:DF 1 "general_operand"
- "fm,f,G,Yd*roF,FYd*r,C,x,m,x,C ,*x,m ,*x"))]
+ "Yf*fm,Yf*f,G ,Yd*roF,Yd*rF,C,x,m,x,C ,*x,m ,*x"))]
"!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
(define_insn "*movsf_internal"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=f,m,f,?r ,?m,x,x,x,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
+ "=Yf*f,m ,Yf*f,?r ,?m,x,x,x,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
(match_operand:SF 1 "general_operand"
- "fm,f,G,rmF,Fr,C,x,m,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
+ "Yf*fm,Yf*f,G ,rmF,rF,C,x,m,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
(cond [(eq_attr "alternative" "0,1,2")
(const_string "fmov")
(eq_attr "alternative" "3,4")
- (const_string "multi")
+ (const_string "imov")
(eq_attr "alternative" "5")
(const_string "sselog1")
(eq_attr "alternative" "9,10,11,14,15")
})
(define_insn "*zero_extendsidi2_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*x")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?!*y,?*Yi,*x")
(zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
+ (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
"TARGET_64BIT"
"@
- mov\t{%k1, %k0|%k0, %k1}
+ mov{l}\t{%1, %k0|%k0, %1}
#
movd\t{%1, %0|%0, %1}
movd\t{%1, %0|%0, %1}
;; %%% Kill me once multi-word ops are sane.
(define_insn "zero_extendsidi2_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*x")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?!*y,?*Yi,*x")
(zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
+ (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"@
;
else
{
- enum ix86_stack_slot slot = (virtuals_instantiated
- ? SLOT_TEMP
- : SLOT_VIRTUAL);
- rtx temp = assign_386_stack_local (SFmode, slot);
+ rtx temp = assign_386_stack_local (SFmode, SLOT_TEMP);
emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
DONE;
}
DONE;
}
else
- {
- enum ix86_stack_slot slot = (virtuals_instantiated
- ? SLOT_TEMP
- : SLOT_VIRTUAL);
- operands[2] = assign_386_stack_local (<MODE>mode, slot);
- }
+ operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
})
(define_insn "*truncxfsf2_mixed"
(define_insn "*floathi<mode>2_i387_with_temp"
[(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
(float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))
- (clobber (match_operand:HI 2 "memory_operand" "=m,m"))]
+ (clobber (match_operand:HI 2 "memory_operand" "=X,m"))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)"
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_split
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (float:MODEF (match_dup 2)))])
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)]
{
rtx op1 = operands[1];
emit_insn (gen_sse2_loadld (operands[4],
CONST0_RTX (V4SImode), operands[2]));
}
- emit_insn
- (gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
+ if (<ssevecmode>mode == V4SFmode)
+ emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
+ else
+ emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)]
{
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
emit_insn (gen_sse2_loadld (operands[4],
CONST0_RTX (V4SImode), operands[1]));
- emit_insn
- (gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
+ if (<ssevecmode>mode == V4SFmode)
+ emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
+ else
+ emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)]
{
rtx op1 = operands[1];
operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0);
else
gcc_unreachable ();
- emit_insn
- (gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
+ if (<ssevecmode>mode == V4SFmode)
+ emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
+ else
+ emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(const_int 0)]
{
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
emit_insn (gen_sse2_loadld (operands[4],
CONST0_RTX (V4SImode), operands[1]));
- emit_insn
- (gen_sse2_cvtdq2<ssevecmodesuffix> (operands[3], operands[4]));
+ if (<ssevecmode>mode == V4SFmode)
+ emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
+ else
+ emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
DONE;
})
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_insn "*float<SWI48x:mode><MODEF:mode>2_sse_nointerunit"
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (float:MODEF (match_dup 2)))])
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
- && SSE_REG_P (operands[0])))"
+ && SSE_REG_P (SUBREG_REG (operands[0]))))"
[(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_insn "*float<SWI48x:mode><X87MODEF:mode>2_i387_with_temp"
DONE;
}
else
- {
- enum ix86_stack_slot slot = (virtuals_instantiated
- ? SLOT_TEMP
- : SLOT_VIRTUAL);
- operands[2] = assign_386_stack_local (DImode, slot);
- }
+ operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
})
(define_expand "floatunsdisf2"
DONE;
})
\f
+;; Load effective address instructions
+
+(define_insn_and_split "*lea<mode>"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (match_operand:SWI48 1 "lea_address_operand" "p"))]
+ ""
+{
+ rtx addr = operands[1];
+
+ if (SImode_address_operand (addr, VOIDmode))
+ {
+ gcc_assert (TARGET_64BIT);
+ return "lea{l}\t{%E1, %k0|%k0, %E1}";
+ }
+ else
+ return "lea{<imodesuffix>}\t{%E1, %0|%0, %E1}";
+}
+ "reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
+ [(const_int 0)]
+{
+ ix86_split_lea_for_addr (operands, <MODE>mode);
+ DONE;
+}
+ [(set_attr "type" "lea")
+ (set (attr "mode")
+ (if_then_else
+ (match_operand 1 "SImode_address_operand")
+ (const_string "SI")
+ (const_string "<MODE>")))])
+\f
;; Add instructions
(define_expand "add<mode>3"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-(define_insn_and_split "*lea_1"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (subreg:SI (match_operand:DI 1 "lea_address_operand" "p") 0))]
- "TARGET_64BIT"
- "lea{l}\t{%a1, %0|%0, %a1}"
- "&& reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
- [(const_int 0)]
-{
- ix86_split_lea_for_addr (operands, SImode);
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea<mode>_2"
- [(set (match_operand:SWI48 0 "register_operand" "=r")
- (match_operand:SWI48 1 "lea_address_operand" "p"))]
- ""
- "lea{<imodesuffix>}\t{%a1, %0|%0, %a1}"
- "reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
- [(const_int 0)]
-{
- ix86_split_lea_for_addr (operands, <MODE>mode);
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*lea_3_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (subreg:SI (match_operand:DI 1 "lea_address_operand" "p") 0)))]
- "TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn "*lea_4_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (match_operand:SI 1 "lea_address_operand" "p")))]
- "TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn "*lea_5_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (and:DI
- (subreg:DI (match_operand:SI 1 "lea_address_operand" "p") 0)
- (match_operand:DI 2 "const_32bit_mask" "n")))]
- "TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn "*lea_6_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (and:DI
- (match_operand:DI 1 "lea_address_operand" "p")
- (match_operand:DI 2 "const_32bit_mask" "n")))]
- "TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
(define_insn "*add<mode>_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
(plus:SWI48
[(set (reg FLAGS_REG)
(compare
(plus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0,<r>")
+ (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>,0"))
(const_int 0)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m,<r>")
(plus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
}
default:
+ if (which_alternative == 2)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
(define_insn "*addsi_2_zext"
[(set (reg FLAGS_REG)
(compare
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "x86_64_general_operand" "rme"))
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
+ (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
+ (set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (PLUS, SImode, operands)"
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
if (x86_maybe_negate_const_int (&operands[2], SImode))
return "sub{l}\t{%2, %k0|%k0, %2}";
(define_insn "*add<mode>_3"
[(set (reg FLAGS_REG)
(compare
- (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>"))
- (match_operand:SWI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:SWI 0 "=<r>"))]
+ (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>,0"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")))
+ (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
"ix86_match_ccmode (insn, CCZmode)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
(define_insn "*addsi_3_zext"
[(set (reg FLAGS_REG)
(compare
- (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme"))
- (match_operand:SI 1 "nonimmediate_operand" "%0")))
- (set (match_operand:DI 0 "register_operand" "=r")
+ (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
+ (match_operand:SI 1 "nonimmediate_operand" "%0,r")))
+ (set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
&& ix86_binary_operator_ok (PLUS, SImode, operands)"
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
if (x86_maybe_negate_const_int (&operands[2], SImode))
return "sub{l}\t{%2, %k0|%k0, %2}";
[(set (reg FLAGS_REG)
(compare
(plus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "%0")
- (match_operand:SWI 2 "<general_operand>" "<g>"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")
+ (match_operand:SWI 2 "<general_operand>" "<g>,0"))
(const_int 0)))
- (clobber (match_scratch:SWI 0 "=<r>"))]
+ (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
\f
-;; Overflow setting add and subtract instructions
+;; Overflow setting add instructions
(define_insn "*add<mode>3_cconly_overflow"
[(set (reg:CCC FLAGS_REG)
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
-(define_insn "*sub<mode>3_cconly_overflow"
+(define_insn "*add<mode>3_cc_overflow"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
- (minus:SWI
- (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
- (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
- (match_dup 0)))]
- ""
- "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
- [(set_attr "type" "icmp")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*<plusminus_insn><mode>3_cc_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (plusminus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
+ (plus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
(match_dup 1)))
(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
- (plusminus:SWI (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ (plus:SWI (match_dup 1) (match_dup 2)))]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
-(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
+(define_insn "*addsi3_zext_cc_overflow"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
- (plusminus:SI
- (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
+ (plus:SI
+ (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "x86_64_general_operand" "rme"))
(match_dup 1)))
(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
+ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
+ "add{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
[(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
(match_dup 3))
(const_int 0)]))]
- "operands[2] = gen_lowpart (SImode, operands[2]);
- operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
+{
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);
+})
(define_split
[(set (match_operand 0 "flags_reg_operand" "")
[(set (match_dup 0)
(match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
(const_int 0)]))]
- "operands[2] = gen_lowpart (QImode, operands[2]);
- operands[3] = gen_lowpart (QImode, operands[3]);")
+{
+ operands[2] = gen_lowpart (QImode, operands[2]);
+ operands[3] = gen_lowpart (QImode, operands[3]);
+})
;; %%% This used to optimize known byte-wide and operations to memory,
;; and sometimes to QImode registers. If this is considered useful,
(and:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
(match_operand:SWIM 2 "<general_szext_operand>" "")))]
""
- "ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;")
+{
+ if (<MODE>mode == DImode
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff
+ && REG_P (operands[1]))
+ emit_insn (gen_zero_extendsidi2 (operands[0],
+ gen_lowpart (SImode, operands[1])));
+ else
+ ix86_expand_binary_operator (AND, <MODE>mode, operands);
+ DONE;
+})
(define_insn "*anddi_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
enum machine_mode mode;
gcc_assert (CONST_INT_P (operands[2]));
- if (INTVAL (operands[2]) == 0xff)
- mode = QImode;
+ if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff)
+ mode = SImode;
+ else if (INTVAL (operands[2]) == 0xffff)
+ mode = HImode;
else
{
- gcc_assert (INTVAL (operands[2]) == 0xffff);
- mode = HImode;
+ gcc_assert (INTVAL (operands[2]) == 0xff);
+ mode = QImode;
}
operands[1] = gen_lowpart (mode, operands[1]);
- if (mode == QImode)
- return "movz{bl|x}\t{%1, %k0|%k0, %1}";
- else
+ if (mode == SImode)
+ return "mov{l}\t{%1, %k0|%k0, %1}";
+ else if (mode == HImode)
return "movz{wl|x}\t{%1, %k0|%k0, %1}";
+ else
+ return "movz{bl|x}\t{%1, %k0|%k0, %1}";
}
default:
enum machine_mode mode;
gcc_assert (CONST_INT_P (operands[2]));
- if (INTVAL (operands[2]) == 0xff)
- mode = QImode;
+ if (INTVAL (operands[2]) == 0xffff)
+ mode = HImode;
else
{
- gcc_assert (INTVAL (operands[2]) == 0xffff);
- mode = HImode;
+ gcc_assert (INTVAL (operands[2]) == 0xff);
+ mode = QImode;
}
operands[1] = gen_lowpart (mode, operands[1]);
- if (mode == QImode)
- return "movz{bl|x}\t{%1, %0|%0, %1}";
- else
+ if (mode == HImode)
return "movz{wl|x}\t{%1, %0|%0, %1}";
+ else
+ return "movz{bl|x}\t{%1, %0|%0, %1}";
}
default:
(const_int 8) (const_int 8))
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
+})
;; Since AND can be encoded with sign extended immediate, this is only
;; profitable when 7th bit is not set.
(and:QI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (QImode, operands[0]);
- operands[1] = gen_lowpart (QImode, operands[1]);
- operands[2] = gen_lowpart (QImode, operands[2]);")
+{
+ operands[0] = gen_lowpart (QImode, operands[0]);
+ operands[1] = gen_lowpart (QImode, operands[1]);
+ operands[2] = gen_lowpart (QImode, operands[2]);
+})
\f
;; Logical inclusive and exclusive OR instructions
(const_int 8) (const_int 8))
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
+})
;; Since OR can be encoded with sign extended immediate, this is only
;; profitable when 7th bit is set.
(any_or:QI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (QImode, operands[0]);
- operands[1] = gen_lowpart (QImode, operands[1]);
- operands[2] = gen_lowpart (QImode, operands[2]);")
+{
+ operands[0] = gen_lowpart (QImode, operands[0]);
+ operands[1] = gen_lowpart (QImode, operands[1]);
+ operands[2] = gen_lowpart (QImode, operands[2]);
+})
(define_expand "xorqi_cc_ext_1"
[(parallel [
(match_dup 0)))
(set (match_dup 1)
(if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:SWI48 3 "register_operand" "r")
+ (match_operand:SWI48 3 "register_operand" "")
(match_dup 1)))]
"TARGET_CMOVE"
"operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
})
;; Avoid useless masking of count operand.
-(define_insn_and_split "*ashl<mode>3_mask"
+(define_insn "*ashl<mode>3_mask"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
(ashift:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0")
(subreg:QI
(and:SI
- (match_operand:SI 2 "nonimmediate_operand" "c")
+ (match_operand:SI 2 "register_operand" "c")
(match_operand:SI 3 "const_int_operand" "n")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
== GET_MODE_BITSIZE (<MODE>mode)-1"
- "#"
- "&& 1"
- [(parallel [(set (match_dup 0)
- (ashift:SWI48 (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
{
- if (can_create_pseudo_p ())
- operands [2] = force_reg (SImode, operands[2]);
-
- operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
+ return "sal{<imodesuffix>}\t{%b2, %0|%0, %b2}";
}
[(set_attr "type" "ishift")
(set_attr "mode" "<MODE>")])
;; See comment above `ashl<mode>3' about how this works.
-(define_expand "<shiftrt_insn><mode>3"
+(define_expand "<shift_insn><mode>3"
[(set (match_operand:SDWIM 0 "<shift_operand>" "")
(any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
;; Avoid useless masking of count operand.
-(define_insn_and_split "*<shiftrt_insn><mode>3_mask"
+(define_insn "*<shift_insn><mode>3_mask"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
(any_shiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0")
(subreg:QI
(and:SI
- (match_operand:SI 2 "nonimmediate_operand" "c")
+ (match_operand:SI 2 "register_operand" "c")
(match_operand:SI 3 "const_int_operand" "n")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
== GET_MODE_BITSIZE (<MODE>mode)-1"
- "#"
- "&& 1"
- [(parallel [(set (match_dup 0)
- (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
{
- if (can_create_pseudo_p ())
- operands [2] = force_reg (SImode, operands[2]);
-
- operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
+ return "<shift>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
}
[(set_attr "type" "ishift")
(set_attr "mode" "<MODE>")])
-(define_insn_and_split "*<shiftrt_insn><mode>3_doubleword"
+(define_insn_and_split "*<shift_insn><mode>3_doubleword"
[(set (match_operand:DWI 0 "register_operand" "=r")
(any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "<S>c")))
"#"
"(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
[(const_int 0)]
- "ix86_split_<shiftrt_insn> (operands, NULL_RTX, <MODE>mode); DONE;"
+ "ix86_split_<shift_insn> (operands, NULL_RTX, <MODE>mode); DONE;"
[(set_attr "type" "multi")])
;; By default we don't ask for a scratch register, because when DWImode
(match_dup 3)]
"TARGET_CMOVE"
[(const_int 0)]
- "ix86_split_<shiftrt_insn> (operands, operands[3], <DWI>mode); DONE;")
+ "ix86_split_<shift_insn> (operands, operands[3], <DWI>mode); DONE;")
(define_insn "x86_64_shrd"
[(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
DONE;
})
-(define_insn "*bmi2_<shiftrt_insn><mode>3_1"
+(define_insn "*bmi2_<shift_insn><mode>3_1"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(match_operand:SWI48 2 "register_operand" "r")))]
"TARGET_BMI2"
- "<shiftrt>x\t{%2, %1, %0|%0, %1, %2}"
+ "<shift>x\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ishiftx")
(set_attr "mode" "<MODE>")])
-(define_insn "*<shiftrt_insn><mode>3_1"
+(define_insn "*<shift_insn><mode>3_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
(any_shiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm")
default:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "<shiftrt>{<imodesuffix>}\t%0";
+ return "<shift>{<imodesuffix>}\t%0";
else
- return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set_attr "isa" "*,bmi2")
(any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))]
"operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
-(define_insn "*bmi2_<shiftrt_insn>si3_1_zext"
+(define_insn "*bmi2_<shift_insn>si3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
(match_operand:SI 2 "register_operand" "r"))))]
"TARGET_64BIT && TARGET_BMI2"
- "<shiftrt>x\t{%2, %1, %k0|%k0, %1, %2}"
+ "<shift>x\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "type" "ishiftx")
(set_attr "mode" "SI")])
-(define_insn "*<shiftrt_insn>si3_1_zext"
+(define_insn "*<shift_insn>si3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,rm")
default:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "<shiftrt>{l}\t%k0";
+ return "<shift>{l}\t%k0";
else
- return "<shiftrt>{l}\t{%2, %k0|%k0, %2}";
+ return "<shift>{l}\t{%2, %k0|%k0, %2}";
}
}
[(set_attr "isa" "*,bmi2")
(zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
"operands[2] = gen_lowpart (SImode, operands[2]);")
-(define_insn "*<shiftrt_insn><mode>3_1"
+(define_insn "*<shift_insn><mode>3_1"
[(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m")
(any_shiftrt:SWI12
(match_operand:SWI12 1 "nonimmediate_operand" "0")
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "<shiftrt>{<imodesuffix>}\t%0";
+ return "<shift>{<imodesuffix>}\t%0";
else
- return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*<shiftrt_insn>qi3_1_slp"
+(define_insn "*<shift_insn>qi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(any_shiftrt:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "cI")))
{
if (operands[1] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "<shiftrt>{b}\t%0";
+ return "<shift>{b}\t%0";
else
- return "<shiftrt>{b}\t{%1, %0|%0, %1}";
+ return "<shift>{b}\t{%1, %0|%0, %1}";
}
[(set_attr "type" "ishift1")
(set (attr "length_immediate")
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
-(define_insn "*<shiftrt_insn><mode>3_cmp"
+(define_insn "*<shift_insn><mode>3_cmp"
[(set (reg FLAGS_REG)
(compare
(any_shiftrt:SWI
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "<shiftrt>{<imodesuffix>}\t%0";
+ return "<shift>{<imodesuffix>}\t%0";
else
- return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*<shiftrt_insn>si3_cmp_zext"
+(define_insn "*<shift_insn>si3_cmp_zext"
[(set (reg FLAGS_REG)
(compare
(any_shiftrt:SI (match_operand:SI 1 "register_operand" "0")
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "<shiftrt>{l}\t%k0";
+ return "<shift>{l}\t%k0";
else
- return "<shiftrt>{l}\t{%2, %k0|%k0, %2}";
+ return "<shift>{l}\t{%2, %k0|%k0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(const_string "*")))
(set_attr "mode" "SI")])
-(define_insn "*<shiftrt_insn><mode>3_cconly"
+(define_insn "*<shift_insn><mode>3_cconly"
[(set (reg FLAGS_REG)
(compare
(any_shiftrt:SWI
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "<shiftrt>{<imodesuffix>}\t%0";
+ return "<shift>{<imodesuffix>}\t%0";
else
- return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return "<shift>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
;; Avoid useless masking of count operand.
-(define_insn_and_split "*<rotate_insn><mode>3_mask"
+(define_insn "*<rotate_insn><mode>3_mask"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
(any_rotate:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0")
(subreg:QI
(and:SI
- (match_operand:SI 2 "nonimmediate_operand" "c")
+ (match_operand:SI 2 "register_operand" "c")
(match_operand:SI 3 "const_int_operand" "n")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
== GET_MODE_BITSIZE (<MODE>mode)-1"
- "#"
- "&& 1"
- [(parallel [(set (match_dup 0)
- (any_rotate:SWI48 (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
{
- if (can_create_pseudo_p ())
- operands [2] = force_reg (SImode, operands[2]);
-
- operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);
+ return "<rotate>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
}
[(set_attr "type" "rotate")
(set_attr "mode" "<MODE>")])
[(simple_return)]
"ix86_can_use_return_insn_p ()"
{
+ ix86_maybe_emit_epilogue_vzeroupper ();
if (crtl->args.pops_args)
{
rtx popc = GEN_INT (crtl->args.pops_args);
[(simple_return)]
"!TARGET_SEH"
{
+ ix86_maybe_emit_epilogue_vzeroupper ();
if (crtl->args.pops_args)
{
rtx popc = GEN_INT (crtl->args.pops_args);
"!TARGET_64BIT && TARGET_GNU_TLS"
{
output_asm_insn
- ("lea{l}\t{%a2@tlsgd(,%1,1), %0|%0, %a2@tlsgd[%1*1]}", operands);
+ ("lea{l}\t{%E2@tlsgd(,%1,1), %0|%0, %E2@tlsgd[%1*1]}", operands);
if (TARGET_SUN_TLS)
#ifdef HAVE_AS_IX86_TLSGDPLT
return "call\t%a2@tlsgdplt";
if (!TARGET_X32)
fputs (ASM_BYTE "0x66\n", asm_out_file);
output_asm_insn
- ("lea{q}\t{%a1@tlsgd(%%rip), %%rdi|rdi, %a1@tlsgd[rip]}", operands);
+ ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands);
fputs (ASM_SHORT "0x6666\n", asm_out_file);
fputs ("\trex64\n", asm_out_file);
if (TARGET_SUN_TLS)
(unspec:SI [(match_operand:SI 2 "tls_symbolic_operand" "")]
UNSPEC_TLSDESC))))]
"!TARGET_64BIT && TARGET_GNU2_TLS"
- "lea{l}\t{%a2@TLSDESC(%1), %0|%0, %a2@TLSDESC[%1]}"
+ "lea{l}\t{%E2@TLSDESC(%1), %0|%0, %E2@TLSDESC[%1]}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")
(set_attr "length" "6")
(unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
UNSPEC_TLSDESC))]
"TARGET_64BIT && TARGET_GNU2_TLS"
- "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[rip]}"
+ "lea{q}\t{%E1@TLSDESC(%%rip), %0|%0, %E1@TLSDESC[rip]}"
[(set_attr "type" "lea")
(set_attr "mode" "DI")
(set_attr "length" "7")
else if (optimize_insn_for_size_p ())
FAIL;
else
- ix86_expand_rint (operand0, operand1);
+ ix86_expand_rint (operands[0], operands[1]);
}
else
{
&& <SWI248x:MODE>mode != HImode
&& ((<SWI248x:MODE>mode != DImode) || TARGET_64BIT)
&& !flag_trapping_math && !flag_rounding_math)
- ix86_expand_lround (operand0, operand1);
+ ix86_expand_lround (operands[0], operands[1]);
else
ix86_emit_i387_round (operands[0], operands[1]);
DONE;
else if (optimize_insn_for_size_p ())
FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
- ix86_expand_floorceil (operand0, operand1, true);
+ ix86_expand_floorceil (operands[0], operands[1], true);
else
- ix86_expand_floorceildf_32 (operand0, operand1, true);
+ ix86_expand_floorceildf_32 (operands[0], operands[1], true);
}
else
{
{
if (TARGET_64BIT && optimize_insn_for_size_p ())
FAIL;
- ix86_expand_lfloorceil (operand0, operand1, true);
+ ix86_expand_lfloorceil (operands[0], operands[1], true);
DONE;
})
else if (optimize_insn_for_size_p ())
FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
- ix86_expand_floorceil (operand0, operand1, false);
+ ix86_expand_floorceil (operands[0], operands[1], false);
else
- ix86_expand_floorceildf_32 (operand0, operand1, false);
+ ix86_expand_floorceildf_32 (operands[0], operands[1], false);
}
else
{
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math"
{
- ix86_expand_lfloorceil (operand0, operand1, false);
+ ix86_expand_lfloorceil (operands[0], operands[1], false);
DONE;
})
else if (optimize_insn_for_size_p ())
FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
- ix86_expand_trunc (operand0, operand1);
+ ix86_expand_trunc (operands[0], operands[1]);
else
- ix86_expand_truncdf_32 (operand0, operand1);
+ ix86_expand_truncdf_32 (operands[0], operands[1]);
}
else
{
emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, operands[1]));
else
{
- enum ix86_stack_slot slot = (virtuals_instantiated
- ? SLOT_TEMP
- : SLOT_VIRTUAL);
- rtx temp = assign_386_stack_local (<MODE>mode, slot);
+ rtx temp = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
emit_move_insn (temp, operands[1]);
emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, temp));
[(parallel [(set (match_operand 1 "memory_operand" "")
(match_operand 2 "register_operand" ""))
(set (match_operand 0 "register_operand" "")
- (match_operand 3 "" ""))])]
+ (match_operand 3 "" ""))
+ (unspec [(const_int 0)] UNSPEC_STOS)])]
""
"ix86_current_function_needs_cld = 1;")
(match_operand:DI 2 "register_operand" "a"))
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
- (const_int 8)))]
+ (const_int 8)))
+ (unspec [(const_int 0)] UNSPEC_STOS)]
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosq"
(match_operand:SI 2 "register_operand" "a"))
(set (match_operand:P 0 "register_operand" "=D")
(plus:P (match_dup 1)
- (const_int 4)))]
+ (const_int 4)))
+ (unspec [(const_int 0)] UNSPEC_STOS)]
"!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stos{l|d}"
[(set_attr "type" "str")
(match_operand:HI 2 "register_operand" "a"))
(set (match_operand:P 0 "register_operand" "=D")
(plus:P (match_dup 1)
- (const_int 2)))]
+ (const_int 2)))
+ (unspec [(const_int 0)] UNSPEC_STOS)]
"!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosw"
[(set_attr "type" "str")
(match_operand:QI 2 "register_operand" "a"))
(set (match_operand:P 0 "register_operand" "=D")
(plus:P (match_dup 1)
- (const_int 1)))]
+ (const_int 1)))
+ (unspec [(const_int 0)] UNSPEC_STOS)]
"!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
"stosb"
[(set_attr "type" "str")
(define_insn "*x86_mov<mode>cc_0_m1_neg"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
- [(reg FLAGS_REG) (const_int 0)])))]
+ [(reg FLAGS_REG) (const_int 0)])))
+ (clobber (reg:CC FLAGS_REG))]
""
"sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
[(set_attr "type" "icmov")
(set_attr "mode" "<MODE>")])
-(define_insn_and_split "*movqicc_noc"
+(define_insn "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
- (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:QI 2 "register_operand" "r,0")
(match_operand:QI 3 "register_operand" "0,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
"#"
- "&& reload_completed"
- [(set (match_dup 0)
- (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
- (match_dup 2)
- (match_dup 3)))]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- operands[3] = gen_lowpart (SImode, operands[3]);"
[(set_attr "type" "icmov")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "QI")])
+
+(define_split
+ [(set (match_operand 0 "register_operand")
+ (if_then_else (match_operator 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)])
+ (match_operand 2 "register_operand")
+ (match_operand 3 "register_operand")))]
+ "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL
+ && (GET_MODE (operands[0]) == QImode
+ || GET_MODE (operands[0]) == HImode)
+ && reload_completed"
+ [(set (match_dup 0)
+ (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ operands[3] = gen_lowpart (SImode, operands[3]);
+})
(define_expand "mov<mode>cc"
[(set (match_operand:X87MODEF 0 "register_operand" "")
(set_attr "mode" "DF,DF,DI,DI")])
(define_split
- [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
+ [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
- (const_int 0)])
- (match_operand:DF 2 "nonimmediate_operand" "")
- (match_operand:DF 3 "nonimmediate_operand" "")))]
+ [(reg FLAGS_REG) (const_int 0)])
+ (match_operand:DF 2 "nonimmediate_operand")
+ (match_operand:DF 3 "nonimmediate_operand")))]
"!TARGET_64BIT && reload_completed"
[(set (match_dup 2)
- (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
- (match_dup 5)
- (match_dup 6)))
+ (if_then_else:SI (match_dup 1) (match_dup 4) (match_dup 5)))
(set (match_dup 3)
- (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
- (match_dup 7)
- (match_dup 8)))]
+ (if_then_else:SI (match_dup 1) (match_dup 6) (match_dup 7)))]
{
- split_double_mode (DImode, &operands[2], 2, &operands[5], &operands[7]);
+ split_double_mode (DImode, &operands[2], 2, &operands[4], &operands[6]);
split_double_mode (DImode, &operands[0], 1, &operands[2], &operands[3]);
})
;; The % modifier is not operational anymore in peephole2's, so we have to
;; swap the operands manually in the case of addition and multiplication.
- "if (COMMUTATIVE_ARITH_P (operands[2]))
- operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
- GET_MODE (operands[2]),
- operands[0], operands[1]);
- else
- operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
- GET_MODE (operands[2]),
- operands[1], operands[0]);")
+{
+ rtx op0, op1;
+
+ if (COMMUTATIVE_ARITH_P (operands[2]))
+ op0 = operands[0], op1 = operands[1];
+ else
+ op0 = operands[1], op1 = operands[0];
+
+ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
+ GET_MODE (operands[2]),
+ op0, op1);
+})
;; Conditional addition patterns
(define_expand "add<mode>cc"
default:
operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{<imodesuffix>}\t{%a2, %0|%0, %a2}";
+ return "lea{<imodesuffix>}\t{%E2, %0|%0, %E2}";
}
}
[(set (attr "type")
emit_insn (gen_set_got (pic_offset_table_rtx));
DONE;
})
-\f
+
+(define_insn_and_split "nonlocal_goto_receiver"
+ [(unspec_volatile [(const_int 0)] UNSPECV_NLGR)]
+ "TARGET_MACHO && !TARGET_64BIT && flag_pic"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ if (crtl->uses_pic_offset_table)
+ {
+ rtx xops[3];
+ rtx label_rtx = gen_label_rtx ();
+ rtx tmp;
+
+ /* Get a new pic base. */
+ emit_insn (gen_set_got_labelled (pic_offset_table_rtx, label_rtx));
+ /* Correct this with the offset from the new to the old. */
+ xops[0] = xops[1] = pic_offset_table_rtx;
+ label_rtx = gen_rtx_LABEL_REF (SImode, label_rtx);
+ tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, label_rtx),
+ UNSPEC_MACHOPIC_OFFSET);
+ xops[2] = gen_rtx_CONST (Pmode, tmp);
+ ix86_expand_binary_operator (MINUS, SImode, xops);
+ }
+ else
+ /* No pic reg restore needed. */
+ emit_note (NOTE_INSN_DELETED);
+
+ DONE;
+})
+
;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
(define_split
[(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))
(clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- if (GET_CODE (operands[3]) != ASHIFT)
- operands[2] = gen_lowpart (SImode, operands[2]);
- PUT_MODE (operands[3], SImode);")
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ if (GET_CODE (operands[3]) != ASHIFT)
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ PUT_MODE (operands[3], SImode);
+})
; Promote the QImode tests, as i386 has encoding of the AND
; instruction with 32-bit sign-extended immediate and thus the
[(parallel [(set (match_dup 0)
(neg:SI (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);")
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+})
(define_split
[(set (match_operand 0 "register_operand" "")
|| optimize_insn_for_size_p ())))"
[(set (match_dup 0)
(not:SI (match_dup 1)))]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (SImode, operands[1]);")
-
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (if_then_else (match_operator 1 "ordered_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand 2 "register_operand" "")
- (match_operand 3 "register_operand" "")))]
- "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
- && (GET_MODE (operands[0]) == HImode
- || (GET_MODE (operands[0]) == QImode
- && (TARGET_PROMOTE_QImode
- || optimize_insn_for_size_p ())))"
- [(set (match_dup 0)
- (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- operands[3] = gen_lowpart (SImode, operands[3]);")
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+})
\f
;; RTL Peephole optimizations, run before sched2. These primarily look to
;; transform a complex memory operation into two memory to register operations.
"(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
&& peep2_reg_dead_p (4, operands[0])
&& !reg_overlap_mentioned_p (operands[0], operands[1])
+ && !reg_overlap_mentioned_p (operands[0], operands[2])
+ && (<MODE>mode != QImode
+ || immediate_operand (operands[2], QImode)
+ || q_regs_operand (operands[2], QImode))
&& ix86_match_ccmode (peep2_next_insn (3),
(GET_CODE (operands[3]) == PLUS
|| GET_CODE (operands[3]) == MINUS)
[(parallel [(set (match_dup 4) (match_dup 5))
(set (match_dup 1) (match_op_dup 3 [(match_dup 1)
(match_dup 2)]))])]
- "operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
- operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
- copy_rtx (operands[1]),
- copy_rtx (operands[2]));
- operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
- operands[5], const0_rtx);")
+{
+ operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
+ operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+ copy_rtx (operands[1]),
+ copy_rtx (operands[2]));
+ operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+ operands[5], const0_rtx);
+})
(define_peephole2
[(parallel [(set (match_operand:SWI 0 "register_operand" "")
[(parallel [(set (match_dup 3) (match_dup 4))
(set (match_dup 1) (match_op_dup 2 [(match_dup 1)
(match_dup 0)]))])]
- "operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
- operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
- copy_rtx (operands[1]),
- copy_rtx (operands[0]));
- operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
- operands[4], const0_rtx);")
+{
+ operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
+ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
+ copy_rtx (operands[1]),
+ copy_rtx (operands[0]));
+ operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
+ operands[4], const0_rtx);
+})
(define_peephole2
[(set (match_operand:SWI12 0 "register_operand" "")
&& REG_P (operands[0]) && REG_P (operands[4])
&& REGNO (operands[0]) == REGNO (operands[4])
&& peep2_reg_dead_p (4, operands[0])
+ && (<MODE>mode != QImode
+ || immediate_operand (operands[2], SImode)
+ || q_regs_operand (operands[2], SImode))
&& !reg_overlap_mentioned_p (operands[0], operands[1])
+ && !reg_overlap_mentioned_p (operands[0], operands[2])
&& ix86_match_ccmode (peep2_next_insn (3),
(GET_CODE (operands[3]) == PLUS
|| GET_CODE (operands[3]) == MINUS)
? CCGOCmode : CCNOmode)"
[(parallel [(set (match_dup 4) (match_dup 5))
(set (match_dup 1) (match_dup 6))])]
- "operands[2] = gen_lowpart (<MODE>mode, operands[2]);
- operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
- operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
- copy_rtx (operands[1]), operands[2]);
- operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
- operands[5], const0_rtx);
- operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
- copy_rtx (operands[1]),
- copy_rtx (operands[2]));")
+{
+ operands[2] = gen_lowpart (<MODE>mode, operands[2]);
+ operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
+ operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+ copy_rtx (operands[1]), operands[2]);
+ operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+ operands[5], const0_rtx);
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+ copy_rtx (operands[1]),
+ copy_rtx (operands[2]));
+})
;; Attempt to always use XOR for zeroing registers.
(define_peephole2
int locality = INTVAL (operands[2]);
gcc_assert (rw == 0 || rw == 1);
- gcc_assert (locality >= 0 && locality <= 3);
- gcc_assert (GET_MODE (operands[0]) == Pmode
- || GET_MODE (operands[0]) == VOIDmode);
+ gcc_assert (IN_RANGE (locality, 0, 3));
+ if (TARGET_PREFETCHW && rw)
+ operands[2] = GEN_INT (3);
/* Use 3dNOW prefetch in case we are asking for write prefetch not
supported by SSE counterpart or the SSE prefetch is not available
(K6 machines). Otherwise use SSE prefetch as it allows specifying
of locality. */
- if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
+ else if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
operands[2] = GEN_INT (3);
else
operands[1] = const0_rtx;
})
-(define_insn "*prefetch_sse_<mode>"
- [(prefetch (match_operand:P 0 "address_operand" "p")
+(define_insn "*prefetch_sse"
+ [(prefetch (match_operand 0 "address_operand" "p")
(const_int 0)
(match_operand:SI 1 "const_int_operand" ""))]
"TARGET_PREFETCH_SSE"
};
int locality = INTVAL (operands[1]);
- gcc_assert (locality >= 0 && locality <= 3);
+ gcc_assert (IN_RANGE (locality, 0, 3));
return patterns[locality];
}
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "prefetch")
(set (attr "length_address")
- (symbol_ref "memory_address_length (operands[0])"))
+ (symbol_ref "memory_address_length (operands[0], false)"))
(set_attr "memory" "none")])
-(define_insn "*prefetch_3dnow_<mode>"
- [(prefetch (match_operand:P 0 "address_operand" "p")
+(define_insn "*prefetch_3dnow"
+ [(prefetch (match_operand 0 "address_operand" "p")
(match_operand:SI 1 "const_int_operand" "n")
(const_int 3))]
- "TARGET_3DNOW"
+ "TARGET_3DNOW || TARGET_PREFETCHW"
{
if (INTVAL (operands[1]) == 0)
return "prefetch\t%a0";
}
[(set_attr "type" "mmx")
(set (attr "length_address")
- (symbol_ref "memory_address_length (operands[0])"))
+ (symbol_ref "memory_address_length (operands[0], false)"))
(set_attr "memory" "none")])
(define_expand "stack_protect_set"
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")]
- ""
+ "!TARGET_HAS_BIONIC"
{
rtx (*insn)(rtx, rtx);
UNSPEC_SP_SET))
(set (match_scratch:PTR 2 "=&r") (const_int 0))
(clobber (reg:CC FLAGS_REG))]
- ""
+ "!TARGET_HAS_BIONIC"
"mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
[(set_attr "type" "multi")])
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")
(match_operand 2 "" "")]
- ""
+ "!TARGET_HAS_BIONIC"
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
(match_operand:PTR 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
(clobber (match_scratch:PTR 3 "=&r"))]
- ""
+ "!TARGET_HAS_BIONIC"
"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
[(set_attr "type" "multi")])
(match_operand:SI 3 "const_int_operand" "i")]
UNSPECV_LWPVAL_INTRINSIC)]
"TARGET_LWP"
- "/* Avoid unused variable warning. */
- (void) operand0;")
+ ;; Avoid unused variable warning.
+ "(void) operands[0];")
(define_insn "*lwp_lwpval<mode>3_1"
[(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")
(define_insn "rdrand<mode>_1"
[(set (match_operand:SWI248 0 "register_operand" "=r")
- (unspec:SWI248 [(const_int 0)] UNSPEC_RDRAND))
+ (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))
(set (reg:CCC FLAGS_REG)
- (unspec:CCC [(const_int 0)] UNSPEC_RDRAND))]
+ (unspec_volatile:CCC [(const_int 0)] UNSPECV_RDRAND))]
"TARGET_RDRND"
"rdrand\t%0"
[(set_attr "type" "other")
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