Backported from mainline

[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.md

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 781e671..f09717d 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7923,7 +7923,18 @@
         (const_int 0)))
    (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
        (and:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
+  "TARGET_64BIT
+   && ix86_match_ccmode
+       (insn,
+        /* If we are going to emit andl instead of andq, and the operands[2]
+           constant might have the SImode sign bit set, make sure the sign
+           flag isn't tested, because the instruction will set the sign flag
+           based on bit 31 rather than bit 63.  If it isn't CONST_INT,
+           conservatively assume it might have bit 31 set.  */
+        (satisfies_constraint_Z (operands[2])
+         && (!CONST_INT_P (operands[2])
+             || val_signbit_known_set_p (SImode, INTVAL (operands[2]))))
+        ? CCZmode : CCNOmode)
    && ix86_binary_operator_ok (AND, DImode, operands)"
   "@
    and{l}\t{%k2, %k0|%k0, %k2}
@@ -12077,8 +12088,8 @@
 
 (define_insn "bmi_bextr_<mode>"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
-        (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r")
-                       (match_operand:SWI48 2 "nonimmediate_operand" "rm")]
+        (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
+                       (match_operand:SWI48 2 "register_operand" "r")]
                        UNSPEC_BEXTR))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_BMI"