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2012-07-04 Tristan Gingold <gingold@adacore.com>
[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.md
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6e2c123..eba1b26 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -80,8 +80,6 @@
   ;; Prologue support
   UNSPEC_STACK_ALLOC
   UNSPEC_SET_GOT
-  UNSPEC_REG_SAVE
-  UNSPEC_DEF_CFA
   UNSPEC_SET_RIP
   UNSPEC_SET_GOT_OFFSET
   UNSPEC_MEMORY_BLOCKAGE
@@ -170,9 +168,6 @@
   ;; For CRC32 support
   UNSPEC_CRC32
 
-  ;; For RDRAND support
-  UNSPEC_RDRAND
-
   ;; For BMI support
   UNSPEC_BEXTR
 
@@ -201,6 +196,9 @@
   UNSPECV_RDGSBASE
   UNSPECV_WRFSBASE
   UNSPECV_WRGSBASE
+
+  ;; For RDRAND support
+  UNSPECV_RDRAND
 ])
 
 ;; Constants to represent rounding modes in the ROUND instruction
@@ -2361,8 +2359,8 @@
 ;; into register when rax is not available
 (define_insn "*movabs<mode>_1"
   [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
-       (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))]
-  "TARGET_64BIT && ix86_check_movabs (insn, 0)"
+       (match_operand:SWI1248x 1 "nonmemory_operand" "a,r<i>"))]
+  "TARGET_LP64 && ix86_check_movabs (insn, 0)"
   "@
    movabs{<imodesuffix>}\t{%1, %P0|%P0, %1}
    mov{<imodesuffix>}\t{%1, %a0|%a0, %1}"
@@ -2376,7 +2374,7 @@
 (define_insn "*movabs<mode>_2"
   [(set (match_operand:SWI1248x 0 "register_operand" "=a,r")
         (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
-  "TARGET_64BIT && ix86_check_movabs (insn, 1)"
+  "TARGET_LP64 && ix86_check_movabs (insn, 1)"
   "@
    movabs{<imodesuffix>}\t{%P1, %0|%0, %P1}
    mov{<imodesuffix>}\t{%a1, %0|%0, %a1}"
@@ -5811,10 +5809,10 @@
   [(set (reg FLAGS_REG)
        (compare
          (plus:SWI
-           (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
-           (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
+           (match_operand:SWI 1 "nonimmediate_operand" "%0,0,<r>")
+           (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>,0"))
          (const_int 0)))
-   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
+   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m,<r>")
        (plus:SWI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
@@ -5831,6 +5829,13 @@
        }
 
     default:
+      if (which_alternative == 2)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+        
+      gcc_assert (rtx_equal_p (operands[0], operands[1]));
       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 
@@ -5852,10 +5857,10 @@
 (define_insn "*addsi_2_zext"
   [(set (reg FLAGS_REG)
        (compare
-         (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-                  (match_operand:SI 2 "x86_64_general_operand" "rme"))
+         (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
+                  (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
          (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
+   (set (match_operand:DI 0 "register_operand" "=r,r")
        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
    && ix86_binary_operator_ok (PLUS, SImode, operands)"
@@ -5872,6 +5877,12 @@
        }
 
     default:
+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+
       if (x86_maybe_negate_const_int (&operands[2], SImode))
         return "sub{l}\t{%2, %k0|%k0, %2}";
 
@@ -5892,9 +5903,9 @@
 (define_insn "*add<mode>_3"
   [(set (reg FLAGS_REG)
        (compare
-         (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>"))
-         (match_operand:SWI 1 "nonimmediate_operand" "%0")))
-   (clobber (match_scratch:SWI 0 "=<r>"))]
+         (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>,0"))
+         (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")))
+   (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
   "ix86_match_ccmode (insn, CCZmode)
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
 {
@@ -5910,6 +5921,13 @@
        }
 
     default:
+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+
+      gcc_assert (rtx_equal_p (operands[0], operands[1]));
       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 
@@ -5931,9 +5949,9 @@
 (define_insn "*addsi_3_zext"
   [(set (reg FLAGS_REG)
        (compare
-         (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme"))
-         (match_operand:SI 1 "nonimmediate_operand" "%0")))
-   (set (match_operand:DI 0 "register_operand" "=r")
+         (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
+         (match_operand:SI 1 "nonimmediate_operand" "%0,r")))
+   (set (match_operand:DI 0 "register_operand" "=r,r")
        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
    && ix86_binary_operator_ok (PLUS, SImode, operands)"
@@ -5950,6 +5968,12 @@
        }
 
     default:
+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+
       if (x86_maybe_negate_const_int (&operands[2], SImode))
         return "sub{l}\t{%2, %k0|%k0, %2}";
 
@@ -6060,10 +6084,10 @@
   [(set (reg FLAGS_REG)
        (compare
          (plus:SWI
-           (match_operand:SWI 1 "nonimmediate_operand" "%0")
-           (match_operand:SWI 2 "<general_operand>" "<g>"))
+           (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")
+           (match_operand:SWI 2 "<general_operand>" "<g>,0"))
          (const_int 0)))
-   (clobber (match_scratch:SWI 0 "=<r>"))]
+   (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
 {
@@ -6079,6 +6103,13 @@
        }
 
     default:
+      if (which_alternative == 1)
+       {
+         rtx tmp;
+         tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+       }
+
+      gcc_assert (rtx_equal_p (operands[0], operands[1]));
       if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
         return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
 
@@ -16349,7 +16380,8 @@
 (define_insn "*x86_mov<mode>cc_0_m1_neg"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
        (neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
-                   [(reg FLAGS_REG) (const_int 0)])))]
+                   [(reg FLAGS_REG) (const_int 0)])))
+   (clobber (reg:CC FLAGS_REG))]
   ""
   "sbb{<imodesuffix>}\t%0, %0"
   [(set_attr "type" "alu")
@@ -17175,6 +17207,9 @@
   "(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
    && peep2_reg_dead_p (4, operands[0])
    && !reg_overlap_mentioned_p (operands[0], operands[1])
+   && (<MODE>mode != QImode
+       || immediate_operand (operands[2], QImode)
+       || q_regs_operand (operands[2], QImode))
    && ix86_match_ccmode (peep2_next_insn (3),
                         (GET_CODE (operands[3]) == PLUS
                          || GET_CODE (operands[3]) == MINUS)
@@ -18110,9 +18145,9 @@
 
 (define_insn "rdrand<mode>_1"
   [(set (match_operand:SWI248 0 "register_operand" "=r")
-       (unspec:SWI248 [(const_int 0)] UNSPEC_RDRAND))
+       (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))
    (set (reg:CCC FLAGS_REG)
-       (unspec:CCC [(const_int 0)] UNSPEC_RDRAND))]
+       (unspec_volatile:CCC [(const_int 0)] UNSPECV_RDRAND))]
   "TARGET_RDRND"
   "rdrand\t%0"
   [(set_attr "type" "other")
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