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* config/i386/i386.md (absneg): New code iterator.
[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.md
index 10f172e..d428c3b 100644 (file)
 (define_code_iterator umaxmin [umax umin])
 
 ;; Base name for integer and FP insn mnemonic
-(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")])
+(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")
+                                (umax "maxu") (umin "minu")])
 (define_code_attr maxminfprefix [(smax "max") (smin "min")])
 
 ;; Mapping of parallel logic operators
 ;; Base name for insn mnemonic.
 (define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])
 
+;; Mapping of abs neg operators
+(define_code_iterator absneg [abs neg])
+
+;; Base name for x87 insn mnemonic.
+(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
+
 ;; All single word integer modes.
 (define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
 
 
 ;; Changing of sign for FP values is doable using integer unit too.
 
-(define_expand "neg<mode>2"
+(define_expand "<code><mode>2"
   [(set (match_operand:X87MODEF 0 "register_operand" "")
-       (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+       (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
   "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
-  "ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;")
-
-(define_expand "abs<mode>2"
-  [(set (match_operand:X87MODEF 0 "register_operand" "")
-       (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
-  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
-  "ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;")
+  "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
 
 (define_insn "*absneg<mode>2_mixed"
   [(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
   "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
   "#")
 
-(define_expand "negtf2"
-  [(set (match_operand:TF 0 "register_operand" "")
-       (neg:TF (match_operand:TF 1 "register_operand" "")))]
-  "TARGET_64BIT"
-  "ix86_expand_fp_absneg_operator (NEG, TFmode, operands); DONE;")
-
-(define_expand "abstf2"
+(define_expand "<code>tf2"
   [(set (match_operand:TF 0 "register_operand" "")
-       (abs:TF (match_operand:TF 1 "register_operand" "")))]
+       (absneg:TF (match_operand:TF 1 "register_operand" "")))]
   "TARGET_64BIT"
-  "ix86_expand_fp_absneg_operator (ABS, TFmode, operands); DONE;")
+  "ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
 
 (define_insn "*absnegtf2_sse"
   [(set (match_operand:TF 0 "register_operand" "=x,x")
 ;; Conditionalize these after reload. If they match before reload, we
 ;; lose the clobber and ability to use integer instructions.
 
-(define_insn "*neg<mode>2_1"
+(define_insn "*<code><mode>2_1"
   [(set (match_operand:X87MODEF 0 "register_operand" "=f")
-       (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
+       (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
   "TARGET_80387
-   && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
-  "fchs"
+   && (reload_completed
+       || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
+  "f<absnegprefix>"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*abs<mode>2_1"
-  [(set (match_operand:X87MODEF 0 "register_operand" "=f")
-       (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
-  "TARGET_80387
-   && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "*negextendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-       (neg:DF (float_extend:DF
-                 (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
-
-(define_insn "*negextenddfxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (neg:XF (float_extend:XF
-                 (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")])
-
-(define_insn "*negextendsfxf2"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-       (neg:XF (float_extend:XF
-                 (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")])
-
-(define_insn "*absextendsfdf2"
+(define_insn "*<code>extendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
-       (abs:DF (float_extend:DF
-                 (match_operand:SF 1 "register_operand" "0"))))]
+       (absneg:DF (float_extend:DF
+                    (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
-  "fabs"
+  "f<absnegprefix>"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "DF")])
 
-(define_insn "*absextenddfxf2"
+(define_insn "*<code>extendsfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
-       (abs:XF (float_extend:XF
-         (match_operand:DF 1 "register_operand" "0"))))]
+       (absneg:XF (float_extend:XF
+                    (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_80387"
-  "fabs"
+  "f<absnegprefix>"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")])
 
-(define_insn "*absextendsfxf2"
+(define_insn "*<code>extenddfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
-       (abs:XF (float_extend:XF
-         (match_operand:SF 1 "register_operand" "0"))))]
+       (absneg:XF (float_extend:XF
+                     (match_operand:DF 1 "register_operand" "0"))))]
   "TARGET_80387"
-  "fabs"
+  "f<absnegprefix>"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")])