(define_code_iterator umaxmin [umax umin])
;; Base name for integer and FP insn mnemonic
-(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")])
+(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")
+ (umax "maxu") (umin "minu")])
(define_code_attr maxminfprefix [(smax "max") (smin "min")])
;; Mapping of parallel logic operators
;; Base name for insn mnemonic.
(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])
+;; Mapping of abs neg operators
+(define_code_iterator absneg [abs neg])
+
+;; Base name for x87 insn mnemonic.
+(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
+
;; All single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
;; Changing of sign for FP values is doable using integer unit too.
-(define_expand "neg<mode>2"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
- "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
- "ix86_expand_fp_absneg_operator (NEG, <MODE>mode, operands); DONE;")
-
-(define_expand "abs<mode>2"
+(define_expand "<code><mode>2"
[(set (match_operand:X87MODEF 0 "register_operand" "")
- (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+ (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
- "ix86_expand_fp_absneg_operator (ABS, <MODE>mode, operands); DONE;")
+ "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
(define_insn "*absneg<mode>2_mixed"
[(set (match_operand:MODEF 0 "register_operand" "=x,x,f,!r")
"TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"#")
-(define_expand "negtf2"
+(define_expand "<code>tf2"
[(set (match_operand:TF 0 "register_operand" "")
- (neg:TF (match_operand:TF 1 "register_operand" "")))]
+ (absneg:TF (match_operand:TF 1 "register_operand" "")))]
"TARGET_64BIT"
- "ix86_expand_fp_absneg_operator (NEG, TFmode, operands); DONE;")
-
-(define_expand "abstf2"
- [(set (match_operand:TF 0 "register_operand" "")
- (abs:TF (match_operand:TF 1 "register_operand" "")))]
- "TARGET_64BIT"
- "ix86_expand_fp_absneg_operator (ABS, TFmode, operands); DONE;")
+ "ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
(define_insn "*absnegtf2_sse"
[(set (match_operand:TF 0 "register_operand" "=x,x")
;; Conditionalize these after reload. If they match before reload, we
;; lose the clobber and ability to use integer instructions.
-(define_insn "*neg<mode>2_1"
- [(set (match_operand:X87MODEF 0 "register_operand" "=f")
- (neg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
- "TARGET_80387
- && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
- "fchs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*abs<mode>2_1"
+(define_insn "*<code><mode>2_1"
[(set (match_operand:X87MODEF 0 "register_operand" "=f")
- (abs:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
+ (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
"TARGET_80387
- && (reload_completed || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
- "fabs"
+ && (reload_completed
+ || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
+ "f<absnegprefix>"
[(set_attr "type" "fsgn")
(set_attr "mode" "<MODE>")])
-(define_insn "*negextendsfdf2"
+(define_insn "*<code>extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (float_extend:DF
- (match_operand:SF 1 "register_operand" "0"))))]
+ (absneg:DF (float_extend:DF
+ (match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
- "fchs"
+ "f<absnegprefix>"
[(set_attr "type" "fsgn")
(set_attr "mode" "DF")])
-(define_insn "*negextenddfxf2"
+(define_insn "*<code>extendsfxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
- (neg:XF (float_extend:XF
- (match_operand:DF 1 "register_operand" "0"))))]
+ (absneg:XF (float_extend:XF
+ (match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387"
- "fchs"
+ "f<absnegprefix>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
-(define_insn "*negextendsfxf2"
+(define_insn "*<code>extenddfxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
- (neg:XF (float_extend:XF
- (match_operand:SF 1 "register_operand" "0"))))]
+ (absneg:XF (float_extend:XF
+ (match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387"
- "fchs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "XF")])
-
-(define_insn "*absextendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (float_extend:DF
- (match_operand:SF 1 "register_operand" "0"))))]
- "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "DF")])
-
-(define_insn "*absextenddfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (abs:XF (float_extend:XF
- (match_operand:DF 1 "register_operand" "0"))))]
- "TARGET_80387"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "XF")])
-
-(define_insn "*absextendsfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (abs:XF (float_extend:XF
- (match_operand:SF 1 "register_operand" "0"))))]
- "TARGET_80387"
- "fabs"
+ "f<absnegprefix>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
[(return)]
"ix86_can_use_return_insn_p ()"
{
- if (current_function_pops_args)
+ if (crtl->args.pops_args)
{
- rtx popc = GEN_INT (current_function_pops_args);
+ rtx popc = GEN_INT (crtl->args.pops_args);
emit_jump_insn (gen_return_pop_internal (popc));
DONE;
}
(define_expand "fmodxf3"
[(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))
- (use (match_operand:XF 2 "register_operand" ""))]
+ (use (match_operand:XF 1 "general_operand" ""))
+ (use (match_operand:XF 2 "general_operand" ""))]
"TARGET_USE_FANCY_MATH_387"
{
rtx label = gen_label_rtx ();
- rtx op2;
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = gen_reg_rtx (XFmode);
- if (rtx_equal_p (operands[1], operands[2]))
- {
- op2 = gen_reg_rtx (XFmode);
- emit_move_insn (op2, operands[2]);
- }
- else
- op2 = operands[2];
+ emit_move_insn (op1, operands[1]);
+ emit_move_insn (op2, operands[2]);
emit_label (label);
- emit_insn (gen_fpremxf4_i387 (operands[1], op2, operands[1], op2));
+ emit_insn (gen_fpremxf4_i387 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
LABEL_NUSES (label) = 1;
- emit_move_insn (operands[0], operands[1]);
+ emit_move_insn (operands[0], op1);
DONE;
})
(define_expand "remainderxf3"
[(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))
- (use (match_operand:XF 2 "register_operand" ""))]
+ (use (match_operand:XF 1 "general_operand" ""))
+ (use (match_operand:XF 2 "general_operand" ""))]
"TARGET_USE_FANCY_MATH_387"
{
rtx label = gen_label_rtx ();
- rtx op2;
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = gen_reg_rtx (XFmode);
- if (rtx_equal_p (operands[1], operands[2]))
- {
- op2 = gen_reg_rtx (XFmode);
- emit_move_insn (op2, operands[2]);
- }
- else
- op2 = operands[2];
+ emit_move_insn (op1, operands[1]);
+ emit_move_insn (op2, operands[2]);
emit_label (label);
- emit_insn (gen_fprem1xf4_i387 (operands[1], op2, operands[1], op2));
+ emit_insn (gen_fprem1xf4_i387 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
LABEL_NUSES (label) = 1;
- emit_move_insn (operands[0], operands[1]);
+ emit_move_insn (operands[0], op1);
DONE;
})
"TARGET_64BIT
&& INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
&& INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
- "*
{
int i;
operands[0] = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, operands[0], operands[4]));
- output_asm_insn (\"jmp\\t%A1\", operands);
+ output_asm_insn ("jmp\t%A1", operands);
for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
{
operands[4] = adjust_address (operands[0], DImode, i*16);
operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
PUT_MODE (operands[4], TImode);
if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
- output_asm_insn (\"rex\", operands);
- output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
+ output_asm_insn ("rex", operands);
+ output_asm_insn ("movaps\t{%5, %4|%4, %5}", operands);
}
- (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
- CODE_LABEL_NUMBER (operands[3]));
- return \"\";
+ (*targetm.asm_out.internal_label) (asm_out_file, "L",
+ CODE_LABEL_NUMBER (operands[3]));
+ return "";
}
- "
[(set_attr "type" "other")
(set_attr "length_immediate" "0")
(set_attr "length_address" "0")
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