(define_code_iterator maxmin [smax smin umax umin])
;; Base name for integer and FP insn mnemonic
-(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")
- (umax "maxu") (umin "minu")])
-(define_code_attr maxminfprefix [(smax "max") (smin "min")])
+(define_code_attr maxmin_int [(smax "maxs") (smin "mins")
+ (umax "maxu") (umin "minu")])
+(define_code_attr maxmin_float [(smax "max") (smin "min")])
;; Mapping of logic operators
(define_code_iterator any_logic [and ior xor])
(define_code_iterator any_or [ior xor])
;; Base name for insn mnemonic.
-(define_code_attr logicprefix [(and "and") (ior "or") (xor "xor")])
+(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
;; Mapping of shift-right operators
(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
(define_code_iterator absneg [abs neg])
;; Base name for x87 insn mnemonic.
-(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
+(define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")])
;; Used in signed and unsigned widening multiplications.
(define_code_iterator any_extend [sign_extend zero_extend])
(clobber (reg:CC FLAGS_REG))]
""
"#"
- "&& reload_completed"
+ "reload_completed"
[(parallel [(set (match_dup 1)
(ashiftrt:SWIM248 (match_dup 4) (match_dup 5)))
(clobber (reg:CC FLAGS_REG))])
(clobber (reg:CC FLAGS_REG))]
""
"#"
- "&& reload_completed"
+ "reload_completed"
[(set (match_dup 1) (const_int 0))
(parallel [(set (match_dup 0)
(udiv:SWIM248 (match_dup 2) (match_dup 3)))
(match_operand:SWI248 2 "<general_operand>" "<g>,r<i>")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, QImode, operands)"
"@
- <logicprefix>{b}\t{%2, %0|%0, %2}
- <logicprefix>{b}\t{%2, %0|%0, %2}
- <logicprefix>{l}\t{%k2, %k0|%k0, %k2}"
+ <logic>{b}\t{%2, %0|%0, %2}
+ <logic>{b}\t{%2, %0|%0, %2}
+ <logic>{l}\t{%k2, %k0|%k0, %k2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI,QI,SI")])
(match_operand:SI 2 "general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "<logicprefix>{b}\t{%1, %0|%0, %1}"
+ "<logic>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(any_or:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(any_or:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<logicprefix>{l}\t{%2, %k0|%k0, %2}"
+ "<logic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "<logicprefix>{b}\t{%1, %0|%0, %1}"
+ "<logic>{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
(clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_match_ccmode (insn, CCNOmode)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<logicprefix>{<imodesuffix>}\t{%2, %0|%0, %2}"
+ "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(match_operand 2 "const_int_operand" "n")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
+ "<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
(set_attr "modrm" "1")
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
+ "<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
- "<logicprefix>{b}\t{%2, %h0|%h0, %2}"
+ "<logic>{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(const_int 8))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
- "<logicprefix>{b}\t{%h2, %h0|%h0, %h2}"
+ "<logic>{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
"TARGET_80387
&& (reload_completed
|| !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "<MODE>")])
(absneg:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "DF")])
(absneg:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
(define_insn "*<code>extenddfxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(absneg:XF (float_extend:XF
- (match_operand:DF 1 "register_operand" "0"))))]
+ (match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387"
- "f<absnegprefix>"
+ "f<absneg_mnemonic>"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
DONE;
})
-(define_insn "*btdi_rex64"
+(define_insn "*bt<mode>"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
- (zero_extract:DI
- (match_operand:DI 0 "register_operand" "r")
+ (zero_extract:SWI48
+ (match_operand:SWI48 0 "register_operand" "r")
(const_int 1)
- (match_operand:DI 1 "nonmemory_operand" "rN"))
- (const_int 0)))]
- "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
- "bt{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "DI")])
-
-(define_insn "*btsi"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (zero_extract:SI
- (match_operand:SI 0 "register_operand" "r")
- (const_int 1)
- (match_operand:SI 1 "nonmemory_operand" "rN"))
+ (match_operand:SWI48 1 "nonmemory_operand" "rN"))
(const_int 0)))]
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
- "bt{l}\t{%1, %0|%0, %1}"
+ "bt{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
\f
;; Store-flag instructions.
FAIL;
})
-;; zero_extend in SImode is correct, since this is what combine pass
-;; generates from shift insn with QImode operand. Actually, the mode of
-;; operand 2 (bit offset operand) doesn't matter since bt insn takes
+;; zero_extend in SImode is correct also for DImode, since this is what combine
+;; pass generates from shift insn with QImode operand. Actually, the mode
+;; of operand 2 (bit offset operand) doesn't matter since bt insn takes
;; appropriate modulo of the bit offset value.
-(define_insn_and_split "*jcc_btdi_rex64"
+(define_insn_and_split "*jcc_bt<mode>"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
- [(zero_extract:DI
- (match_operand:DI 1 "register_operand" "r")
+ [(zero_extract:SWI48
+ (match_operand:SWI48 1 "register_operand" "r")
(const_int 1)
(zero_extend:SI
(match_operand:QI 2 "register_operand" "r")))
(label_ref (match_operand 3 "" ""))
(pc)))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
+ "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
- (zero_extract:DI
+ (zero_extract:SWI48
(match_dup 1)
(const_int 1)
(match_dup 2))
(label_ref (match_dup 3))
(pc)))]
{
- operands[2] = simplify_gen_subreg (DImode, operands[2], QImode, 0);
+ operands[2] = simplify_gen_subreg (<MODE>mode, operands[2], QImode, 0);
PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
})
-;; avoid useless masking of bit offset operand
-(define_insn_and_split "*jcc_btdi_mask_rex64"
+;; Avoid useless masking of bit offset operand. "and" in SImode is correct
+;; also for DImode, this is what combine produces.
+(define_insn_and_split "*jcc_bt<mode>_mask"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
- [(zero_extract:DI
- (match_operand:DI 1 "register_operand" "r")
+ [(zero_extract:SWI48
+ (match_operand:SWI48 1 "register_operand" "r")
(const_int 1)
(and:SI
(match_operand:SI 2 "register_operand" "r")
(label_ref (match_operand 4 "" ""))
(pc)))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))
- && (INTVAL (operands[3]) & 0x3f) == 0x3f"
+ "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
+ && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
+ == GET_MODE_BITSIZE (<MODE>mode)-1"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
- (zero_extract:DI
+ (zero_extract:SWI48
(match_dup 1)
(const_int 1)
(match_dup 2))
(label_ref (match_dup 4))
(pc)))]
{
- operands[2] = simplify_gen_subreg (DImode, operands[2], SImode, 0);
-
- PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
-})
-
-(define_insn_and_split "*jcc_btsi"
- [(set (pc)
- (if_then_else (match_operator 0 "bt_comparison_operator"
- [(zero_extract:SI
- (match_operand:SI 1 "register_operand" "r")
- (const_int 1)
- (zero_extend:SI
- (match_operand:QI 2 "register_operand" "r")))
- (const_int 0)])
- (label_ref (match_operand 3 "" ""))
- (pc)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
- "#"
- "&& 1"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (zero_extract:SI
- (match_dup 1)
- (const_int 1)
- (match_dup 2))
- (const_int 0)))
- (set (pc)
- (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
- (label_ref (match_dup 3))
- (pc)))]
-{
- operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
+ operands[2] = simplify_gen_subreg (<MODE>mode, operands[2], SImode, 0);
PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
})
-;; avoid useless masking of bit offset operand
-(define_insn_and_split "*jcc_btsi_mask"
- [(set (pc)
- (if_then_else (match_operator 0 "bt_comparison_operator"
- [(zero_extract:SI
- (match_operand:SI 1 "register_operand" "r")
- (const_int 1)
- (and:SI
- (match_operand:SI 2 "register_operand" "r")
- (match_operand:SI 3 "const_int_operand" "n")))])
- (label_ref (match_operand 4 "" ""))
- (pc)))
- (clobber (reg:CC FLAGS_REG))]
- "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
- && (INTVAL (operands[3]) & 0x1f) == 0x1f"
- "#"
- "&& 1"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (zero_extract:SI
- (match_dup 1)
- (const_int 1)
- (match_dup 2))
- (const_int 0)))
- (set (pc)
- (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
- (label_ref (match_dup 4))
- (pc)))]
- "PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
-
(define_insn_and_split "*jcc_btsi_1"
[(set (pc)
(if_then_else (match_operator 0 "bt_comparison_operator"
(match_operand:MODEF 1 "nonimmediate_operand" "%x")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
- "v<maxminfprefix>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ "v<maxmin_float>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseadd")
(set_attr "prefix" "vex")
(set_attr "mode" "<MODE>")])
(match_operand:MODEF 1 "nonimmediate_operand" "%0")
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
- "<maxminfprefix>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
+ "<maxmin_float>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])