(UNSPECV_XCHG 12)
(UNSPECV_LOCK 13)
(UNSPECV_PROLOGUE_USE 14)
+ (UNSPECV_CLD 15)
])
;; Constants to represent pcomtrue/pcomfalse variants
;; Instruction suffix for REX 64bit operators.
(define_mode_attr rex64suffix [(SI "") (DI "{q}")])
+
+;; This mode iterator allows :P to be used for patterns that operate on
+;; pointer-sized quantities. Exactly one of the two alternatives will match.
+(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+
\f
;; Scheduling descriptions
[(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
UNSPEC_FNSTSW))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
- && TARGET_USE_<MODE>MODE_FIOP
+ && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
&& (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "multi")
(clobber (match_operand:HI 0 "register_operand" "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
- && TARGET_USE_<MODE>MODE_FIOP
+ && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
&& (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
"#"
"&& reload_completed"
(define_split
[(set (match_operand:DF 0 "push_operand" "")
(match_operand:DF 1 "any_fp_register_operand" ""))]
- "!TARGET_64BIT && reload_completed"
- [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
- (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
- "")
-
-(define_split
- [(set (match_operand:DF 0 "push_operand" "")
- (match_operand:DF 1 "any_fp_register_operand" ""))]
- "TARGET_64BIT && reload_completed"
- [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
- (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
+ "reload_completed"
+ [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
+ (set (mem:DF (reg:P SP_REG)) (match_dup 1))]
"")
(define_split
(define_split
[(set (match_operand:XF 0 "push_operand" "")
(match_operand:XF 1 "any_fp_register_operand" ""))]
- "!TARGET_64BIT"
- [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
- (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
- "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
-
-(define_split
- [(set (match_operand:XF 0 "push_operand" "")
- (match_operand:XF 1 "any_fp_register_operand" ""))]
- "TARGET_64BIT"
- [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
- (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
+ ""
+ [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
+ (set (mem:XF (reg:P SP_REG)) (match_dup 1))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
;; Do not use integer registers when optimizing for size
(define_split
[(set (match_operand:DF 0 "push_operand" "")
(float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
- "!TARGET_64BIT"
- [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
- (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
-
-(define_split
- [(set (match_operand:DF 0 "push_operand" "")
- (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
- "TARGET_64BIT"
- [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
- (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
+ ""
+ [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
+ (set (mem:DF (reg:P SP_REG)) (float_extend:DF (match_dup 1)))])
(define_insn "*dummy_extendsfxf2"
[(set (match_operand:XF 0 "push_operand" "=<")
[(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
""
- [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
- (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
- "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
-
-(define_split
- [(set (match_operand:XF 0 "push_operand" "")
- (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
- "TARGET_64BIT"
- [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
- (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
+ [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
+ (set (mem:XF (reg:P SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_split
[(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
""
- [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
- (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
- "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
-
-(define_split
- [(set (match_operand:XF 0 "push_operand" "")
- (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
- "TARGET_64BIT"
- [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
- (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
+ [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
+ (set (mem:DF (reg:P SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_expand "extendsfdf2"
(const_int 1))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
- "bts{q} %1,%0"
+ "bts{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")])
(define_insn "*btrq"
(const_int 0))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
- "btr{q} %1,%0"
+ "btr{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")])
(define_insn "*btcq"
(not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
- "btc{q} %1,%0"
+ "btc{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")])
;; Allow Nocona to avoid these instructions if a register is available.
emit_insn (gen_xordi3 (operands[0], operands[0], op1));
DONE;
})
+
+(define_insn "*btdi_rex64"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:DI
+ (match_operand:DI 0 "register_operand" "r")
+ (const_int 1)
+ (match_operand:DI 1 "nonmemory_operand" "rN"))
+ (const_int 0)))]
+ "TARGET_64BIT && (TARGET_USE_BT || optimize_size)"
+ "bt{q}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")])
+
+(define_insn "*btsi"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:SI
+ (match_operand:SI 0 "register_operand" "r")
+ (const_int 1)
+ (match_operand:SI 1 "nonmemory_operand" "rN"))
+ (const_int 0)))]
+ "TARGET_USE_BT || optimize_size"
+ "bt{l}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")])
\f
;; Store-flag instructions.
(const_int 2)
(const_int 6)))])
+;; ??? Handle alignment requirements for compare and branch fused macro-op;
+;; the branch instruction does not start at a 16-byte boundary or cross
+;; a 16-byte boundary.
+
+(define_insn "*jcc_fused_1"
+ [(set (pc)
+ (if_then_else (match_operator 1 "comparison_operator"
+ [(match_operand:SWI 2 "register_operand" "<r>")
+ (match_operand:SWI 3 "const0_operand" "n")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT"
+{
+ return "test{<imodesuffix>}\t%2, %2\n\t"
+ "%+j%E1\t%l0\t" ASM_COMMENT_START " fused";
+}
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*jcc_fused_2"
+ [(set (pc)
+ (if_then_else (match_operator 1 "comparison_operator"
+ [(match_operand:SWI 2 "register_operand" "<r>")
+ (match_operand:SWI 3 "const0_operand" "n")])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT"
+{
+ return "test{<imodesuffix>}\t%2, %2\n\t"
+ "%+j%e1\t%l0\t" ASM_COMMENT_START " fused";
+}
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*jcc_fused_3"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "ix86_comparison_uns_operator"
+ [(match_operand:SWI 2 "nonimmediate_operand" "<r>,m,<r>")
+ (match_operand:SWI 3 "<general_operand>" "<r><i>,<r>,m")])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT
+ && !(MEM_P (operands[2])
+ && (MEM_P (operands[3]) || CONST_INT_P (operands[3])))"
+{
+ return "cmp{<imodesuffix>}\t{%3, %2|%2, %3}\n\t"
+ "%+j%E1\t%l0\t" ASM_COMMENT_START " fused";
+}
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*jcc_fused_4"
+ [(set (pc)
+ (if_then_else
+ (match_operator 1 "ix86_comparison_uns_operator"
+ [(match_operand:SWI 2 "nonimmediate_operand" "<r>,m,<r>")
+ (match_operand:SWI 3 "<general_operand>" "<r><i>,<r>,m")])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))]
+ "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT
+ && !(MEM_P (operands[2])
+ && (MEM_P (operands[3]) || CONST_INT_P (operands[3])))"
+{
+ return "cmp{<imodesuffix>}\t{%3, %2|%2, %3}\n\t"
+ "%+j%e1\t%l0\t" ASM_COMMENT_START " fused";
+}
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")])
+
;; In general it is not safe to assume too much about CCmode registers,
;; so simplify-rtx stops when it sees a second one. Under certain
;; conditions this is safe on x86, so help combine not create
FAIL;
})
+;; zero_extend in SImode is correct, since this is what combine pass
+;; generates from shift insn with QImode operand. Actually, the mode of
+;; operand 2 (bit offset operand) doesn't matter since bt insn takes
+;; appropriate modulo of the bit offset value.
+
+(define_insn_and_split "*jcc_btdi_rex64"
+ [(set (pc)
+ (if_then_else (match_operator 0 "bt_comparison_operator"
+ [(zero_extract:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 1)
+ (zero_extend:SI
+ (match_operand:QI 2 "register_operand" "r")))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_64BIT && (TARGET_USE_BT || optimize_size)"
+ "#"
+ "&& 1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:DI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+{
+ operands[2] = simplify_gen_subreg (DImode, operands[2], QImode, 0);
+
+ PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
+})
+
+;; avoid useless masking of bit offset operand
+(define_insn_and_split "*jcc_btdi_mask_rex64"
+ [(set (pc)
+ (if_then_else (match_operator 0 "bt_comparison_operator"
+ [(zero_extract:DI
+ (match_operand:DI 1 "register_operand" "r")
+ (const_int 1)
+ (and:SI
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "const_int_operand" "n")))])
+ (label_ref (match_operand 4 "" ""))
+ (pc)))]
+ "TARGET_64BIT && (TARGET_USE_BT || optimize_size)
+ && (INTVAL (operands[3]) & 0x3f) == 0x3f"
+ "#"
+ "&& 1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:DI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
+ (label_ref (match_dup 4))
+ (pc)))]
+{
+ operands[2] = simplify_gen_subreg (DImode, operands[2], SImode, 0);
+
+ PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
+})
+
+(define_insn_and_split "*jcc_btsi"
+ [(set (pc)
+ (if_then_else (match_operator 0 "bt_comparison_operator"
+ [(zero_extract:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (const_int 1)
+ (zero_extend:SI
+ (match_operand:QI 2 "register_operand" "r")))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_USE_BT || optimize_size"
+ "#"
+ "&& 1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:SI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+{
+ operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
+
+ PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
+})
+
+;; avoid useless masking of bit offset operand
+(define_insn_and_split "*jcc_btsi_mask"
+ [(set (pc)
+ (if_then_else (match_operator 0 "bt_comparison_operator"
+ [(zero_extract:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (const_int 1)
+ (and:SI
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "const_int_operand" "n")))])
+ (label_ref (match_operand 4 "" ""))
+ (pc)))]
+ "(TARGET_USE_BT || optimize_size)
+ && (INTVAL (operands[3]) & 0x1f) == 0x1f"
+ "#"
+ "&& 1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:SI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
+ (label_ref (match_dup 4))
+ (pc)))]
+ "PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
+
+(define_insn_and_split "*jcc_btsi_1"
+ [(set (pc)
+ (if_then_else (match_operator 0 "bt_comparison_operator"
+ [(and:SI
+ (lshiftrt:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:QI 2 "register_operand" "r"))
+ (const_int 1))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_USE_BT || optimize_size"
+ "#"
+ "&& 1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:SI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+{
+ operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
+
+ PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
+})
+
+;; avoid useless masking of bit offset operand
+(define_insn_and_split "*jcc_btsi_mask_1"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "bt_comparison_operator"
+ [(and:SI
+ (lshiftrt:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (subreg:QI
+ (and:SI
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "const_int_operand" "n")) 0))
+ (const_int 1))
+ (const_int 0)])
+ (label_ref (match_operand 4 "" ""))
+ (pc)))]
+ "(TARGET_USE_BT || optimize_size)
+ && (INTVAL (operands[3]) & 0x1f) == 0x1f"
+ "#"
+ "&& 1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:SI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
+ (label_ref (match_dup 4))
+ (pc)))]
+ "PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
+
;; Define combination compare-and-branch fp compare instructions to use
;; during early optimization. Splitting the operation apart early makes
;; for bad code when we want to reverse the operation.
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 5 "=a,a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[3]))
- && TARGET_USE_<MODE>MODE_FIOP
+ && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
&& GET_MODE (operands[1]) == GET_MODE (operands[3])
&& !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
&& ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
"")
(define_insn "*indirect_jump"
- [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
- "!TARGET_64BIT"
- "jmp\t%A0"
- [(set_attr "type" "ibr")
- (set_attr "length_immediate" "0")])
-
-(define_insn "*indirect_jump_rtx64"
- [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
- "TARGET_64BIT"
+ [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))]
+ ""
"jmp\t%A0"
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
})
(define_insn "*tablejump_1"
- [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
- (use (label_ref (match_operand 1 "" "")))]
- "!TARGET_64BIT"
- "jmp\t%A0"
- [(set_attr "type" "ibr")
- (set_attr "length_immediate" "0")])
-
-(define_insn "*tablejump_1_rtx64"
- [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
+ [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))
(use (label_ref (match_operand 1 "" "")))]
- "TARGET_64BIT"
+ ""
"jmp\t%A0"
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
- operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
+ operands[0], const0_rtx,
+ GEN_INT ((DEFAULT_ABI == SYSV_ABI ? X86_64_SSE_REGPARM_MAX
+ : X64_SSE_REGPARM_MAX)
+ - 1),
NULL, 0);
for (i = 0; i < XVECLEN (operands[2], 0); i++)
DONE;
})
-(define_insn_and_split "eh_return_si"
- [(set (pc)
- (unspec [(match_operand:SI 0 "register_operand" "c")]
- UNSPEC_EH_RETURN))]
- "!TARGET_64BIT"
- "#"
- "reload_completed"
- [(const_int 0)]
- "ix86_expand_epilogue (2); DONE;")
-
-(define_insn_and_split "eh_return_di"
+(define_insn_and_split "eh_return_<mode>"
[(set (pc)
- (unspec [(match_operand:DI 0 "register_operand" "c")]
+ (unspec [(match_operand:P 0 "register_operand" "c")]
UNSPEC_EH_RETURN))]
- "TARGET_64BIT"
+ ""
"#"
"reload_completed"
[(const_int 0)]
;; Gcc is slightly more smart about handling normal two address instructions
;; so use special patterns for add and mull.
-(define_insn "*fop_sf_comm_mixed"
- [(set (match_operand:SF 0 "register_operand" "=f,x")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "nonimmediate_operand" "fm,xm")]))]
- "TARGET_MIX_SSE_I387
+(define_insn "*fop_<mode>_comm_mixed"
+ [(set (match_operand:MODEF 0 "register_operand" "=f,x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "fm,xm")]))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
&& COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
- (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator" "")
(const_string "ssemul")
(const_string "sseadd"))
- (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*fop_sf_comm_sse"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "%0")
- (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE_MATH
+(define_insn "*fop_<mode>_comm_sse"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "%0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator" "")
(const_string "ssemul")
(const_string "sseadd")))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*fop_sf_comm_i387"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "%0")
- (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
+(define_insn "*fop_<mode>_comm_i387"
+ [(set (match_operand:MODEF 0 "register_operand" "=f")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "%0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "fm")]))]
"TARGET_80387
&& COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop")))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*fop_sf_1_mixed"
- [(set (match_operand:SF 0 "register_operand" "=f,f,x")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
- (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm")]))]
- "TARGET_MIX_SSE_I387
+(define_insn "*fop_<mode>_1_mixed"
+ [(set (match_operand:MODEF 0 "register_operand" "=f,f,x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm")]))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
&& !COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(and (eq_attr "alternative" "2")
- (match_operand:SF 3 "mult_operator" ""))
+ (match_operand:MODEF 3 "mult_operator" ""))
(const_string "ssemul")
(and (eq_attr "alternative" "2")
- (match_operand:SF 3 "div_operator" ""))
+ (match_operand:MODEF 3 "div_operator" ""))
(const_string "ssediv")
(eq_attr "alternative" "2")
(const_string "sseadd")
- (match_operand:SF 3 "mult_operator" "")
+ (match_operand:MODEF 3 "mult_operator" "")
(const_string "fmul")
- (match_operand:SF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*rcpsf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x")
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
-(define_insn "*fop_sf_1_sse"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "register_operand" "0")
- (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE_MATH
+(define_insn "*fop_<mode>_1_sse"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "register_operand" "0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !COMMUTATIVE_ARITH_P (operands[3])"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:SF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator" "")
(const_string "ssemul")
- (match_operand:SF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator" "")
(const_string "ssediv")
]
(const_string "sseadd")))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
;; This pattern is not fully shadowed by the pattern above.
-(define_insn "*fop_sf_1_i387"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
- (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
+(define_insn "*fop_<mode>_1_i387"
+ [(set (match_operand:MODEF 0 "register_operand" "=f,f")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "0,fm")
+ (match_operand:MODEF 2 "nonimmediate_operand" "fm,0")]))]
"TARGET_80387 && !TARGET_SSE_MATH
&& !COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:SF 3 "mult_operator" "")
- (const_string "fmul")
- (match_operand:SF 3 "div_operator" "")
- (const_string "fdiv")
- ]
- (const_string "fop")))
- (set_attr "mode" "SF")])
-
-;; ??? Add SSE splitters for these!
-(define_insn "*fop_sf_2<mode>_i387"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (match_operator:SF 3 "binary_fp_operator"
- [(float:SF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
- (match_operand:SF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
- "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (cond [(match_operand:SF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator" "")
(const_string "fmul")
- (match_operand:SF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
- (set_attr "fp_int_src" "true")
(set_attr "mode" "<MODE>")])
-(define_insn "*fop_sf_3<mode>_i387"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "register_operand" "0,0")
- (float:SF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
- "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (cond [(match_operand:SF 3 "mult_operator" "")
- (const_string "fmul")
- (match_operand:SF 3 "div_operator" "")
- (const_string "fdiv")
- ]
- (const_string "fop")))
- (set_attr "fp_int_src" "true")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*fop_df_comm_mixed"
- [(set (match_operand:DF 0 "register_operand" "=f,x")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "nonimmediate_operand" "fm,xm")]))]
- "TARGET_SSE2 && TARGET_MIX_SSE_I387
- && COMMUTATIVE_ARITH_P (operands[3])
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (if_then_else (eq_attr "alternative" "1")
- (if_then_else (match_operand:DF 3 "mult_operator" "")
- (const_string "ssemul")
- (const_string "sseadd"))
- (if_then_else (match_operand:DF 3 "mult_operator" "")
- (const_string "fmul")
- (const_string "fop"))))
- (set_attr "mode" "DF")])
-
-(define_insn "*fop_df_comm_sse"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "%0")
- (match_operand:DF 2 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE2 && TARGET_SSE_MATH
- && COMMUTATIVE_ARITH_P (operands[3])
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (if_then_else (match_operand:DF 3 "mult_operator" "")
- (const_string "ssemul")
- (const_string "sseadd")))
- (set_attr "mode" "DF")])
-
-(define_insn "*fop_df_comm_i387"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "%0")
- (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
- "TARGET_80387
- && COMMUTATIVE_ARITH_P (operands[3])
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (if_then_else (match_operand:DF 3 "mult_operator" "")
- (const_string "fmul")
- (const_string "fop")))
- (set_attr "mode" "DF")])
-
-(define_insn "*fop_df_1_mixed"
- [(set (match_operand:DF 0 "register_operand" "=f,f,x")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
- (match_operand:DF 2 "nonimmediate_operand" "fm,0,xm")]))]
- "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
- && !COMMUTATIVE_ARITH_P (operands[3])
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (cond [(and (eq_attr "alternative" "2")
- (match_operand:DF 3 "mult_operator" ""))
- (const_string "ssemul")
- (and (eq_attr "alternative" "2")
- (match_operand:DF 3 "div_operator" ""))
- (const_string "ssediv")
- (eq_attr "alternative" "2")
- (const_string "sseadd")
- (match_operand:DF 3 "mult_operator" "")
- (const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
- (const_string "fdiv")
- ]
- (const_string "fop")))
- (set_attr "mode" "DF")])
-
-(define_insn "*fop_df_1_sse"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "register_operand" "0")
- (match_operand:DF 2 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE2 && TARGET_SSE_MATH
- && !COMMUTATIVE_ARITH_P (operands[3])"
- "* return output_387_binary_op (insn, operands);"
- [(set_attr "mode" "DF")
- (set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
- (const_string "ssemul")
- (match_operand:DF 3 "div_operator" "")
- (const_string "ssediv")
- ]
- (const_string "sseadd")))])
-
-;; This pattern is not fully shadowed by the pattern above.
-(define_insn "*fop_df_1_i387"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
- (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
- "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
- && !COMMUTATIVE_ARITH_P (operands[3])
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
- (const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
- (const_string "fdiv")
- ]
- (const_string "fop")))
- (set_attr "mode" "DF")])
-
;; ??? Add SSE splitters for these!
-(define_insn "*fop_df_2<mode>_i387"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (match_operator:DF 3 "binary_fp_operator"
- [(float:DF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
- (match_operand:DF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
- && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+(define_insn "*fop_<MODEF:mode>_2_i387"
+ [(set (match_operand:MODEF 0 "register_operand" "=f,f")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(float:MODEF
+ (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
+ (match_operand:MODEF 2 "register_operand" "0,0")]))]
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_size)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator" "")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*fop_df_3<mode>_i387"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "register_operand" "0,0")
- (float:DF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
- && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ (set_attr "mode" "<X87MODEI12:MODE>")])
+
+(define_insn "*fop_<MODEF:mode>_3_i387"
+ [(set (match_operand:MODEF 0 "register_operand" "=f,f")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "register_operand" "0,0")
+ (float:MODEF
+ (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_size)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator" "")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(define_insn "*fop_df_4_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
- [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
+ [(float_extend:DF
+ (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
(match_operand:DF 2 "register_operand" "0,f")]))]
"TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
(const_string "fop")))
(set_attr "mode" "XF")])
-(define_insn "*fop_xf_2<mode>_i387"
+(define_insn "*fop_xf_2_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
- [(float:XF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
- (match_operand:XF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
+ [(float:XF
+ (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
+ (match_operand:XF 2 "register_operand" "0,0")]))]
+ "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "")
(set_attr "fp_int_src" "true")
(set_attr "mode" "<MODE>")])
-(define_insn "*fop_xf_3<mode>_i387"
+(define_insn "*fop_xf_3_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,0")
- (float:XF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
+ (float:XF
+ (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
+ "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*fop_xf_5_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(const_string "fdiv")
]
(const_string "fop")))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*fop_xf_6_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(const_string "fdiv")
]
(const_string "fop")))
- (set_attr "mode" "SF")])
+ (set_attr "mode" "<MODE>")])
(define_split
[(set (match_operand 0 "register_operand" "")
\f
;; Block operation instructions
+(define_insn "cld"
+ [(unspec_volatile [(const_int 0)] UNSPECV_CLD)]
+ ""
+ "cld"
+ [(set_attr "length" "1")
+ (set_attr "length_immediate" "0")
+ (set_attr "modrm" "0")])
+
(define_expand "movmemsi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:BLK 1 "memory_operand" ""))
(set (match_operand 2 "register_operand" "")
(match_operand 5 "" ""))])]
"TARGET_SINGLE_STRINGOP || optimize_size"
- "")
+ "ix86_current_function_needs_cld = 1;")
(define_insn "*strmovdi_rex_1"
[(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
(match_operand 3 "memory_operand" ""))
(use (match_dup 4))])]
""
- "")
+ "ix86_current_function_needs_cld = 1;")
(define_insn "*rep_movdi_rex64"
[(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
(set (match_operand 0 "register_operand" "")
(match_operand 3 "" ""))])]
"TARGET_SINGLE_STRINGOP || optimize_size"
- "")
+ "ix86_current_function_needs_cld = 1;")
(define_insn "*strsetdi_rex_1"
[(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
(use (match_operand 3 "register_operand" ""))
(use (match_dup 1))])]
""
- "")
+ "ix86_current_function_needs_cld = 1;")
(define_insn "*rep_stosdi_rex64"
[(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
(clobber (match_operand 1 "register_operand" ""))
(clobber (match_dup 2))])]
""
- "")
+ "ix86_current_function_needs_cld = 1;")
(define_insn "*cmpstrnqi_nz_1"
[(set (reg:CC FLAGS_REG)
(clobber (match_operand 1 "register_operand" ""))
(clobber (match_dup 2))])]
""
- "")
+ "ix86_current_function_needs_cld = 1;")
(define_insn "*cmpstrnqi_1"
[(set (reg:CC FLAGS_REG)
(clobber (match_operand 1 "register_operand" ""))
(clobber (reg:CC FLAGS_REG))])]
""
- "")
+ "ix86_current_function_needs_cld = 1;")
(define_insn "*strlenqi_1"
[(set (match_operand:SI 0 "register_operand" "=&c")
(set_attr "length" "5")])
(define_insn "allocate_stack_worker_64"
- [(set (match_operand:DI 0 "register_operand" "=a")
+ [(set (match_operand:DI 0 "register_operand" "+a")
(unspec_volatile:DI [(match_dup 0)] UNSPECV_STACK_PROBE))
(set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
(clobber (reg:DI R10_REG))
(use (match_operand:DI 2 "const_int_operand" "i"))
(use (label_ref:DI (match_operand 3 "" "X")))]
"TARGET_64BIT
- && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
+ && INTVAL (operands[4]) + X86_64_SSE_REGPARM_MAX * 16 - 16 < 128
&& INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
{
int i;
operands[0] = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, operands[0], operands[4]));
output_asm_insn ("jmp\t%A1", operands);
- for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
+ for (i = X86_64_SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
{
operands[4] = adjust_address (operands[0], DImode, i*16);
operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
[(set_attr "type" "other")
(set_attr "length_immediate" "0")
(set_attr "length_address" "0")
- (set_attr "length" "135")
+ (set_attr "length" "34")
(set_attr "memory" "store")
(set_attr "modrm" "0")
(set_attr "mode" "DI")])