(UNSPEC_INDNTPOFF 8)
; Prologue support
- (UNSPEC_STACK_PROBE 10)
(UNSPEC_STACK_ALLOC 11)
(UNSPEC_SET_GOT 12)
(UNSPEC_SSE_PROLOGUE_SAVE 13)
; x87 Floating point
(UNSPEC_FPATAN 65)
(UNSPEC_FYL2X 66)
- (UNSPEC_FSCALE 67)
+ (UNSPEC_FYL2XP1 67)
(UNSPEC_FRNDINT 68)
(UNSPEC_F2XM1 69)
+ ; x87 Double output FP
(UNSPEC_SINCOS_COS 80)
(UNSPEC_SINCOS_SIN 81)
+ (UNSPEC_TAN_ONE 82)
+ (UNSPEC_TAN_TAN 83)
+ (UNSPEC_XTRACT_FRACT 84)
+ (UNSPEC_XTRACT_EXP 85)
+ (UNSPEC_FSCALE_FRACT 86)
+ (UNSPEC_FSCALE_EXP 87)
+ (UNSPEC_FPREM_F 88)
+ (UNSPEC_FPREM_U 89)
+ (UNSPEC_FPREM1_F 90)
+ (UNSPEC_FPREM1_U 91)
+
+ ; x87 Rounding
+ (UNSPEC_FRNDINT_FLOOR 96)
+ (UNSPEC_FRNDINT_CEIL 97)
+ (UNSPEC_FRNDINT_TRUNC 98)
+ (UNSPEC_FRNDINT_MASK_PM 99)
; REP instruction
(UNSPEC_REP 75)
+
+ (UNSPEC_EH_RETURN 76)
])
(define_constants
[(UNSPECV_BLOCKAGE 0)
- (UNSPECV_EH_RETURN 13)
+ (UNSPECV_STACK_PROBE 10)
(UNSPECV_EMMS 31)
(UNSPECV_LDMXCSR 37)
(UNSPECV_STMXCSR 40)
(UNSPECV_MWAIT 70)
])
+;; Registers by name.
+(define_constants
+ [(BP_REG 6)
+ (SP_REG 7)
+ (FLAGS_REG 17)
+ (FPSR_REG 18)
+ (DIRFLAG_REG 19)
+ ])
+
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
;; from i386.c.
icmp,test,ibr,setcc,icmov,
push,pop,call,callv,leave,
str,cld,
- fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
+ fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
sselog,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
;; The CPU unit operations uses.
(define_attr "unit" "integer,i387,sse,mmx,unknown"
- (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
+ (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
(const_string "i387")
(eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
(const_int 1)))
;; The (bounding maximum) length of an instruction in bytes.
-;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
-;; to split it and compute proper length as for other insns.
+;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
+;; Later we may want to split them and compute proper length as for
+;; other insns.
(define_attr "length" ""
- (cond [(eq_attr "type" "other,multi,fistp")
+ (cond [(eq_attr "type" "other,multi,fistp,frndint")
(const_int 16)
(eq_attr "type" "fcmp")
(const_int 4)
(const_string "none")
(eq_attr "type" "fistp,leave")
(const_string "both")
+ (eq_attr "type" "frndint")
+ (const_string "load")
(eq_attr "type" "push")
(if_then_else (match_operand 1 "memory_operand" "")
(const_string "both")
(define_attr "fp_int_src" "false,true"
(const_string "false"))
+;; Defines rounding mode of an FP operation.
+
+(define_attr "i387_cw" "floor,ceil,trunc,mask_pm,uninitialized,any"
+ (const_string "any"))
+
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "length" "128")
(set_attr "type" "multi")])
\f
+;; Scheduling descriptions
+
(include "pentium.md")
(include "ppro.md")
(include "k6.md")
(include "athlon.md")
+
+\f
+;; Operand and operator predicates
+
+(include "predicates.md")
+
\f
;; Compare instructions.
;; after the cmp) will actually emit the cmpM.
(define_expand "cmpdi"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "x86_64_general_operand" "")))]
""
})
(define_expand "cmpsi"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SI 0 "cmpsi_operand" "")
(match_operand:SI 1 "general_operand" "")))]
""
})
(define_expand "cmphi"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
(match_operand:HI 1 "general_operand" "")))]
""
})
(define_expand "cmpqi"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
(match_operand:QI 1 "general_operand" "")))]
"TARGET_QIMODE_MATH"
(set_attr "mode" "DI")])
(define_expand "cmpdi_1_rex64"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" "")))]
"TARGET_64BIT"
(set_attr "mode" "SI")])
(define_expand "cmpsi_1"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
(match_operand:SI 1 "general_operand" "ri,mr")))]
""
(set_attr "mode" "QI")])
(define_expand "cmpqi_ext_3"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC
(subreg:QI
(zero_extract:SI
;; the old patterns did, but with many more of them.
(define_expand "cmpxf"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
(match_operand:XF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387"
})
(define_expand "cmpdf"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
(match_operand:DF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387 || TARGET_SSE2"
})
(define_expand "cmpsf"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
(match_operand:SF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387 || TARGET_SSE"
;; CCFPmode compare with exceptions
;; CCFPUmode compare with no exceptions
-;; %%% It is an unfortunate fact that ftst has no non-popping variant,
-;; and that fp moves clobber the condition codes, and that there is
-;; currently no way to describe this fact to reg-stack. So there are
-;; no splitters yet for this.
+(define_insn "*cmpfp_0_sf"
+ [(set (match_operand:HI 0 "register_operand" "=a")
+ (unspec:HI
+ [(compare:CCFP
+ (match_operand:SF 1 "register_operand" "f")
+ (match_operand:SF 2 "const0_operand" "X"))]
+ UNSPEC_FNSTSW))]
+ "TARGET_80387"
+ "* return output_fp_compare (insn, operands, 2, 0);"
+ [(set_attr "type" "multi")
+ (set_attr "mode" "SF")])
-;; %%% YIKES! This scheme does not retain a strong connection between
-;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
-;; work! Only allow tos/mem with tos in op 0.
-;;
-;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
-;; things aren't as bad as they sound...
+(define_insn "*cmpfp_0_df"
+ [(set (match_operand:HI 0 "register_operand" "=a")
+ (unspec:HI
+ [(compare:CCFP
+ (match_operand:DF 1 "register_operand" "f")
+ (match_operand:DF 2 "const0_operand" "X"))]
+ UNSPEC_FNSTSW))]
+ "TARGET_80387"
+ "* return output_fp_compare (insn, operands, 2, 0);"
+ [(set_attr "type" "multi")
+ (set_attr "mode" "DF")])
-(define_insn "*cmpfp_0"
+(define_insn "*cmpfp_0_xf"
[(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI
- [(compare:CCFP (match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "X"))]
- UNSPEC_FNSTSW))]
- "TARGET_80387
- && FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])"
-{
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "ftst\;fnstsw\t%0\;fstp\t%y0";
- else
- return "ftst\;fnstsw\t%0";
-}
+ [(compare:CCFP
+ (match_operand:XF 1 "register_operand" "f")
+ (match_operand:XF 2 "const0_operand" "X"))]
+ UNSPEC_FNSTSW))]
+ "TARGET_80387"
+ "* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi")
- (set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
- (const_string "SF")
- (match_operand:DF 1 "" "")
- (const_string "DF")
- ]
- (const_string "XF")))])
+ (set_attr "mode" "XF")])
;; We may not use "#" to split and emit these, since the REG_DEAD notes
;; used to manage the reg stack popping would not be preserved.
(define_insn "*cmpfp_2_sf"
- [(set (reg:CCFP 18)
+ [(set (reg:CCFP FPSR_REG)
(compare:CCFP
(match_operand:SF 0 "register_operand" "f")
(match_operand:SF 1 "nonimmediate_operand" "fm")))]
(set_attr "mode" "SF")])
(define_insn "*cmpfp_2_df"
- [(set (reg:CCFP 18)
+ [(set (reg:CCFP FPSR_REG)
(compare:CCFP
(match_operand:DF 0 "register_operand" "f")
(match_operand:DF 1 "nonimmediate_operand" "fm")))]
(set_attr "mode" "DF")])
(define_insn "*cmpfp_2_xf"
- [(set (reg:CCFP 18)
+ [(set (reg:CCFP FPSR_REG)
(compare:CCFP
(match_operand:XF 0 "register_operand" "f")
(match_operand:XF 1 "register_operand" "f")))]
(set_attr "mode" "XF")])
(define_insn "*cmpfp_2u"
- [(set (reg:CCFPU 18)
+ [(set (reg:CCFPU FPSR_REG)
(compare:CCFPU
(match_operand 0 "register_operand" "f")
(match_operand 1 "register_operand" "f")))]
;; via pushes.
(define_insn "*ficom_1"
- [(set (reg:CCFP 18)
+ [(set (reg:CCFP FPSR_REG)
(compare:CCFP
(match_operand 0 "register_operand" "f,f")
(float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
;; for separating cc0_setter and cc0_user?
(define_split
- [(set (reg:CCFP 18)
+ [(set (reg:CCFP FPSR_REG)
(compare:CCFP
(match_operand:SF 0 "register_operand" "")
(float (match_operand:SI 1 "register_operand" ""))))]
"0 && TARGET_80387 && reload_completed"
- [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
- (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
- (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
+ [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 1))
+ (set (reg:CCFP FPSR_REG) (compare:CCFP (match_dup 0) (match_dup 2)))
+ (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
"operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
;; FP compares, step 2
;; Move the fpsw to ax.
-(define_insn "*x86_fnstsw_1"
+(define_insn "x86_fnstsw_1"
[(set (match_operand:HI 0 "register_operand" "=a")
- (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
+ (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
"TARGET_80387"
"fnstsw\t%0"
[(set_attr "length" "2")
;; Get ax into flags, general case.
(define_insn "x86_sahf_1"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
"!TARGET_64BIT"
"sahf"
;; Pentium Pro can do steps 1 through 3 in one go.
(define_insn "*cmpfp_i"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (match_operand 0 "register_operand" "f")
(match_operand 1 "register_operand" "f")))]
"TARGET_80387 && TARGET_CMOVE
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& FLOAT_MODE_P (GET_MODE (operands[0]))
- && GET_MODE (operands[0]) == GET_MODE (operands[0])"
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 0);"
[(set_attr "type" "fcmp")
(set (attr "mode")
(set_attr "athlon_decode" "vector")])
(define_insn "*cmpfp_i_sse"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
(match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
"TARGET_80387
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
- && GET_MODE (operands[0]) == GET_MODE (operands[0])"
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 0);"
[(set_attr "type" "fcmp,ssecomi")
(set (attr "mode")
(set_attr "athlon_decode" "vector")])
(define_insn "*cmpfp_i_sse_only"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (match_operand 0 "register_operand" "x")
(match_operand 1 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
- && GET_MODE (operands[0]) == GET_MODE (operands[0])"
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 0);"
[(set_attr "type" "ssecomi")
(set (attr "mode")
(set_attr "athlon_decode" "vector")])
(define_insn "*cmpfp_iu"
- [(set (reg:CCFPU 17)
+ [(set (reg:CCFPU FLAGS_REG)
(compare:CCFPU (match_operand 0 "register_operand" "f")
(match_operand 1 "register_operand" "f")))]
"TARGET_80387 && TARGET_CMOVE
(set_attr "athlon_decode" "vector")])
(define_insn "*cmpfp_iu_sse"
- [(set (reg:CCFPU 17)
+ [(set (reg:CCFPU FLAGS_REG)
(compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
(match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
"TARGET_80387
(set_attr "athlon_decode" "vector")])
(define_insn "*cmpfp_iu_sse_only"
- [(set (reg:CCFPU 17)
+ [(set (reg:CCFPU FLAGS_REG)
(compare:CCFPU (match_operand 0 "register_operand" "x")
(match_operand 1 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
(define_insn "*popsi1_epilogue"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
- (mem:SI (reg:SI 7)))
- (set (reg:SI 7)
- (plus:SI (reg:SI 7) (const_int 4)))
+ (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (mem:BLK (scratch)))]
"!TARGET_64BIT"
"pop{l}\t%0"
(define_insn "popsi1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
- (mem:SI (reg:SI 7)))
- (set (reg:SI 7)
- (plus:SI (reg:SI 7) (const_int 4)))]
+ (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG) (const_int 4)))]
"!TARGET_64BIT"
"pop{l}\t%0"
[(set_attr "type" "pop")
(define_insn "*movsi_xor"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "const0_operand" "i"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
"xor{l}\t{%0, %0|%0, %0}"
[(set_attr "type" "alu1")
(define_insn "*movsi_or"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "immediate_operand" "i"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& operands[1] == constm1_rtx
&& (TARGET_PENTIUM || optimize_size)"
(define_insn "*movstricthi_xor"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
(match_operand:HI 1 "const0_operand" "i"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
"xor{w}\t{%0, %0|%0, %0}"
(define_insn "*movstrictqi_xor"
[(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
(match_operand:QI 1 "const0_operand" "i"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
"xor{b}\t{%0, %0|%0, %0}"
[(set_attr "type" "alu1")
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
-(define_insn "*movsi_insv_1_rex64"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
+(define_insn "movdi_insv_1_rex64"
+ [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
- (match_operand:SI 1 "nonmemory_operand" "Qn"))]
+ (match_operand:DI 1 "nonmemory_operand" "Qn"))]
"TARGET_64BIT"
"mov{b}\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
;; We need to define this as both peepholer and splitter for case
;; peephole2 pass is not run.
+;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
[(set (match_operand:DI 0 "push_operand" "")
(match_operand:DI 1 "immediate_operand" ""))]
(define_split
[(set (match_operand:DI 0 "push_operand" "")
(match_operand:DI 1 "immediate_operand" ""))]
- "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
+ "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 0) (match_dup 1))
(define_insn "*popdi1_epilogue_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
- (mem:DI (reg:DI 7)))
- (set (reg:DI 7)
- (plus:DI (reg:DI 7) (const_int 8)))
+ (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG)
+ (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (mem:BLK (scratch)))]
"TARGET_64BIT"
"pop{q}\t%0"
(define_insn "popdi1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
- (mem:DI (reg:DI 7)))
- (set (reg:DI 7)
- (plus:DI (reg:DI 7) (const_int 8)))]
+ (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG)
+ (plus:DI (reg:DI SP_REG) (const_int 8)))]
"TARGET_64BIT"
"pop{q}\t%0"
[(set_attr "type" "pop")
(define_insn "*movdi_xor_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const0_operand" "i"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
&& reload_completed"
"xor{l}\t{%k0, %k0|%k0, %k0}"
(define_insn "*movdi_or_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const_int_operand" "i"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
&& reload_completed
&& operands[1] == constm1_rtx"
"ix86_split_long_move (operands); DONE;")
(define_insn "*movdi_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y")
- (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y,!*Y,!*y")
+ (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm,*y,*Y"))]
"TARGET_64BIT
&& (TARGET_INTER_UNIT_MOVES || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (get_attr_type (insn))
{
+ case TYPE_SSECVT:
+ if (which_alternative == 11)
+ return "movq2dq\t{%1, %0|%0, %1}";
+ else
+ return "movdq2q\t{%1, %0|%0, %1}";
case TYPE_SSEMOV:
if (get_attr_mode (insn) == MODE_TI)
return "movdqa\t{%1, %0|%0, %1}";
(const_string "mmxmov")
(eq_attr "alternative" "8,9,10")
(const_string "ssemov")
+ (eq_attr "alternative" "11,12")
+ (const_string "ssecvt")
(eq_attr "alternative" "4")
(const_string "multi")
(and (ne (symbol_ref "flag_pic") (const_int 0))
(const_string "lea")
]
(const_string "imov")))
- (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
- (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
- (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
+ (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*")
+ (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*")
+ (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI,DI,DI")])
(define_insn "*movdi_1_rex64_nointerunit"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
;; We need to define this as both peepholer and splitter for case
;; peephole2 pass is not run.
+;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
[(set (match_operand:DI 0 "memory_operand" "")
(match_operand:DI 1 "immediate_operand" ""))]
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
(match_operand:DI 1 "immediate_operand" ""))]
- "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
+ "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 2) (match_dup 3))
[(set (match_operand:SF 0 "push_operand" "")
(match_operand:SF 1 "any_fp_register_operand" ""))]
"!TARGET_64BIT"
- [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
- (set (mem:SF (reg:SI 7)) (match_dup 1))])
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
+ (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
(define_split
[(set (match_operand:SF 0 "push_operand" "")
(match_operand:SF 1 "any_fp_register_operand" ""))]
"TARGET_64BIT"
- [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
- (set (mem:SF (reg:DI 7)) (match_dup 1))])
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
+ (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
(define_insn "*movsf_1"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
[(set (match_operand:DF 0 "push_operand" "")
(match_operand:DF 1 "any_fp_register_operand" ""))]
"!TARGET_64BIT && reload_completed"
- [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
- (set (mem:DF (reg:SI 7)) (match_dup 1))]
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
+ (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
"")
(define_split
[(set (match_operand:DF 0 "push_operand" "")
(match_operand:DF 1 "any_fp_register_operand" ""))]
"TARGET_64BIT && reload_completed"
- [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
- (set (mem:DF (reg:DI 7)) (match_dup 1))]
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
+ (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
"")
(define_split
[(set (match_operand:XF 0 "push_operand" "")
(match_operand:XF 1 "any_fp_register_operand" ""))]
"!TARGET_64BIT"
- [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
- (set (mem:XF (reg:SI 7)) (match_dup 1))]
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
+ (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_split
[(set (match_operand:XF 0 "push_operand" "")
(match_operand:XF 1 "any_fp_register_operand" ""))]
"TARGET_64BIT"
- [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
- (set (mem:XF (reg:DI 7)) (match_dup 1))]
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
+ (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
;; Do not use integer registers when optimizing for size
(define_insn "zero_extendhisi2_and"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
"#"
[(set_attr "type" "alu1")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:HI 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_insn "*zero_extendhisi2_movzwl"
[(parallel
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(define_insn "*zero_extendqihi2_and"
[(set (match_operand:HI 0 "register_operand" "=r,?&q")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
"#"
[(set_attr "type" "alu1")
(define_insn "*zero_extendqihi2_movzbw_and"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
"#"
[(set_attr "type" "imovx,alu1")
(define_split
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
&& (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
(define_split
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
&& (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
(define_split
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_expand "zero_extendqisi2"
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(define_insn "*zero_extendqisi2_and"
[(set (match_operand:SI 0 "register_operand" "=r,?&q")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
"#"
[(set_attr "type" "alu1")
(define_insn "*zero_extendqisi2_movzbw_and"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
"#"
[(set_attr "type" "imovx,alu1")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
&& (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
&& (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:QI 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
;; %%% Kill me once multi-word ops are sane.
(define_insn "zero_extendsidi2_32"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
"@
#
(define_insn "*zero_extendsidi2_32_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
"@
#
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(set (match_dup 4) (const_int 0))]
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(zero_extend:DI (match_operand:SI 1 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && reload_completed
&& !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
[(set (match_dup 3) (match_dup 1))
(define_expand "extendsidi2"
[(parallel [(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (match_scratch:SI 2 ""))])]
""
{
(define_insn "*extendsidi2_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
(sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (match_scratch:SI 2 "=X,X,X,&r"))]
"!TARGET_64BIT"
"#")
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (match_operand:SI 2 "register_operand" ""))]
"(reload_completed
&& dead_or_set_p (insn, operands[1])
&& !reg_mentioned_p (operands[1], operands[0]))"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(set (match_dup 4) (match_dup 1))]
"split_di (&operands[0], 1, &operands[3], &operands[4]);")
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (match_operand:SI 2 "register_operand" ""))]
"reload_completed"
[(const_int 0)]
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (match_scratch:SI 2 ""))]
"reload_completed"
[(const_int 0)]
[(set (match_operand:DF 0 "push_operand" "")
(float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
"!TARGET_64BIT"
- [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
- (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
+ (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
(define_split
[(set (match_operand:DF 0 "push_operand" "")
(float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
"TARGET_64BIT"
- [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
- (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
+ (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
(define_insn "*dummy_extendsfxf2"
[(set (match_operand:XF 0 "push_operand" "=<")
[(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
""
- [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
- (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
+ (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_split
[(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
"TARGET_64BIT"
- [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
- (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
+ (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_split
[(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
""
- [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
- (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
+ (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_split
[(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
"TARGET_64BIT"
- [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
- (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
+ (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_expand "extendsfdf2"
(define_expand "fix_truncxfdi2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(fix:DI (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"")
(define_expand "fix_truncdfdi2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(fix:DI (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
{
if (TARGET_64BIT && TARGET_SSE2)
(define_expand "fix_truncsfdi2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(fix:DI (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
{
if (TARGET_SSE && TARGET_64BIT)
(define_insn_and_split "*fix_truncdi_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
(fix:DI (match_operand 1 "register_operand" "f,f")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
&& !reload_completed && !reload_in_progress
&& (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
DONE;
}
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "DI")])
(define_insn "fix_truncdi_nomemory"
&& (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
"#"
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "DI")])
(define_insn "fix_truncdi_memory"
(clobber (match_scratch:DF 4 "=&1f"))]
"TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
&& (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
- "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
+ "* return output_fix_trunc (insn, operands);"
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "DI")])
(define_split
(define_expand "fix_truncxfsi2"
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
(fix:SI (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"")
(define_expand "fix_truncdfsi2"
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
(fix:SI (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || TARGET_SSE2"
{
if (TARGET_SSE2)
(define_expand "fix_truncsfsi2"
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
(fix:SI (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || TARGET_SSE"
{
if (TARGET_SSE)
(define_insn_and_split "*fix_truncsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
(fix:SI (match_operand 1 "register_operand" "f,f")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
&& !reload_completed && !reload_in_progress
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
DONE;
}
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "SI")])
(define_insn "fix_truncsi_nomemory"
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
"#"
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "SI")])
(define_insn "fix_truncsi_memory"
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
"* return output_fix_trunc (insn, operands);"
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "SI")])
;; When SSE available, it is always faster to use it!
(define_expand "fix_truncxfhi2"
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
(fix:HI (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"")
(define_expand "fix_truncdfhi2"
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
(fix:HI (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 && !TARGET_SSE2"
"")
(define_expand "fix_truncsfhi2"
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
(fix:HI (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 && !TARGET_SSE"
"")
(define_insn_and_split "*fix_trunchi_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
(fix:HI (match_operand 1 "register_operand" "f,f")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
&& !reload_completed && !reload_in_progress
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
"#"
- ""
+ "&& 1"
[(const_int 0)]
{
ix86_optimize_mode_switching = 1;
DONE;
}
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "HI")])
(define_insn "fix_trunchi_nomemory"
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
"#"
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "HI")])
(define_insn "fix_trunchi_memory"
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
"* return output_fix_trunc (insn, operands);"
[(set_attr "type" "fistp")
+ (set_attr "i387_cw" "trunc")
(set_attr "mode" "HI")])
(define_split
(set (match_dup 0) (match_dup 4))]
"")
-;; %% Not used yet.
(define_insn "x86_fnstcw_1"
[(set (match_operand:HI 0 "memory_operand" "=m")
- (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
+ (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
"TARGET_80387"
"fnstcw\t%0"
[(set_attr "length" "2")
(set_attr "unit" "i387")])
(define_insn "x86_fldcw_1"
- [(set (reg:HI 18)
+ [(set (reg:HI FPSR_REG)
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387"
"fldcw\t%0"
emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
}
+ break;
case 2:
{
rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
emit_insn (gen_sse_shufps (op0, tmp, tmp,
const1_rtx));
}
+ break;
case 2:
{
rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
emit_move_insn (tmp, operands[1]);
emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
}
+ break;
case 3:
{
rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
emit_insn (gen_sse_shufps (op0, tmp, tmp,
GEN_INT (3)));
}
+ break;
default:
abort ();
}
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "roiF,riF")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
"#")
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
+ [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
UNSPEC_ADD_CARRY))
(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
(parallel [(set (match_dup 3)
- (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+ (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
(match_dup 4))
(match_dup 5)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"split_di (operands+0, 1, operands+0, operands+3);
split_di (operands+1, 1, operands+1, operands+4);
split_di (operands+2, 1, operands+2, operands+5);")
(plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
(match_operand:DI 1 "nonimmediate_operand" "%0,0"))
(match_operand:DI 2 "x86_64_general_operand" "re,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
"adc{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "DI")])
(define_insn "*adddi3_cc_rex64"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "x86_64_general_operand" "re,rm")]
UNSPEC_ADD_CARRY))
(plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
(match_operand:QI 1 "nonimmediate_operand" "%0,0"))
(match_operand:QI 2 "general_operand" "qi,qm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, QImode, operands)"
"adc{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
(match_operand:HI 1 "nonimmediate_operand" "%0,0"))
(match_operand:HI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, HImode, operands)"
"adc{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
(match_operand:SI 1 "nonimmediate_operand" "%0,0"))
(match_operand:SI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
"adc{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
(match_operand:SI 1 "nonimmediate_operand" "%0"))
(match_operand:SI 2 "general_operand" "rim"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
"adc{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
(define_insn "*addsi3_cc"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "ri,rm")]
UNSPEC_ADD_CARRY))
(set_attr "mode" "SI")])
(define_insn "addqi3_cc"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
(match_operand:QI 2 "general_operand" "qi,qm")]
UNSPEC_ADD_CARRY))
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
(match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "x86_64_nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(set (match_dup 0)
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
(match_operand:SI 2 "general_operand" "rmni,rni,rni")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand 0 "register_operand" "")
(plus (match_operand 1 "register_operand" "")
(match_operand 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(const_int 0)]
(zero_extend:DI
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
(match_operand:SI 2 "general_operand" "rmni,rni"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
{
switch (get_attr_type (insn))
(zero_extend:DI
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "nonmemory_operand" ""))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(set (match_dup 0)
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
(match_operand:HI 2 "general_operand" "ri,rm,rni")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, HImode, operands)"
{
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
(match_operand:HI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, HImode, operands)"
{
[(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
(plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
(match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, QImode, operands)"
{
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "qn,qmn,rn")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, QImode, operands)"
{
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(plus:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qn,qnm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 1 "incdec_operand" "")
(const_string "incdec")
(const_string "alu1")))
(set_attr "mode" "QI")])
(const_int 8)
(const_int 8))
(match_operand:QI 2 "general_operand" "Qmn")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
{
switch (get_attr_type (insn))
(const_int 8)
(const_int 8))
(match_operand:QI 2 "nonmemory_operand" "Qn")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
{
switch (get_attr_type (insn))
(match_operand 2 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"add{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
(minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "general_operand" "roiF,riF")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
"#")
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
+ [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
(parallel [(set (match_dup 3)
(minus:SI (match_dup 4)
- (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+ (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
(match_dup 5))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"split_di (operands+0, 1, operands+0, operands+3);
split_di (operands+1, 1, operands+1, operands+4);
split_di (operands+2, 1, operands+2, operands+5);")
(minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
(match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
"sbb{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:DI 2 "x86_64_general_operand" "re,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
"sub{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
(match_operand:QI 2 "general_operand" "qi,qm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, QImode, operands)"
"sbb{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
(match_operand:HI 2 "general_operand" "ri,rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, HImode, operands)"
"sbb{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
(match_operand:SI 2 "general_operand" "ri,rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, SImode, operands)"
"sbb{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(minus:SI (match_operand:SI 1 "register_operand" "0,0")
(plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
(match_operand:SI 2 "general_operand" "ri,rm")))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
"sbb{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:SI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, SImode, operands)"
"sub{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(zero_extend:DI
(minus:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "general_operand" "rim"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
"sub{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
(minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
(minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:HI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, HImode, operands)"
"sub{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
[(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
(minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
(minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "general_operand" "qn,qmn")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, QImode, operands)"
"sub{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(minus:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qn,qmn")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"sub{b}\t{%1, %0|%0, %1}"
[(parallel [(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT"
"")
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"@
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:SI 2 "general_operand" "K,i,mr")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
"@
imul{l}\t{%2, %1, %0|%0, %1, %2}
(zero_extend:DI
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:SI 2 "general_operand" "K,i,mr"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"@
[(parallel [(set (match_operand:HI 0 "register_operand" "")
(mult:HI (match_operand:HI 1 "register_operand" "")
(match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_HIMODE_MATH"
"")
[(set (match_operand:HI 0 "register_operand" "=r,r,r")
(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:HI 2 "general_operand" "K,i,mr")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
"@
imul{w}\t{%2, %1, %0|%0, %1, %2}
[(parallel [(set (match_operand:QI 0 "register_operand" "")
(mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "register_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
"")
[(set (match_operand:QI 0 "register_operand" "=a")
(mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
(match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"mul{b}\t%2"
(match_operand:QI 1 "nonimmediate_operand" ""))
(zero_extend:HI
(match_operand:QI 2 "register_operand" ""))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
"")
[(set (match_operand:HI 0 "register_operand" "=a")
(mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
(zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"mul{b}\t%2"
[(parallel [(set (match_operand:HI 0 "register_operand" "")
(mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
(sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
"")
[(set (match_operand:HI 0 "register_operand" "=a")
(mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
(sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"imul{b}\t%2"
(match_operand:DI 1 "nonimmediate_operand" ""))
(zero_extend:TI
(match_operand:DI 2 "register_operand" ""))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT"
"")
[(set (match_operand:TI 0 "register_operand" "=A")
(mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
(zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"mul{q}\t%2"
(match_operand:SI 1 "nonimmediate_operand" ""))
(zero_extend:DI
(match_operand:SI 2 "register_operand" ""))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"!TARGET_64BIT"
"")
[(set (match_operand:DI 0 "register_operand" "=A")
(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"mul{l}\t%2"
(match_operand:DI 1 "nonimmediate_operand" ""))
(sign_extend:TI
(match_operand:DI 2 "register_operand" ""))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT"
"")
[(set (match_operand:TI 0 "register_operand" "=A")
(mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
(sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"imul{q}\t%2"
(match_operand:SI 1 "nonimmediate_operand" ""))
(sign_extend:DI
(match_operand:SI 2 "register_operand" ""))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"!TARGET_64BIT"
"")
[(set (match_operand:DI 0 "register_operand" "=A")
(mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"imul{l}\t%2"
(match_operand:DI 2 "register_operand" "")))
(const_int 64))))
(clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT"
"")
(match_operand:DI 2 "nonimmediate_operand" "rm")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=1"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"mul{q}\t%2"
(match_operand:SI 2 "register_operand" "")))
(const_int 32))))
(clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=1"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
"mul{l}\t%2"
[(set_attr "type" "imul")
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32)))))
(clobber (match_scratch:SI 3 "=1"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"mul{l}\t%2"
(match_operand:DI 2 "register_operand" "")))
(const_int 64))))
(clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT"
"")
(match_operand:DI 2 "nonimmediate_operand" "rm")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=1"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"imul{q}\t%2"
(match_operand:SI 2 "register_operand" "")))
(const_int 32))))
(clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=1"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
"imul{l}\t%2"
[(set_attr "type" "imul")
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32)))))
(clobber (match_scratch:SI 3 "=1"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"imul{l}\t%2"
[(set (match_operand:QI 0 "register_operand" "=a")
(div:QI (match_operand:HI 1 "register_operand" "0")
(match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"idiv{b}\t%2"
[(set_attr "type" "idiv")
[(set (match_operand:QI 0 "register_operand" "=a")
(udiv:QI (match_operand:HI 1 "register_operand" "0")
(match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"div{b}\t%2"
[(set_attr "type" "idiv")
(match_operand:DI 2 "nonimmediate_operand" "")))
(set (match_operand:DI 3 "register_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT"
"")
(match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
(set (match_operand:DI 1 "register_operand" "=&d,&d")
(mod:DI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
"#"
[(set_attr "type" "multi")])
(match_operand:DI 3 "nonimmediate_operand" "rm")))
(set (match_operand:DI 1 "register_operand" "=&d")
(mod:DI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
"#"
[(set_attr "type" "multi")])
(set (match_operand:DI 3 "register_operand" "=d")
(mod:DI (match_dup 1) (match_dup 2)))
(use (match_operand:DI 4 "register_operand" "3"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"idiv{q}\t%2"
[(set_attr "type" "idiv")
(match_operand:DI 2 "nonimmediate_operand" "")))
(set (match_operand:DI 3 "register_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed"
[(parallel [(set (match_dup 3)
(ashiftrt:DI (match_dup 4) (const_int 63)))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_dup 0)
(div:DI (reg:DI 0) (match_dup 2)))
(set (match_dup 3)
(mod:DI (reg:DI 0) (match_dup 2)))
(use (match_dup 3))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
/* Avoid use of cltd in favor of a mov+shift. */
if (!TARGET_USE_CLTD && !optimize_size)
(match_operand:SI 2 "nonimmediate_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
(set (match_operand:SI 1 "register_operand" "=&d,&d")
(mod:SI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!optimize_size && !TARGET_USE_CLTD"
"#"
[(set_attr "type" "multi")])
(match_operand:SI 3 "nonimmediate_operand" "rm")))
(set (match_operand:SI 1 "register_operand" "=&d")
(mod:SI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"optimize_size || TARGET_USE_CLTD"
"#"
[(set_attr "type" "multi")])
(set (match_operand:SI 3 "register_operand" "=d")
(mod:SI (match_dup 1) (match_dup 2)))
(use (match_operand:SI 4 "register_operand" "3"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"idiv{l}\t%2"
[(set_attr "type" "idiv")
(match_operand:SI 2 "nonimmediate_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(parallel [(set (match_dup 3)
(ashiftrt:SI (match_dup 4) (const_int 31)))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_dup 0)
(div:SI (reg:SI 0) (match_dup 2)))
(set (match_dup 3)
(mod:SI (reg:SI 0) (match_dup 2)))
(use (match_dup 3))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
/* Avoid use of cltd in favor of a mov+shift. */
if (!TARGET_USE_CLTD && !optimize_size)
(match_operand:HI 2 "nonimmediate_operand" "rm")))
(set (match_operand:HI 3 "register_operand" "=&d")
(mod:HI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"cwtd\;idiv{w}\t%2"
[(set_attr "type" "multi")
(match_operand:DI 2 "nonimmediate_operand" "rm")))
(set (match_operand:DI 3 "register_operand" "=&d")
(umod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"xor{q}\t%3, %3\;div{q}\t%2"
[(set_attr "type" "multi")
(set (match_operand:DI 3 "register_operand" "=d")
(umod:DI (match_dup 1) (match_dup 2)))
(use (match_dup 3))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"div{q}\t%2"
[(set_attr "type" "idiv")
(match_operand:DI 2 "nonimmediate_operand" "")))
(set (match_operand:DI 3 "register_operand" "")
(umod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 3) (const_int 0))
(parallel [(set (match_dup 0)
(set (match_dup 3)
(umod:DI (match_dup 1) (match_dup 2)))
(use (match_dup 3))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_insn "udivmodsi4"
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(set (match_operand:SI 3 "register_operand" "=&d")
(umod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"xor{l}\t%3, %3\;div{l}\t%2"
[(set_attr "type" "multi")
(set (match_operand:SI 3 "register_operand" "=d")
(umod:SI (match_dup 1) (match_dup 2)))
(use (match_dup 3))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"div{l}\t%2"
[(set_attr "type" "idiv")
(match_operand:SI 2 "nonimmediate_operand" "")))
(set (match_operand:SI 3 "register_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(set (match_dup 3) (const_int 0))
(parallel [(set (match_dup 0)
(set (match_dup 3)
(umod:SI (match_dup 1) (match_dup 2)))
(use (match_dup 3))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_expand "udivmodhi4"
(set (match_operand:HI 3 "register_operand" "")
(umod:HI (match_dup 1) (match_dup 2)))
(use (match_dup 4))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_HIMODE_MATH"
"operands[4] = gen_reg_rtx (HImode);")
(set (match_operand:HI 3 "register_operand" "=d")
(umod:HI (match_dup 1) (match_dup 2)))
(use (match_operand:HI 4 "register_operand" "3"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"div{w}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "HI")])
-;; We can not use div/idiv for double division, because it causes
+;; We cannot use div/idiv for double division, because it causes
;; "division by zero" on the overflow and that's not what we expect
;; from truncate. Because true (non truncating) double division is
;; never generated, we can't create this insn anyway.
; (set (match_operand:SI 3 "register_operand" "=d")
; (truncate:SI
; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
-; (clobber (reg:CC 17))]
+; (clobber (reg:CC FLAGS_REG))]
; ""
; "div{l}\t{%2, %0|%0, %2}"
; [(set_attr "type" "idiv")])
(set_attr "pent_pair" "uv,np,uv")])
(define_expand "testsi_ccno_1"
- [(set (reg:CCNO 17)
+ [(set (reg:CCNO FLAGS_REG)
(compare:CCNO
(and:SI (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:SI 1 "nonmemory_operand" ""))
(set_attr "pent_pair" "uv,np,uv")])
(define_expand "testqi_ccz_1"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
(match_operand:QI 1 "nonmemory_operand" ""))
(const_int 0)))]
"")
(define_insn "*testqi_1"
- [(set (reg 17)
+ [(set (reg FLAGS_REG)
(compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
(match_operand:QI 1 "general_operand" "n,n,qn,n"))
(const_int 0)))]
(set_attr "pent_pair" "uv,np,uv,np")])
(define_expand "testqi_ext_ccno_0"
- [(set (reg:CCNO 17)
+ [(set (reg:CCNO FLAGS_REG)
(compare:CCNO
(and:SI
(zero_extract:SI
(match_operand 2 "const_int_operand" ""))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)"
- [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
+ [(set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))]
{
HOST_WIDE_INT len = INTVAL (operands[1]);
HOST_WIDE_INT pos = INTVAL (operands[2]);
|| (ix86_match_ccmode (insn, CCNOmode)
&& !(INTVAL (operands[1]) & ~(127 << 8))))
&& GET_MODE (operands[0]) != QImode"
- [(set (reg:CCNO 17)
+ [(set (reg:CCNO FLAGS_REG)
(compare:CCNO
(and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
(match_dup 1))
|| (ix86_match_ccmode (insn, CCNOmode)
&& !(INTVAL (operands[1]) & ~127)))
&& GET_MODE (operands[0]) != QImode"
- [(set (reg:CCNO 17)
+ [(set (reg:CCNO FLAGS_REG)
(compare:CCNO
(and:QI (match_dup 0)
(match_dup 1))
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "x86_64_szext_general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"ix86_expand_binary_operator (AND, DImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (AND, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
(match_operand:SI 2 "general_operand" "ri,rm,L")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, SImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand 0 "register_operand" "")
(and (match_dup 0)
(const_int -65536)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (HImode, operands[0]);")
[(set (match_operand 0 "ext_register_operand" "")
(and (match_dup 0)
(const_int -256)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (QImode, operands[0]);")
[(set (match_operand 0 "ext_register_operand" "")
(and (match_dup 0)
(const_int -65281)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
[(parallel [(set (zero_extract:SI (match_dup 0)
(const_int 8)
(zero_extract:SI (match_dup 0)
(const_int 8)
(const_int 8))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (SImode, operands[0]);")
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(zero_extend:DI
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
"and{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (AND, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
(match_operand:HI 2 "general_operand" "ri,rm,L")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, HImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (AND, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "qi,qmi,ri")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, QImode, operands)"
"@
and{b}\t{%2, %0|%0, %2}
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(and:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qi,qmi")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"and{b}\t{%1, %0|%0, %1}"
(const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(const_int 8))
(zero_extend:SI
(match_operand:QI 2 "general_operand" "Qm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(const_int 8))
(zero_extend:SI
(match_operand 2 "ext_register_operand" "Q"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(match_operand 2 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"and{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
[(set (match_operand 0 "register_operand" "")
(and (match_operand 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)
(and:SI (zero_extract:SI (match_dup 1)
(const_int 8) (const_int 8))
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
[(set (match_operand 0 "register_operand" "")
(and (match_operand 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)
[(parallel [(set (strict_low_part (match_dup 0))
(and:QI (match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (QImode, operands[0]);
operands[1] = gen_lowpart (QImode, operands[1]);
operands[2] = gen_lowpart (QImode, operands[2]);")
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "x86_64_general_operand" "re,rme")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& ix86_binary_operator_ok (IOR, DImode, operands)"
"or{q}\t{%2, %0|%0, %2}"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "ri,rmi")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (IOR, SImode, operands)"
"or{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(zero_extend:DI
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
"or{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:DI 0 "register_operand" "=rm")
(ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"or{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
(match_operand:HI 2 "general_operand" "rmi,ri")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (IOR, HImode, operands)"
"or{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "qmi,qi,ri")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (IOR, QImode, operands)"
"@
or{b}\t{%2, %0|%0, %2}
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
(ior:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qmi,qi")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"or{b}\t{%1, %0|%0, %1}"
(const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_size)"
"or{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(const_int 8))
(zero_extend:SI
(match_operand:QI 2 "general_operand" "Qm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)"
"or{b}\t{%2, %h0|%h0, %2}"
(const_int 8))
(zero_extend:SI
(match_operand 2 "ext_register_operand" "Q"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)"
"or{b}\t{%2, %h0|%h0, %2}"
(zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_size)"
"ior{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
[(set (match_operand 0 "register_operand" "")
(ior (match_operand 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)
(ior:SI (zero_extract:SI (match_dup 1)
(const_int 8) (const_int 8))
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
[(set (match_operand 0 "register_operand" "")
(ior (match_operand 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)
[(parallel [(set (strict_low_part (match_dup 0))
(ior:QI (match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (QImode, operands[0]);
operands[1] = gen_lowpart (QImode, operands[1]);
operands[2] = gen_lowpart (QImode, operands[2]);")
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "x86_64_general_operand" "re,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& ix86_binary_operator_ok (XOR, DImode, operands)"
"@
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
(match_operand:SI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (XOR, SImode, operands)"
"xor{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(zero_extend:DI
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
(match_operand:SI 2 "general_operand" "rim"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
"xor{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:DI 0 "register_operand" "=r")
(xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
(match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
"xor{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
(match_operand:HI 2 "general_operand" "rmi,ri")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (XOR, HImode, operands)"
"xor{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:QI 2 "general_operand" "qmi,qi,ri")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (XOR, QImode, operands)"
"@
xor{b}\t{%2, %0|%0, %2}
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(xor:QI (match_dup 0)
(match_operand:QI 1 "general_operand" "qi,qmi")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"xor{b}\t{%1, %0|%0, %1}"
(const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_size)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(const_int 8))
(zero_extend:SI
(match_operand:QI 2 "general_operand" "Qm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)"
"xor{b}\t{%2, %h0|%h0, %2}"
(const_int 8))
(zero_extend:SI
(match_operand 2 "ext_register_operand" "Q"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)"
"xor{b}\t{%2, %h0|%h0, %2}"
(zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_size)"
"xor{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(define_expand "xorqi_cc_ext_1"
[(parallel [
- (set (reg:CCNO 17)
+ (set (reg:CCNO FLAGS_REG)
(compare:CCNO
(xor:SI
(zero_extract:SI
[(set (match_operand 0 "register_operand" "")
(xor (match_operand 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)
(xor:SI (zero_extract:SI (match_dup 1)
(const_int 8) (const_int 8))
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
[(set (match_operand 0 "register_operand" "")
(xor (match_operand 1 "general_operand" "")
(match_operand 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
&& (!TARGET_PARTIAL_REG_STALL || optimize_size)
[(parallel [(set (strict_low_part (match_dup 0))
(xor:QI (match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (QImode, operands[0]);
operands[1] = gen_lowpart (QImode, operands[1]);
operands[2] = gen_lowpart (QImode, operands[2]);")
(define_expand "negdi2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
(define_insn "*negdi2_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(neg:DI (match_operand:DI 1 "general_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
&& ix86_unary_operator_ok (NEG, DImode, operands)"
"#")
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(neg:DI (match_operand:DI 1 "general_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && reload_completed"
[(parallel
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
(set (match_dup 0) (neg:SI (match_dup 2)))])
(parallel
[(set (match_dup 1)
- (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+ (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
(match_dup 3))
(const_int 0)))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel
[(set (match_dup 1)
(neg:SI (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"split_di (operands+1, 1, operands+2, operands+3);
split_di (operands+0, 1, operands+0, operands+1);")
(define_insn "*negdi2_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
"neg{q}\t%0"
[(set_attr "type" "negnot")
;; flag being the only useful item.
(define_insn "*negdi2_cmpz_rex64"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(define_expand "negsi2"
[(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
(neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
(define_insn "*negsi2_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (NEG, SImode, operands)"
"neg{l}\t%0"
[(set_attr "type" "negnot")
(lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
(const_int 32)))
(const_int 32)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
"neg{l}\t%k0"
[(set_attr "type" "negnot")
;; flag being the only useful item.
(define_insn "*negsi2_cmpz"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(set_attr "mode" "SI")])
(define_insn "*negsi2_cmpz_zext"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (lshiftrt:DI
(neg:DI (ashift:DI
(match_operand:DI 1 "register_operand" "0")
(define_expand "neghi2"
[(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
(neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_HIMODE_MATH"
"ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
(define_insn "*neghi2_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (NEG, HImode, operands)"
"neg{w}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "HI")])
(define_insn "*neghi2_cmpz"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(define_expand "negqi2"
[(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
(neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
"ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
(define_insn "*negqi2_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (NEG, QImode, operands)"
"neg{b}\t%0"
[(set_attr "type" "negnot")
(set_attr "mode" "QI")])
(define_insn "*negqi2_cmpz"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(define_expand "negsf2"
[(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
(neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"if (TARGET_SSE)
{
(define_insn "negsf2_memory"
[(set (match_operand:SF 0 "memory_operand" "=m")
(neg:SF (match_operand:SF 1 "memory_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (NEG, SFmode, operands)"
"#")
[(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
(neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
(use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE
&& (reload_in_progress || reload_completed
|| (register_operand (operands[0], VOIDmode)
[(set (match_operand:SF 0 "memory_operand" "")
(neg:SF (match_operand:SF 1 "memory_operand" "")))
(use (match_operand:SF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
[(parallel [(set (match_dup 0)
(neg:SF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(neg:SF (match_operand:SF 1 "register_operand" "")))
(use (match_operand:V4SF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && !SSE_REG_P (operands[0])"
[(parallel [(set (match_dup 0)
(neg:SF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(neg:SF (match_operand:SF 1 "register_operand" "")))
(use (match_operand:V4SF 2 "nonimmediate_operand" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 0)
(xor:V4SF (match_dup 1)
(define_insn "*negsf2_if"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
(neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && !TARGET_SSE
&& ix86_unary_operator_ok (NEG, SFmode, operands)"
"#")
(define_split
[(set (match_operand:SF 0 "fp_register_operand" "")
(neg:SF (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(neg:SF (match_dup 1)))]
(define_split
[(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
(neg:SF (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[1] = gen_int_mode (0x80000000, SImode);
operands[0] = gen_lowpart (SImode, operands[0]);")
(define_split
[(set (match_operand 0 "memory_operand" "")
(neg (match_operand 1 "memory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
int size = GET_MODE_SIZE (GET_MODE (operands[1]));
(define_expand "negdf2"
[(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
(neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"if (TARGET_SSE2)
{
(define_insn "negdf2_memory"
[(set (match_operand:DF 0 "memory_operand" "=m")
(neg:DF (match_operand:DF 1 "memory_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (NEG, DFmode, operands)"
"#")
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
(use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_SSE2
&& (reload_in_progress || reload_completed
|| (register_operand (operands[0], VOIDmode)
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
(use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_SSE2
&& (reload_in_progress || reload_completed
|| (register_operand (operands[0], VOIDmode)
[(set (match_operand:DF 0 "memory_operand" "")
(neg:DF (match_operand:DF 1 "memory_operand" "")))
(use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
[(parallel [(set (match_dup 0)
(neg:DF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(neg:DF (match_operand:DF 1 "register_operand" "")))
(use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && !SSE_REG_P (operands[0])
&& (!TARGET_64BIT || FP_REG_P (operands[0]))"
[(parallel [(set (match_dup 0)
(neg:DF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(neg:DF (match_operand:DF 1 "register_operand" "")))
(use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
[(parallel [(set (match_dup 0)
(xor:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (DImode, operands[0]);
operands[1] = gen_lowpart (DImode, operands[1]);
operands[2] = gen_lowpart (DImode, operands[2]);")
[(set (match_operand:DF 0 "register_operand" "")
(neg:DF (match_operand:DF 1 "register_operand" "")))
(use (match_operand:V2DF 2 "nonimmediate_operand" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 0)
(xor:V2DF (match_dup 1)
(define_insn "*negdf2_if"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_80387
&& ix86_unary_operator_ok (NEG, DFmode, operands)"
"#")
(define_insn "*negdf2_if_rex64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_80387
&& ix86_unary_operator_ok (NEG, DFmode, operands)"
"#")
(define_split
[(set (match_operand:DF 0 "fp_register_operand" "")
(neg:DF (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(neg:DF (match_dup 1)))]
(define_split
[(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
(neg:DF (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[4] = gen_int_mode (0x80000000, SImode);
split_di (operands+0, 1, operands+2, operands+3);")
(define_expand "negxf2"
[(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
(define_insn "*negxf2_if"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387
&& ix86_unary_operator_ok (NEG, XFmode, operands)"
"#")
(define_split
[(set (match_operand:XF 0 "fp_register_operand" "")
(neg:XF (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(neg:XF (match_dup 1)))]
(define_split
[(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
(neg:XF (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[1] = GEN_INT (0x8000);
operands[0] = gen_rtx_REG (SImode,
true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
(define_expand "abssf2"
[(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
(neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"if (TARGET_SSE)
{
(define_insn "abssf2_memory"
[(set (match_operand:SF 0 "memory_operand" "=m")
(abs:SF (match_operand:SF 1 "memory_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (ABS, SFmode, operands)"
"#")
[(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
(abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
(use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE
&& (reload_in_progress || reload_completed
|| (register_operand (operands[0], VOIDmode)
[(set (match_operand:SF 0 "memory_operand" "")
(abs:SF (match_operand:SF 1 "memory_operand" "")))
(use (match_operand:V4SF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
[(parallel [(set (match_dup 0)
(abs:SF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(abs:SF (match_operand:SF 1 "register_operand" "")))
(use (match_operand:V4SF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && !SSE_REG_P (operands[0])"
[(parallel [(set (match_dup 0)
(abs:SF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(abs:SF (match_operand:SF 1 "register_operand" "")))
(use (match_operand:V4SF 2 "nonimmediate_operand" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 0)
(and:V4SF (match_dup 1)
(define_insn "*abssf2_if"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
(abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
"#")
(define_split
[(set (match_operand:SF 0 "fp_register_operand" "")
(abs:SF (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(abs:SF (match_dup 1)))]
(define_split
[(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
(abs:SF (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[1] = gen_int_mode (~0x80000000, SImode);
operands[0] = gen_lowpart (SImode, operands[0]);")
(define_split
[(set (match_operand 0 "memory_operand" "")
(abs (match_operand 1 "memory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
int size = GET_MODE_SIZE (GET_MODE (operands[1]));
(define_expand "absdf2"
[(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
(neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"if (TARGET_SSE2)
{
(define_insn "absdf2_memory"
[(set (match_operand:DF 0 "memory_operand" "=m")
(abs:DF (match_operand:DF 1 "memory_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_unary_operator_ok (ABS, DFmode, operands)"
"#")
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
(abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
(use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_SSE2
&& (reload_in_progress || reload_completed
|| (register_operand (operands[0], VOIDmode)
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
(abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
(use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_SSE2
&& (reload_in_progress || reload_completed
|| (register_operand (operands[0], VOIDmode)
[(set (match_operand:DF 0 "memory_operand" "")
(abs:DF (match_operand:DF 1 "memory_operand" "")))
(use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
[(parallel [(set (match_dup 0)
(abs:DF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(abs:DF (match_operand:DF 1 "register_operand" "")))
(use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && !SSE_REG_P (operands[0])"
[(parallel [(set (match_dup 0)
(abs:DF (match_dup 1)))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(abs:DF (match_operand:DF 1 "register_operand" "")))
(use (match_operand:V2DF 2 "nonimmediate_operand" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 0)
(and:V2DF (match_dup 1)
(define_insn "*absdf2_if"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
(abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_80387
&& ix86_unary_operator_ok (ABS, DFmode, operands)"
"#")
(define_insn "*absdf2_if_rex64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
(abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_80387
&& ix86_unary_operator_ok (ABS, DFmode, operands)"
"#")
(define_split
[(set (match_operand:DF 0 "fp_register_operand" "")
(abs:DF (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(abs:DF (match_dup 1)))]
(define_split
[(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
(abs:DF (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[4] = gen_int_mode (~0x80000000, SImode);
split_di (operands+0, 1, operands+2, operands+3);")
(define_expand "absxf2"
[(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
"ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
(define_insn "*absxf2_if"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
(abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387
&& ix86_unary_operator_ok (ABS, XFmode, operands)"
"#")
(define_split
[(set (match_operand:XF 0 "fp_register_operand" "")
(abs:XF (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(abs:XF (match_dup 1)))]
(define_split
[(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
(abs:XF (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[1] = GEN_INT (~0x8000);
operands[0] = gen_rtx_REG (SImode,
true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
(set (match_operand:DI 0 "nonimmediate_operand" "")
(not:DI (match_dup 1)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (reg:CCNO 17)
+ [(parallel [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (xor:DI (match_dup 1) (const_int -1))
(const_int 0)))
(set (match_dup 0)
(set (match_operand:SI 0 "nonimmediate_operand" "")
(not:SI (match_dup 1)))]
"ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (reg:CCNO 17)
+ [(parallel [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (xor:SI (match_dup 1) (const_int -1))
(const_int 0)))
(set (match_dup 0)
(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (not:SI (match_dup 1))))]
"ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (reg:CCNO 17)
+ [(parallel [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (xor:SI (match_dup 1) (const_int -1))
(const_int 0)))
(set (match_dup 0)
(set (match_operand:HI 0 "nonimmediate_operand" "")
(not:HI (match_dup 1)))]
"ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (reg:CCNO 17)
+ [(parallel [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (xor:HI (match_dup 1) (const_int -1))
(const_int 0)))
(set (match_dup 0)
(set (match_operand:QI 0 "nonimmediate_operand" "")
(not:QI (match_dup 1)))]
"ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (reg:CCNO 17)
+ [(parallel [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (xor:QI (match_dup 1) (const_int -1))
(const_int 0)))
(set (match_dup 0)
;; than 31.
(define_expand "ashldi3"
- [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
- (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))])]
+ [(set (match_operand:DI 0 "shiftdi_operand" "")
+ (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
-{
- if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
- {
- emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
- DONE;
- }
- ix86_expand_binary_operator (ASHIFT, DImode, operands);
- DONE;
-})
+ "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
(define_insn "*ashldi3_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
(match_operand:QI 2 "nonmemory_operand" "cJ,M")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "register_operand" "")
(match_operand:QI 2 "immediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(set (match_dup 0)
(const_string "ishift")))
(set_attr "mode" "DI")])
-(define_insn "ashldi3_1"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ashift:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "Jc")))
- (clobber (match_scratch:SI 3 "=&r"))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && TARGET_CMOVE"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*ashldi3_2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ashift:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "Jc")))
- (clobber (reg:CC 17))]
+(define_insn "*ashldi3_1"
+ [(set (match_operand:DI 0 "register_operand" "=&r,r")
+ (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
+ (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"#"
[(set_attr "type" "multi")])
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
+;; By default we don't ask for a scratch register, because when DImode
+;; values are manipulated, registers are already at a premium. But if
+;; we have one handy, we won't turn it away.
+(define_peephole2
+ [(match_scratch:SI 3 "r")
+ (parallel [(set (match_operand:DI 0 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])
+ (match_dup 3)]
+ "!TARGET_64BIT && TARGET_CMOVE"
[(const_int 0)]
"ix86_split_ashldi (operands, operands[3]); DONE;")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && reload_completed"
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
[(const_int 0)]
"ix86_split_ashldi (operands, NULL_RTX); DONE;")
(match_operand:QI 2 "nonmemory_operand" "I,c"))
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
(minus:QI (const_int 32) (match_dup 2)))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"@
shld{l}\t{%2, %1, %0|%0, %1, %2}
(set_attr "athlon_decode" "vector")])
(define_expand "x86_shift_adj_1"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
(const_int 32))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "")
- (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
+ (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
(match_operand:SI 1 "register_operand" "")
(match_dup 0)))
(set (match_dup 1)
- (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
+ (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
(match_operand:SI 3 "register_operand" "r")
(match_dup 1)))]
"TARGET_CMOVE"
JUMP_LABEL (tmp) = label;
emit_move_insn (operands[0], operands[1]);
- emit_move_insn (operands[1], const0_rtx);
+ ix86_expand_clear (operands[1]);
emit_label (label);
LABEL_NUSES (label) = 1;
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
(match_operand:QI 2 "nonmemory_operand" "cI,M")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFT, SImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand 0 "register_operand" "")
(ashift (match_operand 1 "index_register_operand" "")
(match_operand:QI 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(const_int 0)]
[(set (match_operand 0 "register_operand" "")
(ashift (match_operand 1 "register_operand" "")
(match_operand:QI 2 "const_int_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(const_int 0)]
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
(match_operand:QI 2 "nonmemory_operand" "cI,M"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
{
switch (get_attr_type (insn))
[(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI (ashift (match_operand 1 "register_operand" "")
(match_operand:QI 2 "const_int_operand" ""))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
[(set (match_dup 0) (zero_extend:DI
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
(match_operand:QI 2 "nonmemory_operand" "cI,M")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
{
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "cI")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
{
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
(match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
{
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "cI,cI")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
{
;; See comment above `ashldi3' about how this works.
(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))])]
+ [(set (match_operand:DI 0 "shiftdi_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
-{
- if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
- {
- emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
- DONE;
- }
- ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
- DONE;
-})
+ "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
-(define_insn "ashrdi3_63_rex64"
+(define_insn "*ashrdi3_63_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
(match_operand:DI 2 "const_int_operand" "i,i")))
- (clobber (reg:CC 17))]
- "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && INTVAL (operands[2]) == 63
+ && (TARGET_USE_CLTD || optimize_size)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"@
{cqto|cqo}
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"sar{q}\t%0"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "J,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"@
sar{q}\t{%2, %0|%0, %2}
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
-
-(define_insn "ashrdi3_1"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "Jc")))
- (clobber (match_scratch:SI 3 "=&r"))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && TARGET_CMOVE"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*ashrdi3_2"
+(define_insn "*ashrdi3_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "Jc")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"#"
[(set_attr "type" "multi")])
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
+;; By default we don't ask for a scratch register, because when DImode
+;; values are manipulated, registers are already at a premium. But if
+;; we have one handy, we won't turn it away.
+(define_peephole2
+ [(match_scratch:SI 3 "r")
+ (parallel [(set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])
+ (match_dup 3)]
+ "!TARGET_64BIT && TARGET_CMOVE"
[(const_int 0)]
"ix86_split_ashrdi (operands, operands[3]); DONE;")
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && reload_completed"
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
[(const_int 0)]
"ix86_split_ashrdi (operands, NULL_RTX); DONE;")
(match_operand:QI 2 "nonmemory_operand" "I,c"))
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
(minus:QI (const_int 32) (match_dup 2)))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"@
shrd{l}\t{%2, %1, %0|%0, %1, %2}
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
(match_operand:SI 2 "const_int_operand" "i,i")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
[(set (match_operand:DI 0 "register_operand" "=*d,r")
(zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
(match_operand:SI 2 "const_int_operand" "i,i"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
&& INTVAL (operands[2]) == 31
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"sar{l}\t%0"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const1_operand" ""))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"sar{l}\t%k0"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
sar{l}\t{%2, %0|%0, %2}
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
sar{l}\t{%2, %k0|%k0, %2}
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"sar{w}\t%0"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"@
sar{w}\t{%2, %0|%0, %2}
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"sar{b}\t%0"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(ashiftrt:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
&& (! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"@
sar{b}\t{%2, %0|%0, %2}
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
(ashiftrt:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
;; See comment above `ashldi3' about how this works.
(define_expand "lshrdi3"
- [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))])]
+ [(set (match_operand:DI 0 "shiftdi_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
-{
- if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
- {
- emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
- DONE;
- }
- ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
- DONE;
-})
+ "ix86_expand_binary_operator (LSHIFTRT, DImode, operands); DONE;")
(define_insn "*lshrdi3_1_one_bit_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{q}\t%0"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "J,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
shr{q}\t{%2, %0|%0, %2}
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
-(define_insn "lshrdi3_1"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "Jc")))
- (clobber (match_scratch:SI 3 "=&r"))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && TARGET_CMOVE"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*lshrdi3_2"
+(define_insn "*lshrdi3_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "Jc")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"#"
[(set_attr "type" "multi")])
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
+;; By default we don't ask for a scratch register, because when DImode
+;; values are manipulated, registers are already at a premium. But if
+;; we have one handy, we won't turn it away.
+(define_peephole2
+ [(match_scratch:SI 3 "r")
+ (parallel [(set (match_operand:DI 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])
+ (match_dup 3)]
+ "!TARGET_64BIT && TARGET_CMOVE"
[(const_int 0)]
"ix86_split_lshrdi (operands, operands[3]); DONE;")
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
- "!TARGET_64BIT && reload_completed"
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
[(const_int 0)]
"ix86_split_lshrdi (operands, NULL_RTX); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{l}\t%0"
[(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{l}\t%k0"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
shr{l}\t{%2, %0|%0, %2}
(zero_extend:DI
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
shr{l}\t{%2, %k0|%k0, %2}
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{w}\t%0"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"@
shr{w}\t{%2, %0|%0, %2}
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{b}\t%0"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(lshiftrt:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"shr{b}\t%0"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"@
shr{b}\t{%2, %0|%0, %2}
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
(lshiftrt:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{q}\t%0"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "e,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
"@
rol{q}\t{%2, %0|%0, %2}
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATE, SImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{l}\t%0"
(zero_extend:DI
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const1_operand" ""))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{l}\t%k0"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATE, SImode, operands)"
"@
rol{l}\t{%2, %0|%0, %2}
(zero_extend:DI
(rotate:SI (match_operand:SI 1 "register_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
"@
rol{l}\t{%2, %k0|%k0, %2}
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATE, HImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{w}\t%0"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATE, HImode, operands)"
"@
rol{w}\t{%2, %0|%0, %2}
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(rotate:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{b}\t%0"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATE, QImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"rol{b}\t%0"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
(rotate:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATE, QImode, operands)"
"@
rol{b}\t{%2, %0|%0, %2}
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{q}\t%0"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "J,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
"@
ror{q}\t{%2, %0|%0, %2}
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATERT, SImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{l}\t%0"
(zero_extend:DI
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:QI 2 "const1_operand" ""))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{l}\t%k0"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATERT, SImode, operands)"
"@
ror{l}\t{%2, %0|%0, %2}
(zero_extend:DI
(rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
"@
ror{l}\t{%2, %k0|%k0, %2}
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATERT, HImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{w}\t%0"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATERT, HImode, operands)"
"@
ror{w}\t{%2, %0|%0, %2}
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATERT, QImode, operands)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{b}\t%0"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(rotatert:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (TARGET_SHIFT1 || optimize_size)"
"ror{b}\t%0"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ROTATERT, QImode, operands)"
"@
ror{b}\t{%2, %0|%0, %2}
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
(rotatert:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"(! TARGET_PARTIAL_REG_STALL || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
})
(define_expand "insv"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
- (match_operand:SI 1 "immediate_operand" "")
- (match_operand:SI 2 "immediate_operand" ""))
- (match_operand:SI 3 "register_operand" ""))]
+ [(set (zero_extract (match_operand 0 "ext_register_operand" "")
+ (match_operand 1 "immediate_operand" "")
+ (match_operand 2 "immediate_operand" ""))
+ (match_operand 3 "register_operand" ""))]
""
{
/* Handle extractions from %ah et al. */
matches the predicate, so check it again here. */
if (! register_operand (operands[0], VOIDmode))
FAIL;
+
+ if (TARGET_64BIT)
+ emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
+ else
+ emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
+
+ DONE;
})
;; %%% bts, btr, btc, bt.
(define_expand "seq"
[(set (match_operand:QI 0 "register_operand" "")
- (eq:QI (reg:CC 17) (const_int 0)))]
+ (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
(define_expand "sne"
[(set (match_operand:QI 0 "register_operand" "")
- (ne:QI (reg:CC 17) (const_int 0)))]
+ (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
(define_expand "sgt"
[(set (match_operand:QI 0 "register_operand" "")
- (gt:QI (reg:CC 17) (const_int 0)))]
+ (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
(define_expand "sgtu"
[(set (match_operand:QI 0 "register_operand" "")
- (gtu:QI (reg:CC 17) (const_int 0)))]
+ (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
(define_expand "slt"
[(set (match_operand:QI 0 "register_operand" "")
- (lt:QI (reg:CC 17) (const_int 0)))]
+ (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
(define_expand "sltu"
[(set (match_operand:QI 0 "register_operand" "")
- (ltu:QI (reg:CC 17) (const_int 0)))]
+ (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
(define_expand "sge"
[(set (match_operand:QI 0 "register_operand" "")
- (ge:QI (reg:CC 17) (const_int 0)))]
+ (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
(define_expand "sgeu"
[(set (match_operand:QI 0 "register_operand" "")
- (geu:QI (reg:CC 17) (const_int 0)))]
+ (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
(define_expand "sle"
[(set (match_operand:QI 0 "register_operand" "")
- (le:QI (reg:CC 17) (const_int 0)))]
+ (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
(define_expand "sleu"
[(set (match_operand:QI 0 "register_operand" "")
- (leu:QI (reg:CC 17) (const_int 0)))]
+ (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
""
"if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
(define_expand "sunordered"
[(set (match_operand:QI 0 "register_operand" "")
- (unordered:QI (reg:CC 17) (const_int 0)))]
+ (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
(define_expand "sordered"
[(set (match_operand:QI 0 "register_operand" "")
- (ordered:QI (reg:CC 17) (const_int 0)))]
+ (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387"
"if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
(define_expand "suneq"
[(set (match_operand:QI 0 "register_operand" "")
- (uneq:QI (reg:CC 17) (const_int 0)))]
+ (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
(define_expand "sunge"
[(set (match_operand:QI 0 "register_operand" "")
- (unge:QI (reg:CC 17) (const_int 0)))]
+ (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
(define_expand "sungt"
[(set (match_operand:QI 0 "register_operand" "")
- (ungt:QI (reg:CC 17) (const_int 0)))]
+ (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
(define_expand "sunle"
[(set (match_operand:QI 0 "register_operand" "")
- (unle:QI (reg:CC 17) (const_int 0)))]
+ (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
(define_expand "sunlt"
[(set (match_operand:QI 0 "register_operand" "")
- (unlt:QI (reg:CC 17) (const_int 0)))]
+ (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
(define_expand "sltgt"
[(set (match_operand:QI 0 "register_operand" "")
- (ltgt:QI (reg:CC 17) (const_int 0)))]
+ (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
"TARGET_80387 || TARGET_SSE"
"if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
[(set_attr "type" "setcc")
(set_attr "mode" "QI")])
-(define_insn "setcc_2"
+(define_insn "*setcc_2"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(match_operator:QI 1 "ix86_comparison_operator"
[(reg 17) (const_int 0)]))]
(match_operand 2 "register_operand" "f")])
(label_ref (match_operand 3 "" ""))
(pc)))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))]
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))]
"TARGET_CMOVE && TARGET_80387
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& FLOAT_MODE_P (GET_MODE (operands[1]))
(match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
(label_ref (match_operand 3 "" ""))
(pc)))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))]
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))]
"TARGET_80387
&& SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
(match_operand 2 "nonimmediate_operand" "xm")])
(label_ref (match_operand 3 "" ""))
(pc)))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))]
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))]
"SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
&& ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
(match_operand 2 "register_operand" "f")])
(pc)
(label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))]
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))]
"TARGET_CMOVE && TARGET_80387
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& FLOAT_MODE_P (GET_MODE (operands[1]))
(match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
(pc)
(label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))]
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))]
"TARGET_80387
&& SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
(match_operand 2 "nonimmediate_operand" "xm")])
(pc)
(label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))]
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))]
"SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
&& ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
(match_operand 2 "nonimmediate_operand" "fm")])
(label_ref (match_operand 3 "" ""))
(pc)))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
"TARGET_80387
&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
(match_operand 2 "nonimmediate_operand" "fm")])
(pc)
(label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
"TARGET_80387
&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
(match_operand 2 "register_operand" "f")])
(label_ref (match_operand 3 "" ""))
(pc)))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
"TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1]))
(match_operand 2 "register_operand" "f")])
(pc)
(label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
"TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1]))
&& ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
"#")
-(define_split
+(define_insn "*fp_jcc_7"
+ [(set (pc)
+ (if_then_else (match_operator 0 "comparison_operator"
+ [(match_operand 1 "register_operand" "f")
+ (match_operand 2 "const_double_operand" "C")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))
+ (clobber (match_scratch:HI 4 "=a"))]
+ "TARGET_80387
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && operands[2] == CONST0_RTX (GET_MODE (operands[1]))
+ && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
+ && SELECT_CC_MODE (GET_CODE (operands[0]),
+ operands[1], operands[2]) == CCFPmode
+ && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ "#")
+
+(define_split
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(match_operand 1 "register_operand" "")
(match_operand 2 "nonimmediate_operand" "")])
(match_operand 3 "" "")
(match_operand 4 "" "")))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))]
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))]
"reload_completed"
[(const_int 0)]
{
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(match_operand 1 "register_operand" "")
- (match_operand 2 "nonimmediate_operand" "")])
+ (match_operand 2 "general_operand" "")])
(match_operand 3 "" "")
(match_operand 4 "" "")))
- (clobber (reg:CCFP 18))
- (clobber (reg:CCFP 17))
+ (clobber (reg:CCFP FPSR_REG))
+ (clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 5 "=a"))]
"reload_completed"
- [(set (pc)
- (if_then_else (match_dup 6)
- (match_dup 3)
- (match_dup 4)))]
+ [(const_int 0)]
{
ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
operands[3], operands[4], operands[5]);
(plus:SI (match_dup 1)
(const_int -1)))
(clobber (match_scratch:SI 3 "=X,X,r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_USE_LOOP
&& (reload_in_progress || reload_completed
|| register_operand (operands[2], VOIDmode))"
(plus:SI (match_dup 1)
(const_int -1)))
(clobber (match_scratch:SI 2 ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_USE_LOOP
&& reload_completed
&& REGNO (operands[1]) != 2"
- [(parallel [(set (reg:CCZ 17)
+ [(parallel [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (plus:SI (match_dup 1) (const_int -1))
(const_int 0)))
(set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
- (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
(match_dup 0)
(pc)))]
"")
(plus:SI (match_dup 1)
(const_int -1)))
(clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_USE_LOOP
&& reload_completed
&& (! REG_P (operands[2])
|| ! rtx_equal_p (operands[1], operands[2]))"
[(set (match_dup 3) (match_dup 1))
- (parallel [(set (reg:CCZ 17)
+ (parallel [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (plus:SI (match_dup 3) (const_int -1))
(const_int 0)))
(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
(set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
+ (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
(match_dup 0)
(pc)))]
"")
[(reg 17) (const_int 0)]))
(parallel [(set (match_operand 3 "q_regs_operand" "")
(zero_extend (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
&& ! reg_overlap_mentioned_p (operands[3], operands[0])"
(define_expand "call_pop"
[(parallel [(call (match_operand:QI 0 "" "")
(match_operand:SI 1 "" ""))
- (set (reg:SI 7)
- (plus:SI (reg:SI 7)
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "" "")))])]
"!TARGET_64BIT"
{
(define_insn "*call_pop_0"
[(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
(match_operand:SI 1 "" ""))
- (set (reg:SI 7) (plus:SI (reg:SI 7)
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "")))]
"!TARGET_64BIT"
{
(define_insn "*call_pop_1"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
(match_operand:SI 1 "" ""))
- (set (reg:SI 7) (plus:SI (reg:SI 7)
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
"!TARGET_64BIT"
{
(match_operand 1 "" ""))]
"!SIBLING_CALL_P (insn) && !TARGET_64BIT"
{
- if (constant_call_address_operand (operands[0], QImode))
+ if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
return "call\t%A0";
}
(match_operand 1 "" ""))]
"SIBLING_CALL_P (insn) && !TARGET_64BIT"
{
- if (constant_call_address_operand (operands[0], QImode))
+ if (constant_call_address_operand (operands[0], Pmode))
return "jmp\t%P0";
return "jmp\t%A0";
}
(match_operand 1 "" ""))]
"!SIBLING_CALL_P (insn) && TARGET_64BIT"
{
- if (constant_call_address_operand (operands[0], QImode))
+ if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
return "call\t%A0";
}
[(parallel [(set (match_operand 0 "" "")
(call (match_operand:QI 1 "" "")
(match_operand:SI 2 "" "")))
- (set (reg:SI 7)
- (plus:SI (reg:SI 7)
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
(match_operand:SI 4 "" "")))])]
"!TARGET_64BIT"
{
(define_insn "set_got"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
{ return output_set_got (operands[0]); }
[(set_attr "type" "multi")
emit_move_insn (tmp, ra);
if (Pmode == SImode)
- emit_insn (gen_eh_return_si (sa));
+ emit_jump_insn (gen_eh_return_si (sa));
else
- emit_insn (gen_eh_return_di (sa));
+ emit_jump_insn (gen_eh_return_di (sa));
emit_barrier ();
DONE;
})
(define_insn_and_split "eh_return_si"
- [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
- UNSPECV_EH_RETURN)]
+ [(set (pc)
+ (unspec [(match_operand:SI 0 "register_operand" "c")]
+ UNSPEC_EH_RETURN))]
"!TARGET_64BIT"
"#"
"reload_completed"
"ix86_expand_epilogue (2); DONE;")
(define_insn_and_split "eh_return_di"
- [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
- UNSPECV_EH_RETURN)]
+ [(set (pc)
+ (unspec [(match_operand:DI 0 "register_operand" "c")]
+ UNSPEC_EH_RETURN))]
"TARGET_64BIT"
"#"
"reload_completed"
"ix86_expand_epilogue (2); DONE;")
(define_insn "leave"
- [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
- (set (reg:SI 6) (mem:SI (reg:SI 6)))
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
+ (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
(clobber (mem:BLK (scratch)))]
"!TARGET_64BIT"
"leave"
[(set_attr "type" "leave")])
(define_insn "leave_rex64"
- [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
- (set (reg:DI 6) (mem:DI (reg:DI 6)))
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
+ (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
(clobber (mem:BLK (scratch)))]
"TARGET_64BIT"
"leave"
[(set (match_operand:SI 0 "register_operand" "")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
(clobber (match_scratch:SI 2 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
[(set (match_operand:SI 0 "register_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&r"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_CMOVE"
"#"
"&& reload_completed"
[(set (match_dup 2) (const_int -1))
- (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
+ (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
(set (match_dup 0) (ctz:SI (match_dup 1)))])
(set (match_dup 0) (if_then_else:SI
- (eq (reg:CCZ 17) (const_int 0))
+ (eq (reg:CCZ FLAGS_REG) (const_int 0))
(match_dup 2)
(match_dup 0)))
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_insn_and_split "*ffs_no_cmove"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&q"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"#"
"reload_completed"
- [(parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
+ [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
(set (match_dup 0) (ctz:SI (match_dup 1)))])
(set (strict_low_part (match_dup 3))
- (eq:QI (reg:CCZ 17) (const_int 0)))
+ (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
(parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
operands[3] = gen_lowpart (QImode, operands[2]);
ix86_expand_clear (operands[2]);
})
(define_insn "*ffssi_1"
- [(set (reg:CCZ 17)
+ [(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
"bsf{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
+(define_expand "ffsdi2"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
+ (clobber (match_scratch:DI 2 ""))
+ (clobber (reg:CC 17))])]
+ "TARGET_64BIT && TARGET_CMOVE"
+ "")
+
+(define_insn_and_split "*ffs_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
+ (clobber (match_scratch:DI 2 "=&r"))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT && TARGET_CMOVE"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (const_int -1))
+ (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
+ (set (match_dup 0) (ctz:DI (match_dup 1)))])
+ (set (match_dup 0) (if_then_else:DI
+ (eq (reg:CCZ 17) (const_int 0))
+ (match_dup 2)
+ (match_dup 0)))
+ (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
+ (clobber (reg:CC 17))])]
+ "")
+
+(define_insn "*ffsdi_1"
+ [(set (reg:CCZ 17)
+ (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (ctz:DI (match_dup 1)))]
+ "TARGET_64BIT"
+ "bsf{q}\t{%1, %0|%0, %1}"
+ [(set_attr "prefix_0f" "1")])
+
(define_insn "ctzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"bsf{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
+(define_insn "ctzdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT"
+ "bsf{q}\t{%1, %0|%0, %1}"
+ [(set_attr "prefix_0f" "1")])
+
(define_expand "clzsi2"
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(minus:SI (const_int 31)
(clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel
[(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (const_int 31)
(clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"bsr{l}\t{%1, %0|%0, %1}"
[(set_attr "prefix_0f" "1")])
+
+(define_expand "clzdi2"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (minus:DI (const_int 63)
+ (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
+ (clobber (reg:CC 17))])
+ (parallel
+ [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
+ (clobber (reg:CC 17))])]
+ "TARGET_64BIT"
+ "")
+
+(define_insn "*bsr_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (minus:DI (const_int 63)
+ (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
+ (clobber (reg:CC 17))]
+ "TARGET_64BIT"
+ "bsr{q}\t{%1, %0|%0, %1}"
+ [(set_attr "prefix_0f" "1")])
\f
;; Thread-local storage patterns for ELF.
;;
UNSPEC_TLS_GD))
(clobber (match_scratch:SI 4 "=d"))
(clobber (match_scratch:SI 5 "=c"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_GNU_TLS"
"lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
[(set_attr "type" "multi")
UNSPEC_TLS_GD))
(clobber (match_scratch:SI 4 "=d"))
(clobber (match_scratch:SI 5 "=c"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_SUN_TLS"
"lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
UNSPEC_TLS_GD))
(clobber (match_scratch:SI 4 ""))
(clobber (match_scratch:SI 5 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
{
if (flag_pic)
UNSPEC_TLS_LD_BASE))
(clobber (match_scratch:SI 3 "=d"))
(clobber (match_scratch:SI 4 "=c"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_GNU_TLS"
"lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
[(set_attr "type" "multi")
UNSPEC_TLS_LD_BASE))
(clobber (match_scratch:SI 3 "=d"))
(clobber (match_scratch:SI 4 "=c"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_SUN_TLS"
"lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
UNSPEC_TLS_LD_BASE))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
{
if (flag_pic)
UNSPEC_DTPOFF))))
(clobber (match_scratch:SI 4 "=d"))
(clobber (match_scratch:SI 5 "=c"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"#"
""
UNSPEC_TLS_GD))
(clobber (match_dup 4))
(clobber (match_dup 5))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
;; Load and add the thread base pointer from %gs:0.
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
(match_operand:SI 1 "register_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
[(set_attr "type" "alu")
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
(match_operand:DI 1 "register_operand" "0")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
[(set_attr "type" "alu")
(set_attr "mode" "XF")
(set_attr "athlon_decode" "direct")])
+(define_insn "fpremxf4"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "0")
+ (match_operand:XF 3 "register_operand" "1")]
+ UNSPEC_FPREM_F))
+ (set (match_operand:XF 1 "register_operand" "=u")
+ (unspec:XF [(match_dup 2) (match_dup 3)]
+ UNSPEC_FPREM_U))
+ (set (reg:CCFP FPSR_REG)
+ (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fprem"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "XF")])
+
+(define_expand "fmodsf3"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))
+ (use (match_operand:SF 2 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx label = gen_label_rtx ();
+
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = gen_reg_rtx (XFmode);
+
+ emit_insn(gen_extendsfxf2 (op1, operands[1]));
+ emit_insn(gen_extendsfxf2 (op2, operands[2]));
+
+ emit_label (label);
+
+ emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
+ ix86_emit_fp_unordered_jump (label);
+
+ emit_insn (gen_truncxfsf2_noop (operands[0], op1));
+ DONE;
+})
+
+(define_expand "fmoddf3"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))
+ (use (match_operand:DF 2 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx label = gen_label_rtx ();
+
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ emit_insn (gen_extenddfxf2 (op2, operands[2]));
+
+ emit_label (label);
+
+ emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
+ ix86_emit_fp_unordered_jump (label);
+
+ emit_insn (gen_truncxfdf2_noop (operands[0], op1));
+ DONE;
+})
+
+(define_expand "fmodxf3"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))
+ (use (match_operand:XF 2 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx label = gen_label_rtx ();
+
+ emit_label (label);
+
+ emit_insn (gen_fpremxf4 (operands[1], operands[2],
+ operands[1], operands[2]));
+ ix86_emit_fp_unordered_jump (label);
+
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
+(define_insn "fprem1xf4"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "0")
+ (match_operand:XF 3 "register_operand" "1")]
+ UNSPEC_FPREM1_F))
+ (set (match_operand:XF 1 "register_operand" "=u")
+ (unspec:XF [(match_dup 2) (match_dup 3)]
+ UNSPEC_FPREM1_U))
+ (set (reg:CCFP FPSR_REG)
+ (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fprem1"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "XF")])
+
+(define_expand "dremsf3"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))
+ (use (match_operand:SF 2 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx label = gen_label_rtx ();
+
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = gen_reg_rtx (XFmode);
+
+ emit_insn(gen_extendsfxf2 (op1, operands[1]));
+ emit_insn(gen_extendsfxf2 (op2, operands[2]));
+
+ emit_label (label);
+
+ emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
+ ix86_emit_fp_unordered_jump (label);
+
+ emit_insn (gen_truncxfsf2_noop (operands[0], op1));
+ DONE;
+})
+
+(define_expand "dremdf3"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))
+ (use (match_operand:DF 2 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx label = gen_label_rtx ();
+
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ emit_insn (gen_extenddfxf2 (op2, operands[2]));
+
+ emit_label (label);
+
+ emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
+ ix86_emit_fp_unordered_jump (label);
+
+ emit_insn (gen_truncxfdf2_noop (operands[0], op1));
+ DONE;
+})
+
+(define_expand "dremxf3"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))
+ (use (match_operand:XF 2 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx label = gen_label_rtx ();
+
+ emit_label (label);
+
+ emit_insn (gen_fprem1xf4 (operands[1], operands[2],
+ operands[1], operands[2]));
+ ix86_emit_fp_unordered_jump (label);
+
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
(define_insn "*sindf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
;; With sincos pattern defined, sin and cos builtin function will be
;; expanded to sincos pattern with one of its outputs left unused.
;; Cse pass will detected, if two sincos patterns can be combined,
-;; otherwise sincos pattern will be splitted back to sin or cos pattern,
+;; otherwise sincos pattern will be split back to sin or cos pattern,
;; depending on the unused output.
(define_insn "sincosdf3"
[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
"")
+(define_insn "*tandf3_1"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:DF 1 "register_operand" "=u")
+ (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fptan"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "DF")])
+
+;; optimize sequence: fptan
+;; fstp %st(0)
+;; fld1
+;; into fptan insn.
+
+(define_peephole2
+ [(parallel[(set (match_operand:DF 0 "register_operand" "")
+ (unspec:DF [(match_operand:DF 2 "register_operand" "")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:DF 1 "register_operand" "")
+ (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])
+ (set (match_dup 0)
+ (match_operand:DF 3 "immediate_operand" ""))]
+ "standard_80387_constant_p (operands[3]) == 2"
+ [(parallel[(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_TAN_ONE))
+ (set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])]
+ "")
+
+(define_expand "tandf2"
+ [(parallel [(set (match_dup 2)
+ (unspec:DF [(match_operand:DF 1 "register_operand" "")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:DF 0 "register_operand" "")
+ (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (DFmode);
+})
+
+(define_insn "*tansf3_1"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:SF 1 "register_operand" "=u")
+ (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fptan"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "SF")])
+
+;; optimize sequence: fptan
+;; fstp %st(0)
+;; fld1
+;; into fptan insn.
+
+(define_peephole2
+ [(parallel[(set (match_operand:SF 0 "register_operand" "")
+ (unspec:SF [(match_operand:SF 2 "register_operand" "")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:SF 1 "register_operand" "")
+ (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])
+ (set (match_dup 0)
+ (match_operand:SF 3 "immediate_operand" ""))]
+ "standard_80387_constant_p (operands[3]) == 2"
+ [(parallel[(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_TAN_ONE))
+ (set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])]
+ "")
+
+(define_expand "tansf2"
+ [(parallel [(set (match_dup 2)
+ (unspec:SF [(match_operand:SF 1 "register_operand" "")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:SF 0 "register_operand" "")
+ (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (SFmode);
+})
+
+(define_insn "*tanxf3_1"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:XF 1 "register_operand" "=u")
+ (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fptan"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "XF")])
+
+;; optimize sequence: fptan
+;; fstp %st(0)
+;; fld1
+;; into fptan insn.
+
+(define_peephole2
+ [(parallel[(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:XF 1 "register_operand" "")
+ (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])
+ (set (match_dup 0)
+ (match_operand:XF 3 "immediate_operand" ""))]
+ "standard_80387_constant_p (operands[3]) == 2"
+ [(parallel[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_TAN_ONE))
+ (set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])]
+ "")
+
+(define_expand "tanxf2"
+ [(parallel [(set (match_dup 2)
+ (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_TAN_ONE))
+ (set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (XFmode);
+})
+
(define_insn "atan2df3_1"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")
DONE;
})
+(define_expand "atandf2"
+ [(parallel [(set (match_operand:DF 0 "register_operand" "")
+ (unspec:DF [(match_dup 2)
+ (match_operand:DF 1 "register_operand" "")]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:DF 3 ""))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (DFmode);
+ emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
+})
+
(define_insn "atan2sf3_1"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0")
DONE;
})
-(define_insn "atan2xf3_1"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 2 "register_operand" "0")
- (match_operand:XF 1 "register_operand" "u")]
+(define_expand "atansf2"
+ [(parallel [(set (match_operand:SF 0 "register_operand" "")
+ (unspec:SF [(match_dup 2)
+ (match_operand:SF 1 "register_operand" "")]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:SF 3 ""))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (SFmode);
+ emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
+})
+
+(define_insn "atan2xf3_1"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "0")
+ (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
DONE;
})
-(define_insn "*fyl2x_sfxf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (unspec:SF [(match_operand:SF 2 "register_operand" "0")
- (match_operand:XF 1 "register_operand" "u")]
- UNSPEC_FYL2X))
- (clobber (match_scratch:SF 3 "=1"))]
+(define_expand "atanxf2"
+ [(parallel [(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_dup 2)
+ (match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:XF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
- "fyl2x"
- [(set_attr "type" "fpspc")
- (set_attr "mode" "SF")])
+{
+ operands[2] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
+})
-(define_insn "*fyl2x_dfxf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (unspec:DF [(match_operand:DF 2 "register_operand" "0")
- (match_operand:XF 1 "register_operand" "u")]
- UNSPEC_FYL2X))
- (clobber (match_scratch:DF 3 "=1"))]
+(define_expand "asindf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
+ (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
+ (set (match_dup 6) (sqrt:XF (match_dup 5)))
+ (parallel [(set (match_dup 7)
+ (unspec:XF [(match_dup 6) (match_dup 2)]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:XF 8 ""))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 7)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
- "fyl2x"
- [(set_attr "type" "fpspc")
- (set_attr "mode" "DF")])
+{
+ int i;
+
+ for (i=2; i<8; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+
+ emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "asinsf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
+ (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
+ (set (match_dup 6) (sqrt:XF (match_dup 5)))
+ (parallel [(set (match_dup 7)
+ (unspec:XF [(match_dup 6) (match_dup 2)]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:XF 8 ""))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 7)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<8; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+
+ emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
+})
-(define_insn "*fyl2x_xf3"
+(define_expand "asinxf2"
+ [(set (match_dup 2)
+ (mult:XF (match_operand:XF 1 "register_operand" "")
+ (match_dup 1)))
+ (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
+ (set (match_dup 5) (sqrt:XF (match_dup 4)))
+ (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_dup 5) (match_dup 1)]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:XF 6 ""))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<6; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+
+ emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "acosdf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
+ (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
+ (set (match_dup 6) (sqrt:XF (match_dup 5)))
+ (parallel [(set (match_dup 7)
+ (unspec:XF [(match_dup 2) (match_dup 6)]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:XF 8 ""))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 7)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<8; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+
+ emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "acossf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
+ (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
+ (set (match_dup 6) (sqrt:XF (match_dup 5)))
+ (parallel [(set (match_dup 7)
+ (unspec:XF [(match_dup 2) (match_dup 6)]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:XF 8 ""))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 7)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<8; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+
+ emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "acosxf2"
+ [(set (match_dup 2)
+ (mult:XF (match_operand:XF 1 "register_operand" "")
+ (match_dup 1)))
+ (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
+ (set (match_dup 5) (sqrt:XF (match_dup 4)))
+ (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_dup 1) (match_dup 5)]
+ UNSPEC_FPATAN))
+ (clobber (match_scratch:XF 6 ""))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<6; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+
+ emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_insn "fyl2x_xf3"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 2 "register_operand" "0")
(match_operand:XF 1 "register_operand" "u")]
(set_attr "mode" "XF")])
(define_expand "logsf2"
- [(parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_operand:SF 1 "register_operand" "")
- (match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:SF 3 ""))])]
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (parallel [(set (match_dup 4)
+ (unspec:XF [(match_dup 2)
+ (match_dup 3)] UNSPEC_FYL2X))
+ (clobber (match_scratch:XF 5 ""))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
operands[2] = gen_reg_rtx (XFmode);
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+
temp = standard_80387_constant_rtx (4); /* fldln2 */
- emit_move_insn (operands[2], temp);
+ emit_move_insn (operands[3], temp);
})
(define_expand "logdf2"
- [(parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_operand:DF 1 "register_operand" "")
- (match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:DF 3 ""))])]
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (parallel [(set (match_dup 4)
+ (unspec:XF [(match_dup 2)
+ (match_dup 3)] UNSPEC_FYL2X))
+ (clobber (match_scratch:XF 5 ""))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
operands[2] = gen_reg_rtx (XFmode);
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+
temp = standard_80387_constant_rtx (4); /* fldln2 */
- emit_move_insn (operands[2], temp);
+ emit_move_insn (operands[3], temp);
})
(define_expand "logxf2"
})
(define_expand "log10sf2"
- [(parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_operand:SF 1 "register_operand" "")
- (match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:SF 3 ""))])]
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (parallel [(set (match_dup 4)
+ (unspec:XF [(match_dup 2)
+ (match_dup 3)] UNSPEC_FYL2X))
+ (clobber (match_scratch:XF 5 ""))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
operands[2] = gen_reg_rtx (XFmode);
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+
temp = standard_80387_constant_rtx (3); /* fldlg2 */
- emit_move_insn (operands[2], temp);
+ emit_move_insn (operands[3], temp);
})
(define_expand "log10df2"
- [(parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_operand:DF 1 "register_operand" "")
- (match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:DF 3 ""))])]
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (parallel [(set (match_dup 4)
+ (unspec:XF [(match_dup 2)
+ (match_dup 3)] UNSPEC_FYL2X))
+ (clobber (match_scratch:XF 5 ""))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
operands[2] = gen_reg_rtx (XFmode);
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+
temp = standard_80387_constant_rtx (3); /* fldlg2 */
- emit_move_insn (operands[2], temp);
+ emit_move_insn (operands[3], temp);
})
(define_expand "log10xf2"
})
(define_expand "log2sf2"
- [(parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_operand:SF 1 "register_operand" "")
- (match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:SF 3 ""))])]
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (parallel [(set (match_dup 4)
+ (unspec:XF [(match_dup 2)
+ (match_dup 3)] UNSPEC_FYL2X))
+ (clobber (match_scratch:XF 5 ""))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
})
(define_expand "log2df2"
- [(parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_operand:DF 1 "register_operand" "")
- (match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:DF 3 ""))])]
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (parallel [(set (match_dup 4)
+ (unspec:XF [(match_dup 2)
+ (match_dup 3)] UNSPEC_FYL2X))
+ (clobber (match_scratch:XF 5 ""))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 4)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+
+ emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
})
(define_expand "log2xf2"
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
})
-(define_insn "*fscale_sfxf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (unspec:SF [(match_operand:XF 2 "register_operand" "0")
- (match_operand:XF 1 "register_operand" "u")]
- UNSPEC_FSCALE))
- (clobber (match_scratch:SF 3 "=1"))]
+(define_insn "fyl2xp1_xf3"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "0")
+ (match_operand:XF 1 "register_operand" "u")]
+ UNSPEC_FYL2XP1))
+ (clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
- "fscale\;fstp\t%y1"
+ "fyl2xp1"
[(set_attr "type" "fpspc")
- (set_attr "mode" "SF")])
+ (set_attr "mode" "XF")])
-(define_insn "*fscale_dfxf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (unspec:DF [(match_operand:XF 2 "register_operand" "0")
- (match_operand:XF 1 "register_operand" "u")]
- UNSPEC_FSCALE))
- (clobber (match_scratch:DF 3 "=1"))]
+(define_expand "log1psf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
- "fscale\;fstp\t%y1"
- [(set_attr "type" "fpspc")
- (set_attr "mode" "DF")])
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
-(define_insn "*fscale_xf3"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 2 "register_operand" "0")
- (match_operand:XF 1 "register_operand" "u")]
- UNSPEC_FSCALE))
- (clobber (match_scratch:XF 3 "=1"))]
+ emit_insn (gen_extendsfxf2 (op1, operands[1]));
+ ix86_emit_i387_log1p (op0, op1);
+ emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "log1pdf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
- "fscale\;fstp\t%y1"
- [(set_attr "type" "fpspc")
- (set_attr "mode" "XF")])
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
-(define_insn "*frndintxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_FRNDINT))]
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ ix86_emit_i387_log1p (op0, op1);
+ emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "log1pxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
- "frndint"
+{
+ ix86_emit_i387_log1p (operands[0], operands[1]);
+ DONE;
+})
+
+(define_insn "*fxtractxf3"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
+ UNSPEC_XTRACT_FRACT))
+ (set (match_operand:XF 1 "register_operand" "=u")
+ (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fxtract"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
+(define_expand "logbsf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (parallel [(set (match_dup 3)
+ (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
+ (set (match_dup 4)
+ (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 4)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (XFmode);
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "logbdf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (parallel [(set (match_dup 3)
+ (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
+ (set (match_dup 4)
+ (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 4)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (XFmode);
+ operands[3] = gen_reg_rtx (XFmode);
+ operands[4] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "logbxf2"
+ [(parallel [(set (match_dup 2)
+ (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_XTRACT_FRACT))
+ (set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "ilogbsi2"
+ [(parallel [(set (match_dup 2)
+ (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_XTRACT_FRACT))
+ (set (match_operand:XF 3 "register_operand" "")
+ (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
+ (parallel [(set (match_operand:SI 0 "register_operand" "")
+ (fix:SI (match_dup 3)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (XFmode);
+ operands[3] = gen_reg_rtx (XFmode);
+})
+
(define_insn "*f2xm1xf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
+(define_insn "*fscalexf4"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 2 "register_operand" "0")
+ (match_operand:XF 3 "register_operand" "1")]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_operand:XF 1 "register_operand" "=u")
+ (unspec:XF [(match_dup 2) (match_dup 3)]
+ UNSPEC_FSCALE_EXP))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fscale"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "XF")])
+
(define_expand "expsf2"
[(set (match_dup 2)
(float_extend:XF (match_operand:SF 1 "register_operand" "")))
(set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
(set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
(set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
- (clobber (match_scratch:SF 5 ""))])]
+ (parallel [(set (match_dup 10)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 11)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
int i;
- for (i=2; i<10; i++)
+ for (i=2; i<12; i++)
operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
emit_move_insn (operands[3], temp);
(set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
(set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
(set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
-
(set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
(set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
- (clobber (match_scratch:DF 5 ""))])]
+ (parallel [(set (match_dup 10)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 11)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
int i;
- for (i=2; i<10; i++)
+ for (i=2; i<12; i++)
operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
emit_move_insn (operands[3], temp);
(set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
(set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
- (clobber (match_scratch:XF 5 ""))])]
+ (unspec:XF [(match_dup 8) (match_dup 4)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 9)
+ (unspec:XF [(match_dup 8) (match_dup 4)]
+ UNSPEC_FSCALE_EXP))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
int i;
- for (i=2; i<9; i++)
+ for (i=2; i<10; i++)
operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
emit_move_insn (operands[2], temp);
(set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
(set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
(set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
- (clobber (match_scratch:SF 5 ""))])]
+ (parallel [(set (match_dup 10)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 11)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
int i;
- for (i=2; i<10; i++)
+ for (i=2; i<12; i++)
operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (6); /* fldl2t */
emit_move_insn (operands[3], temp);
(set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
(set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
(set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
- (parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
- (clobber (match_scratch:DF 5 ""))])]
+ (parallel [(set (match_dup 10)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 11)
+ (unspec:XF [(match_dup 9) (match_dup 5)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 10)))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
int i;
- for (i=2; i<10; i++)
+ for (i=2; i<12; i++)
operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (6); /* fldl2t */
emit_move_insn (operands[3], temp);
emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
})
-(define_expand "exp10xf2"
- [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
- (match_dup 2)))
- (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
- (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
- (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
- (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
- (clobber (match_scratch:XF 5 ""))])]
- "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+(define_expand "exp10xf2"
+ [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
+ (match_dup 2)))
+ (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
+ (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
+ (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
+ (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
+ (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_dup 8) (match_dup 4)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 9)
+ (unspec:XF [(match_dup 8) (match_dup 4)]
+ UNSPEC_FSCALE_EXP))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx temp;
+ int i;
+
+ for (i=2; i<10; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+ temp = standard_80387_constant_rtx (6); /* fldl2t */
+ emit_move_insn (operands[2], temp);
+ emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "exp2sf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
+ (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
+ (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
+ (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
+ (parallel [(set (match_dup 8)
+ (unspec:XF [(match_dup 7) (match_dup 3)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 9)
+ (unspec:XF [(match_dup 7) (match_dup 3)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 8)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<10; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "exp2df2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
+ (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
+ (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
+ (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
+ (parallel [(set (match_dup 8)
+ (unspec:XF [(match_dup 7) (match_dup 3)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 9)
+ (unspec:XF [(match_dup 7) (match_dup 3)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 8)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<10; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "exp2xf2"
+ [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
+ (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
+ (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
+ (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
+ (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
+ (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_dup 7) (match_dup 3)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 8)
+ (unspec:XF [(match_dup 7) (match_dup 3)]
+ UNSPEC_FSCALE_EXP))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=2; i<9; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+ emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "expm1df2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
+ (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
+ (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
+ (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
+ (parallel [(set (match_dup 8)
+ (unspec:XF [(match_dup 7) (match_dup 5)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 9)
+ (unspec:XF [(match_dup 7) (match_dup 5)]
+ UNSPEC_FSCALE_EXP))])
+ (parallel [(set (match_dup 11)
+ (unspec:XF [(match_dup 10) (match_dup 9)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 12)
+ (unspec:XF [(match_dup 10) (match_dup 9)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
+ (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 14)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx temp;
+ int i;
+
+ for (i=2; i<15; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+ temp = standard_80387_constant_rtx (5); /* fldl2e */
+ emit_move_insn (operands[3], temp);
+ emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "expm1sf2"
+ [(set (match_dup 2)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
+ (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
+ (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
+ (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
+ (parallel [(set (match_dup 8)
+ (unspec:XF [(match_dup 7) (match_dup 5)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 9)
+ (unspec:XF [(match_dup 7) (match_dup 5)]
+ UNSPEC_FSCALE_EXP))])
+ (parallel [(set (match_dup 11)
+ (unspec:XF [(match_dup 10) (match_dup 9)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 12)
+ (unspec:XF [(match_dup 10) (match_dup 9)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
+ (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 14)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx temp;
+ int i;
+
+ for (i=2; i<15; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+ temp = standard_80387_constant_rtx (5); /* fldl2e */
+ emit_move_insn (operands[3], temp);
+ emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
+})
+
+(define_expand "expm1xf2"
+ [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
+ (match_dup 2)))
+ (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
+ (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
+ (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
+ (parallel [(set (match_dup 7)
+ (unspec:XF [(match_dup 6) (match_dup 4)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 8)
+ (unspec:XF [(match_dup 6) (match_dup 4)]
+ UNSPEC_FSCALE_EXP))])
+ (parallel [(set (match_dup 10)
+ (unspec:XF [(match_dup 9) (match_dup 8)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 11)
+ (unspec:XF [(match_dup 9) (match_dup 8)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
+ (set (match_operand:XF 0 "register_operand" "")
+ (plus:XF (match_dup 12) (match_dup 7)))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx temp;
+ int i;
+
+ for (i=2; i<13; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+ temp = standard_80387_constant_rtx (5); /* fldl2e */
+ emit_move_insn (operands[2], temp);
+ emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
+})
+\f
+
+(define_insn "frndintxf2"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "frndint"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "XF")])
+
+(define_expand "rintdf2"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2 (op0, op1));
+
+ emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "rintsf2"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extendsfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2 (op0, op1));
+
+ emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "rintxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ emit_insn (gen_frndintxf2 (operands[0], operands[1]));
+ DONE;
+})
+
+(define_insn "frndintxf2_floor"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "floor")
+ (set_attr "mode" "XF")])
+
+(define_expand "floordf2"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "floorsf2"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_extendsfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "floorxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_frndintxf2_floor (operands[0], operands[1], op2, op3));
+ DONE;
+})
+
+(define_insn "frndintxf2_ceil"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_CEIL))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+ "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "ceil")
+ (set_attr "mode" "XF")])
+
+(define_expand "ceildf2"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "ceilsf2"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_extendsfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "ceilxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
- rtx temp;
- int i;
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
- for (i=2; i<9; i++)
- operands[i] = gen_reg_rtx (XFmode);
- temp = standard_80387_constant_rtx (6); /* fldl2t */
- emit_move_insn (operands[2], temp);
- emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_frndintxf2_ceil (operands[0], operands[1], op2, op3));
+ DONE;
})
-(define_expand "exp2sf2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:SF 1 "register_operand" "")))
- (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
- (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
- (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
- (parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_dup 7) (match_dup 3)] UNSPEC_FSCALE))
- (clobber (match_scratch:SF 3 ""))])]
+(define_insn "frndintxf2_trunc"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_TRUNC))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
+ "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "trunc")
+ (set_attr "mode" "XF")])
+
+(define_expand "btruncdf2"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
{
- int i;
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
- for (i=2; i<8; i++)
- operands[i] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ DONE;
})
-(define_expand "exp2df2"
- [(set (match_dup 2)
- (float_extend:XF (match_operand:DF 1 "register_operand" "")))
- (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
- (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
- (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
- (parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_dup 7) (match_dup 3)] UNSPEC_FSCALE))
- (clobber (match_scratch:DF 3 ""))])]
- "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+(define_expand "btruncsf2"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
- int i;
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
- for (i=2; i<8; i++)
- operands[i] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_extendsfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ DONE;
})
-(define_expand "exp2xf2"
- [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
- (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
- (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
- (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
- (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_dup 7) (match_dup 3)] UNSPEC_FSCALE))
- (clobber (match_scratch:XF 3 ""))])]
- "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+(define_expand "btruncxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
- int i;
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
- for (i=2; i<8; i++)
- operands[i] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
+ emit_insn (gen_frndintxf2_trunc (operands[0], operands[1], op2, op3));
+ DONE;
})
-(define_expand "atansf2"
- [(parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_dup 2)
- (match_operand:SF 1 "register_operand" "")]
- UNSPEC_FPATAN))
- (clobber (match_scratch:SF 3 ""))])]
+(define_insn "frndintxf2_mask_pm"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_MASK_PM))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
+ "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "mask_pm")
+ (set_attr "mode" "XF")])
+
+(define_expand "nearbyintdf2"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations"
{
- operands[2] = gen_reg_rtx (SFmode);
- emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_extenddfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ DONE;
})
-(define_expand "atandf2"
- [(parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_dup 2)
- (match_operand:DF 1 "register_operand" "")]
- UNSPEC_FPATAN))
- (clobber (match_scratch:DF 3 ""))])]
- "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+(define_expand "nearbyintsf2"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
- operands[2] = gen_reg_rtx (DFmode);
- emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_extendsfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
+
+ emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ DONE;
})
-(define_expand "atanxf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_dup 2)
- (match_operand:XF 1 "register_operand" "")]
- UNSPEC_FPATAN))
- (clobber (match_scratch:XF 3 ""))])]
- "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+(define_expand "nearbyintxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
- operands[2] = gen_reg_rtx (XFmode);
- emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
+ rtx op2 = assign_386_stack_local (HImode, 1);
+ rtx op3 = assign_386_stack_local (HImode, 2);
+
+ ix86_optimize_mode_switching = 1;
+
+ emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1],
+ op2, op3));
+ DONE;
})
+
\f
;; Block operation instructions
(define_insn "cld"
- [(set (reg:SI 19) (const_int 0))]
+ [(set (reg:SI DIRFLAG_REG) (const_int 0))]
""
"cld"
[(set_attr "type" "cld")])
-(define_expand "movstrsi"
+(define_expand "movmemsi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:BLK 1 "memory_operand" ""))
(use (match_operand:SI 2 "nonmemory_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))]
"! optimize_size"
{
- if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
+ if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
})
-(define_expand "movstrdi"
+(define_expand "movmemdi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:BLK 1 "memory_operand" ""))
(use (match_operand:DI 2 "nonmemory_operand" ""))
(use (match_operand:DI 3 "const_int_operand" ""))]
"TARGET_64BIT"
{
- if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
+ if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
DONE;
else
FAIL;
[(set (match_dup 4) (match_operand 3 "memory_operand" ""))
(set (match_operand 1 "memory_operand" "") (match_dup 4))
(parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
{
rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
(match_operand 4 "" ""))
(set (match_operand 2 "register_operand" "")
(match_operand 5 "" ""))
- (use (reg:SI 19))])]
+ (use (reg:SI DIRFLAG_REG))])]
"TARGET_SINGLE_STRINGOP || optimize_size"
"")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 8)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"movsq"
[(set_attr "type" "str")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 4)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"{movsl|movsd}"
[(set_attr "type" "str")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 4)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"{movsl|movsd}"
[(set_attr "type" "str")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 2)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"movsw"
[(set_attr "type" "str")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 2)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"movsw"
[(set_attr "type" "str")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 1)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"movsb"
[(set_attr "type" "str")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 1)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"movsb"
[(set_attr "type" "str")
(set (match_operand 1 "memory_operand" "")
(match_operand 3 "memory_operand" ""))
(use (match_dup 4))
- (use (reg:SI 19))])]
+ (use (reg:SI DIRFLAG_REG))])]
""
"")
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT"
"{rep\;movsq|rep movsq}"
[(set_attr "type" "str")
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT"
"{rep\;movsl|rep movsd}"
[(set_attr "type" "str")
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT"
"{rep\;movsl|rep movsd}"
[(set_attr "type" "str")
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT"
"{rep\;movsb|rep movsb}"
[(set_attr "type" "str")
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT"
"{rep\;movsb|rep movsb}"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set_attr "mode" "SI")])
-(define_expand "clrstrsi"
+(define_expand "clrmemsi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:SI 1 "nonmemory_operand" ""))
(use (match_operand 2 "const_int_operand" ""))]
""
{
- if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
+ if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
DONE;
else
FAIL;
})
-(define_expand "clrstrdi"
+(define_expand "clrmemdi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:DI 1 "nonmemory_operand" ""))
(use (match_operand 2 "const_int_operand" ""))]
"TARGET_64BIT"
{
- if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
+ if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
DONE;
else
FAIL;
(match_operand 2 "register_operand" ""))
(parallel [(set (match_operand 0 "register_operand" "")
(match_dup 3))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
{
if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
(match_operand 2 "register_operand" ""))
(set (match_operand 0 "register_operand" "")
(match_operand 3 "" ""))
- (use (reg:SI 19))])]
+ (use (reg:SI DIRFLAG_REG))])]
"TARGET_SINGLE_STRINGOP || optimize_size"
"")
(define_insn "*strsetdi_rex_1"
- [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
- (match_operand:SI 2 "register_operand" "a"))
+ [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
+ (match_operand:DI 2 "register_operand" "a"))
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 8)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"stosq"
[(set_attr "type" "str")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 4)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"{stosl|stosd}"
[(set_attr "type" "str")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 4)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"{stosl|stosd}"
[(set_attr "type" "str")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 2)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"stosw"
[(set_attr "type" "str")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 2)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"stosw"
[(set_attr "type" "str")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 1)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"stosb"
[(set_attr "type" "str")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 1)))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
"stosb"
[(set_attr "type" "str")
(set (match_operand 2 "memory_operand" "") (const_int 0))
(use (match_operand 3 "register_operand" ""))
(use (match_dup 1))
- (use (reg:SI 19))])]
+ (use (reg:SI DIRFLAG_REG))])]
""
"")
(const_int 0))
(use (match_operand:DI 2 "register_operand" "a"))
(use (match_dup 4))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT"
"{rep\;stosq|rep stosq}"
[(set_attr "type" "str")
(const_int 0))
(use (match_operand:SI 2 "register_operand" "a"))
(use (match_dup 4))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT"
"{rep\;stosl|rep stosd}"
[(set_attr "type" "str")
(const_int 0))
(use (match_operand:SI 2 "register_operand" "a"))
(use (match_dup 4))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT"
"{rep\;stosl|rep stosd}"
[(set_attr "type" "str")
(const_int 0))
(use (match_operand:QI 2 "register_operand" "a"))
(use (match_dup 4))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"!TARGET_64BIT"
"{rep\;stosb|rep stosb}"
[(set_attr "type" "str")
(const_int 0))
(use (match_operand:QI 2 "register_operand" "a"))
(use (match_dup 4))
- (use (reg:SI 19))]
+ (use (reg:SI DIRFLAG_REG))]
"TARGET_64BIT"
"{rep\;stosb|rep stosb}"
[(set_attr "type" "str")
(define_expand "cmpintqi"
[(set (match_dup 1)
- (gtu:QI (reg:CC 17) (const_int 0)))
+ (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (match_dup 2)
- (ltu:QI (reg:CC 17) (const_int 0)))
+ (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
(parallel [(set (match_operand:QI 0 "register_operand" "")
(minus:QI (match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"operands[1] = gen_reg_rtx (QImode);
operands[2] = gen_reg_rtx (QImode);")
;; zero. Emit extra code to make sure that a zero-length compare is EQ.
(define_expand "cmpstrqi_nz_1"
- [(parallel [(set (reg:CC 17)
+ [(parallel [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand 4 "memory_operand" "")
(match_operand 5 "memory_operand" "")))
(use (match_operand 2 "register_operand" ""))
(use (match_operand:SI 3 "immediate_operand" ""))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand 0 "register_operand" ""))
(clobber (match_operand 1 "register_operand" ""))
(clobber (match_dup 2))])]
"")
(define_insn "*cmpstrqi_nz_1"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
(mem:BLK (match_operand:SI 5 "register_operand" "1"))))
(use (match_operand:SI 6 "register_operand" "2"))
(use (match_operand:SI 3 "immediate_operand" "i"))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand:SI 0 "register_operand" "=S"))
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (match_operand:SI 2 "register_operand" "=c"))]
(set_attr "prefix_rep" "1")])
(define_insn "*cmpstrqi_nz_rex_1"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
(mem:BLK (match_operand:DI 5 "register_operand" "1"))))
(use (match_operand:DI 6 "register_operand" "2"))
(use (match_operand:SI 3 "immediate_operand" "i"))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand:DI 0 "register_operand" "=S"))
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (match_operand:DI 2 "register_operand" "=c"))]
;; The same, but the count is not known to not be zero.
(define_expand "cmpstrqi_1"
- [(parallel [(set (reg:CC 17)
+ [(parallel [(set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_operand 2 "register_operand" "")
(const_int 0))
(compare:CC (match_operand 4 "memory_operand" "")
(match_operand 5 "memory_operand" ""))
(const_int 0)))
(use (match_operand:SI 3 "immediate_operand" ""))
- (use (reg:CC 17))
- (use (reg:SI 19))
+ (use (reg:CC FLAGS_REG))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand 0 "register_operand" ""))
(clobber (match_operand 1 "register_operand" ""))
(clobber (match_dup 2))])]
"")
(define_insn "*cmpstrqi_1"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
(const_int 0))
(compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
(mem:BLK (match_operand:SI 5 "register_operand" "1")))
(const_int 0)))
(use (match_operand:SI 3 "immediate_operand" "i"))
- (use (reg:CC 17))
- (use (reg:SI 19))
+ (use (reg:CC FLAGS_REG))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand:SI 0 "register_operand" "=S"))
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (match_operand:SI 2 "register_operand" "=c"))]
(set_attr "prefix_rep" "1")])
(define_insn "*cmpstrqi_rex_1"
- [(set (reg:CC 17)
+ [(set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
(const_int 0))
(compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
(mem:BLK (match_operand:DI 5 "register_operand" "1")))
(const_int 0)))
(use (match_operand:SI 3 "immediate_operand" "i"))
- (use (reg:CC 17))
- (use (reg:SI 19))
+ (use (reg:CC FLAGS_REG))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand:DI 0 "register_operand" "=S"))
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (match_operand:DI 2 "register_operand" "=c"))]
(define_expand "strlenqi_1"
[(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand 1 "register_operand" ""))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(match_operand:QI 2 "register_operand" "a")
(match_operand:SI 3 "immediate_operand" "i")
(match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand:SI 1 "register_operand" "=D"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
"repnz{\;| }scasb"
[(set_attr "type" "str")
(match_operand:QI 2 "register_operand" "a")
(match_operand:DI 3 "immediate_operand" "i")
(match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand:DI 1 "register_operand" "=D"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"repnz{\;| }scasb"
[(set_attr "type" "str")
;; This one handles cmpstr*_nz_1...
(define_peephole2
[(parallel[
- (set (reg:CC 17)
+ (set (reg:CC FLAGS_REG)
(compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
(mem:BLK (match_operand 5 "register_operand" ""))))
(use (match_operand 6 "register_operand" ""))
(use (match_operand:SI 3 "immediate_operand" ""))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand 0 "register_operand" ""))
(clobber (match_operand 1 "register_operand" ""))
(clobber (match_operand 2 "register_operand" ""))])
(set (match_operand:QI 7 "register_operand" "")
- (gtu:QI (reg:CC 17) (const_int 0)))
+ (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (match_operand:QI 8 "register_operand" "")
- (ltu:QI (reg:CC 17) (const_int 0)))
+ (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (reg 17)
(compare (match_dup 7) (match_dup 8)))
]
"peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
[(parallel[
- (set (reg:CC 17)
+ (set (reg:CC FLAGS_REG)
(compare:CC (mem:BLK (match_dup 4))
(mem:BLK (match_dup 5))))
(use (match_dup 6))
(use (match_dup 3))
- (use (reg:SI 19))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_dup 0))
(clobber (match_dup 1))
(clobber (match_dup 2))])]
;; ...and this one handles cmpstr*_1.
(define_peephole2
[(parallel[
- (set (reg:CC 17)
+ (set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_operand 6 "register_operand" "")
(const_int 0))
(compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
(mem:BLK (match_operand 5 "register_operand" "")))
(const_int 0)))
(use (match_operand:SI 3 "immediate_operand" ""))
- (use (reg:CC 17))
- (use (reg:SI 19))
+ (use (reg:CC FLAGS_REG))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_operand 0 "register_operand" ""))
(clobber (match_operand 1 "register_operand" ""))
(clobber (match_operand 2 "register_operand" ""))])
(set (match_operand:QI 7 "register_operand" "")
- (gtu:QI (reg:CC 17) (const_int 0)))
+ (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (match_operand:QI 8 "register_operand" "")
- (ltu:QI (reg:CC 17) (const_int 0)))
+ (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (reg 17)
(compare (match_dup 7) (match_dup 8)))
]
"peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
[(parallel[
- (set (reg:CC 17)
+ (set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_dup 6)
(const_int 0))
(compare:CC (mem:BLK (match_dup 4))
(mem:BLK (match_dup 5)))
(const_int 0)))
(use (match_dup 3))
- (use (reg:CC 17))
- (use (reg:SI 19))
+ (use (reg:CC FLAGS_REG))
+ (use (reg:SI DIRFLAG_REG))
(clobber (match_dup 0))
(clobber (match_dup 1))
(clobber (match_dup 2))])]
(if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
(const_int -1)
(const_int 0)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"sbb{q}\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
(if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
(const_int -1)
(const_int 0)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
""
"sbb{l}\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
(match_operand:SF 2 "nonimmediate_operand" ""))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_SSE"
"")
(match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE && TARGET_IEEE_FP"
"#")
(match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE && !TARGET_IEEE_FP
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"#")
(match_operand:SF 2 "nonimmediate_operand" ""))
(match_operand:SF 3 "register_operand" "")
(match_operand:SF 4 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
(match_operand:SF 2 "register_operand" ""))
(match_operand:SF 3 "register_operand" "")
(match_operand:SF 4 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
|| (operands_match_p (operands[1], operands[4])
&& operands_match_p (operands[2], operands[3])))"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (match_dup 2)
(match_dup 1)))
(set (match_dup 0)
- (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
+ (if_then_else:SF (ge (reg:CCFP FLAGS_REG) (const_int 0))
(match_dup 1)
(match_dup 2)))])
(match_operand:DF 2 "nonimmediate_operand" ""))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_SSE2 && TARGET_SSE_MATH"
"#")
(match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
"#")
(match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"#")
(match_operand:DF 2 "nonimmediate_operand" ""))
(match_operand:DF 3 "register_operand" "")
(match_operand:DF 4 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
(match_operand:DF 2 "register_operand" ""))
(match_operand:DF 3 "register_operand" "")
(match_operand:DF 4 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
|| (operands_match_p (operands[1], operands[4])
&& operands_match_p (operands[2], operands[3])))"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (match_dup 2)
(match_dup 1)))
(set (match_dup 0)
- (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
+ (if_then_else:DF (ge (reg:CCFP FLAGS_REG) (const_int 0))
(match_dup 1)
(match_dup 2)))])
(match_operand:SF 2 "nonimmediate_operand" ""))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_SSE"
"#")
(match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE && TARGET_IEEE_FP"
"#")
(match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE && !TARGET_IEEE_FP
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"#")
(match_operand:SF 2 "nonimmediate_operand" ""))
(match_operand:SF 3 "register_operand" "")
(match_operand:SF 4 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
(match_operand:SF 2 "register_operand" ""))
(match_operand:SF 3 "register_operand" "")
(match_operand:SF 4 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
|| (operands_match_p (operands[1], operands[4])
&& operands_match_p (operands[2], operands[3])))"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
- (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
+ (if_then_else:SF (gt (reg:CCFP FLAGS_REG) (const_int 0))
(match_dup 1)
(match_dup 2)))])
(match_operand:DF 2 "nonimmediate_operand" ""))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_SSE2 && TARGET_SSE_MATH"
"#")
(match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
"#")
(match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
(match_dup 1)
(match_dup 2)))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"#")
(match_operand:DF 2 "nonimmediate_operand" ""))
(match_operand:DF 3 "register_operand" "")
(match_operand:DF 4 "nonimmediate_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
(match_operand:DF 2 "register_operand" ""))
(match_operand:DF 3 "register_operand" "")
(match_operand:DF 4 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ((operands_match_p (operands[1], operands[3])
&& operands_match_p (operands[2], operands[4]))
|| (operands_match_p (operands[1], operands[4])
&& operands_match_p (operands[2], operands[3])))"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
- (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
+ (if_then_else:DF (gt (reg:CCFP FLAGS_REG) (const_int 0))
(match_dup 1)
(match_dup 2)))])
[(set (match_operand:SI 0 "register_operand" "=r,r")
(plus:SI (match_operand:SI 1 "register_operand" "0,r")
(match_operand:SI 2 "immediate_operand" "i,i")))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))]
"!TARGET_64BIT"
{
[(set (match_operand:DI 0 "register_operand" "=r,r")
(plus:DI (match_operand:DI 1 "register_operand" "0,r")
(match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))]
"TARGET_64BIT"
{
(plus:DI (match_operand:DI 1 "register_operand" "0,r")
(match_operand:DI 3 "immediate_operand" "i,i")))
(use (match_operand:DI 2 "register_operand" "r,r"))
- (clobber (reg:CC 17))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))]
"TARGET_64BIT"
{
(match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
(match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
(clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
/* Avoid combine from being smart and converting min/max
(match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
(match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
(clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"#")
(match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
(match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
(clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE2
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
/* Avoid combine from being smart and converting min/max
(match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
(match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
(clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_SSE
&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
"#")
(match_operand 2 "nonimmediate_operand" "")
(match_operand 3 "nonimmediate_operand" "")))
(clobber (match_operand 6 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!SSE_REG_P (operands[0]) && reload_completed
&& VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
[(const_int 0)]
(match_operand:SF 2 "register_operand" "")
(match_operand:SF 3 "register_operand" "")))
(clobber (match_operand 6 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed"
[(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
(set (match_dup 2) (and:V4SF (match_dup 2)
(match_operand:DF 2 "register_operand" "")
(match_operand:DF 3 "register_operand" "")))
(clobber (match_operand 6 "" ""))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed"
[(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
(set (match_dup 2) (and:V2DF (match_dup 2)
(define_split
[(set (match_operand:SF 0 "register_operand" "")
- (if_then_else (match_operator:SF 1 "comparison_operator"
+ (if_then_else (match_operator 1 "comparison_operator"
[(match_operand:SF 4 "nonimmediate_operand" "")
(match_operand:SF 5 "nonimmediate_operand" "")])
(match_operand:SF 2 "nonmemory_operand" "")
if (const0_operand (operands[2], GET_MODE (operands[2])))
{
operands[7] = operands[3];
- operands[6] = gen_rtx_NOT (V4SFmode, operands[5]);
+ operands[6] = gen_rtx_NOT (V4SFmode, operands[8]);
}
else
{
operands[7] = operands[2];
- operands[6] = operands[0];
+ operands[6] = operands[8];
}
operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
})
(define_split
[(set (match_operand:DF 0 "register_operand" "")
- (if_then_else (match_operator:DF 1 "comparison_operator"
+ (if_then_else (match_operator 1 "comparison_operator"
[(match_operand:DF 4 "nonimmediate_operand" "")
(match_operand:DF 5 "nonimmediate_operand" "")])
(match_operand:DF 2 "nonmemory_operand" "")
})
(define_insn "allocate_stack_worker_1"
- [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
- (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
+ [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
+ UNSPECV_STACK_PROBE)
+ (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
(clobber (match_scratch:SI 1 "=0"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_STACK_PROBE"
"call\t__alloca"
[(set_attr "type" "multi")
(set_attr "length" "5")])
(define_expand "allocate_stack_worker_postreload"
- [(parallel [(unspec:SI [(match_operand:SI 0 "register_operand" "a")]
- UNSPEC_STACK_PROBE)
- (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
+ [(parallel [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
+ UNSPECV_STACK_PROBE)
+ (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
(clobber (match_dup 0))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(define_insn "allocate_stack_worker_rex64"
- [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
- (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
+ [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
+ UNSPECV_STACK_PROBE)
+ (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
(clobber (match_scratch:DI 1 "=0"))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_STACK_PROBE"
"call\t__alloca"
[(set_attr "type" "multi")
(set_attr "length" "5")])
(define_expand "allocate_stack_worker_rex64_postreload"
- [(parallel [(unspec:DI [(match_operand:DI 0 "register_operand" "a")]
- UNSPEC_STACK_PROBE)
- (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
+ [(parallel [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
+ UNSPECV_STACK_PROBE)
+ (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
(clobber (match_dup 0))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
""
"")
(define_expand "allocate_stack"
[(parallel [(set (match_operand:SI 0 "register_operand" "=r")
- (minus:SI (reg:SI 7)
+ (minus:SI (reg:SI SP_REG)
(match_operand:SI 1 "general_operand" "")))
- (clobber (reg:CC 17))])
- (parallel [(set (reg:SI 7)
- (minus:SI (reg:SI 7) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel [(set (reg:SI SP_REG)
+ (minus:SI (reg:SI SP_REG) (match_dup 1)))
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_STACK_PROBE"
{
#ifdef CHECK_STACK_LIMIT
(match_operator 3 "promotable_binary_operator"
[(match_operand 1 "register_operand" "")
(match_operand 2 "aligned_operand" "")]))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& ((GET_MODE (operands[0]) == HImode
&& ((!optimize_size && !TARGET_FAST_PREFIX)
&& (TARGET_PROMOTE_QImode || optimize_size)))"
[(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
if (GET_CODE (operands[3]) != ASHIFT)
&& ! optimize_size
&& ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
|| (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
- [(parallel [(set (reg:CCNO 17)
+ [(parallel [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (and:SI (match_dup 1) (match_dup 2))
(const_int 0)))
(set (match_dup 0)
&& ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
&& ! TARGET_FAST_PREFIX
&& ! optimize_size"
- [(set (reg:CCNO 17)
+ [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (and:SI (match_dup 0) (match_dup 1))
(const_int 0)))]
"operands[1]
(define_split
[(set (match_operand 0 "register_operand" "")
(neg (match_operand 1 "register_operand" "")))
- (clobber (reg:CC 17))]
+ (clobber (reg:CC FLAGS_REG))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
&& (TARGET_PROMOTE_QImode || optimize_size)))"
[(parallel [(set (match_dup 0)
(neg:SI (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);")
&& get_attr_length (insn) >= ix86_cost->large_insn
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 1) (const_int 0))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(set (match_dup 0) (match_dup 1))]
"")
&& get_attr_length (insn) >= ix86_cost->large_insn
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 2) (const_int 0))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(set (match_dup 0) (match_dup 1))]
"operands[2] = gen_lowpart (SImode, operands[1]);")
&& get_attr_length (insn) >= ix86_cost->large_insn
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 2) (const_int 0))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(set (match_dup 0) (match_dup 1))]
"operands[2] = gen_lowpart (SImode, operands[1]);")
(match_scratch:SI 3 "r")]
"ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
[(set (match_dup 3) (match_dup 0))
- (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
+ (set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))]
"")
;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
;; Don't split NOTs with a displacement operand, because resulting XOR
;; will not be pairable anyway.
;;
-;; On AMD K6, NOT is vector decoded with memory operand that can not be
+;; On AMD K6, NOT is vector decoded with memory operand that cannot be
;; represented using a modRM byte. The XOR replacement is long decoded,
;; so this split helps here as well.
;;
|| (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
[(parallel [(set (match_dup 0)
(xor:SI (match_dup 1) (const_int -1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_peephole2
|| (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
[(parallel [(set (match_dup 0)
(xor:HI (match_dup 1) (const_int -1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_peephole2
|| (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
[(parallel [(set (match_dup 0)
(xor:QI (match_dup 1) (const_int -1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
;; Non pairable "test imm, reg" instructions can be translated to
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
[(parallel
- [(set (reg:CCNO 17)
+ [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (and:SI (match_dup 0)
(match_dup 1))
(const_int 0)))
&& true_regnum (operands[0]) != 0
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
[(parallel
- [(set (reg:CCNO 17)
+ [(set (reg:CCNO FLAGS_REG)
(compare:CCNO (and:QI (match_dup 0)
(match_dup 1))
(const_int 0)))
&& ix86_match_ccmode (insn, CCNOmode)
&& true_regnum (operands[0]) != 0
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
- [(parallel [(set (reg:CCNO 17)
+ [(parallel [(set (reg:CCNO FLAGS_REG)
(compare:CCNO
(and:SI
(zero_extract:SI
(match_operator:SI 3 "arith_or_logical_operator"
[(match_dup 0)
(match_operand:SI 1 "memory_operand" "")]))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"! optimize_size && ! TARGET_READ_MODIFY"
[(set (match_dup 2) (match_dup 1))
(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_peephole2
(match_operator:SI 3 "arith_or_logical_operator"
[(match_operand:SI 1 "memory_operand" "")
(match_dup 0)]))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"! optimize_size && ! TARGET_READ_MODIFY"
[(set (match_dup 2) (match_dup 1))
(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 2) (match_dup 0)]))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
; Don't do logical operations with memory outputs
(match_operator:SI 3 "arith_or_logical_operator"
[(match_dup 0)
(match_operand:SI 1 "nonmemory_operand" "")]))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"! optimize_size && ! TARGET_READ_MODIFY_WRITE"
[(set (match_dup 2) (match_dup 0))
(parallel [(set (match_dup 2)
(match_op_dup 3 [(match_dup 2) (match_dup 1)]))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(set (match_dup 0) (match_dup 2))]
"")
(match_operator:SI 3 "arith_or_logical_operator"
[(match_operand:SI 1 "nonmemory_operand" "")
(match_dup 0)]))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"! optimize_size && ! TARGET_READ_MODIFY_WRITE"
[(set (match_dup 2) (match_dup 0))
(parallel [(set (match_dup 2)
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(set (match_dup 0) (match_dup 2))]
"")
&& (! TARGET_USE_MOV0 || optimize_size)
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int 0))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
operands[0]);")
&& (! TARGET_USE_MOV0 || optimize_size)
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
- (clobber (reg:CC 17))])])
+ (clobber (reg:CC FLAGS_REG))])])
;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
(define_peephole2
&& (optimize_size || TARGET_PENTIUM)
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int -1))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
operands[0]);")
(match_operand:SI 1 "nonmemory_operand" "")))]
"peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_peephole2
(match_operand:DI 2 "nonmemory_operand" "")) 0))]
"peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[2] = gen_lowpart (SImode, operands[2]);")
(define_peephole2
(match_operand:DI 1 "x86_64_general_operand" "")))]
"peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_peephole2
"exact_log2 (INTVAL (operands[1])) >= 0
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
(define_peephole2
"exact_log2 (INTVAL (operands[1])) >= 0
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
(define_peephole2
&& REGNO (operands[0]) == REGNO (operands[1])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
;; The ESP adjustments can be done by the push and pop instructions. Resulting
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
- (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
+ (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
(clobber (mem:BLK (scratch)))])])
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
- (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
- (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
+ (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
+ (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
(clobber (mem:BLK (scratch)))])])
;; Convert esp subtractions to push.
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
+ (clobber (reg:CC FLAGS_REG))])]
"optimize_size || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
- (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
+ (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
+ (clobber (reg:CC FLAGS_REG))])]
"optimize_size || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
- (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
- (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
+ (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
+ (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
;; Convert epilogue deallocator to pop.
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_ADD_ESP_4"
- [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
+ [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (mem:BLK (scratch)))])]
"")
(define_peephole2
[(match_scratch:SI 0 "r")
(match_scratch:SI 1 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_ADD_ESP_8"
- [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
+ [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (mem:BLK (scratch)))])
- (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
+ (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
"")
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size"
- [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
+ [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (mem:BLK (scratch)))])
- (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
+ (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
"")
;; Convert esp additions to pop.
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
+ (clobber (reg:CC FLAGS_REG))])]
""
- [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
+ [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
"")
;; Two pops case is tricky, since pop causes dependency on destination register.
(define_peephole2
[(match_scratch:SI 0 "r")
(match_scratch:SI 1 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))])]
""
- [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
- (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
+ [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
+ (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
"")
(define_peephole2
[(match_scratch:SI 0 "r")
- (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))])]
"optimize_size"
- [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
- (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
- (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
+ [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
+ (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
"")
\f
;; Convert compares with 1 to shorter inc/dec operations when CF is not
(match_operand:SI 1 "incdec_operand" "")))]
"ix86_match_ccmode (insn, CCGCmode)
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
- [(parallel [(set (reg:CCGC 17)
+ [(parallel [(set (reg:CCGC FLAGS_REG)
(compare:CCGC (match_dup 0)
(match_dup 1)))
(clobber (match_dup 0))])]
(match_operand:HI 1 "incdec_operand" "")))]
"ix86_match_ccmode (insn, CCGCmode)
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
- [(parallel [(set (reg:CCGC 17)
+ [(parallel [(set (reg:CCGC FLAGS_REG)
(compare:CCGC (match_dup 0)
(match_dup 1)))
(clobber (match_dup 0))])]
(match_operand:QI 1 "incdec_operand" "")))]
"ix86_match_ccmode (insn, CCGCmode)
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
- [(parallel [(set (reg:CCGC 17)
+ [(parallel [(set (reg:CCGC FLAGS_REG)
(compare:CCGC (match_dup 0)
(match_dup 1)))
(clobber (match_dup 0))])]
(const_int 128)))]
"ix86_match_ccmode (insn, CCGCmode)
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
- [(parallel [(set (reg:CCGC 17)
+ [(parallel [(set (reg:CCGC FLAGS_REG)
(compare:CCGC (match_dup 0)
(const_int 128)))
(clobber (match_dup 0))])]
(const_int 128)))]
"ix86_match_ccmode (insn, CCGCmode)
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
- [(parallel [(set (reg:CCGC 17)
+ [(parallel [(set (reg:CCGC FLAGS_REG)
(compare:CCGC (match_dup 0)
(const_int 128)))
(clobber (match_dup 0))])]
\f
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
- (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
+ (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
(clobber (mem:BLK (scratch)))])])
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
- (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
- (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
+ (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
+ (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
(clobber (mem:BLK (scratch)))])])
;; Convert esp subtractions to push.
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
+ (clobber (reg:CC FLAGS_REG))])]
"optimize_size || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
- (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
+ (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
+ (clobber (reg:CC FLAGS_REG))])]
"optimize_size || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
- (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
- (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
+ (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
+ (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
;; Convert epilogue deallocator to pop.
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_ADD_ESP_4"
- [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
+ [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (mem:BLK (scratch)))])]
"")
(define_peephole2
[(match_scratch:DI 0 "r")
(match_scratch:DI 1 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size || !TARGET_ADD_ESP_8"
- [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
+ [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (mem:BLK (scratch)))])
- (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
+ (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
"")
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
- (clobber (reg:CC 17))
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
+ (clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_size"
- [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
+ [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (mem:BLK (scratch)))])
- (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
+ (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
"")
;; Convert esp additions to pop.
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))])]
""
- [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
+ [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
"")
;; Two pops case is tricky, since pop causes dependency on destination register.
(define_peephole2
[(match_scratch:DI 0 "r")
(match_scratch:DI 1 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
+ (clobber (reg:CC FLAGS_REG))])]
""
- [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
- (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
+ [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
+ (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
"")
(define_peephole2
[(match_scratch:DI 0 "r")
- (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
- (clobber (reg:CC 17))])]
+ (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
+ (clobber (reg:CC FLAGS_REG))])]
"optimize_size"
- [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
- (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
- (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
+ [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
+ (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
+ (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
"")
\f
+;; Convert imul by three, five and nine into lea
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (mult:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "INTVAL (operands[2]) == 3
+ || INTVAL (operands[2]) == 5
+ || INTVAL (operands[2]) == 9"
+ [(set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 1) (match_dup 2))
+ (match_dup 1)))]
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "!optimize_size
+ && (INTVAL (operands[2]) == 3
+ || INTVAL (operands[2]) == 5
+ || INTVAL (operands[2]) == 9)"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 0) (match_dup 2))
+ (match_dup 0)))]
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (mult:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "const_int_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT
+ && (INTVAL (operands[2]) == 3
+ || INTVAL (operands[2]) == 5
+ || INTVAL (operands[2]) == 9)"
+ [(set (match_dup 0)
+ (plus:DI (mult:DI (match_dup 1) (match_dup 2))
+ (match_dup 1)))]
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
+(define_peephole2
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:DI 2 "const_int_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT
+ && !optimize_size
+ && (INTVAL (operands[2]) == 3
+ || INTVAL (operands[2]) == 5
+ || INTVAL (operands[2]) == 9)"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0)
+ (plus:DI (mult:DI (match_dup 0) (match_dup 2))
+ (match_dup 0)))]
+ { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
+
;; Imul $32bit_imm, mem, reg is vector decoded, while
;; imul $32bit_imm, reg, reg is direct decoded.
(define_peephole2
(parallel [(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_K8 && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_peephole2
(parallel [(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_K8 && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
(define_peephole2
(zero_extend:DI
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_K8 && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
"")
;; imul $8/16bit_imm, regmem, reg is vector decoded.
[(parallel [(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "const_int_operand" "")))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(match_scratch:DI 3 "r")]
"TARGET_K8 && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(match_scratch:SI 3 "r")]
"TARGET_K8 && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);
[(parallel [(set (match_operand:HI 0 "register_operand" "")
(mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "immediate_operand" "")))
- (clobber (reg:CC 17))])
+ (clobber (reg:CC FLAGS_REG))])
(match_scratch:HI 3 "r")]
"TARGET_K8 && !optimize_size"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
- (clobber (reg:CC 17))])]
+ (clobber (reg:CC FLAGS_REG))])]
{
if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
(match_operand:SI 2 "" "")))
- (set (reg:SI 7) (plus:SI (reg:SI 7)
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "")))]
"!TARGET_64BIT"
{
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
(match_operand:SI 2 "" "")))
- (set (reg:SI 7) (plus:SI (reg:SI 7)
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
"!TARGET_64BIT"
{
- if (constant_call_address_operand (operands[1], QImode))
+ if (constant_call_address_operand (operands[1], Pmode))
{
if (SIBLING_CALL_P (insn))
return "jmp\t%P1";
(match_operand:SI 2 "" "")))]
"!SIBLING_CALL_P (insn) && !TARGET_64BIT"
{
- if (constant_call_address_operand (operands[1], QImode))
+ if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
return "call\t%*%1";
}
(match_operand:SI 2 "" "")))]
"SIBLING_CALL_P (insn) && !TARGET_64BIT"
{
- if (constant_call_address_operand (operands[1], QImode))
+ if (constant_call_address_operand (operands[1], Pmode))
return "jmp\t%P1";
return "jmp\t%*%1";
}
(match_operand:DI 2 "" "")))]
"!SIBLING_CALL_P (insn) && TARGET_64BIT"
{
- if (constant_call_address_operand (operands[1], QImode))
+ if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
return "call\t%A1";
}
})
(define_insn "movv8qi_internal"
- [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
- (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
+ [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
+ (match_operand:V8QI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
"TARGET_MMX
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
pxor\t%0, %0
movq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
+ movdq2q\t{%1, %0|%0, %1}
+ movq2dq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxmov")
+ [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
(set_attr "mode" "DI")])
(define_insn "movv4hi_internal"
- [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
- (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
+ [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
+ (match_operand:V4HI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
"TARGET_MMX
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
pxor\t%0, %0
movq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
+ movdq2q\t{%1, %0|%0, %1}
+ movq2dq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxmov")
+ [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
(set_attr "mode" "DI")])
-(define_insn "movv2si_internal"
- [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
- (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
+(define_insn "*movv2si_internal"
+ [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
+ (match_operand:V2SI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
"TARGET_MMX
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
pxor\t%0, %0
movq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
+ movdq2q\t{%1, %0|%0, %1}
+ movq2dq\t{%1, %0|%0, %1}
+ movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
+ [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
(set_attr "mode" "DI")])
(define_insn "movv2sf_internal"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
- (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*x,?m")
+ (match_operand:V2SF 1 "vector_move_operand" "C,ym,y,*Y,y,*xm,*x"))]
"TARGET_3DNOW
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
pxor\t%0, %0
movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
+ movq\t{%1, %0|%0, %1}
+ movdq2q\t{%1, %0|%0, %1}
+ movq2dq\t{%1, %0|%0, %1}
+ movlps\t{%1, %0|%0, %1}
+ movlps\t{%1, %0|%0, %1}"
+ [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
+ (set_attr "mode" "DI,DI,DI,DI,DI,V2SF,V2SF")])
(define_expand "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(define_insn "movv16qi_internal"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
+ (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
"TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
(match_operand 1 "register_operand" ""))]
"!TARGET_64BIT && reload_completed
&& (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
- [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
+ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 3)))
(set (match_dup 2) (match_dup 1))]
"operands[2] = change_address (operands[0], GET_MODE (operands[0]),
stack_pointer_rtx);
(match_operand 1 "register_operand" ""))]
"TARGET_64BIT && reload_completed
&& (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
- [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
+ [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 3)))
(set (match_dup 2) (match_dup 1))]
"operands[2] = change_address (operands[0], GET_MODE (operands[0]),
stack_pointer_rtx);
[(set_attr "type" "sseadd")
(set_attr "mode" "SF")])
+;; ??? Should probably be done by generic code instead.
+(define_expand "negv4sf2"
+ [(set (match_operand:V4SF 0 "register_operand" "")
+ (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
+ (match_dup 2)))]
+ "TARGET_SSE"
+{
+ rtx m0 = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
+ rtx vm0 = gen_rtx_CONST_VECTOR (V4SFmode, gen_rtvec (4, m0, m0, m0, m0));
+ operands[2] = force_reg (V4SFmode, vm0);
+})
+
(define_insn "mulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
;; TImode, since backend insist on eliminating casts
;; on memory operands
;; sse_andti3_sf_1 - the operation taking SF scalar operands.
-;; We can not accept memory operand here as instruction reads
+;; We cannot accept memory operand here as instruction reads
;; whole scalar. This is generated only post reload by GCC
;; scalar float operations that expands to logicals (fabs)
;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
(set_attr "mode" "SF")])
(define_insn "sse_comi"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (vec_select:SF
(match_operand:V4SF 0 "register_operand" "x")
(parallel [(const_int 0)]))
(set_attr "mode" "SF")])
(define_insn "sse_ucomi"
- [(set (reg:CCFPU 17)
+ [(set (reg:CCFPU FLAGS_REG)
(compare:CCFPU (vec_select:SF
(match_operand:V4SF 0 "register_operand" "x")
(parallel [(const_int 0)]))
(set_attr "mode" "DF")])
(define_insn "sse2_comi"
- [(set (reg:CCFP 17)
+ [(set (reg:CCFP FLAGS_REG)
(compare:CCFP (vec_select:DF
(match_operand:V2DF 0 "register_operand" "x")
(parallel [(const_int 0)]))
(set_attr "mode" "DF")])
(define_insn "sse2_ucomi"
- [(set (reg:CCFPU 17)
+ [(set (reg:CCFPU FLAGS_REG)
(compare:CCFPU (vec_select:DF
(match_operand:V2DF 0 "register_operand" "x")
(parallel [(const_int 0)]))
(parallel [(const_int 0)])))))]
"TARGET_SSE2"
"pmuludq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "mode" "TI")])
+ [(set_attr "type" "mmxmul")
+ (set_attr "mode" "DI")])
(define_insn "sse2_umulv2siv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
[(unspec_volatile [(match_operand 0 "address_operand" "p")]
UNSPECV_CLFLUSH)]
"TARGET_SSE2"
- "clflush %0"
+ "clflush\t%a0"
[(set_attr "type" "sse")
(set_attr "memory" "unknown")])
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