;; X -- don't print any sort of PIC '@' suffix for a symbol.
;; & -- print some in-use local-dynamic symbol name.
;; H -- print a memory address offset by 8; used for sse high-parts
-;; Y -- print condition for SSE5 com* instruction.
;; + -- print a branch hint as 'cs' or 'ds' prefix
;; ; -- print a semicolon (after prefixes due to bug in older gas).
(UNSPEC_ADD_CARRY 34)
(UNSPEC_FLDCW 35)
(UNSPEC_REP 36)
- (UNSPEC_EH_RETURN 37)
(UNSPEC_LD_MPIC 38) ; load_macho_picbase
(UNSPEC_TRUNC_NOOP 39)
(UNSPEC_PCMPESTR 144)
(UNSPEC_PCMPISTR 145)
- ;; For SSE5
- (UNSPEC_SSE5_INTRINSIC 150)
- (UNSPEC_SSE5_UNSIGNED_CMP 151)
- (UNSPEC_SSE5_TRUEFALSE 152)
- (UNSPEC_SSE5_PERMUTE 153)
- (UNSPEC_FRCZ 154)
- (UNSPEC_CVTPH2PS 155)
- (UNSPEC_CVTPS2PH 156)
-
+ ; For FMA4 support
+ (UNSPEC_FMA4_INTRINSIC 150)
+ (UNSPEC_FMA4_FMADDSUB 151)
+ (UNSPEC_FMA4_FMSUBADD 152)
; For AES support
(UNSPEC_AESENC 159)
(UNSPEC_AESENCLAST 160)
(UNSPECV_CLD 15)
(UNSPECV_VZEROALL 16)
(UNSPECV_VZEROUPPER 17)
+ (UNSPECV_RDTSC 18)
+ (UNSPECV_RDTSCP 19)
+ (UNSPECV_RDPMC 20)
+ (UNSPECV_VSWAPMOV 21)
])
;; Constants to represent pcomtrue/pcomfalse variants
(COM_TRUE_P 5)
])
-;; Constants used in the SSE5 pperm instruction
-(define_constants
- [(PPERM_SRC 0x00) /* copy source */
- (PPERM_INVERT 0x20) /* invert source */
- (PPERM_REVERSE 0x40) /* bit reverse source */
- (PPERM_REV_INV 0x60) /* bit reverse & invert src */
- (PPERM_ZERO 0x80) /* all 0's */
- (PPERM_ONES 0xa0) /* all 1's */
- (PPERM_SIGN 0xc0) /* propagate sign bit */
- (PPERM_INV_SIGN 0xe0) /* invert & propagate sign */
- (PPERM_SRC1 0x00) /* use first source byte */
- (PPERM_SRC2 0x10) /* use second source byte */
- ])
-
;; Registers by name.
(define_constants
[(AX_REG 0)
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
- (if_then_else (ior (eq_attr "mode" "HI")
- (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI")))
- (const_int 1)
- (const_int 0)))
+ (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+ (const_int 0)
+ (eq_attr "mode" "HI")
+ (const_int 1)
+ (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Set when string REP prefix is used.
(define_attr "prefix_rep" ""
- (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
- (const_int 1)
- (const_int 0)))
+ (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+ (const_int 0)
+ (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
(cond [(ne (symbol_ref "!TARGET_64BIT") (const_int 0))
(const_int 0)
(and (eq_attr "mode" "DI")
- (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
+ (and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
+ (eq_attr "unit" "!mmx")))
(const_int 1)
(and (eq_attr "mode" "QI")
(ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
]
(const_int 0)))
-;; There are also additional prefixes in SSSE3.
-(define_attr "prefix_extra" "" (const_int 0))
+;; There are also additional prefixes in 3DNOW, SSSE3.
+;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
+;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
+;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
+(define_attr "prefix_extra" ""
+ (cond [(eq_attr "type" "ssemuladd,sse4arg")
+ (const_int 2)
+ (eq_attr "type" "sseiadd1,ssecvt1")
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Prefix used: original, VEX or maybe VEX.
(define_attr "prefix" "orig,vex,maybe_vex"
(const_string "vex")
(const_string "orig")))
-;; There is a 8bit immediate for VEX.
-(define_attr "prefix_vex_imm8" "" (const_int 0))
-
;; VEX W bit is used.
(define_attr "prefix_vex_w" "" (const_int 0))
;; The length of VEX prefix
+;; Only instructions with 0f prefix can have 2 byte VEX prefix,
+;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
+;; still prefix_0f 1, with prefix_extra 1.
(define_attr "length_vex" ""
- (if_then_else (eq_attr "prefix_0f" "1")
+ (if_then_else (and (eq_attr "prefix_0f" "1")
+ (eq_attr "prefix_extra" "0"))
(if_then_else (eq_attr "prefix_vex_w" "1")
(symbol_ref "ix86_attr_length_vex_default (insn, 1, 1)")
(symbol_ref "ix86_attr_length_vex_default (insn, 1, 0)"))
(eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
- (ior (match_operand:SI 1 "register_operand" "")
- (match_operand:HI 1 "register_operand" "")))
+ (and (eq (symbol_ref "TARGET_64BIT") (const_int 0))
+ (ior (match_operand:SI 1 "register_operand" "")
+ (match_operand:HI 1 "register_operand" ""))))
(const_int 0)
(and (eq_attr "type" "push")
(not (match_operand 1 "memory_operand" "")))
(and (eq_attr "prefix" "maybe_vex")
(ne (symbol_ref "TARGET_AVX") (const_int 0))))
(plus (attr "length_vex")
- (plus (attr "prefix_vex_imm8")
+ (plus (attr "length_immediate")
(plus (attr "modrm")
(attr "length_address"))))]
(plus (plus (attr "modrm")
;; Base name for x87 insn mnemonic.
(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
+;; Used in signed and unsigned widening multiplications.
+(define_code_iterator any_extend [sign_extend zero_extend])
+
+;; Used in signed and unsigned divisions.
+(define_code_iterator any_div [div udiv])
+
+;; Various insn prefixes for signed and unsigned operations.
+(define_code_attr u [(sign_extend "") (zero_extend "u")
+ (div "") (udiv "u")])
+(define_code_attr s [(sign_extend "s") (zero_extend "u")])
+
+;; Instruction prefix for signed and unsigned operations.
+(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")
+ (div "i") (udiv "")])
+
;; All single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
;; Single word integer modes without QImode.
(define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])
+;; Single word integer modes without QImode and HImode.
+(define_mode_iterator SWI48 [SI (DI "TARGET_64BIT")])
+
+;; All math-dependant single and double word integer modes.
+(define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
+ (HI "TARGET_HIMODE_MATH")
+ SI DI (TI "TARGET_64BIT")])
+
+;; Math-dependant single word integer modes.
+(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
+ (HI "TARGET_HIMODE_MATH")
+ SI (DI "TARGET_64BIT")])
+
+;; Math-dependant single word integer modes without QImode.
+(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
+ SI (DI "TARGET_64BIT")])
+
+;; Half mode for double word integer modes.
+(define_mode_iterator DWIH [(SI "!TARGET_64BIT")
+ (DI "TARGET_64BIT")])
+
+;; Double word integer modes.
+(define_mode_attr DWI [(SI "DI") (DI "TI")])
+(define_mode_attr dwi [(SI "di") (DI "ti")])
+
;; Instruction suffix for integer modes.
(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
;; Immediate operand constraint for integer modes.
(define_mode_attr i [(QI "n") (HI "n") (SI "i") (DI "e")])
+;; General operand constraint for word modes.
+(define_mode_attr g [(SI "g") (DI "rme")])
+
+;; Immediate operand constraint for double integer modes.
+(define_mode_attr di [(SI "iF") (DI "e")])
+
;; General operand predicate for integer modes.
(define_mode_attr general_operand
[(QI "general_operand")
(HI "general_operand")
(SI "general_operand")
- (DI "x86_64_general_operand")])
+ (DI "x86_64_general_operand")
+ (TI "x86_64_general_operand")])
;; SSE and x87 SFmode and DFmode floating point modes
(define_mode_iterator MODEF [SF DF])
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
-
\f
;; Scheduling descriptions
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "cmpqi_ext_3_insn_rex64"
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_4"
(compare:CC (match_operand:XF 1 "nonmemory_operand" "")
(match_operand:XF 2 "nonmemory_operand" "")))
(set (pc) (if_then_else
- (match_operator 0 "comparison_operator"
+ (match_operator 0 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(compare:CC (match_operand:XF 2 "nonmemory_operand" "")
(match_operand:XF 3 "nonmemory_operand" "")))
(set (match_operand:QI 0 "register_operand" "")
- (match_operator 1 "comparison_operator"
+ (match_operator 1 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)]))]
"TARGET_80387"
(compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
(match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
(set (pc) (if_then_else
- (match_operator 0 "comparison_operator"
+ (match_operator 0 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
(match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
(set (match_operand:QI 0 "register_operand" "")
- (match_operator 1 "comparison_operator"
+ (match_operator 1 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)]))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
(unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
"TARGET_80387"
"fnstsw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "SI")
(set_attr "unit" "i387")])
#ifdef HAVE_AS_IX86_SAHF
return "sahf";
#else
- return ".byte\t0x9e";
+ return ASM_BYTE "0x9e";
#endif
}
[(set_attr "length" "1")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set (attr "prefix_rep")
+ (if_then_else (eq_attr "type" "ssecomi")
+ (const_string "0")
+ (const_string "*")))
+ (set (attr "prefix_data16")
+ (cond [(eq_attr "type" "fcmp")
+ (const_string "*")
+ (eq_attr "mode" "DF")
+ (const_string "1")
+ ]
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set (attr "prefix_rep")
+ (if_then_else (eq_attr "type" "ssecomi")
+ (const_string "0")
+ (const_string "*")))
+ (set (attr "prefix_data16")
+ (cond [(eq_attr "type" "fcmp")
+ (const_string "*")
+ (eq_attr "mode" "DF")
+ (const_string "1")
+ ]
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
(const_string "orig")
(const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(const_string "DI")
(and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
(const_string "8")
(const_string "*")))
+ (set_attr "prefix_rex" "*,*,*,*,*,*,*,1,*,1,*,*,*,*,*,*,*,*,*")
+ (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,1,*,*,*")
(set (attr "prefix")
(if_then_else (eq_attr "alternative" "11,12,13,14,15,16")
(const_string "maybe_vex")
[(set (match_dup 0)
(match_dup 2))])
-
;; %%% Kill this when call knows how to work this out.
(define_split
[(set (match_operand:SF 0 "push_operand" "")
(if_then_else (eq_attr "alternative" "0,1,2,3,4")
(const_string "orig")
(const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
(if_then_else (eq_attr "alternative" "0,1,2,3,4")
(const_string "orig")
(const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
}
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
&& (TARGET_ZERO_EXTEND_WITH_AND
&& optimize_function_for_speed_p (cfun))
&& !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0) (const_int 0))
- (set (strict_low_part (match_dup 2)) (match_dup 1))]
- "operands[2] = gen_lowpart (QImode, operands[0]);")
+ [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+{
+ operands[2] = gen_lowpart (QImode, operands[0]);
+ ix86_expand_clear (operands[0]);
+})
;; Rest is handled by single and.
(define_split
[(set_attr "type" "alu1")
(set_attr "mode" "SI")])
-(define_insn "*zero_extendqisi2_movzbw_and"
+(define_insn "*zero_extendqisi2_movzbl_and"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
(clobber (reg:CC FLAGS_REG))]
[(set_attr "type" "imovx,alu1")
(set_attr "mode" "SI")])
-(define_insn "*zero_extendqisi2_movzbw"
+(define_insn "*zero_extendqisi2_movzbl"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"(!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
&& (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
&& (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
&& !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0) (const_int 0))
- (set (strict_low_part (match_dup 2)) (match_dup 1))]
- "operands[2] = gen_lowpart (QImode, operands[0]);")
+ [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+{
+ operands[2] = gen_lowpart (QImode, operands[0]);
+ ix86_expand_clear (operands[0]);
+})
;; Rest is handled by single and.
(define_split
"TARGET_64BIT"
"@
{cltq|cdqe}
- movs{lq|x}\t{%1,%0|%0, %1}"
+ movs{lq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")
(set_attr "prefix_0f" "0")
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_64BIT"
- "movs{wq|x}\t{%1,%0|%0, %1}"
+ "movs{wq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"TARGET_64BIT"
- "movs{bq|x}\t{%1,%0|%0, %1}"
+ "movs{bq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
case 0:
return "{cwtl|cwde}";
default:
- return "movs{wl|x}\t{%1,%0|%0, %1}";
+ return "movs{wl|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
case 0:
return "{cwtl|cwde}";
default:
- return "movs{wl|x}\t{%1,%k0|%k0, %1}";
+ return "movs{wl|x}\t{%1, %k0|%k0, %1}";
}
}
[(set_attr "type" "imovx")
case 0:
return "{cbtw|cbw}";
default:
- return "movs{bw|x}\t{%1,%0|%0, %1}";
+ return "movs{bw|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
""
- "movs{bl|x}\t{%1,%0|%0, %1}"
+ "movs{bl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(zero_extend:DI
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
"TARGET_64BIT"
- "movs{bl|x}\t{%1,%k0|%k0, %1}"
+ "movs{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
\f
"%vcvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "prefix" "maybe_vex")
+ (set_attr "prefix_rex" "1")
(set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
&& !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& (TARGET_64BIT || <MODE>mode != DImode))
&& TARGET_SSE_MATH)
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
&& !TARGET_FISTTP
&& !(SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& (TARGET_64BIT || <MODE>mode != DImode))
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
"TARGET_80387"
"fnstcw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")])
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387"
"fldcw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")
(set_attr "athlon_decode" "vector")
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(parallel [(set (match_dup 0)
&& !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode))
{
rtx reg = gen_reg_rtx (XFmode);
+ rtx insn;
+
emit_insn (gen_float<SSEMODEI24:mode>xf2 (reg, operands[1]));
-/* Avoid references to nonexistent function in dead code in XFmode case. */
-#define gen_truncxfxf2 gen_truncxfdf2
- emit_insn (gen_truncxf<X87MODEF:mode>2 (operands[0], reg));
-#undef gen_truncxfxf2
+
+ if (<X87MODEF:MODE>mode == SFmode)
+ insn = gen_truncxfsf2 (operands[0], reg);
+ else if (<X87MODEF:MODE>mode == DFmode)
+ insn = gen_truncxfdf2 (operands[0], reg);
+ else
+ gcc_unreachable ();
+
+ emit_insn (insn);
DONE;
}
}")
&& flag_trapping_math)
|| !(TARGET_INTER_UNIT_CONVERSIONS
|| optimize_function_for_size_p (cfun)))))
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(parallel [(set (match_dup 0) (float:X87MODEF (match_dup 1)))
\f
;; Add instructions
-;; %%% splits for addditi3
-
-(define_expand "addti3"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))]
- "TARGET_64BIT"
- "ix86_expand_binary_operator (PLUS, TImode, operands); DONE;")
-
-(define_insn "*addti3_1"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
- (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0,0")
- (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, TImode, operands)"
- "#")
-
-(define_split
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
- UNSPEC_ADD_CARRY))
- (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))])
- (parallel [(set (match_dup 3)
- (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 4))
- (match_dup 5)))
- (clobber (reg:CC FLAGS_REG))])]
- "split_ti (&operands[0], 3, &operands[0], &operands[3]);")
-
-;; %%% splits for addsidi3
-; [(set (match_operand:DI 0 "nonimmediate_operand" "")
-; (plus:DI (match_operand:DI 1 "general_operand" "")
-; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
-
-(define_expand "adddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))]
+(define_expand "add<mode>3"
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
+ (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
+ (match_operand:SDWIM 2 "<general_operand>" "")))]
""
- "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
-
-(define_insn "*adddi3_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "roiF,riF")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "#")
+ "ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;")
-(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
+(define_insn_and_split "*add<dwi>3_doubleword"
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
+ (plus:<DWI>
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
+ (match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
- UNSPEC_ADD_CARRY))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
+ "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
+ "#"
+ "reload_completed"
+ [(parallel [(set (reg:CC FLAGS_REG)
+ (unspec:CC [(match_dup 1) (match_dup 2)]
+ UNSPEC_ADD_CARRY))
+ (set (match_dup 0)
+ (plus:DWIH (match_dup 1) (match_dup 2)))])
(parallel [(set (match_dup 3)
- (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 4))
- (match_dup 5)))
+ (plus:DWIH
+ (plus:DWIH
+ (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+ (match_dup 4))
+ (match_dup 5)))
(clobber (reg:CC FLAGS_REG))])]
- "split_di (&operands[0], 3, &operands[0], &operands[3]);")
+ "split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
-(define_insn "adddi3_carry_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
- (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
+(define_insn "add<mode>3_carry"
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (plus:SWI
+ (plus:SWI (match_operand:SWI 3 "ix86_carry_flag_operator" "")
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "adc{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "DI")])
-
-(define_insn "*adddi3_cc_rex64"
- [(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
- UNSPEC_ADD_CARRY))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "add{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
-
-(define_insn "*<plusminus_insn><mode>3_cc_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (plusminus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
- (match_dup 1)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
- (plusminus:SWI (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*add<mode>3_cconly_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (plus:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>m"))
- (match_dup 1)))
- (clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
- "add{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*sub<mode>3_cconly_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
- (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
- (match_dup 0)))]
- ""
- "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
- [(set_attr "type" "icmp")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (plusminus:SI (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
- (match_operand:SI 2 "general_operand" "g"))
- (match_dup 1)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "SI")])
-
-(define_insn "addqi3_carry"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
- (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:QI 2 "general_operand" "qn,qm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, QImode, operands)"
- "adc{b}\t{%2, %0|%0, %2}"
+ "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
- (set_attr "mode" "QI")])
-
-(define_insn "addhi3_carry"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
- (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:HI 2 "general_operand" "rn,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, HImode, operands)"
- "adc{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "HI")])
-
-(define_insn "addsi3_carry"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:SI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, SImode, operands)"
- "adc{l}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*addsi3_carry_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 1 "nonimmediate_operand" "%0"))
- (match_operand:SI 2 "general_operand" "g"))))
+ (zero_extend:DI
+ (plus:SI
+ (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
+ (match_operand:SI 1 "nonimmediate_operand" "%0"))
+ (match_operand:SI 2 "general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
"adc{l}\t{%2, %k0|%k0, %2}"
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
-(define_insn "*addsi3_cc"
+(define_insn "*add<mode>3_cc"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")]
- UNSPEC_ADD_CARRY))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (plus:SI (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, SImode, operands)"
- "add{l}\t{%2, %0|%0, %2}"
+ (unspec:CC
+ [(match_operand:SWI48 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SWI48 2 "<general_operand>" "r<i>,rm")]
+ UNSPEC_ADD_CARRY))
+ (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
+ (plus:SWI48 (match_dup 1) (match_dup 2)))]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "addqi3_cc"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qn,qm")]
- UNSPEC_ADD_CARRY))
+ (unspec:CC
+ [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:QI 2 "general_operand" "qn,qm")]
+ UNSPEC_ADD_CARRY))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
(plus:QI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, QImode, operands)"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-(define_expand "addsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))]
- ""
- "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
+(define_insn "*add<mode>3_cconly_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (plus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "%0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>m"))
+ (match_dup 1)))
+ (clobber (match_scratch:SWI 0 "=<r>"))]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"
+ [(set_attr "type" "alu")
+ (set_attr "mode" "<MODE>")])
(define_insn "*lea_1"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "no_seg_address_operand" "p"))]
- "!TARGET_64BIT"
- "lea{l}\t{%a1, %0|%0, %a1}"
+ [(set (match_operand:DWIH 0 "register_operand" "=r")
+ (match_operand:DWIH 1 "no_seg_address_operand" "p"))]
+ ""
+ "lea{<imodesuffix>}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "lea")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*lea_1_rex64"
+(define_insn "*lea_2"
[(set (match_operand:SI 0 "register_operand" "=r")
(subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
"TARGET_64BIT"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
-(define_insn "*lea_1_zext"
+(define_insn "*lea_2_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
- (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
+ (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
"TARGET_64BIT"
"lea{l}\t{%a1, %k0|%k0, %a1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
-(define_insn "*lea_2_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (match_operand:DI 1 "no_seg_address_operand" "p"))]
- "TARGET_64BIT"
- "lea{q}\t{%a1, %0|%0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "DI")])
-
-;; The lea patterns for non-Pmodes needs to be matched by several
-;; insns converted to real lea by splitters.
-
-(define_insn_and_split "*lea_general_1"
- [(set (match_operand 0 "register_operand" "=r")
- (plus (plus (match_operand 1 "index_register_operand" "l")
- (match_operand 2 "register_operand" "r"))
- (match_operand 3 "immediate_operand" "i")))]
- "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
- || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
- && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE (operands[0]) == GET_MODE (operands[2])
- && (GET_MODE (operands[0]) == GET_MODE (operands[3])
- || GET_MODE (operands[3]) == VOIDmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
+(define_insn "*add<mode>_1"
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
+ (plus:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r")
+ (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>,0,l<i>")))
+ (clobber (reg:CC FLAGS_REG))]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
{
- rtx pat;
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
- operands[3]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
+ switch (get_attr_type (insn))
+ {
+ case TYPE_LEA:
+ operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
+ return "lea{<imodesuffix>}\t{%a2, %0|%0, %a2}";
-(define_insn_and_split "*lea_general_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
- (match_operand:SI 2 "register_operand" "r"))
- (match_operand:SI 3 "immediate_operand" "i"))))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
- (match_dup 2))
- (match_dup 3)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea_general_2"
- [(set (match_operand 0 "register_operand" "=r")
- (plus (mult (match_operand 1 "index_register_operand" "l")
- (match_operand 2 "const248_operand" "i"))
- (match_operand 3 "nonmemory_operand" "ri")))]
- "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
- || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
- && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && (GET_MODE (operands[0]) == GET_MODE (operands[3])
- || GET_MODE (operands[3]) == VOIDmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx pat;
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
- operands[3]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea_general_2_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
- (match_operand:SI 2 "const248_operand" "n"))
- (match_operand:SI 3 "nonmemory_operand" "ri"))))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
- (match_dup 2))
- (match_dup 3)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea_general_3"
- [(set (match_operand 0 "register_operand" "=r")
- (plus (plus (mult (match_operand 1 "index_register_operand" "l")
- (match_operand 2 "const248_operand" "i"))
- (match_operand 3 "register_operand" "r"))
- (match_operand 4 "immediate_operand" "i")))]
- "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
- || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
- && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE (operands[0]) == GET_MODE (operands[3])"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx pat;
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- operands[4] = gen_lowpart (Pmode, operands[4]);
- pat = gen_rtx_PLUS (Pmode,
- gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
- operands[2]),
- operands[3]),
- operands[4]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea_general_3_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (plus:SI (plus:SI (mult:SI
- (match_operand:SI 1 "index_register_operand" "l")
- (match_operand:SI 2 "const248_operand" "n"))
- (match_operand:SI 3 "register_operand" "r"))
- (match_operand:SI 4 "immediate_operand" "i"))))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
- (match_dup 2))
- (match_dup 3))
- (match_dup 4)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- operands[4] = gen_lowpart (Pmode, operands[4]);
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn "*adddi_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r,r")
- (match_operand:DI 2 "x86_64_general_operand" "rme,re,0,le")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_LEA:
- operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{q}\t{%a2, %0|%0, %a2}";
-
- case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
- }
+ case TYPE_INCDEC:
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ if (operands[2] == const1_rtx)
+ return "inc{<imodesuffix>}\t%0";
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{<imodesuffix>}\t%0";
+ }
default:
/* Use add as much as possible to replace lea for AGU optimization. */
if (which_alternative == 2 && TARGET_OPT_AGU)
- return "add{q}\t{%1, %0|%0, %1}";
+ return "add{<imodesuffix>}\t{%1, %0|%0, %1}";
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
/* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
}
- return "add{q}\t{%2, %0|%0, %2}";
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
(const_string "lea")
; Current assemblers are broken and do not allow @GOTOFF in
; ought but a memory context.
- (match_operand:DI 2 "pic_symbolic_operand" "")
+ (match_operand:SWI48 2 "pic_symbolic_operand" "")
(const_string "lea")
- (match_operand:DI 2 "incdec_operand" "")
+ (match_operand:SWI48 2 "incdec_operand" "")
(const_string "incdec")
]
(const_string "alu")))
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<MODE>")])
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed
- && ix86_lea_for_add_ok (PLUS, insn, operands)"
- [(set (match_dup 0)
- (plus:DI (match_dup 1)
- (match_dup 2)))]
- "")
+;; It may seem that nonimmediate operand is proper one for operand 1.
+;; The addsi_1 pattern allows nonimmediate operand at that place and
+;; we take care in ix86_binary_operator_ok to not allow two memory
+;; operands so proper swapping will be done in reload. This allow
+;; patterns constructed from addsi_1 to match.
-(define_insn "*adddi_2_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, DImode, operands)
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+(define_insn "*addsi_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
+ (match_operand:SI 2 "general_operand" "g,li"))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
{
switch (get_attr_type (insn))
{
+ case TYPE_LEA:
+ operands[2] = XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 0);
+ return "lea{l}\t{%a2, %k0|%k0, %a2}";
+
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
+ return "inc{l}\t%k0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
+ return "dec{l}\t%k0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* ???? We ought to handle there the 32bit case too
- - do we need new constraint? */
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
}
- return "add{q}\t{%2, %0|%0, %2}";
+ return "add{l}\t{%2, %k0|%k0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
+ (cond [(eq_attr "alternative" "1")
+ (const_string "lea")
+ ; Current assemblers are broken and do not allow @GOTOFF in
+ ; ought but a memory context.
+ (match_operand:SI 2 "pic_symbolic_operand" "")
+ (const_string "lea")
+ (match_operand:SI 2 "incdec_operand" "")
+ (const_string "incdec")
+ ]
+ (const_string "alu")))
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "SI")])
-(define_insn "*adddi_3_rex64"
- [(set (reg FLAGS_REG)
- (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
- (match_operand:DI 1 "x86_64_general_operand" "%0")))
- (clobber (match_scratch:DI 0 "=r"))]
- "TARGET_64BIT
- && ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+(define_insn "*addhi_1"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:HI 2 "general_operand" "rn,rm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, HImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
+ return "inc{w}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
+ return "dec{w}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* ???? We ought to handle there the 32bit case too
- - do we need new constraint? */
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
- }
- return "add{q}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{w}\t{%2, %0|%0, %2}";
+ }
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "HI")])
-; For comparisons against 1, -1 and 128, we may generate better code
-; by converting cmp to add, inc or dec as done by peephole2. This pattern
-; is matched then. We can't accept general immediate, because for
-; case of overflows, the result is messed up.
-; This pattern also don't hold of 0x8000000000000000, since the value overflows
-; when negated.
-; Also carry flag is reversed compared to cmp, so this conversion is valid
-; only for comparisons not depending on it.
-(define_insn "*adddi_4_rex64"
- [(set (reg FLAGS_REG)
- (compare (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:DI 2 "x86_64_immediate_operand" "e")))
- (clobber (match_scratch:DI 0 "=rm"))]
- "TARGET_64BIT
- && ix86_match_ccmode (insn, CCGCmode)"
+;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
+;; type optimizations enabled by define-splits. This is not important
+;; for PII, and in fact harmful because of partial register stalls.
+
+(define_insn "*addhi_1_lea"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
+ (match_operand:HI 2 "general_operand" "rn,rm,ln")))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, HImode, operands)"
{
switch (get_attr_type (insn))
{
+ case TYPE_LEA:
+ return "#";
case TYPE_INCDEC:
- if (operands[2] == constm1_rtx)
- return "inc{q}\t%0";
+ if (operands[2] == const1_rtx)
+ return "inc{w}\t%0";
else
- {
- gcc_assert (operands[2] == const1_rtx);
- return "dec{q}\t%0";
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{w}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if ((INTVAL (operands[2]) == -128
- || (INTVAL (operands[2]) > 0
- && INTVAL (operands[2]) != 128))
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
- return "sub{q}\t{%2, %0|%0, %2}";
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "add{q}\t{%2, %0|%0, %2}";
+ if (CONST_INT_P (operands[2])
+ && (INTVAL (operands[2]) == 128
+ || (INTVAL (operands[2]) < 0
+ && INTVAL (operands[2]) != -128)))
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{w}\t{%2, %0|%0, %2}";
+ }
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
+ (if_then_else (eq_attr "alternative" "2")
+ (const_string "lea")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu"))))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "HI,HI,SI")])
-(define_insn "*adddi_5_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
- (match_operand:DI 2 "x86_64_general_operand" "rme"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=r"))]
- "TARGET_64BIT
- && ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+(define_insn "*addqi_1"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, QImode, operands)"
{
+ int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
+ return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
- }
- return "add{q}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ if (widen)
+ return "sub{l}\t{%2, %k0|%k0, %2}";
+ else
+ return "sub{b}\t{%2, %0|%0, %2}";
+ }
+ if (widen)
+ return "add{l}\t{%k2, %k0|%k0, %k2}";
+ else
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "DI")])
-
+ (set_attr "mode" "QI,QI,SI")])
-(define_insn "*addsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r,r")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r,r")
- (match_operand:SI 2 "general_operand" "g,ri,0,li")))
+;; %%% Potential partial reg stall on alternative 2. What to do?
+(define_insn "*addqi_1_lea"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, SImode, operands)"
+ "!TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, QImode, operands)"
{
+ int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_LEA:
- operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{l}\t{%a2, %0|%0, %a2}";
-
+ return "#";
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
+ return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ gcc_assert (operands[2] == constm1_rtx);
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
}
default:
- /* Use add as much as possible to replace lea for AGU optimization. */
- if (which_alternative == 2 && TARGET_OPT_AGU)
- return "add{l}\t{%1, %0|%0, %1}";
-
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
-
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
- }
- return "add{l}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ if (widen)
+ return "sub{l}\t{%2, %k0|%k0, %2}";
+ else
+ return "sub{b}\t{%2, %0|%0, %2}";
+ }
+ if (widen)
+ return "add{l}\t{%k2, %k0|%k0, %k2}";
+ else
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (cond [(and (eq_attr "alternative" "2")
- (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
- (const_string "lea")
- (eq_attr "alternative" "3")
- (const_string "lea")
- ; Current assemblers are broken and do not allow @GOTOFF in
- ; ought but a memory context.
- (match_operand:SI 2 "pic_symbolic_operand" "")
- (const_string "lea")
- (match_operand:SI 2 "incdec_operand" "")
- (const_string "incdec")
- ]
- (const_string "alu")))
+ (if_then_else (eq_attr "alternative" "3")
+ (const_string "lea")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu"))))
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI")])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (plus (match_operand 1 "register_operand" "")
- (match_operand 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed && ix86_lea_for_add_ok (PLUS, insn, operands)"
- [(const_int 0)]
-{
- rtx pat;
- /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
- may confuse gen_lowpart. */
- if (GET_MODE (operands[0]) != Pmode)
- {
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
- }
- operands[0] = gen_lowpart (SImode, operands[0]);
- pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-})
+ (set_attr "mode" "QI,QI,SI,SI")])
-;; It may seem that nonimmediate operand is proper one for operand 1.
-;; The addsi_1 pattern allows nonimmediate operand at that place and
-;; we take care in ix86_binary_operator_ok to not allow two memory
-;; operands so proper swapping will be done in reload. This allow
-;; patterns constructed from addsi_1 to match.
-(define_insn "addsi_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
- (match_operand:SI 2 "general_operand" "g,li"))))
+(define_insn "*addqi_1_slp"
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
+ (plus:QI (match_dup 0)
+ (match_operand:QI 1 "general_operand" "qn,qnm")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (get_attr_type (insn))
{
- case TYPE_LEA:
- operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{l}\t{%a2, %k0|%k0, %a2}";
-
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{l}\t%k0";
+ if (operands[1] == const1_rtx)
+ return "inc{b}\t%0";
else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%k0";
+ {
+ gcc_assert (operands[1] == constm1_rtx);
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %k0|%k0, %2}";
- }
- return "add{l}\t{%2, %k0|%k0, %2}";
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
+ if (CONST_INT_P (operands[1])
+ && INTVAL (operands[1]) < 0)
+ {
+ operands[1] = GEN_INT (-INTVAL (operands[1]));
+ return "sub{b}\t{%1, %0|%0, %1}";
+ }
+ return "add{b}\t{%1, %0|%0, %1}";
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "1")
- (const_string "lea")
- ; Current assemblers are broken and do not allow @GOTOFF in
- ; ought but a memory context.
- (match_operand:SI 2 "pic_symbolic_operand" "")
- (const_string "lea")
- (match_operand:SI 2 "incdec_operand" "")
- (const_string "incdec")
- ]
- (const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" ""))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
-})
+ (if_then_else (match_operand:QI 1 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu1")))
+ (set (attr "memory")
+ (if_then_else (match_operand 1 "memory_operand" "")
+ (const_string "load")
+ (const_string "none")))
+ (set_attr "mode" "QI")])
-(define_insn "*addsi_2"
+(define_insn "*add<mode>_2"
[(set (reg FLAGS_REG)
(compare
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "g,ri"))
+ (plus:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>"))
(const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
- (plus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm")
+ (plus:SWI48 (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, SImode, operands)
+ && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
case TYPE_INCDEC:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
+ return "inc{<imodesuffix>}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ return "dec{<imodesuffix>}\t%0";
}
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* ???? In DImode, we ought to handle there the 32bit case too
+ - do we need new constraint? */
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
+ /* Avoid overflows. */
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
}
- return "add{l}\t{%2, %0|%0, %2}";
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(define_insn "*addsi_2_zext"
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
(const_string "*")))
(set_attr "mode" "SI")])
-(define_insn "*addsi_3"
+(define_insn "*addhi_2"
[(set (reg FLAGS_REG)
- (compare (neg:SI (match_operand:SI 2 "general_operand" "g"))
- (match_operand:SI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:SI 0 "=r"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+ (compare
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:HI 2 "general_operand" "rmn,rn"))
+ (const_int 0)))
+ (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
+ (plus:HI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (PLUS, HImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
+ return "inc{w}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ return "dec{w}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
- }
- return "add{l}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{w}\t{%2, %0|%0, %2}";
+ }
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "HI")])
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-(define_insn "*addsi_3_zext"
+(define_insn "*addqi_2"
[(set (reg FLAGS_REG)
- (compare (neg:SI (match_operand:SI 2 "general_operand" "g"))
- (match_operand:SI 1 "nonimmediate_operand" "%0")))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
- && ix86_binary_operator_ok (PLUS, SImode, operands)
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+ (compare
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:QI 2 "general_operand" "qmn,qn"))
+ (const_int 0)))
+ (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
+ (plus:QI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (PLUS, QImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return "inc{l}\t%k0";
+ return "inc{b}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%k0";
+ gcc_assert (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %k0|%k0, %2}";
- }
- return "add{l}\t{%2, %k0|%k0, %2}";
+ && INTVAL (operands[2]) < 0)
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{b}\t{%2, %0|%0, %2}";
+ }
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "QI")])
-; For comparisons against 1, -1 and 128, we may generate better code
-; by converting cmp to add, inc or dec as done by peephole2. This pattern
-; is matched then. We can't accept general immediate, because for
-; case of overflows, the result is messed up.
-; This pattern also don't hold of 0x80000000, since the value overflows
-; when negated.
-; Also carry flag is reversed compared to cmp, so this conversion is valid
-; only for comparisons not depending on it.
-(define_insn "*addsi_4"
+(define_insn "*add<mode>_3"
[(set (reg FLAGS_REG)
- (compare (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_scratch:SI 0 "=rm"))]
- "ix86_match_ccmode (insn, CCGCmode)
- && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
+ (compare
+ (neg:SWI48 (match_operand:SWI48 2 "<general_operand>" "<g>"))
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0")))
+ (clobber (match_scratch:SWI48 0 "=r"))]
+ "ix86_match_ccmode (insn, CCZmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ /* Current assemblers are broken and do not allow @GOTOFF in
+ ought but a memory context. */
+ && ! pic_symbolic_operand (operands[2], VOIDmode)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == constm1_rtx)
- return "inc{l}\t%0";
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ if (operands[2] == const1_rtx)
+ return "inc{<imodesuffix>}\t%0";
else
{
- gcc_assert (operands[2] == const1_rtx);
- return "dec{l}\t%0";
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{<imodesuffix>}\t%0";
}
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* ???? In DImode, we ought to handle there the 32bit case too
+ - do we need new constraint? */
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if ((INTVAL (operands[2]) == -128
- || (INTVAL (operands[2]) > 0
- && INTVAL (operands[2]) != 128)))
- return "sub{l}\t{%2, %0|%0, %2}";
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "add{l}\t{%2, %0|%0, %2}";
+ if (CONST_INT_P (operands[2])
+ /* Avoid overflows. */
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
+ && (INTVAL (operands[2]) == 128
+ || (INTVAL (operands[2]) < 0
+ && INTVAL (operands[2]) != -128)))
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
+ }
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*addsi_5"
+;; See comment for addsi_1_zext why we do use nonimmediate_operand
+(define_insn "*addsi_3_zext"
[(set (reg FLAGS_REG)
(compare
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "g"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ (neg:SI (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 1 "nonimmediate_operand" "%0")))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
+ && ix86_binary_operator_ok (PLUS, SImode, operands)
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
+ return "inc{l}\t%k0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ return "dec{l}\t%k0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
}
- return "add{l}\t{%2, %0|%0, %2}";
+ return "add{l}\t{%2, %k0|%k0, %2}";
}
}
[(set (attr "type")
(const_string "*")))
(set_attr "mode" "SI")])
-(define_expand "addhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))]
- "TARGET_HIMODE_MATH"
- "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
-
-;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
-;; type optimizations enabled by define-splits. This is not important
-;; for PII, and in fact harmful because of partial register stalls.
-
-(define_insn "*addhi_1_lea"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:HI 2 "general_operand" "rn,rm,ln")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, HImode, operands)"
+(define_insn "*addhi_3"
+ [(set (reg FLAGS_REG)
+ (compare
+ (neg:HI (match_operand:HI 2 "general_operand" "rmn"))
+ (match_operand:HI 1 "nonimmediate_operand" "%0")))
+ (clobber (match_scratch:HI 0 "=r"))]
+ "ix86_match_ccmode (insn, CCZmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
switch (get_attr_type (insn))
{
- case TYPE_LEA:
- return "#";
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{w}\t%0";
else
- {
+ {
gcc_assert (operands[2] == constm1_rtx);
return "dec{w}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
}
}
[(set (attr "type")
- (if_then_else (eq_attr "alternative" "2")
- (const_string "lea")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu"))))
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu")))
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "HI,HI,SI")])
+ (set_attr "mode" "HI")])
-(define_insn "*addhi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "rn,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, HImode, operands)"
+(define_insn "*addqi_3"
+ [(set (reg FLAGS_REG)
+ (compare
+ (neg:QI (match_operand:QI 2 "general_operand" "qmn"))
+ (match_operand:QI 1 "nonimmediate_operand" "%0")))
+ (clobber (match_scratch:QI 0 "=q"))]
+ "ix86_match_ccmode (insn, CCZmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ return "inc{b}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
+ && INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
- return "add{w}\t{%2, %0|%0, %2}";
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "HI")])
+ (set_attr "mode" "QI")])
-(define_insn "*addhi_2"
+; For comparisons against 1, -1 and 128, we may generate better code
+; by converting cmp to add, inc or dec as done by peephole2. This pattern
+; is matched then. We can't accept general immediate, because for
+; case of overflows, the result is messed up.
+; This pattern also don't hold of 0x8000000000000000, since the value
+; overflows when negated.
+; Also carry flag is reversed compared to cmp, so this conversion is valid
+; only for comparisons not depending on it.
+
+(define_insn "*adddi_4"
[(set (reg FLAGS_REG)
(compare
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "rmn,rn"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
- (plus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, HImode, operands)"
+ (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:DI 2 "x86_64_immediate_operand" "e")))
+ (clobber (match_scratch:DI 0 "=rm"))]
+ "TARGET_64BIT
+ && ix86_match_ccmode (insn, CCGCmode)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ if (operands[2] == constm1_rtx)
+ return "inc{q}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{q}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
- }
- return "add{w}\t{%2, %0|%0, %2}";
+ if ((INTVAL (operands[2]) == -128
+ || (INTVAL (operands[2]) > 0
+ && INTVAL (operands[2]) != 128))
+ /* Avoid overflows. */
+ && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
+ return "sub{q}\t{%2, %0|%0, %2}";
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "add{q}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (if_then_else (match_operand:DI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "HI")])
+ (set_attr "mode" "DI")])
-(define_insn "*addhi_3"
+; For comparisons against 1, -1 and 128, we may generate better code
+; by converting cmp to add, inc or dec as done by peephole2. This pattern
+; is matched then. We can't accept general immediate, because for
+; case of overflows, the result is messed up.
+; This pattern also don't hold of 0x80000000, since the value overflows
+; when negated.
+; Also carry flag is reversed compared to cmp, so this conversion is valid
+; only for comparisons not depending on it.
+
+(define_insn "*addsi_4"
[(set (reg FLAGS_REG)
- (compare (neg:HI (match_operand:HI 2 "general_operand" "rmn"))
- (match_operand:HI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:HI 0 "=r"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ (compare
+ (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "const_int_operand" "n")))
+ (clobber (match_scratch:SI 0 "=rm"))]
+ "ix86_match_ccmode (insn, CCGCmode)
+ && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ if (operands[2] == constm1_rtx)
+ return "inc{l}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{l}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
- }
- return "add{w}\t{%2, %0|%0, %2}";
+ if ((INTVAL (operands[2]) == -128
+ || (INTVAL (operands[2]) > 0
+ && INTVAL (operands[2]) != 128)))
+ return "sub{l}\t{%2, %0|%0, %2}";
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "add{l}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "HI")])
+ (set_attr "mode" "SI")])
; See comments above addsi_4 for details.
+
(define_insn "*addhi_4"
[(set (reg FLAGS_REG)
- (compare (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "const_int_operand" "n")))
+ (compare
+ (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:HI 2 "const_int_operand" "n")))
(clobber (match_scratch:HI 0 "=rm"))]
"ix86_match_ccmode (insn, CCGCmode)
&& (INTVAL (operands[2]) & 0xffff) != 0x8000"
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if ((INTVAL (operands[2]) == -128
|| (INTVAL (operands[2]) > 0
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "HI")])
+; See comments above addsi_4 for details.
-(define_insn "*addhi_5"
+(define_insn "*addqi_4"
[(set (reg FLAGS_REG)
(compare
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
- (match_operand:HI 2 "general_operand" "rmn"))
- (const_int 0)))
- (clobber (match_scratch:HI 0 "=r"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_operand" "n")))
+ (clobber (match_scratch:QI 0 "=qm"))]
+ "ix86_match_ccmode (insn, CCGCmode)
+ && (INTVAL (operands[2]) & 0xff) != 0x80"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ if (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255))
+ return "inc{b}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
- }
- return "add{w}\t{%2, %0|%0, %2}";
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ if (INTVAL (operands[2]) < 0)
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "add{b}\t{%2, %0|%0, %2}";
+ }
+ return "sub{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-(define_expand "addqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))]
- "TARGET_QIMODE_MATH"
- "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
+ (set_attr "mode" "QI")])
-;; %%% Potential partial reg stall on alternative 2. What to do?
-(define_insn "*addqi_1_lea"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
- (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, QImode, operands)"
+(define_insn "*add<mode>_5"
+ [(set (reg FLAGS_REG)
+ (compare
+ (plus:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0")
+ (match_operand:SWI48 2 "<general_operand>" "<g>"))
+ (const_int 0)))
+ (clobber (match_scratch:SWI48 0 "=r"))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ /* Current assemblers are broken and do not allow @GOTOFF in
+ ought but a memory context. */
+ && ! pic_symbolic_operand (operands[2], VOIDmode)"
{
- int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
- case TYPE_LEA:
- return "#";
case TYPE_INCDEC:
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
+ return "inc{<imodesuffix>}\t%0";
else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{<imodesuffix>}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
+ /* Avoid overflows. */
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- if (widen)
- return "sub{l}\t{%2, %k0|%k0, %2}";
- else
- return "sub{b}\t{%2, %0|%0, %2}";
- }
- if (widen)
- return "add{l}\t{%k2, %k0|%k0, %k2}";
- else
- return "add{b}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
+ }
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (eq_attr "alternative" "3")
- (const_string "lea")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu"))))
+ (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu")))
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "QI,QI,SI,SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*addqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, QImode, operands)"
+(define_insn "*addhi_5"
+ [(set (reg FLAGS_REG)
+ (compare
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
+ (match_operand:HI 2 "general_operand" "rmn"))
+ (const_int 0)))
+ (clobber (match_scratch:HI 0 "=r"))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
- int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
+ return "inc{w}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
+ return "dec{w}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- if (widen)
- return "sub{l}\t{%2, %k0|%k0, %2}";
- else
- return "sub{b}\t{%2, %0|%0, %2}";
+ return "sub{w}\t{%2, %0|%0, %2}";
}
- if (widen)
- return "add{l}\t{%k2, %k0|%k0, %k2}";
- else
- return "add{b}\t{%2, %0|%0, %2}";
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "QI,QI,SI")])
+ (set_attr "mode" "HI")])
-(define_insn "*addqi_1_slp"
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
- (plus:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qn,qnm")))
- (clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+(define_insn "*addqi_5"
+ [(set (reg FLAGS_REG)
+ (compare
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
+ (match_operand:QI 2 "general_operand" "qmn"))
+ (const_int 0)))
+ (clobber (match_scratch:QI 0 "=q"))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[1] == const1_rtx)
+ if (operands[2] == const1_rtx)
return "inc{b}\t%0";
else
- {
- gcc_assert (operands[1] == constm1_rtx);
+ {
+ gcc_assert (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255));
return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
- if (CONST_INT_P (operands[1])
- && INTVAL (operands[1]) < 0)
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
+ if (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) < 0)
{
- operands[1] = GEN_INT (-INTVAL (operands[1]));
- return "sub{b}\t{%1, %0|%0, %1}";
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{b}\t{%2, %0|%0, %2}";
}
- return "add{b}\t{%1, %0|%0, %1}";
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 1 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
- (const_string "alu1")))
- (set (attr "memory")
- (if_then_else (match_operand 1 "memory_operand" "")
- (const_string "load")
- (const_string "none")))
+ (const_string "alu")))
(set_attr "mode" "QI")])
-(define_insn "*addqi_2"
- [(set (reg FLAGS_REG)
- (compare
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qmn,qn"))
- (const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
- (plus:QI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, QImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
-
- default:
- /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
- if (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) < 0)
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{b}\t{%2, %0|%0, %2}";
- }
- return "add{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
-(define_insn "*addqi_3"
- [(set (reg FLAGS_REG)
- (compare (neg:QI (match_operand:QI 2 "general_operand" "qmn"))
- (match_operand:QI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:QI 0 "=q"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
-
- default:
- /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
- if (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) < 0)
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{b}\t{%2, %0|%0, %2}";
- }
- return "add{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
-; See comments above addsi_4 for details.
-(define_insn "*addqi_4"
- [(set (reg FLAGS_REG)
- (compare (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_operand" "n")))
- (clobber (match_scratch:QI 0 "=qm"))]
- "ix86_match_ccmode (insn, CCGCmode)
- && (INTVAL (operands[2]) & 0xff) != 0x80"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255))
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == const1_rtx);
- return "dec{b}\t%0";
- }
-
- default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- if (INTVAL (operands[2]) < 0)
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "add{b}\t{%2, %0|%0, %2}";
- }
- return "sub{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
-
-(define_insn "*addqi_5"
- [(set (reg FLAGS_REG)
- (compare
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "general_operand" "qmn"))
- (const_int 0)))
- (clobber (match_scratch:QI 0 "=q"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
-
- default:
- /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
- if (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) < 0)
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{b}\t{%2, %0|%0, %2}";
- }
- return "add{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
-
-(define_insn "addqi_ext_1"
+(define_insn "*addqi_ext_1_rex64"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
- (match_operand:QI 2 "general_operand" "Qmn")))
+ (match_operand:QI 2 "nonmemory_operand" "Qn")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT"
+ "TARGET_64BIT"
{
switch (get_attr_type (insn))
{
|| (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) == 255));
return "dec{b}\t%h0";
- }
+ }
default:
return "add{b}\t{%2, %h0|%h0, %2}";
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
-(define_insn "*addqi_ext_1_rex64"
+(define_insn "addqi_ext_1"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
- (match_operand:QI 2 "nonmemory_operand" "Qn")))
+ (match_operand:QI 2 "general_operand" "Qmn")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
+ "!TARGET_64BIT"
{
switch (get_attr_type (insn))
{
|| (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) == 255));
return "dec{b}\t%h0";
- }
+ }
default:
return "add{b}\t{%2, %h0|%h0, %2}";
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_2"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-;; The patterns that match these are at the end of this file.
-
-(define_expand "addxf3"
- [(set (match_operand:XF 0 "register_operand" "")
- (plus:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
- "TARGET_80387"
- "")
-
-(define_expand "add<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "")
- (plus:MODEF (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
- "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
- || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
- "")
-\f
-;; Subtract instructions
+;; The lea patterns for non-Pmodes needs to be matched by
+;; several insns converted to real lea by splitters.
-;; %%% splits for subditi3
+(define_insn_and_split "*lea_general_1"
+ [(set (match_operand 0 "register_operand" "=r")
+ (plus (plus (match_operand 1 "index_register_operand" "l")
+ (match_operand 2 "register_operand" "r"))
+ (match_operand 3 "immediate_operand" "i")))]
+ "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
+ || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE (operands[0]) == GET_MODE (operands[2])
+ && (GET_MODE (operands[0]) == GET_MODE (operands[3])
+ || GET_MODE (operands[3]) == VOIDmode)"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx pat;
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
+ operands[3]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_expand "subti3"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))]
+(define_insn_and_split "*lea_general_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (plus:SI (plus:SI
+ (match_operand:SI 1 "index_register_operand" "l")
+ (match_operand:SI 2 "register_operand" "r"))
+ (match_operand:SI 3 "immediate_operand" "i"))))]
"TARGET_64BIT"
- "ix86_expand_binary_operator (MINUS, TImode, operands); DONE;")
-
-(define_insn "*subti3_1"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
- (minus:TI (match_operand:TI 1 "nonimmediate_operand" "0,0")
- (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (MINUS, TImode, operands)"
- "#")
-
-(define_split
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))])
- (parallel [(set (match_dup 3)
- (minus:DI (match_dup 4)
- (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 5))))
- (clobber (reg:CC FLAGS_REG))])]
- "split_ti (&operands[0], 3, &operands[0], &operands[3]);")
-
-;; %%% splits for subsidi3
-
-(define_expand "subdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))]
- ""
- "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
-
-(define_insn "*subdi3_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "general_operand" "roiF,riF")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "#")
-
-(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (parallel [(set (match_dup 3)
- (minus:SI (match_dup 4)
- (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 5))))
- (clobber (reg:CC FLAGS_REG))])]
- "split_di (&operands[0], 3, &operands[0], &operands[3]);")
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_insn "subdi3_carry_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sbb{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "DI")])
+(define_insn_and_split "*lea_general_2"
+ [(set (match_operand 0 "register_operand" "=r")
+ (plus (mult (match_operand 1 "index_register_operand" "l")
+ (match_operand 2 "const248_operand" "i"))
+ (match_operand 3 "nonmemory_operand" "ri")))]
+ "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
+ || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && (GET_MODE (operands[0]) == GET_MODE (operands[3])
+ || GET_MODE (operands[3]) == VOIDmode)"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx pat;
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
+ operands[3]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_insn "*subdi_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sub{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
+(define_insn_and_split "*lea_general_2_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (plus:SI (mult:SI
+ (match_operand:SI 1 "index_register_operand" "l")
+ (match_operand:SI 2 "const248_operand" "n"))
+ (match_operand:SI 3 "nonmemory_operand" "ri"))))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_insn "*subdi_2_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sub{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
+(define_insn_and_split "*lea_general_3"
+ [(set (match_operand 0 "register_operand" "=r")
+ (plus (plus (mult (match_operand 1 "index_register_operand" "l")
+ (match_operand 2 "const248_operand" "i"))
+ (match_operand 3 "register_operand" "r"))
+ (match_operand 4 "immediate_operand" "i")))]
+ "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
+ || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE (operands[0]) == GET_MODE (operands[3])"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx pat;
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ operands[4] = gen_lowpart (Pmode, operands[4]);
+ pat = gen_rtx_PLUS (Pmode,
+ gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
+ operands[2]),
+ operands[3]),
+ operands[4]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_insn "*subdi_3_rex63"
- [(set (reg FLAGS_REG)
- (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
+(define_insn_and_split "*lea_general_3_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (plus:SI (plus:SI
+ (mult:SI
+ (match_operand:SI 1 "index_register_operand" "l")
+ (match_operand:SI 2 "const248_operand" "n"))
+ (match_operand:SI 3 "register_operand" "r"))
+ (match_operand:SI 4 "immediate_operand" "i"))))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3))
+ (match_dup 4)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ operands[4] = gen_lowpart (Pmode, operands[4]);
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_insn "subqi3_carry"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
- (match_operand:QI 2 "general_operand" "qn,qm"))))
+;; Convert lea to the lea pattern to avoid flags dependency.
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (plus:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sbb{b}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "QI")])
+ "TARGET_64BIT && reload_completed
+ && ix86_lea_for_add_ok (PLUS, insn, operands)"
+ [(set (match_dup 0)
+ (plus:DI (match_dup 1)
+ (match_dup 2)))]
+ "")
-(define_insn "subhi3_carry"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
- (match_operand:HI 2 "general_operand" "rn,rm"))))
+;; Convert lea to the lea pattern to avoid flags dependency.
+(define_split
+ [(set (match_operand 0 "register_operand" "")
+ (plus (match_operand 1 "register_operand" "")
+ (match_operand 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sbb{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "HI")])
+ "reload_completed && ix86_lea_for_add_ok (PLUS, insn, operands)"
+ [(const_int 0)]
+{
+ rtx pat;
+ /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
+ may confuse gen_lowpart. */
+ if (GET_MODE (operands[0]) != Pmode)
+ {
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+ }
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+})
-(define_insn "subsi3_carry"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 2 "general_operand" "ri,rm"))))
+;; Convert lea to the lea pattern to avoid flags dependency.
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:DI
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" ""))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed
+ && true_regnum (operands[0]) != true_regnum (operands[1])"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+})
+\f
+;; Subtract instructions
+
+(define_expand "sub<mode>3"
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
+ (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
+ (match_operand:SDWIM 2 "<general_operand>" "")))]
+ ""
+ "ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;")
+
+(define_insn_and_split "*sub<dwi>3_doubleword"
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
+ (minus:<DWI>
+ (match_operand:<DWI> 1 "nonimmediate_operand" "0,0")
+ (match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sbb{l}\t{%2, %0|%0, %2}"
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "#"
+ "reload_completed"
+ [(parallel [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (set (match_dup 0)
+ (minus:DWIH (match_dup 1) (match_dup 2)))])
+ (parallel [(set (match_dup 3)
+ (minus:DWIH
+ (match_dup 4)
+ (plus:DWIH
+ (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+ (match_dup 5))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
+
+(define_insn "sub<mode>3_carry"
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (plus:SWI
+ (match_operand:SWI 3 "ix86_carry_flag_operator" "")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))))
+ (clobber (reg:CC FLAGS_REG))]
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sbb{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "subsi3_carry_zext"
+(define_insn "*subsi3_carry_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 1 "register_operand" "0")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
-(define_expand "subsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))]
+(define_insn "*sub<mode>3_cconly_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (minus:SWI
+ (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
+ (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
+ (match_dup 0)))]
""
- "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
+ "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "icmp")
+ (set_attr "mode" "<MODE>")])
-(define_insn "*subsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")))
+(define_insn "*sub<mode>_1"
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %0|%0, %2}"
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*subsi_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*subsi_2"
+(define_insn "*subqi_1_slp"
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
+ (minus:QI (match_dup 0)
+ (match_operand:QI 1 "general_operand" "qn,qm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "sub{b}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")
+ (set_attr "mode" "QI")])
+
+(define_insn "*sub<mode>_2"
[(set (reg FLAGS_REG)
(compare
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm"))
+ (minus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
(const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*subsi_2_zext"
[(set (reg FLAGS_REG)
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*subsi_3"
+(define_insn "*sub<mode>_3"
[(set (reg FLAGS_REG)
- (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_dup 1) (match_dup 2)))]
+ (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*subsi_3_zext"
[(set (reg FLAGS_REG)
&& ix86_binary_operator_ok (MINUS, SImode, operands)"
"sub{l}\t{%2, %1|%1, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "DI")])
-
-(define_expand "subhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))]
- "TARGET_HIMODE_MATH"
- "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
-
-(define_insn "*subhi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (match_operand:HI 2 "general_operand" "rn,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "HI")])
-
-(define_insn "*subhi_2"
- [(set (reg FLAGS_REG)
- (compare
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (match_operand:HI 2 "general_operand" "rn,rm"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "HI")])
-
-(define_insn "*subhi_3"
- [(set (reg FLAGS_REG)
- (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (match_operand:HI 2 "general_operand" "rn,rm")))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "HI")])
-
-(define_expand "subqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))]
- "TARGET_QIMODE_MATH"
- "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
-
-(define_insn "*subqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "general_operand" "qn,qm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "SI")])
-(define_insn "*subqi_1_slp"
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
- (minus:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qn,qm")))
- (clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "sub{b}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "mode" "QI")])
-(define_insn "*subqi_2"
- [(set (reg FLAGS_REG)
- (compare
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "general_operand" "qn,qm"))
- (const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (minus:QI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\t{%2, %0|%0, %2}"
+(define_insn "*<plusminus_insn><mode>3_cc_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (plusminus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
+ (match_dup 1)))
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (plusminus:SWI (match_dup 1) (match_dup 2)))]
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*subqi_3"
- [(set (reg FLAGS_REG)
- (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "general_operand" "qn,qm")))
- (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (minus:QI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\t{%2, %0|%0, %2}"
+(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (plusminus:SI
+ (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
+ (match_operand:SI 2 "general_operand" "g"))
+ (match_dup 1)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+ "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "SI")])
;; The patterns that match these are at the end of this file.
-(define_expand "subxf3"
+(define_expand "<plusminus_insn>xf3"
[(set (match_operand:XF 0 "register_operand" "")
- (minus:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ (plusminus:XF
+ (match_operand:XF 1 "register_operand" "")
+ (match_operand:XF 2 "register_operand" "")))]
"TARGET_80387"
"")
-(define_expand "sub<mode>3"
+(define_expand "<plusminus_insn><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "")
- (minus:MODEF (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+ (plusminus:MODEF
+ (match_operand:MODEF 1 "register_operand" "")
+ (match_operand:MODEF 2 "nonimmediate_operand" "")))]
"(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
\f
;; Multiply instructions
-(define_expand "muldi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))
+(define_expand "mul<mode>3"
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ (mult:SWIM248
+ (match_operand:SWIM248 1 "register_operand" "")
+ (match_operand:SWIM248 2 "<general_operand>" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
+ ""
"")
-;; On AMDFAM10
-;; IMUL reg64, reg64, imm8 Direct
-;; IMUL reg64, mem64, imm8 VectorPath
-;; IMUL reg64, reg64, imm32 Direct
-;; IMUL reg64, mem64, imm32 VectorPath
-;; IMUL reg64, reg64 Direct
-;; IMUL reg64, mem64 Direct
-
-(define_insn "*muldi3_1_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "@
- imul{q}\t{%2, %1, %0|%0, %1, %2}
- imul{q}\t{%2, %1, %0|%0, %1, %2}
- imul{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "imul")
- (set_attr "prefix_0f" "0,0,1")
- (set (attr "athlon_decode")
- (cond [(eq_attr "cpu" "athlon")
- (const_string "vector")
- (eq_attr "alternative" "1")
- (const_string "vector")
- (and (eq_attr "alternative" "2")
- (match_operand 1 "memory_operand" ""))
- (const_string "vector")]
- (const_string "direct")))
- (set (attr "amdfam10_decode")
- (cond [(and (eq_attr "alternative" "0,1")
- (match_operand 1 "memory_operand" ""))
- (const_string "vector")]
- (const_string "direct")))
- (set_attr "mode" "DI")])
-
-(define_expand "mulsi3"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "general_operand" "")))
+(define_expand "mulqi3"
+ [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ (mult:QI
+ (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "nonimmediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- ""
+ "TARGET_QIMODE_MATH"
"")
;; On AMDFAM10
-;; IMUL reg32, reg32, imm8 Direct
-;; IMUL reg32, mem32, imm8 VectorPath
-;; IMUL reg32, reg32, imm32 Direct
-;; IMUL reg32, mem32, imm32 VectorPath
-;; IMUL reg32, reg32 Direct
-;; IMUL reg32, mem32 Direct
-
-(define_insn "*mulsi3_1"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:SI 2 "general_operand" "K,i,mr")))
+;; IMUL reg32/64, reg32/64, imm8 Direct
+;; IMUL reg32/64, mem32/64, imm8 VectorPath
+;; IMUL reg32/64, reg32/64, imm32 Direct
+;; IMUL reg32/64, mem32/64, imm32 VectorPath
+;; IMUL reg32/64, reg32/64 Direct
+;; IMUL reg32/64, mem32/64 Direct
+
+(define_insn "*mul<mode>3_1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r,r,r")
+ (mult:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%rm,rm,0")
+ (match_operand:SWI48 2 "<general_operand>" "K,<i>,mr")))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
- imul{l}\t{%2, %1, %0|%0, %1, %2}
- imul{l}\t{%2, %1, %0|%0, %1, %2}
- imul{l}\t{%2, %0|%0, %2}"
+ imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ imul{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
(match_operand 1 "memory_operand" ""))
(const_string "vector")]
(const_string "direct")))
- (set_attr "mode" "SI")])
-
-(define_insn "*mulsi3_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (zero_extend:DI
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:SI 2 "general_operand" "K,i,mr"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "@
- imul{l}\t{%2, %1, %k0|%k0, %1, %2}
- imul{l}\t{%2, %1, %k0|%k0, %1, %2}
- imul{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "imul")
- (set_attr "prefix_0f" "0,0,1")
- (set (attr "athlon_decode")
- (cond [(eq_attr "cpu" "athlon")
- (const_string "vector")
- (eq_attr "alternative" "1")
- (const_string "vector")
- (and (eq_attr "alternative" "2")
- (match_operand 1 "memory_operand" ""))
- (const_string "vector")]
- (const_string "direct")))
- (set (attr "amdfam10_decode")
- (cond [(and (eq_attr "alternative" "0,1")
- (match_operand 1 "memory_operand" ""))
- (const_string "vector")]
- (const_string "direct")))
- (set_attr "mode" "SI")])
-
-(define_expand "mulhi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
- (mult:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_HIMODE_MATH"
- "")
-
-;; On AMDFAM10
-;; IMUL reg16, reg16, imm8 VectorPath
-;; IMUL reg16, mem16, imm8 VectorPath
-;; IMUL reg16, reg16, imm16 VectorPath
-;; IMUL reg16, mem16, imm16 VectorPath
-;; IMUL reg16, reg16 Direct
-;; IMUL reg16, mem16 Direct
-(define_insn "*mulhi3_1"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r")
- (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:HI 2 "general_operand" "K,n,mr")))
- (clobber (reg:CC FLAGS_REG))]
- "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "@
- imul{w}\t{%2, %1, %0|%0, %1, %2}
- imul{w}\t{%2, %1, %0|%0, %1, %2}
- imul{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "imul")
- (set_attr "prefix_0f" "0,0,1")
- (set (attr "athlon_decode")
- (cond [(eq_attr "cpu" "athlon")
- (const_string "vector")
- (eq_attr "alternative" "1,2")
- (const_string "vector")]
- (const_string "direct")))
- (set (attr "amdfam10_decode")
- (cond [(eq_attr "alternative" "0,1")
- (const_string "vector")]
- (const_string "direct")))
- (set_attr "mode" "HI")])
-
-(define_expand "mulqi3"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
- (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "")
-
-;;On AMDFAM10
-;; MUL reg8 Direct
-;; MUL mem8 Direct
-
-(define_insn "*mulqi3_1"
- [(set (match_operand:QI 0 "register_operand" "=a")
- (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{b}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "direct")))
- (set_attr "amdfam10_decode" "direct")
- (set_attr "mode" "QI")])
-
-(define_expand "umulqihi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
- (mult:HI (zero_extend:HI
- (match_operand:QI 1 "nonimmediate_operand" ""))
- (zero_extend:HI
- (match_operand:QI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "")
-
-(define_insn "*umulqihi3_1"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
- (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{b}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "direct")))
- (set_attr "amdfam10_decode" "direct")
- (set_attr "mode" "QI")])
-
-(define_expand "mulqihi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
- (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
- (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "")
-
-(define_insn "*mulqihi3_insn"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
- (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{b}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "direct")))
- (set_attr "amdfam10_decode" "direct")
- (set_attr "mode" "QI")])
-
-(define_expand "umulditi3"
- [(parallel [(set (match_operand:TI 0 "register_operand" "")
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (zero_extend:TI
- (match_operand:DI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
-
-(define_insn "*umulditi3_insn"
- [(set (match_operand:TI 0 "register_operand" "=A")
- (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
- (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{q}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "DI")])
-
-;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
-(define_expand "umulsidi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (zero_extend:DI
- (match_operand:SI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "!TARGET_64BIT"
- "")
-
-(define_insn "*umulsidi3_insn"
- [(set (match_operand:DI 0 "register_operand" "=A")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
- (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{l}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
-
-(define_expand "mulditi3"
- [(parallel [(set (match_operand:TI 0 "register_operand" "")
- (mult:TI (sign_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (sign_extend:TI
- (match_operand:DI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
+ (set_attr "mode" "<MODE>")])
-(define_insn "*mulditi3_insn"
- [(set (match_operand:TI 0 "register_operand" "=A")
- (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
- (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
+(define_insn "*mulsi3_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+ (zero_extend:DI
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
+ (match_operand:SI 2 "general_operand" "K,i,mr"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{q}\t%2"
+ "@
+ imul{l}\t{%2, %1, %k0|%k0, %1, %2}
+ imul{l}\t{%2, %1, %k0|%k0, %1, %2}
+ imul{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
+ (set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "DI")])
+ (cond [(eq_attr "cpu" "athlon")
+ (const_string "vector")
+ (eq_attr "alternative" "1")
+ (const_string "vector")
+ (and (eq_attr "alternative" "2")
+ (match_operand 1 "memory_operand" ""))
+ (const_string "vector")]
+ (const_string "direct")))
+ (set (attr "amdfam10_decode")
+ (cond [(and (eq_attr "alternative" "0,1")
+ (match_operand 1 "memory_operand" ""))
+ (const_string "vector")]
+ (const_string "direct")))
+ (set_attr "mode" "SI")])
-(define_expand "mulsidi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (sign_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (sign_extend:DI
- (match_operand:SI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "!TARGET_64BIT"
- "")
+;; On AMDFAM10
+;; IMUL reg16, reg16, imm8 VectorPath
+;; IMUL reg16, mem16, imm8 VectorPath
+;; IMUL reg16, reg16, imm16 VectorPath
+;; IMUL reg16, mem16, imm16 VectorPath
+;; IMUL reg16, reg16 Direct
+;; IMUL reg16, mem16 Direct
-(define_insn "*mulsidi3_insn"
- [(set (match_operand:DI 0 "register_operand" "=A")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
- (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
+(define_insn "*mulhi3_1"
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+ (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
+ (match_operand:HI 2 "general_operand" "K,n,mr")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT
+ "TARGET_HIMODE_MATH
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{l}\t%2"
+ "@
+ imul{w}\t{%2, %1, %0|%0, %1, %2}
+ imul{w}\t{%2, %1, %0|%0, %1, %2}
+ imul{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
+ (set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
+ (cond [(eq_attr "cpu" "athlon")
+ (const_string "vector")
+ (eq_attr "alternative" "1,2")
+ (const_string "vector")]
+ (const_string "direct")))
+ (set (attr "amdfam10_decode")
+ (cond [(eq_attr "alternative" "0,1")
+ (const_string "vector")]
+ (const_string "direct")))
+ (set_attr "mode" "HI")])
-(define_expand "umuldi3_highpart"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (zero_extend:TI
- (match_operand:DI 2 "register_operand" "")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
+;;On AMDFAM10
+;; MUL reg8 Direct
+;; MUL mem8 Direct
-(define_insn "*umuldi3_highpart_rex64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" "%a"))
- (zero_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 "=1"))
+(define_insn "*mulqi3_1"
+ [(set (match_operand:QI 0 "register_operand" "=a")
+ (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
+ (match_operand:QI 2 "nonimmediate_operand" "qm")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
+ "TARGET_QIMODE_MATH
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{q}\t%2"
+ "mul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "DI")])
+ (const_string "direct")))
+ (set_attr "amdfam10_decode" "direct")
+ (set_attr "mode" "QI")])
-(define_expand "umulsi3_highpart"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (zero_extend:DI
- (match_operand:SI 2 "register_operand" "")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 ""))
+(define_expand "<u>mul<mode><dwi>3"
+ [(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ (mult:<DWI>
+ (any_extend:<DWI>
+ (match_operand:DWIH 1 "nonimmediate_operand" ""))
+ (any_extend:<DWI>
+ (match_operand:DWIH 2 "register_operand" ""))))
(clobber (reg:CC FLAGS_REG))])]
""
"")
-(define_insn "*umulsi3_highpart_insn"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "%a"))
- (zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=1"))
+(define_expand "<u>mulqihi3"
+ [(parallel [(set (match_operand:HI 0 "register_operand" "")
+ (mult:HI
+ (any_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" ""))
+ (any_extend:HI
+ (match_operand:QI 2 "register_operand" ""))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_QIMODE_MATH"
+ "")
+
+(define_insn "*<u>mul<mode><dwi>3_1"
+ [(set (match_operand:<DWI> 0 "register_operand" "=A")
+ (mult:<DWI>
+ (any_extend:<DWI>
+ (match_operand:DWIH 1 "nonimmediate_operand" "%0"))
+ (any_extend:<DWI>
+ (match_operand:DWIH 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{l}\t%2"
+ "<sgnprefix>mul{<imodesuffix>}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(const_string "vector")
(const_string "double")))
(set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*umulsi3_highpart_zext"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "%a"))
- (zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (const_int 32)))))
- (clobber (match_scratch:SI 3 "=1"))
+(define_insn "*<u>mulqihi3_1"
+ [(set (match_operand:HI 0 "register_operand" "=a")
+ (mult:HI
+ (any_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "%0"))
+ (any_extend:HI
+ (match_operand:QI 2 "nonimmediate_operand" "qm"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
+ "TARGET_QIMODE_MATH
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{l}\t%2"
+ "<sgnprefix>mul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
+ (const_string "direct")))
+ (set_attr "amdfam10_decode" "direct")
+ (set_attr "mode" "QI")])
-(define_expand "smuldi3_highpart"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (sign_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (sign_extend:TI
- (match_operand:DI 2 "register_operand" "")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 ""))
+(define_expand "<s>mul<mode>3_highpart"
+ [(parallel [(set (match_operand:SWI48 0 "register_operand" "")
+ (truncate:SWI48
+ (lshiftrt:<DWI>
+ (mult:<DWI>
+ (any_extend:<DWI>
+ (match_operand:SWI48 1 "nonimmediate_operand" ""))
+ (any_extend:<DWI>
+ (match_operand:SWI48 2 "register_operand" "")))
+ (match_dup 4))))
+ (clobber (match_scratch:SWI48 3 ""))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
+ ""
+ "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
-(define_insn "*smuldi3_highpart_rex64"
+(define_insn "*<s>muldi3_highpart_1"
[(set (match_operand:DI 0 "register_operand" "=d")
(truncate:DI
(lshiftrt:TI
- (mult:TI (sign_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" "%a"))
- (sign_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
+ (mult:TI
+ (any_extend:TI
+ (match_operand:DI 1 "nonimmediate_operand" "%a"))
+ (any_extend:TI
+ (match_operand:DI 2 "nonimmediate_operand" "rm")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=1"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{q}\t%2"
+ "<sgnprefix>mul{q}\t%2"
[(set_attr "type" "imul")
+ (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(set_attr "amdfam10_decode" "double")
(set_attr "mode" "DI")])
-(define_expand "smulsi3_highpart"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (sign_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (sign_extend:DI
- (match_operand:SI 2 "register_operand" "")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC FLAGS_REG))])]
- ""
- "")
-
-(define_insn "*smulsi3_highpart_insn"
+(define_insn "*<s>mulsi3_highpart_1"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
- (mult:DI (sign_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "%a"))
- (sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
+ (mult:DI
+ (any_extend:DI
+ (match_operand:SI 1 "nonimmediate_operand" "%a"))
+ (any_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=1"))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{l}\t%2"
+ "<sgnprefix>mul{l}\t%2"
[(set_attr "type" "imul")
+ (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(set_attr "amdfam10_decode" "double")
(set_attr "mode" "SI")])
-(define_insn "*smulsi3_highpart_zext"
+(define_insn "*<s>mulsi3_highpart_zext"
[(set (match_operand:DI 0 "register_operand" "=d")
(zero_extend:DI (truncate:SI
(lshiftrt:DI
- (mult:DI (sign_extend:DI
+ (mult:DI (any_extend:DI
(match_operand:SI 1 "nonimmediate_operand" "%a"))
- (sign_extend:DI
+ (any_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32)))))
(clobber (match_scratch:SI 3 "=1"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{l}\t%2"
+ "<sgnprefix>mul{l}\t%2"
[(set_attr "type" "imul")
+ (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
"(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
-
-;; SSE5 scalar multiply/add instructions are defined in sse.md.
-
\f
;; Divide instructions
-(define_insn "divqi3"
- [(set (match_operand:QI 0 "register_operand" "=a")
- (div:QI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH"
- "idiv{b}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "QI")])
-
-(define_insn "udivqi3"
+(define_insn "<u>divqi3"
[(set (match_operand:QI 0 "register_operand" "=a")
- (udiv:QI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "nonimmediate_operand" "qm")))
+ (any_div:QI
+ (match_operand:HI 1 "register_operand" "0")
+ (match_operand:QI 2 "nonimmediate_operand" "qm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
- "div{b}\t%2"
+ "<sgnprefix>div{b}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "QI")])
}
})
\f
-;; Remainder instructions.
-
-(define_expand "divmoddi4"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (div:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonimmediate_operand" "")))
- (set (match_operand:DI 3 "register_operand" "")
- (mod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
-
-;; Allow to come the parameter in eax or edx to avoid extra moves.
-;; Penalize eax case slightly because it results in worse scheduling
-;; of code.
-(define_insn "*divmoddi4_nocltd_rex64"
- [(set (match_operand:DI 0 "register_operand" "=&a,?a")
- (div:DI (match_operand:DI 2 "register_operand" "1,0")
- (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
- (set (match_operand:DI 1 "register_operand" "=&d,&d")
- (mod:DI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && optimize_function_for_speed_p (cfun) && !TARGET_USE_CLTD"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmoddi4_cltd_rex64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (div:DI (match_operand:DI 2 "register_operand" "a")
- (match_operand:DI 3 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 1 "register_operand" "=&d")
- (mod:DI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmoddi_noext_rex64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (div:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 3 "register_operand" "=d")
- (mod:DI (match_dup 1) (match_dup 2)))
- (use (match_operand:DI 4 "register_operand" "3"))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "idiv{q}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (div:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonimmediate_operand" "")))
- (set (match_operand:DI 3 "register_operand" "")
- (mod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (match_dup 3)
- (ashiftrt:DI (match_dup 4) (const_int 63)))
- (clobber (reg:CC FLAGS_REG))])
- (parallel [(set (match_dup 0)
- (div:DI (reg:DI 0) (match_dup 2)))
- (set (match_dup 3)
- (mod:DI (reg:DI 0) (match_dup 2)))
- (use (match_dup 3))
- (clobber (reg:CC FLAGS_REG))])]
-{
- /* Avoid use of cltd in favor of a mov+shift. */
- if (!TARGET_USE_CLTD && optimize_function_for_speed_p (cfun))
- {
- if (true_regnum (operands[1]))
- emit_move_insn (operands[0], operands[1]);
- else
- emit_move_insn (operands[3], operands[1]);
- operands[4] = operands[3];
- }
- else
- {
- gcc_assert (!true_regnum (operands[1]));
- operands[4] = operands[1];
- }
-})
-
-
-(define_expand "divmodsi4"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (div:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
- (set (match_operand:SI 3 "register_operand" "")
- (mod:SI (match_dup 1) (match_dup 2)))
+;; Divmod instructions.
+
+(define_expand "divmod<mode>4"
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ (div:SWIM248
+ (match_operand:SWIM248 1 "register_operand" "")
+ (match_operand:SWIM248 2 "nonimmediate_operand" "")))
+ (set (match_operand:SWIM248 3 "register_operand" "")
+ (mod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
""
"")
-;; Allow to come the parameter in eax or edx to avoid extra moves.
-;; Penalize eax case slightly because it results in worse scheduling
-;; of code.
-(define_insn "*divmodsi4_nocltd"
- [(set (match_operand:SI 0 "register_operand" "=&a,?a")
- (div:SI (match_operand:SI 2 "register_operand" "1,0")
- (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
- (set (match_operand:SI 1 "register_operand" "=&d,&d")
- (mod:SI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "optimize_function_for_speed_p (cfun) && !TARGET_USE_CLTD"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmodsi4_cltd"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (div:SI (match_operand:SI 2 "register_operand" "a")
- (match_operand:SI 3 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 1 "register_operand" "=&d")
- (mod:SI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "optimize_function_for_size_p (cfun) || TARGET_USE_CLTD"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmodsi_noext"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (div:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 3 "register_operand" "=d")
- (mod:SI (match_dup 1) (match_dup 2)))
- (use (match_operand:SI 4 "register_operand" "3"))
+(define_insn_and_split "*divmod<mode>4"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=&d")
+ (mod:SWIM248 (match_dup 2) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))]
""
- "idiv{l}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (div:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
- (set (match_operand:SI 3 "register_operand" "")
- (mod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed"
- [(parallel [(set (match_dup 3)
- (ashiftrt:SI (match_dup 4) (const_int 31)))
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 1)
+ (ashiftrt:SWIM248 (match_dup 4) (match_dup 5)))
(clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_dup 0)
- (div:SI (reg:SI 0) (match_dup 2)))
- (set (match_dup 3)
- (mod:SI (reg:SI 0) (match_dup 2)))
- (use (match_dup 3))
+ (div:SWIM248 (match_dup 2) (match_dup 3)))
+ (set (match_dup 1)
+ (mod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_dup 1))
(clobber (reg:CC FLAGS_REG))])]
{
- /* Avoid use of cltd in favor of a mov+shift. */
- if (!TARGET_USE_CLTD && optimize_function_for_speed_p (cfun))
- {
- if (true_regnum (operands[1]))
- emit_move_insn (operands[0], operands[1]);
- else
- emit_move_insn (operands[3], operands[1]);
- operands[4] = operands[3];
- }
+ operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
+
+ if (<MODE>mode != HImode
+ && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
+ operands[4] = operands[2];
else
{
- gcc_assert (!true_regnum (operands[1]));
+ /* Avoid use of cltd in favor of a mov+shift. */
+ emit_move_insn (operands[1], operands[2]);
operands[4] = operands[1];
}
-})
-;; %%% Split me.
-(define_insn "divmodhi4"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (div:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:HI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:HI 3 "register_operand" "=&d")
- (mod:HI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_HIMODE_MATH"
- "cwtd\;idiv{w}\t%2"
- [(set_attr "type" "multi")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
-
-(define_insn "udivmoddi4"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (udiv:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 3 "register_operand" "=&d")
- (umod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "xor{q}\t%3, %3\;div{q}\t%2"
- [(set_attr "type" "multi")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "DI")])
-
-(define_insn "*udivmoddi4_noext"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (udiv:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 3 "register_operand" "=d")
- (umod:DI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "div{q}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (udiv:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonimmediate_operand" "")))
- (set (match_operand:DI 3 "register_operand" "")
- (umod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(set (match_dup 3) (const_int 0))
- (parallel [(set (match_dup 0)
- (udiv:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (umod:DI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
- (clobber (reg:CC FLAGS_REG))])]
- "")
-
-(define_insn "udivmodsi4"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (udiv:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 3 "register_operand" "=&d")
- (umod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "xor{l}\t%3, %3\;div{l}\t%2"
+}
[(set_attr "type" "multi")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*udivmodsi4_noext"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (udiv:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 3 "register_operand" "=d")
- (umod:SI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
+(define_insn "*divmod<mode>4_noext"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=d")
+ (mod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_operand:SWIM248 4 "register_operand" "1"))
(clobber (reg:CC FLAGS_REG))]
""
- "div{l}\t%2"
+ "idiv{<imodesuffix>}\t%3"
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (udiv:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
- (set (match_operand:SI 3 "register_operand" "")
- (umod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed"
- [(set (match_dup 3) (const_int 0))
- (parallel [(set (match_dup 0)
- (udiv:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (umod:SI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
+(define_expand "udivmod<mode>4"
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ (udiv:SWIM248
+ (match_operand:SWIM248 1 "register_operand" "")
+ (match_operand:SWIM248 2 "nonimmediate_operand" "")))
+ (set (match_operand:SWIM248 3 "register_operand" "")
+ (umod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
+ ""
"")
-(define_expand "udivmodhi4"
- [(set (match_dup 4) (const_int 0))
- (parallel [(set (match_operand:HI 0 "register_operand" "")
- (udiv:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "nonimmediate_operand" "")))
- (set (match_operand:HI 3 "register_operand" "")
- (umod:HI (match_dup 1) (match_dup 2)))
- (use (match_dup 4))
+(define_insn_and_split "*udivmod<mode>4"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=&d")
+ (umod:SWIM248 (match_dup 2) (match_dup 3)))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 1) (const_int 0))
+ (parallel [(set (match_dup 0)
+ (udiv:SWIM248 (match_dup 2) (match_dup 3)))
+ (set (match_dup 1)
+ (umod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_dup 1))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_HIMODE_MATH"
- "operands[4] = gen_reg_rtx (HImode);")
+ ""
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")])
-(define_insn "*udivmodhi_noext"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (udiv:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:HI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:HI 3 "register_operand" "=d")
- (umod:HI (match_dup 1) (match_dup 2)))
- (use (match_operand:HI 4 "register_operand" "3"))
+(define_insn "*udivmod<mode>4_noext"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=d")
+ (umod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_operand:SWIM248 4 "register_operand" "1"))
(clobber (reg:CC FLAGS_REG))]
""
- "div{w}\t%2"
+ "div{<imodesuffix>}\t%3"
[(set_attr "type" "idiv")
- (set_attr "mode" "HI")])
+ (set_attr "mode" "<MODE>")])
;; We cannot use div/idiv for double division, because it causes
;; "division by zero" on the overflow and that's not what we expect
[(set_attr "type" "test")
(set_attr "mode" "QI")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "pent_pair" "np")])
(define_insn "*testqi_ext_1"
else if (GET_CODE (val) == SUBREG
&& (submode = GET_MODE (SUBREG_REG (val)),
GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
- && pos + len <= GET_MODE_BITSIZE (submode))
+ && pos + len <= GET_MODE_BITSIZE (submode)
+ && GET_MODE_CLASS (submode) == MODE_INT)
{
/* Narrow a paradoxical subreg to prevent partial register stalls. */
mode = submode;
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return "movz{bq|x}\t{%1,%0|%0, %1}";
+ return "movz{bl|x}\t{%1, %k0|%k0, %1}";
else
- return "movz{wq|x}\t{%1,%0|%0, %1}";
+ return "movz{wl|x}\t{%1, %k0|%k0, %1}";
}
default:
}
[(set_attr "type" "alu,alu,alu,imovx")
(set_attr "length_immediate" "*,*,*,0")
- (set_attr "mode" "SI,DI,DI,DI")])
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (match_operand 1 "ext_QIreg_nomode_operand" "")))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "SI,DI,DI,SI")])
(define_insn "*anddi_2"
[(set (reg FLAGS_REG)
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return "movz{bl|x}\t{%1,%0|%0, %1}";
+ return "movz{bl|x}\t{%1, %0|%0, %1}";
else
- return "movz{wl|x}\t{%1,%0|%0, %1}";
+ return "movz{wl|x}\t{%1, %0|%0, %1}";
}
default:
}
}
[(set_attr "type" "alu,alu,imovx")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (match_operand 1 "ext_QIreg_nomode_operand" "")))
+ (const_string "1")
+ (const_string "*")))
(set_attr "length_immediate" "*,*,0")
(set_attr "mode" "SI")])
}
[(set_attr "type" "alu,alu,imovx")
(set_attr "length_immediate" "*,*,0")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (match_operand 1 "ext_QIreg_nomode_operand" ""))
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "HI,HI,SI")])
(define_insn "*andhi_2"
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
;; Generated by peephole translating test to and. This shows up
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*andqi_ext_1"
"or{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*iorqi_ext_1"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_ext_1"
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_ext_1_rex64"
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_expand "xorqi_cc_ext_1"
}
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_ashlti3"
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*ashlti3_1"
}
[(set_attr "type" "sseishft")
(set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "sse2_lshrti3"
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
(define_insn "*lshrti3_1"
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"bts{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btrq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btr{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btcq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btc{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
;; Allow Nocona to avoid these instructions if a register is available.
"TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
"bt{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btsi"
[(set (reg:CCC FLAGS_REG)
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"bt{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
- (set_attr "prefix_0f" "1")])
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
\f
;; Store-flag instructions.
;; For all sCOND expanders, also expand the compare or test insn that
;; generates cc0. Generate an equality comparison if `seq' or `sne'.
-;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
-;; to avoid partial register stalls. Otherwise do things the setcc+movzx
-;; way, which can later delete the movzx if only QImode is needed.
+(define_insn_and_split "*setcc_di_1"
+ [(set (match_operand:DI 0 "register_operand" "=q")
+ (match_operator:DI 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))]
+ "TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (zero_extend:DI (match_dup 2)))]
+{
+ PUT_MODE (operands[1], QImode);
+ operands[2] = gen_lowpart (QImode, operands[0]);
+})
+
+(define_insn_and_split "*setcc_si_1_and"
+ [(set (match_operand:SI 0 "register_operand" "=q")
+ (match_operator:SI 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL
+ && TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (parallel [(set (match_dup 0) (zero_extend:SI (match_dup 2)))
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ PUT_MODE (operands[1], QImode);
+ operands[2] = gen_lowpart (QImode, operands[0]);
+})
+
+(define_insn_and_split "*setcc_si_1_movzbl"
+ [(set (match_operand:SI 0 "register_operand" "=q")
+ (match_operator:SI 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))]
+ "!TARGET_PARTIAL_REG_STALL
+ && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
+{
+ PUT_MODE (operands[1], QImode);
+ operands[2] = gen_lowpart (QImode, operands[0]);
+})
-(define_insn "*setcc_1"
+(define_insn "*setcc_qi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(match_operator:QI 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))]
[(set_attr "type" "setcc")
(set_attr "mode" "QI")])
-(define_insn "*setcc_2"
+(define_insn "*setcc_qi_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(match_operator:QI 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))]
"vcmp%D1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
(set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
(define_insn "*sse_setcc<mode>"
(match_operator:MODEF 1 "sse_comparison_operator"
[(match_operand:MODEF 2 "register_operand" "0")
(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
+ "SSE_FLOAT_MODE_P (<MODE>mode)"
"cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
-
-(define_insn "*sse5_setcc<mode>"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
- (match_operator:MODEF 1 "sse5_comparison_float_operator"
- [(match_operand:MODEF 2 "register_operand" "x")
- (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE5"
- "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "mode" "<MODE>")])
-
\f
;; Basic conditional jump instructions.
;; We ignore the overflow flag for signed branch instructions.
(pc)))]
"PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
-;; Define combination compare-and-branch fp compare instructions to use
-;; during early optimization. Splitting the operation apart early makes
-;; for bad code when we want to reverse the operation.
-
-(define_insn "*fp_jcc_1_mixed"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f,x")
- (match_operand 2 "nonimmediate_operand" "f,xm")])
- (label_ref (match_operand 3 "" ""))
- (pc)))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_MIX_SSE_I387
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_1_sse"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "x")
- (match_operand 2 "nonimmediate_operand" "xm")])
- (label_ref (match_operand 3 "" ""))
- (pc)))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_SSE_MATH
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_1_387"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f")
- (match_operand 2 "register_operand" "f")])
- (label_ref (match_operand 3 "" ""))
- (pc)))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
- && TARGET_CMOVE
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_2_mixed"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f,x")
- (match_operand 2 "nonimmediate_operand" "f,xm")])
- (pc)
- (label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_MIX_SSE_I387
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_2_sse"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "x")
- (match_operand 2 "nonimmediate_operand" "xm")])
- (pc)
- (label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_SSE_MATH
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_2_387"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f")
- (match_operand 2 "register_operand" "f")])
- (pc)
- (label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
- && TARGET_CMOVE
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
+;; Define combination compare-and-branch fp compare instructions to help
+;; combine.
(define_insn "*fp_jcc_3_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
(label_ref (match_operand 3 "" ""))
"TARGET_80387
&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
&& SELECT_CC_MODE (GET_CODE (operands[0]),
operands[1], operands[2]) == CCFPmode
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_4_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
(pc)
"TARGET_80387
&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
&& SELECT_CC_MODE (GET_CODE (operands[0]),
operands[1], operands[2]) == CCFPmode
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_5_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
(label_ref (match_operand 3 "" ""))
(clobber (match_scratch:HI 4 "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_6_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
(pc)
(clobber (match_scratch:HI 4 "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_7_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "const0_operand" "")])
(label_ref (match_operand 3 "" ""))
(clobber (match_scratch:HI 4 "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
&& SELECT_CC_MODE (GET_CODE (operands[0]),
operands[1], operands[2]) == CCFPmode
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
;; The order of operands in *fp_jcc_8_387 is forced by combine in
(define_insn "*fp_jcc_8<mode>_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operator 1 "float_operator"
[(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r")])
(match_operand 3 "register_operand" "f,f")])
"X87_FLOAT_MODE_P (GET_MODE (operands[3]))
&& (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
&& GET_MODE (operands[1]) == GET_MODE (operands[3])
- && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
&& ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
- && ix86_fp_jump_nontrivial_p (swap_condition (GET_CODE (operands[0])))"
+ && !TARGET_CMOVE"
"#")
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "")
(match_operand 2 "nonimmediate_operand" "")])
(match_operand 3 "" "")
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "")
(match_operand 2 "general_operand" "")])
(match_operand 3 "" "")
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operator 1 "float_operator"
[(match_operand:X87MODEI12 2 "memory_operand" "")])
(match_operand 3 "register_operand" "")])
;; %%% Kill this when reload knows how to do it.
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operator 1 "float_operator"
[(match_operand:X87MODEI12 2 "register_operand" "")])
(match_operand 3 "register_operand" "")])
}
[(set_attr "type" "call")])
-(define_insn "*call_pop_1"
+(define_insn "*call_pop_1_esp"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
(match_operand:SI 1 "" ""))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
- {
- if (SIBLING_CALL_P (insn))
- return "jmp\t%P0";
- else
- return "call\t%P0";
- }
- if (SIBLING_CALL_P (insn))
- return "jmp\t%A0";
- else
- return "call\t%A0";
+ return "call\t%P0";
+ return "call\t%A0";
+}
+ [(set_attr "type" "call")])
+
+(define_insn "*call_pop_1"
+ [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
+ (match_operand:SI 1 "" ""))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 2 "immediate_operand" "i")))]
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+ if (constant_call_address_operand (operands[0], Pmode))
+ return "call\t%P0";
+ return "call\t%A0";
}
[(set_attr "type" "call")])
+(define_insn "*sibcall_pop_1"
+ [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 1 "" ""))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 2 "immediate_operand" "i,i")))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P0
+ jmp\t%A0"
+ [(set_attr "type" "call")])
+
(define_expand "call"
[(call (match_operand:QI 0 "" "")
(match_operand 1 "" ""))
}
[(set_attr "type" "call")])
-(define_insn "*call_1"
+(define_insn "*call_1_esp"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
(match_operand 1 "" ""))]
- "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
}
[(set_attr "type" "call")])
-(define_insn "*sibcall_1"
- [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
+(define_insn "*call_1"
+ [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
(match_operand 1 "" ""))]
- "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
- return "jmp\t%P0";
- return "jmp\t%A0";
+ return "call\t%P0";
+ return "call\t%A0";
}
[(set_attr "type" "call")])
+(define_insn "*sibcall_1"
+ [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U"))
+ (match_operand 1 "" ""))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P0
+ jmp\t%A0"
+ [(set_attr "type" "call")])
+
(define_insn "*call_1_rex64"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
(match_operand 1 "" ""))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)
&& ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
{
if (constant_call_address_operand (operands[0], Pmode))
(clobber (reg:TI XMM15_REG))
(clobber (reg:DI SI_REG))
(clobber (reg:DI DI_REG))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
(define_insn "*call_1_rex64_large"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rm"))
(match_operand 1 "" ""))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
"call\t%A0"
[(set_attr "type" "call")])
(define_insn "*sibcall_1_rex64"
- [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
+ [(call (mem:QI (match_operand:DI 0 "sibcall_insn_operand" "s,U"))
(match_operand 1 "" ""))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t%P0"
- [(set_attr "type" "call")])
-
-(define_insn "*sibcall_1_rex64_v"
- [(call (mem:QI (reg:DI R11_REG))
- (match_operand 0 "" ""))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t{*%%}r11"
+ "TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P0
+ jmp\t%A0"
[(set_attr "type" "call")])
-
;; Call subroutine, returning value in operand 0
-
(define_expand "call_value_pop"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand:QI 1 "" "")
GEN_INT ((TARGET_64BIT
? (ix86_abi == SYSV_ABI
? X86_64_SSE_REGPARM_MAX
- : X64_SSE_REGPARM_MAX)
+ : X86_64_MS_SSE_REGPARM_MAX)
: X86_32_SSE_REGPARM_MAX)
- 1),
NULL, 0);
(set_attr "length_immediate" "0")
(set_attr "modrm" "0")])
+(define_insn "vswapmov"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:SI 1 "register_operand" "r"))
+ (unspec_volatile [(const_int 0)] UNSPECV_VSWAPMOV)]
+ ""
+ "movl.s\t{%1, %0|%0, %1}"
+ [(set_attr "length" "2")
+ (set_attr "length_immediate" "0")
+ (set_attr "modrm" "0")])
+
;; Pad to 16-byte boundary, max skip in op0. Used to avoid
;; branch prediction penalty for the third jump in a 16-byte
;; block on K8.
"TARGET_64BIT"
"lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
[(set_attr "type" "lea")
- (set_attr "length" "6")])
+ (set_attr "length_address" "4")
+ (set_attr "mode" "DI")])
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
- (set_attr "length" "6")])
+ (set_attr "length_address" "4")
+ (set_attr "mode" "DI")])
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
"TARGET_64BIT"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
[(set_attr "type" "imov")
- (set_attr "length" "11")])
+ (set_attr "length_immediate" "0")
+ (set_attr "length_address" "8")
+ (set_attr "mode" "DI")])
(define_expand "epilogue"
[(const_int 0)]
tmp = gen_rtx_MEM (Pmode, tmp);
emit_move_insn (tmp, ra);
- if (Pmode == SImode)
- emit_jump_insn (gen_eh_return_si (sa));
- else
- emit_jump_insn (gen_eh_return_di (sa));
+ emit_jump_insn (gen_eh_return_internal ());
emit_barrier ();
DONE;
})
-(define_insn_and_split "eh_return_<mode>"
- [(set (pc)
- (unspec [(match_operand:P 0 "register_operand" "c")]
- UNSPEC_EH_RETURN))]
+(define_insn_and_split "eh_return_internal"
+ [(eh_return)]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
"ix86_expand_epilogue (2); DONE;")
(ctz:SI (match_dup 1)))]
""
"bsf{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
(define_expand "ffsdi2"
[(set (match_dup 2) (const_int -1))
(ctz:DI (match_dup 1)))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "ctzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clobber (reg:CC FLAGS_REG))]
""
"bsf{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
(define_insn "ctzdi2"
[(set (match_operand:DI 0 "register_operand" "=r")
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_expand "clzsi2"
[(parallel
(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
-(define_insn "*bsr"
+(define_insn "bsr"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (const_int 31)
(clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
""
"bsr{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
(define_insn "popcount<mode>2"
(set_attr "type" "bitmanip")
(set_attr "mode" "DI")])
-(define_insn "*bsr_rex64"
+(define_insn "bsr_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (const_int 63)
(clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsr{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_expand "clzhi2"
(clobber (reg:CC FLAGS_REG))]
""
"bsr{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "HI")])
(define_expand "paritydi2"
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
UNSPEC_TLS_GD)]
"TARGET_64BIT"
- ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\;.word\t0x6666\;rex64\;call\t%P2"
+ { return ASM_BYTE "0x66\n\tlea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\n" ASM_SHORT "0x6666\n\trex64\n\tcall\t%P2"; }
[(set_attr "type" "multi")
(set_attr "length" "16")])
(clobber (reg:CC FLAGS_REG))])]
"!TARGET_64BIT && TARGET_GNU2_TLS"
{
- operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[3] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
ix86_tls_descriptor_calls_expanded_in_cfun = true;
})
""
[(set (match_dup 0) (match_dup 5))]
{
- operands[5] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[5] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
emit_insn (gen_tls_dynamic_gnu2_32 (operands[5], operands[1], operands[2]));
})
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && TARGET_GNU2_TLS"
{
- operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
ix86_tls_descriptor_calls_expanded_in_cfun = true;
})
""
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[4] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
emit_insn (gen_tls_dynamic_gnu2_64 (operands[4], operands[1]));
})
operands[3] = gen_reg_rtx (XFmode);
})
-(define_expand "scalb<mode>3"
+(define_expand "scalb<mode>3"
+ [(use (match_operand:MODEF 0 "register_operand" ""))
+ (use (match_operand:MODEF 1 "general_operand" ""))
+ (use (match_operand:MODEF 2 "general_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0, op1, op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
+ op2 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
+ emit_insn (gen_scalbxf3 (op0, op1, op2));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "significandxf2"
+ [(parallel [(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_XTRACT_FRACT))
+ (set (match_dup 2)
+ (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "significand<mode>2"
[(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "register_operand" ""))]
- "TARGET_USE_FANCY_MATH_387
+ (use (match_operand:MODEF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
- rtx op0, op1, op2;
-
- if (optimize_insn_for_size_p ())
- FAIL;
-
- op0 = gen_reg_rtx (XFmode);
- op1 = gen_reg_rtx (XFmode);
- op2 = gen_reg_rtx (XFmode);
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
- emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
- emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
- emit_insn (gen_scalbxf3 (op0, op1, op2));
+ emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
(unspec:DI [(match_operand:XF 1 "register_operand" "")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
&& flag_unsafe_math_optimizations"
"")
-(define_expand "lfloor<mode>di2"
- [(match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
- && !flag_trapping_math"
-{
- if (optimize_insn_for_size_p ())
- FAIL;
- ix86_expand_lfloorceil (operand0, operand1, true);
- DONE;
-})
-
-(define_expand "lfloor<mode>si2"
- [(match_operand:SI 0 "nonimmediate_operand" "")
+(define_expand "lfloor<MODEF:mode><SWI48:mode>2"
+ [(match_operand:SWI48 0 "nonimmediate_operand" "")
(match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
+ "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math"
{
- if (optimize_insn_for_size_p () && TARGET_64BIT)
+ if (TARGET_64BIT && optimize_insn_for_size_p ())
FAIL;
ix86_expand_lfloorceil (operand0, operand1, true);
DONE;
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
&& flag_unsafe_math_optimizations"
"")
-(define_expand "lceil<mode>di2"
- [(match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
- && !flag_trapping_math"
-{
- ix86_expand_lfloorceil (operand0, operand1, false);
- DONE;
-})
-
-(define_expand "lceil<mode>si2"
- [(match_operand:SI 0 "nonimmediate_operand" "")
+(define_expand "lceil<MODEF:mode><SWI48:mode>2"
+ [(match_operand:SWI48 0 "nonimmediate_operand" "")
(match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
+ "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math"
{
ix86_expand_lfloorceil (operand0, operand1, false);
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
"TARGET_USE_FANCY_MATH_387"
"fxam\n\tfnstsw\t%0"
[(set_attr "type" "multi")
+ (set_attr "length" "4")
(set_attr "unit" "i387")
(set_attr "mode" "<MODE>")])
[(match_operand:MODEF 1 "memory_operand" "")]
UNSPEC_FXAM_MEM))]
"TARGET_USE_FANCY_MATH_387
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(set (match_dup 2)(match_dup 1))
\f
;; Conditional move instructions.
-(define_expand "movdicc"
- [(set (match_operand:DI 0 "register_operand" "")
- (if_then_else:DI (match_operand 1 "comparison_operator" "")
- (match_operand:DI 2 "general_operand" "")
- (match_operand:DI 3 "general_operand" "")))]
- "TARGET_64BIT"
+(define_expand "mov<mode>cc"
+ [(set (match_operand:SWIM 0 "register_operand" "")
+ (if_then_else:SWIM (match_operand 1 "comparison_operator" "")
+ (match_operand:SWIM 2 "general_operand" "")
+ (match_operand:SWIM 3 "general_operand" "")))]
+ ""
"if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-(define_insn "x86_movdicc_0_m1_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
+;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
+;; the register first winds up with `sbbl $0,reg', which is also weird.
+;; So just document what we're doing explicitly.
+
+(define_insn "x86_mov<mode>cc_0_m1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (if_then_else:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
(const_int -1)
(const_int 0)))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "sbb{q}\t%0, %0"
+ ""
+ "sbb{<imodesuffix>}\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "DI")
- (set_attr "length_immediate" "0")])
-
-(define_insn "*x86_movdicc_0_m1_se"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extract:DI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int 1)
- (const_int 0)))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "sbb{q}\t%0, %0"
- [(set_attr "type" "alu")
- (set_attr "use_carry" "1")
- (set_attr "pent_pair" "pu")
- (set_attr "memory" "none")
- (set_attr "imm_disp" "false")
- (set_attr "mode" "DI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*movdicc_c_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:DI 2 "nonimmediate_operand" "rm,0")
- (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_64BIT && TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
- "@
- cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
- (set_attr "mode" "DI")])
-
-(define_expand "movsicc"
- [(set (match_operand:SI 0 "register_operand" "")
- (if_then_else:SI (match_operand 1 "comparison_operator" "")
- (match_operand:SI 2 "general_operand" "")
- (match_operand:SI 3 "general_operand" "")))]
- ""
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-
-;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
-;; the register first winds up with `sbbl $0,reg', which is also weird.
-;; So just document what we're doing explicitly.
-
-(define_insn "x86_movsicc_0_m1"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int -1)
- (const_int 0)))
+(define_insn "*x86_mov<mode>cc_0_m1_se"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (sign_extract:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
+ (const_int 1)
+ (const_int 0)))
(clobber (reg:CC FLAGS_REG))]
""
- "sbb{l}\t%0, %0"
- ; Since we don't have the proper number of operands for an alu insn,
- ; fill in all the blanks.
+ "sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "SI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*x86_movsicc_0_m1_se"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extract:SI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int 1)
- (const_int 0)))
- (clobber (reg:CC FLAGS_REG))]
+(define_insn "*x86_mov<mode>cc_0_m1_neg"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (neg:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")))]
""
- "sbb{l}\t%0, %0"
+ "sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "SI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*movsicc_noc"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:SI 2 "nonimmediate_operand" "rm,0")
- (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
- "@
- cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
- (set_attr "mode" "SI")])
-
-(define_expand "movhicc"
- [(set (match_operand:HI 0 "register_operand" "")
- (if_then_else:HI (match_operand 1 "comparison_operator" "")
- (match_operand:HI 2 "general_operand" "")
- (match_operand:HI 3 "general_operand" "")))]
- "TARGET_HIMODE_MATH"
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-
-(define_insn "*movhicc_noc"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:HI 2 "nonimmediate_operand" "rm,0")
- (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+(define_insn "*mov<mode>cc_noc"
+ [(set (match_operand:SWI248 0 "register_operand" "=r,r")
+ (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)])
+ (match_operand:SWI248 2 "nonimmediate_operand" "rm,0")
+ (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))]
+ "TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %0|%0, %2}
cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
- (set_attr "mode" "HI")])
-
-(define_expand "movqicc"
- [(set (match_operand:QI 0 "register_operand" "")
- (if_then_else:QI (match_operand 1 "comparison_operator" "")
- (match_operand:QI 2 "general_operand" "")
- (match_operand:QI 3 "general_operand" "")))]
- "TARGET_QIMODE_MATH"
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
+ (set_attr "mode" "<MODE>")])
(define_insn_and_split "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
- (const_int 0)])
+ [(match_operand 4 "flags_reg_operand" "")
+ (const_int 0)])
(match_operand:QI 2 "register_operand" "r,0")
(match_operand:QI 3 "register_operand" "0,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
(define_expand "mov<mode>cc"
[(set (match_operand:X87MODEF 0 "register_operand" "")
(if_then_else:X87MODEF
- (match_operand 1 "comparison_operator" "")
+ (match_operand 1 "ix86_fp_comparison_operator" "")
(match_operand:X87MODEF 2 "register_operand" "")
(match_operand:X87MODEF 3 "register_operand" "")))]
"(TARGET_80387 && TARGET_CMOVE)
[(set_attr "type" "fcmov")
(set_attr "mode" "XF")])
-;; All moves in SSE5 pcmov instructions are 128 bits and hence we restrict
-;; the scalar versions to have only XMM registers as operands.
-
-;; SSE5 conditional move
-(define_insn "*sse5_pcmov_<mode>"
- [(set (match_operand:MODEF 0 "register_operand" "=x,x")
- (if_then_else:MODEF
- (match_operand:MODEF 1 "register_operand" "x,0")
- (match_operand:MODEF 2 "register_operand" "0,x")
- (match_operand:MODEF 3 "register_operand" "x,x")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
- [(set_attr "type" "sse4arg")])
-
;; These versions of the min/max patterns are intentionally ignorant of
;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
}
[(set_attr "type" "callv")])
-(define_insn "*call_value_pop_1"
+(define_insn "*call_value_pop_1_esp"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
(match_operand:SI 2 "" "")))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
- {
- if (SIBLING_CALL_P (insn))
- return "jmp\t%P1";
- else
- return "call\t%P1";
- }
- if (SIBLING_CALL_P (insn))
- return "jmp\t%A1";
- else
- return "call\t%A1";
+ return "call\t%P1";
+ return "call\t%A1";
}
[(set_attr "type" "callv")])
+(define_insn "*call_value_pop_1"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
+ (match_operand:SI 2 "" "")))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i")))]
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+ if (constant_call_address_operand (operands[1], Pmode))
+ return "call\t%P1";
+ return "call\t%A1";
+}
+ [(set_attr "type" "callv")])
+
+(define_insn "*sibcall_value_pop_1"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 2 "" "")))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i,i")))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P1
+ jmp\t%A1"
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_0"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
(clobber (reg:TI XMM15_REG))
(clobber (reg:DI SI_REG))
(clobber (reg:DI DI_REG))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
{
if (SIBLING_CALL_P (insn))
return "jmp\t%P1";
}
[(set_attr "type" "callv")])
-(define_insn "*call_value_1"
+(define_insn "*call_value_1_esp"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
(match_operand:SI 2 "" "")))]
- "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
}
[(set_attr "type" "callv")])
-(define_insn "*sibcall_value_1"
+(define_insn "*call_value_1"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
+ (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
(match_operand:SI 2 "" "")))]
- "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
- return "jmp\t%P1";
- return "jmp\t%A1";
+ return "call\t%P1";
+ return "call\t%A1";
}
[(set_attr "type" "callv")])
+(define_insn "*sibcall_value_1"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 2 "" "")))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P1
+ jmp\t%A1"
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_1_rex64"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
(match_operand:DI 2 "" "")))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)
&& ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
{
if (constant_call_address_operand (operands[1], Pmode))
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
(match_operand:DI 2 "" "")))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
- (clobber (reg:TI 27))
- (clobber (reg:TI 28))
- (clobber (reg:TI 45))
- (clobber (reg:TI 46))
- (clobber (reg:TI 47))
- (clobber (reg:TI 48))
- (clobber (reg:TI 49))
- (clobber (reg:TI 50))
- (clobber (reg:TI 51))
- (clobber (reg:TI 52))
+ (clobber (reg:TI XMM6_REG))
+ (clobber (reg:TI XMM7_REG))
+ (clobber (reg:TI XMM8_REG))
+ (clobber (reg:TI XMM9_REG))
+ (clobber (reg:TI XMM10_REG))
+ (clobber (reg:TI XMM11_REG))
+ (clobber (reg:TI XMM12_REG))
+ (clobber (reg:TI XMM13_REG))
+ (clobber (reg:TI XMM14_REG))
+ (clobber (reg:TI XMM15_REG))
(clobber (reg:DI SI_REG))
(clobber (reg:DI DI_REG))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rm"))
(match_operand:DI 2 "" "")))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
"call\t%A1"
[(set_attr "type" "callv")])
(define_insn "*sibcall_value_1_rex64"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
+ (call (mem:QI (match_operand:DI 1 "sibcall_insn_operand" "s,U"))
(match_operand:DI 2 "" "")))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t%P1"
- [(set_attr "type" "callv")])
-
-(define_insn "*sibcall_value_1_rex64_v"
- [(set (match_operand 0 "" "")
- (call (mem:QI (reg:DI R11_REG))
- (match_operand:DI 1 "" "")))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t{*%%}r11"
+ "TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P1
+ jmp\t%A1"
[(set_attr "type" "callv")])
\f
;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
(define_expand "sse_prologue_save"
[(parallel [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(reg:DI 21)
- (reg:DI 22)
- (reg:DI 23)
- (reg:DI 24)
- (reg:DI 25)
- (reg:DI 26)
- (reg:DI 27)
- (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+ (unspec:BLK [(reg:DI XMM0_REG)
+ (reg:DI XMM1_REG)
+ (reg:DI XMM2_REG)
+ (reg:DI XMM3_REG)
+ (reg:DI XMM4_REG)
+ (reg:DI XMM5_REG)
+ (reg:DI XMM6_REG)
+ (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" ""))
(use (match_operand:DI 2 "immediate_operand" ""))
(use (label_ref:DI (match_operand 3 "" "")))])]
(define_insn "*sse_prologue_save_insn"
[(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
(match_operand:DI 4 "const_int_operand" "n")))
- (unspec:BLK [(reg:DI 21)
- (reg:DI 22)
- (reg:DI 23)
- (reg:DI 24)
- (reg:DI 25)
- (reg:DI 26)
- (reg:DI 27)
- (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+ (unspec:BLK [(reg:DI XMM0_REG)
+ (reg:DI XMM1_REG)
+ (reg:DI XMM2_REG)
+ (reg:DI XMM3_REG)
+ (reg:DI XMM4_REG)
+ (reg:DI XMM5_REG)
+ (reg:DI XMM6_REG)
+ (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" "r"))
(use (match_operand:DI 2 "const_int_operand" "i"))
(use (label_ref:DI (match_operand 3 "" "X")))]
}
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "prefetch")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_sse_rex"
}
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "prefetch")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow"
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow_rex"
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_expand "stack_protect_set"
[(match_operand:SI 1 "register_operand" "0")
(match_operand:CRC32MODE 2 "nonimmediate_operand" "<crc32modeconstraint>")]
UNSPEC_CRC32))]
- "TARGET_SSE4_2"
+ "TARGET_SSE4_2 || TARGET_CRC32"
"crc32<crc32modesuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog1")
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_data16")
+ (if_then_else (match_operand:HI 2 "" "")
+ (const_string "1")
+ (const_string "*")))
+ (set (attr "prefix_rex")
+ (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "SI")])
(define_insn "sse4_2_crc32di"
[(match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "rm")]
UNSPEC_CRC32))]
- "TARGET_SSE4_2 && TARGET_64BIT"
+ "TARGET_64BIT && (TARGET_SSE4_2 || TARGET_CRC32)"
"crc32q\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog1")
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
+(define_expand "rdpmc"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:SI 1 "register_operand" "")]
+ ""
+{
+ rtx reg = gen_reg_rtx (DImode);
+ rtx si;
+
+ /* Force operand 1 into ECX. */
+ rtx ecx = gen_rtx_REG (SImode, CX_REG);
+ emit_insn (gen_rtx_SET (VOIDmode, ecx, operands[1]));
+ si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, ecx),
+ UNSPECV_RDPMC);
+
+ if (TARGET_64BIT)
+ {
+ rtvec vec = rtvec_alloc (2);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ rtx upper = gen_reg_rtx (DImode);
+ rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDPMC);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, si);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di);
+ emit_insn (load);
+ upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
+ NULL, 1, OPTAB_DIRECT);
+ reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1,
+ OPTAB_DIRECT);
+ }
+ else
+ emit_insn (gen_rtx_SET (VOIDmode, reg, si));
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg));
+ DONE;
+})
+
+(define_insn "*rdpmc"
+ [(set (match_operand:DI 0 "register_operand" "=A")
+ (unspec_volatile:DI [(match_operand:SI 1 "register_operand" "c")]
+ UNSPECV_RDPMC))]
+ "!TARGET_64BIT"
+ "rdpmc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_insn "*rdpmc_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(match_operand:SI 2 "register_operand" "c")]
+ UNSPECV_RDPMC))
+ (set (match_operand:DI 1 "register_operand" "=d")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDPMC))]
+ "TARGET_64BIT"
+ "rdpmc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_expand "rdtsc"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
+ ""
+{
+ if (TARGET_64BIT)
+ {
+ rtvec vec = rtvec_alloc (2);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ rtx upper = gen_reg_rtx (DImode);
+ rtx lower = gen_reg_rtx (DImode);
+ rtx src = gen_rtx_UNSPEC_VOLATILE (DImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDTSC);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, lower, src);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, src);
+ emit_insn (load);
+ upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
+ NULL, 1, OPTAB_DIRECT);
+ lower = expand_simple_binop (DImode, IOR, lower, upper, lower, 1,
+ OPTAB_DIRECT);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], lower));
+ DONE;
+ }
+})
+
+(define_insn "*rdtsc"
+ [(set (match_operand:DI 0 "register_operand" "=A")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
+ "!TARGET_64BIT"
+ "rdtsc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_insn "*rdtsc_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))
+ (set (match_operand:DI 1 "register_operand" "=d")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
+ "TARGET_64BIT"
+ "rdtsc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_expand "rdtscp"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:SI 1 "memory_operand" "")]
+ ""
+{
+ rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDTSCP);
+ rtx si = gen_rtx_UNSPEC_VOLATILE (SImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDTSCP);
+ rtx reg = gen_reg_rtx (DImode);
+ rtx tmp = gen_reg_rtx (SImode);
+
+ if (TARGET_64BIT)
+ {
+ rtvec vec = rtvec_alloc (3);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ rtx upper = gen_reg_rtx (DImode);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di);
+ RTVEC_ELT (vec, 2) = gen_rtx_SET (VOIDmode, tmp, si);
+ emit_insn (load);
+ upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
+ NULL, 1, OPTAB_DIRECT);
+ reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1,
+ OPTAB_DIRECT);
+ }
+ else
+ {
+ rtvec vec = rtvec_alloc (2);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, tmp, si);
+ emit_insn (load);
+ }
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg));
+ emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
+ DONE;
+})
+
+(define_insn "*rdtscp"
+ [(set (match_operand:DI 0 "register_operand" "=A")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
+ (set (match_operand:SI 1 "register_operand" "=c")
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_RDTSCP))]
+ "!TARGET_64BIT"
+ "rdtscp"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
+
+(define_insn "*rdtscp_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
+ (set (match_operand:DI 1 "register_operand" "=d")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
+ (set (match_operand:SI 2 "register_operand" "=c")
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_RDTSCP))]
+ "TARGET_64BIT"
+ "rdtscp"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
+
(include "mmx.md")
(include "sse.md")
(include "sync.md")
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