;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
+;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
;; The special asm out single letter directives following a '%' are:
-;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
-;; operands[1].
-;; 'L' Print the opcode suffix for a 32-bit integer opcode.
-;; 'W' Print the opcode suffix for a 16-bit integer opcode.
-;; 'B' Print the opcode suffix for an 8-bit integer opcode.
-;; 'Q' Print the opcode suffix for a 64-bit float opcode.
-;; 'S' Print the opcode suffix for a 32-bit float opcode.
-;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
-;; 'J' Print the appropriate jump operand.
-;;
-;; 'b' Print the QImode name of the register for the indicated operand.
-;; %b0 would print %al if operands[0] is reg 0.
-;; 'w' Likewise, print the HImode name of the register.
-;; 'k' Likewise, print the SImode name of the register.
-;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
-;; 'y' Print "st(0)" instead of "st" as a register.
+;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
+;; C -- print opcode suffix for set/cmov insn.
+;; c -- like C, but print reversed condition
+;; E,e -- likewise, but for compare-and-branch fused insn.
+;; F,f -- likewise, but for floating-point.
+;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
+;; otherwise nothing
+;; R -- print the prefix for register names.
+;; z -- print the opcode suffix for the size of the current operand.
+;; Z -- likewise, with special suffixes for x87 instructions.
+;; * -- print a star (in certain assembler syntax)
+;; A -- print an absolute memory reference.
+;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
+;; s -- print a shift double count, followed by the assemblers argument
+;; delimiter.
+;; b -- print the QImode name of the register for the indicated operand.
+;; %b0 would print %al if operands[0] is reg 0.
+;; w -- likewise, print the HImode name of the register.
+;; k -- likewise, print the SImode name of the register.
+;; q -- likewise, print the DImode name of the register.
+;; x -- likewise, print the V4SFmode name of the register.
+;; t -- likewise, print the V8SFmode name of the register.
+;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
+;; y -- print "st(0)" instead of "st" as a register.
+;; d -- print duplicated register operand for AVX instruction.
+;; D -- print condition for SSE cmp instruction.
+;; P -- if PIC, print an @PLT suffix.
+;; X -- don't print any sort of PIC '@' suffix for a symbol.
+;; & -- print some in-use local-dynamic symbol name.
+;; H -- print a memory address offset by 8; used for sse high-parts
+;; + -- print a branch hint as 'cs' or 'ds' prefix
+;; ; -- print a semicolon (after prefixes due to bug in older gas).
;; UNSPEC usage:
(UNSPEC_GOTNTPOFF 7)
(UNSPEC_INDNTPOFF 8)
(UNSPEC_PLTOFF 9)
+ (UNSPEC_MACHOPIC_OFFSET 10)
; Prologue support
(UNSPEC_STACK_ALLOC 11)
(UNSPEC_DEF_CFA 15)
(UNSPEC_SET_RIP 16)
(UNSPEC_SET_GOT_OFFSET 17)
+ (UNSPEC_MEMORY_BLOCKAGE 18)
; TLS support
- (UNSPEC_TP 18)
- (UNSPEC_TLS_GD 19)
- (UNSPEC_TLS_LD_BASE 20)
- (UNSPEC_TLSDESC 21)
+ (UNSPEC_TP 20)
+ (UNSPEC_TLS_GD 21)
+ (UNSPEC_TLS_LD_BASE 22)
+ (UNSPEC_TLSDESC 23)
; Other random patterns
(UNSPEC_SCAS 30)
(UNSPEC_ADD_CARRY 34)
(UNSPEC_FLDCW 35)
(UNSPEC_REP 36)
- (UNSPEC_EH_RETURN 37)
(UNSPEC_LD_MPIC 38) ; load_macho_picbase
(UNSPEC_TRUNC_NOOP 39)
(UNSPEC_LFENCE 45)
(UNSPEC_PSADBW 46)
(UNSPEC_LDDQU 47)
+ (UNSPEC_MS_TO_SYSV_CALL 48)
; Generic math support
(UNSPEC_COPYSIGN 50)
(UNSPEC_FPREM1_U 91)
(UNSPEC_C2_FLAG 95)
+ (UNSPEC_FXAM_MEM 96)
; SSP patterns
(UNSPEC_SP_SET 100)
(UNSPEC_PCMPESTR 144)
(UNSPEC_PCMPISTR 145)
- ;; For SSE5
- (UNSPEC_SSE5_INTRINSIC 150)
- (UNSPEC_SSE5_UNSIGNED_CMP 151)
- (UNSPEC_SSE5_TRUEFALSE 152)
- (UNSPEC_SSE5_PERMUTE 153)
- (UNSPEC_FRCZ 154)
- (UNSPEC_CVTPH2PS 155)
- (UNSPEC_CVTPS2PH 156)
-
+ ; For FMA4 support
+ (UNSPEC_FMA4_INTRINSIC 150)
+ (UNSPEC_FMA4_FMADDSUB 151)
+ (UNSPEC_FMA4_FMSUBADD 152)
; For AES support
(UNSPEC_AESENC 159)
(UNSPEC_AESENCLAST 160)
; For PCLMUL support
(UNSPEC_PCLMUL 165)
+
+ ; For AVX support
+ (UNSPEC_PCMP 166)
+ (UNSPEC_VPERMIL 167)
+ (UNSPEC_VPERMIL2F128 168)
+ (UNSPEC_MASKLOAD 169)
+ (UNSPEC_MASKSTORE 170)
+ (UNSPEC_CAST 171)
+ (UNSPEC_VTESTP 172)
])
(define_constants
(UNSPECV_ALIGN 7)
(UNSPECV_MONITOR 8)
(UNSPECV_MWAIT 9)
- (UNSPECV_CMPXCHG_1 10)
- (UNSPECV_CMPXCHG_2 11)
+ (UNSPECV_CMPXCHG 10)
(UNSPECV_XCHG 12)
(UNSPECV_LOCK 13)
(UNSPECV_PROLOGUE_USE 14)
(UNSPECV_CLD 15)
+ (UNSPECV_VZEROALL 16)
+ (UNSPECV_VZEROUPPER 17)
+ (UNSPECV_RDTSC 18)
+ (UNSPECV_RDTSCP 19)
+ (UNSPECV_RDPMC 20)
+ (UNSPECV_VSWAPMOV 21)
])
;; Constants to represent pcomtrue/pcomfalse variants
(COM_TRUE_P 5)
])
-;; Constants used in the SSE5 pperm instruction
-(define_constants
- [(PPERM_SRC 0x00) /* copy source */
- (PPERM_INVERT 0x20) /* invert source */
- (PPERM_REVERSE 0x40) /* bit reverse source */
- (PPERM_REV_INV 0x60) /* bit reverse & invert src */
- (PPERM_ZERO 0x80) /* all 0's */
- (PPERM_ONES 0xa0) /* all 1's */
- (PPERM_SIGN 0xc0) /* propagate sign bit */
- (PPERM_INV_SIGN 0xe0) /* invert & propagate sign */
- (PPERM_SRC1 0x00) /* use first source byte */
- (PPERM_SRC2 0x10) /* use second source byte */
- ])
-
;; Registers by name.
(define_constants
[(AX_REG 0)
(DX_REG 1)
(CX_REG 2)
+ (BX_REG 3)
(SI_REG 4)
(DI_REG 5)
(BP_REG 6)
(SP_REG 7)
+ (ST0_REG 8)
+ (ST1_REG 9)
+ (ST2_REG 10)
+ (ST3_REG 11)
+ (ST4_REG 12)
+ (ST5_REG 13)
+ (ST6_REG 14)
+ (ST7_REG 15)
(FLAGS_REG 17)
(FPSR_REG 18)
(FPCR_REG 19)
+ (XMM0_REG 21)
+ (XMM1_REG 22)
+ (XMM2_REG 23)
+ (XMM3_REG 24)
+ (XMM4_REG 25)
+ (XMM5_REG 26)
+ (XMM6_REG 27)
+ (XMM7_REG 28)
+ (MM0_REG 29)
+ (MM1_REG 30)
+ (MM2_REG 31)
+ (MM3_REG 32)
+ (MM4_REG 33)
+ (MM5_REG 34)
+ (MM6_REG 35)
+ (MM7_REG 36)
+ (R8_REG 37)
+ (R9_REG 38)
(R10_REG 39)
(R11_REG 40)
+ (R12_REG 41)
+ (R13_REG 42)
+ (XMM8_REG 45)
+ (XMM9_REG 46)
+ (XMM10_REG 47)
+ (XMM11_REG 48)
+ (XMM12_REG 49)
+ (XMM13_REG 50)
+ (XMM14_REG 51)
+ (XMM15_REG 52)
])
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
;; "reload_completed && TARGET_64BIT".
\f
-;; Processor type. This attribute must exactly match the processor_type
-;; enumeration in i386.h.
-(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,
- nocona,core2,generic32,generic64,amdfam10"
- (const (symbol_ref "ix86_tune")))
+;; Processor type.
+(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
+ generic64,amdfam10"
+ (const (symbol_ref "ix86_schedule")))
;; A basic instruction type. Refinements due to arguments to be
;; provided in other attributes.
;; Main data type used by the insn
(define_attr "mode"
- "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
+ "unknown,none,QI,HI,SI,DI,TI,OI,SF,DF,XF,TF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF"
(const_string "unknown"))
;; The CPU unit operations uses.
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
- (if_then_else (ior (eq_attr "mode" "HI")
- (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
- (const_int 1)
- (const_int 0)))
+ (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+ (const_int 0)
+ (eq_attr "mode" "HI")
+ (const_int 1)
+ (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Set when string REP prefix is used.
(define_attr "prefix_rep" ""
- (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
- (const_int 1)
- (const_int 0)))
+ (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+ (const_int 0)
+ (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
+ (const_int 1)
+ ]
+ (const_int 0)))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
;; Set when REX opcode prefix is used.
(define_attr "prefix_rex" ""
- (cond [(and (eq_attr "mode" "DI")
- (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
+ (cond [(ne (symbol_ref "!TARGET_64BIT") (const_int 0))
+ (const_int 0)
+ (and (eq_attr "mode" "DI")
+ (and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
+ (eq_attr "unit" "!mmx")))
(const_int 1)
(and (eq_attr "mode" "QI")
(ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
(ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
(const_int 0))
(const_int 1)
+ (and (eq_attr "type" "imovx")
+ (match_operand:QI 1 "ext_QIreg_operand" ""))
+ (const_int 1)
+ ]
+ (const_int 0)))
+
+;; There are also additional prefixes in 3DNOW, SSSE3.
+;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
+;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
+;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
+(define_attr "prefix_extra" ""
+ (cond [(eq_attr "type" "ssemuladd,sse4arg")
+ (const_int 2)
+ (eq_attr "type" "sseiadd1,ssecvt1")
+ (const_int 1)
]
(const_int 0)))
-;; There are also additional prefixes in SSSE3.
-(define_attr "prefix_extra" "" (const_int 0))
+;; Prefix used: original, VEX or maybe VEX.
+(define_attr "prefix" "orig,vex,maybe_vex"
+ (if_then_else (eq_attr "mode" "OI,V8SF,V4DF")
+ (const_string "vex")
+ (const_string "orig")))
+
+;; VEX W bit is used.
+(define_attr "prefix_vex_w" "" (const_int 0))
+
+;; The length of VEX prefix
+;; Only instructions with 0f prefix can have 2 byte VEX prefix,
+;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
+;; still prefix_0f 1, with prefix_extra 1.
+(define_attr "length_vex" ""
+ (if_then_else (and (eq_attr "prefix_0f" "1")
+ (eq_attr "prefix_extra" "0"))
+ (if_then_else (eq_attr "prefix_vex_w" "1")
+ (symbol_ref "ix86_attr_length_vex_default (insn, 1, 1)")
+ (symbol_ref "ix86_attr_length_vex_default (insn, 1, 0)"))
+ (if_then_else (eq_attr "prefix_vex_w" "1")
+ (symbol_ref "ix86_attr_length_vex_default (insn, 0, 1)")
+ (symbol_ref "ix86_attr_length_vex_default (insn, 0, 0)"))))
;; Set when modrm byte is used.
(define_attr "modrm" ""
(eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
- (ior (match_operand:SI 1 "register_operand" "")
- (match_operand:HI 1 "register_operand" "")))
+ (and (eq (symbol_ref "TARGET_64BIT") (const_int 0))
+ (ior (match_operand:SI 1 "register_operand" "")
+ (match_operand:HI 1 "register_operand" ""))))
(const_int 0)
(and (eq_attr "type" "push")
(not (match_operand 1 "memory_operand" "")))
(not (match_operand 0 "memory_operand" "")))
(const_int 0)
(and (eq_attr "type" "imov")
- (ior (and (match_operand 0 "register_operand" "")
- (match_operand 1 "immediate_operand" ""))
- (ior (and (match_operand 0 "ax_reg_operand" "")
- (match_operand 1 "memory_displacement_only_operand" ""))
- (and (match_operand 0 "memory_displacement_only_operand" "")
- (match_operand 1 "ax_reg_operand" "")))))
+ (and (not (eq_attr "mode" "DI"))
+ (ior (and (match_operand 0 "register_operand" "")
+ (match_operand 1 "immediate_operand" ""))
+ (ior (and (match_operand 0 "ax_reg_operand" "")
+ (match_operand 1 "memory_displacement_only_operand" ""))
+ (and (match_operand 0 "memory_displacement_only_operand" "")
+ (match_operand 1 "ax_reg_operand" ""))))))
(const_int 0)
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand" ""))
(and (eq_attr "type" "callv")
(match_operand 1 "constant_call_address_operand" ""))
(const_int 0)
+ (and (eq_attr "type" "alu,alu1,icmp,test")
+ (match_operand 0 "ax_reg_operand" ""))
+ (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")
]
(const_int 1)))
(eq_attr "unit" "i387")
(plus (const_int 2)
(plus (attr "prefix_data16")
- (attr "length_address")))]
+ (attr "length_address")))
+ (ior (eq_attr "prefix" "vex")
+ (and (eq_attr "prefix" "maybe_vex")
+ (ne (symbol_ref "TARGET_AVX") (const_int 0))))
+ (plus (attr "length_vex")
+ (plus (attr "length_immediate")
+ (plus (attr "modrm")
+ (attr "length_address"))))]
(plus (plus (attr "modrm")
(plus (attr "prefix_0f")
(plus (attr "prefix_rex")
(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
(const_string "any"))
+;; Define attribute to classify add/sub insns that consumes carry flag (CF)
+(define_attr "use_carry" "0,1" (const_string "0"))
+
+;; Define attribute to indicate unaligned ssemov insns
+(define_attr "movu" "0,1" (const_string "0"))
+
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "length" "128")
;; Mapping of unsigned max and min
(define_code_iterator umaxmin [umax umin])
+;; Mapping of signed/unsigned max and min
+(define_code_iterator maxmin [smax smin umax umin])
+
;; Base name for integer and FP insn mnemonic
(define_code_attr maxminiprefix [(smax "maxs") (smin "mins")
(umax "maxu") (umin "minu")])
;; Base name for x87 insn mnemonic.
(define_code_attr absnegprefix [(abs "abs") (neg "chs")])
+;; Used in signed and unsigned widening multiplications.
+(define_code_iterator any_extend [sign_extend zero_extend])
+
+;; Used in signed and unsigned divisions.
+(define_code_iterator any_div [div udiv])
+
+;; Various insn prefixes for signed and unsigned operations.
+(define_code_attr u [(sign_extend "") (zero_extend "u")
+ (div "") (udiv "u")])
+(define_code_attr s [(sign_extend "s") (zero_extend "u")])
+
+;; Instruction prefix for signed and unsigned operations.
+(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")
+ (div "i") (udiv "")])
+
;; All single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
+;; Single word integer modes without QImode.
+(define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])
+
+;; Single word integer modes without QImode and HImode.
+(define_mode_iterator SWI48 [SI (DI "TARGET_64BIT")])
+
+;; All math-dependant single and double word integer modes.
+(define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
+ (HI "TARGET_HIMODE_MATH")
+ SI DI (TI "TARGET_64BIT")])
+
+;; Math-dependant single word integer modes.
+(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
+ (HI "TARGET_HIMODE_MATH")
+ SI (DI "TARGET_64BIT")])
+
+;; Math-dependant single word integer modes without QImode.
+(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
+ SI (DI "TARGET_64BIT")])
+
+;; Half mode for double word integer modes.
+(define_mode_iterator DWIH [(SI "!TARGET_64BIT")
+ (DI "TARGET_64BIT")])
+
+;; Double word integer modes.
+(define_mode_attr DWI [(SI "DI") (DI "TI")])
+(define_mode_attr dwi [(SI "di") (DI "ti")])
+
;; Instruction suffix for integer modes.
(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
(define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])
;; Immediate operand constraint for integer modes.
-(define_mode_attr i [(QI "i") (HI "i") (SI "i") (DI "e")])
+(define_mode_attr i [(QI "n") (HI "n") (SI "i") (DI "e")])
+
+;; General operand constraint for word modes.
+(define_mode_attr g [(SI "g") (DI "rme")])
+
+;; Immediate operand constraint for double integer modes.
+(define_mode_attr di [(SI "iF") (DI "e")])
;; General operand predicate for integer modes.
(define_mode_attr general_operand
[(QI "general_operand")
(HI "general_operand")
(SI "general_operand")
- (DI "x86_64_general_operand")])
+ (DI "x86_64_general_operand")
+ (TI "x86_64_general_operand")])
;; SSE and x87 SFmode and DFmode floating point modes
(define_mode_iterator MODEF [SF DF])
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
-
\f
;; Scheduling descriptions
(include "k6.md")
(include "athlon.md")
(include "geode.md")
+(include "atom.md")
\f
;; Operand and operator predicates and constraints
(include "constraints.md")
\f
-;; Compare instructions.
+;; Compare and branch/compare and store instructions.
+
+(define_expand "cbranchti4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:TI 1 "nonimmediate_operand" "")
+ (match_operand:TI 2 "x86_64_general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_64BIT"
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (TImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
-;; All compare insns have expanders that save the operands away without
-;; actually generating RTL. The bCOND or sCOND (emitted immediately
-;; after the cmp) will actually emit the cmpM.
+(define_expand "cbranchdi4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:DI 2 "x86_64_general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (DImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
-(define_expand "cmpti"
+(define_expand "cstoredi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "x86_64_general_operand" "")))]
+ (compare:CC (match_operand:DI 2 "nonimmediate_operand" "")
+ (match_operand:DI 3 "x86_64_general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
"TARGET_64BIT"
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (TImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (DImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
-(define_expand "cmpdi"
+(define_expand "cbranchsi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "x86_64_general_operand" "")))]
+ (compare:CC (match_operand:SI 1 "cmpsi_operand" "")
+ (match_operand:SI 2 "general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (DImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (SImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
DONE;
})
-(define_expand "cmpsi"
+(define_expand "cstoresi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
- (match_operand:SI 1 "general_operand" "")))]
+ (compare:CC (match_operand:SI 2 "cmpsi_operand" "")
+ (match_operand:SI 3 "general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (SImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (SImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
-(define_expand "cmphi"
+(define_expand "cbranchhi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
- (match_operand:HI 1 "general_operand" "")))]
+ (compare:CC (match_operand:HI 1 "nonimmediate_operand" "")
+ (match_operand:HI 2 "general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (HImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (HImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
DONE;
})
-(define_expand "cmpqi"
+(define_expand "cstorehi4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
- (match_operand:QI 1 "general_operand" "")))]
- "TARGET_QIMODE_MATH"
+ (compare:CC (match_operand:HI 2 "nonimmediate_operand" "")
+ (match_operand:HI 3 "general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
+ ""
{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[0] = force_reg (QImode, operands[0]);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (HImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
+ DONE;
+})
+
+
+(define_expand "cbranchqi4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:QI 1 "nonimmediate_operand" "")
+ (match_operand:QI 2 "general_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+{
+ if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ operands[1] = force_reg (QImode, operands[1]);
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
+
+
+(define_expand "cstoreqi4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:QI 2 "nonimmediate_operand" "")
+ (match_operand:QI 3 "general_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
+ ""
+{
+ if (MEM_P (operands[2]) && MEM_P (operands[3]))
+ operands[2] = force_reg (QImode, operands[2]);
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
+
(define_insn "cmpdi_ccno_1_rex64"
[(set (reg FLAGS_REG)
(compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
- (match_operand:DI 1 "const0_operand" "n,n")))]
+ (match_operand:DI 1 "const0_operand" "")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"@
test{q}\t%0, %0
(define_insn "*cmpsi_ccno_1"
[(set (reg FLAGS_REG)
(compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
- (match_operand:SI 1 "const0_operand" "n,n")))]
+ (match_operand:SI 1 "const0_operand" "")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
test{l}\t%0, %0
(define_insn "*cmphi_ccno_1"
[(set (reg FLAGS_REG)
(compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
- (match_operand:HI 1 "const0_operand" "n,n")))]
+ (match_operand:HI 1 "const0_operand" "")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
test{w}\t%0, %0
(define_insn "*cmphi_minus_1"
[(set (reg FLAGS_REG)
(compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
- (match_operand:HI 1 "general_operand" "ri,mr"))
+ (match_operand:HI 1 "general_operand" "rn,mr"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCGOCmode)"
"cmp{w}\t{%1, %0|%0, %1}"
(define_insn "*cmphi_1"
[(set (reg FLAGS_REG)
(compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
- (match_operand:HI 1 "general_operand" "ri,mr")))]
+ (match_operand:HI 1 "general_operand" "rn,mr")))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& ix86_match_ccmode (insn, CCmode)"
"cmp{w}\t{%1, %0|%0, %1}"
(define_insn "*cmpqi_ccno_1"
[(set (reg FLAGS_REG)
(compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
- (match_operand:QI 1 "const0_operand" "n,n")))]
+ (match_operand:QI 1 "const0_operand" "")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
test{b}\t%0, %0
(define_insn "*cmpqi_1"
[(set (reg FLAGS_REG)
(compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
- (match_operand:QI 1 "general_operand" "qi,mq")))]
+ (match_operand:QI 1 "general_operand" "qn,mq")))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %0|%0, %1}"
(define_insn "*cmpqi_minus_1"
[(set (reg FLAGS_REG)
(compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
- (match_operand:QI 1 "general_operand" "qi,mq"))
+ (match_operand:QI 1 "general_operand" "qn,mq"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCGOCmode)"
"cmp{b}\t{%1, %0|%0, %1}"
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)
- (match_operand:QI 1 "const0_operand" "n")))]
+ (match_operand:QI 1 "const0_operand" "")))]
"ix86_match_ccmode (insn, CCNOmode)"
"test{b}\t%h0, %h0"
[(set_attr "type" "test")
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "cmpqi_ext_3_insn_rex64"
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_4"
;; which would allow mix and match FP modes on the compares. Which is what
;; the old patterns did, but with many more of them.
-(define_expand "cmpxf"
+(define_expand "cbranchxf4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:XF 1 "nonmemory_operand" "")
+ (match_operand:XF 2 "nonmemory_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "ix86_fp_comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_80387"
+{
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
+
+(define_expand "cstorexf4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:XF 0 "nonmemory_operand" "")
- (match_operand:XF 1 "nonmemory_operand" "")))]
+ (compare:CC (match_operand:XF 2 "nonmemory_operand" "")
+ (match_operand:XF 3 "nonmemory_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "ix86_fp_comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
"TARGET_80387"
{
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
+ DONE;
+})
+
+(define_expand "cbranch<mode>4"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
+ (match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
+ (set (pc) (if_then_else
+ (match_operator 0 "ix86_fp_comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+{
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
DONE;
})
-(define_expand "cmp<mode>"
+(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:MODEF 0 "cmp_fp_expander_operand" "")
- (match_operand:MODEF 1 "cmp_fp_expander_operand" "")))]
+ (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
+ (match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
+ (set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "ix86_fp_comparison_operator"
+ [(reg:CC FLAGS_REG)
+ (const_int 0)]))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
+ DONE;
+})
+
+(define_expand "cbranchcc4"
+ [(set (pc) (if_then_else
+ (match_operator 0 "comparison_operator"
+ [(match_operand 1 "flags_reg_operand" "")
+ (match_operand 2 "const0_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ ""
+{
+ ix86_compare_op0 = operands[1];
+ ix86_compare_op1 = operands[2];
+ ix86_expand_branch (GET_CODE (operands[0]), operands[3]);
+ DONE;
+})
+
+(define_expand "cstorecc4"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (match_operator 1 "comparison_operator"
+ [(match_operand 2 "flags_reg_operand" "")
+ (match_operand 3 "const0_operand" "")]))]
+ ""
+{
+ ix86_compare_op0 = operands[2];
+ ix86_compare_op1 = operands[3];
+ ix86_expand_setcc (GET_CODE (operands[1]), operands[0]);
DONE;
})
+
;; FP compares, step 1:
;; Set the FP condition codes.
;;
(unspec:HI
[(compare:CCFP
(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "X"))]
+ (match_operand 2 "const0_operand" ""))]
UNSPEC_FNSTSW))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
[(set (reg:CCFP FLAGS_REG)
(compare:CCFP
(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "X")))
+ (match_operand 2 "const0_operand" "")))
(clobber (match_operand:HI 0 "register_operand" "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
[(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
UNSPEC_FNSTSW))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
- && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
+ && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
&& (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "multi")
(clobber (match_operand:HI 0 "register_operand" "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
- && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
+ && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
&& (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
"#"
"&& reload_completed"
(unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
"TARGET_80387"
"fnstsw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "SI")
(set_attr "unit" "i387")])
#ifdef HAVE_AS_IX86_SAHF
return "sahf";
#else
- return ".byte\t0x9e";
+ return ASM_BYTE "0x9e";
#endif
}
[(set_attr "length" "1")
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 0);"
[(set_attr "type" "fcmp,ssecomi")
+ (set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set (attr "prefix_rep")
+ (if_then_else (eq_attr "type" "ssecomi")
+ (const_string "0")
+ (const_string "*")))
+ (set (attr "prefix_data16")
+ (cond [(eq_attr "type" "fcmp")
+ (const_string "*")
+ (eq_attr "mode" "DF")
+ (const_string "1")
+ ]
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 0);"
[(set_attr "type" "ssecomi")
+ (set_attr "prefix" "maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
[(set_attr "type" "fcmp,ssecomi")
+ (set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set (attr "prefix_rep")
+ (if_then_else (eq_attr "type" "ssecomi")
+ (const_string "0")
+ (const_string "*")))
+ (set (attr "prefix_data16")
+ (cond [(eq_attr "type" "fcmp")
+ (const_string "*")
+ (eq_attr "mode" "DF")
+ (const_string "1")
+ ]
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
[(set_attr "type" "ssecomi")
+ (set_attr "prefix" "maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
+ (set_attr "prefix_rep" "0")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "DF")
+ (const_string "1")
+ (const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")])
(define_insn "*movsi_xor"
[(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "const0_operand" "i"))
+ (match_operand:SI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
+ "reload_completed"
"xor{l}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "SI")
(match_operand:SI 1 "immediate_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
- && operands[1] == constm1_rtx
- && (TARGET_MOVE_M1_VIA_OR || optimize_size)"
+ && operands[1] == constm1_rtx"
{
operands[1] = constm1_rtx;
return "or{l}\t{%1, %0|%0, %1}";
(define_insn "*movsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=r ,m ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Yi,*x")
+ "=r,m ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Yi,*x")
(match_operand:SI 1 "general_operand"
- "rinm,rin,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r ,m "))]
+ "g ,ri,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r ,m "))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (get_attr_type (insn))
{
case TYPE_SSELOG1:
if (get_attr_mode (insn) == MODE_TI)
- return "pxor\t%0, %0";
- return "xorps\t%0, %0";
+ return "%vpxor\t%0, %d0";
+ return "%vxorps\t%0, %d0";
case TYPE_SSEMOV:
switch (get_attr_mode (insn))
{
case MODE_TI:
- return "movdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_V4SF:
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_SI:
- return "movd\t{%1, %0|%0, %1}";
+ return "%vmovd\t{%1, %0|%0, %1}";
case MODE_SF:
- return "movss\t{%1, %0|%0, %1}";
+ return "%vmovss\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
- case TYPE_MMXADD:
+ case TYPE_MMX:
return "pxor\t%0, %0";
case TYPE_MMXMOV:
}
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
- (const_string "mmxadd")
+ (const_string "mmx")
(eq_attr "alternative" "3,4,5")
(const_string "mmxmov")
(eq_attr "alternative" "6")
(const_string "lea")
]
(const_string "imov")))
+ (set (attr "prefix")
+ (if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
+ (const_string "orig")
+ (const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(const_string "DI")
;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushhi2_rex64"
[(set (match_operand:HI 0 "push_operand" "=X")
- (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
+ (match_operand:HI 1 "nonmemory_no_elim_operand" "rn"))]
"TARGET_64BIT"
"push{q}\t%q1"
[(set_attr "type" "push")
}
}
[(set (attr "type")
- (cond [(ne (symbol_ref "optimize_size") (const_int 0))
+ (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
(const_string "imov")
(and (eq_attr "alternative" "0")
(ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(match_operand:HI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
- "!TARGET_PARTIAL_REG_STALL || optimize_size"
+ "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
"xchg{l}\t%k1, %k0"
[(set_attr "type" "imov")
(set_attr "mode" "SI")
(define_expand "movstricthi"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
(match_operand:HI 1 "general_operand" ""))]
- "! TARGET_PARTIAL_REG_STALL || optimize_size"
+ ""
{
+ if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
+ FAIL;
/* Don't generate memory->memory moves, go through a register */
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
(define_insn "*movstricthi_1"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
(match_operand:HI 1 "general_operand" "rn,m"))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"mov{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "imov")
(define_insn "*movstricthi_xor"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
- (match_operand:HI 1 "const0_operand" "i"))
+ (match_operand:HI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
+ "reload_completed"
"xor{w}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "HI")
;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushqi2_rex64"
[(set (match_operand:QI 0 "push_operand" "=X")
- (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
+ (match_operand:QI 1 "nonmemory_no_elim_operand" "qn"))]
"TARGET_64BIT"
"push{q}\t%q1"
[(set_attr "type" "push")
(cond [(and (eq_attr "alternative" "5")
(not (match_operand:QI 1 "aligned_operand" "")))
(const_string "imovx")
- (ne (symbol_ref "optimize_size") (const_int 0))
+ (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
(const_string "imov")
(and (eq_attr "alternative" "3")
(ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(and (eq_attr "alternative" "0,1")
(and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
(const_int 0))
- (and (eq (symbol_ref "optimize_size")
+ (and (eq (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(const_int 0))))))
(match_operand:QI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
- "!TARGET_PARTIAL_REG_STALL || optimize_size"
+ "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
"xchg{l}\t%k1, %k0"
[(set_attr "type" "imov")
(set_attr "mode" "SI")
(define_expand "movstrictqi"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
(match_operand:QI 1 "general_operand" ""))]
- "! TARGET_PARTIAL_REG_STALL || optimize_size"
+ ""
{
+ if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
+ FAIL;
/* Don't generate memory->memory moves, go through a register. */
if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (QImode, operands[1]);
(define_insn "*movstrictqi_1"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(match_operand:QI 1 "general_operand" "*qn,m"))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"mov{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "imov")
(define_insn "*movstrictqi_xor"
[(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
- (match_operand:QI 1 "const0_operand" "i"))
+ (match_operand:QI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
+ "reload_completed"
"xor{b}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")
"TARGET_64BIT"
"movz{bl|x}\t{%h1, %k0|%k0, %h1}"
[(set_attr "type" "imovx")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "SI")])
(define_insn "*movsi_extzv_1"
[(set (match_operand:SI 0 "register_operand" "=R")
(define_insn "*movdi_xor_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (match_operand:DI 1 "const0_operand" "i"))
+ (match_operand:DI 1 "const0_operand" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
+ "TARGET_64BIT
&& reload_completed"
"xor{l}\t%k0, %k0";
[(set_attr "type" "alu1")
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const_int_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (TARGET_MOVE_M1_VIA_OR || optimize_size)
+ "TARGET_64BIT
&& reload_completed
&& operands[1] == constm1_rtx"
{
pxor\t%0, %0
movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}
- pxor\t%0, %0
- movq\t{%1, %0|%0, %1}
- movdqa\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
+ %vpxor\t%0, %d0
+ %vmovq\t{%1, %0|%0, %1}
+ %vmovdqa\t{%1, %0|%0, %1}
+ %vmovq\t{%1, %0|%0, %1}
xorps\t%0, %0
movlps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}
movlps\t{%1, %0|%0, %1}"
[(set_attr "type" "*,*,mmx,mmxmov,mmxmov,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
+ (set (attr "prefix")
+ (if_then_else (eq_attr "alternative" "5,6,7,8")
+ (const_string "vex")
+ (const_string "orig")))
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF")])
(define_split
return "movdq2q\t{%1, %0|%0, %1}";
case TYPE_SSEMOV:
+ if (TARGET_AVX)
+ {
+ if (get_attr_mode (insn) == MODE_TI)
+ return "vmovdqa\t{%1, %0|%0, %1}";
+ else
+ return "vmovq\t{%1, %0|%0, %1}";
+ }
+
if (get_attr_mode (insn) == MODE_TI)
return "movdqa\t{%1, %0|%0, %1}";
/* FALLTHRU */
return "movq\t{%1, %0|%0, %1}";
case TYPE_SSELOG1:
- case TYPE_MMXADD:
+ return "%vpxor\t%0, %d0";
+
+ case TYPE_MMX:
return "pxor\t%0, %0";
case TYPE_MULTI:
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5")
- (const_string "mmxadd")
+ (const_string "mmx")
(eq_attr "alternative" "6,7,8,9,10")
(const_string "mmxmov")
(eq_attr "alternative" "11")
(const_string "lea")
]
(const_string "imov")))
- (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")
- (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")
+ (set (attr "modrm")
+ (if_then_else
+ (and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
+ (const_string "0")
+ (const_string "*")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
+ (const_string "8")
+ (const_string "*")))
+ (set_attr "prefix_rex" "*,*,*,*,*,*,*,1,*,1,*,*,*,*,*,*,*,*,*")
+ (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,1,*,*,*")
+ (set (attr "prefix")
+ (if_then_else (eq_attr "alternative" "11,12,13,14,15,16")
+ (const_string "maybe_vex")
+ (const_string "orig")))
(set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,DI,DI,TI,TI,DI,DI,DI,DI,DI,DI")])
;; Stores and loads of ax to arbitrary constant address.
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "double")])
+(define_expand "movoi"
+ [(set (match_operand:OI 0 "nonimmediate_operand" "")
+ (match_operand:OI 1 "general_operand" ""))]
+ "TARGET_AVX"
+ "ix86_expand_move (OImode, operands); DONE;")
+
+(define_insn "*movoi_internal"
+ [(set (match_operand:OI 0 "nonimmediate_operand" "=x,x,m")
+ (match_operand:OI 1 "vector_move_operand" "C,xm,x"))]
+ "TARGET_AVX
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ return "vxorps\t%0, %0, %0";
+ case 1:
+ case 2:
+ if (misaligned_operand (operands[0], OImode)
+ || misaligned_operand (operands[1], OImode))
+ return "vmovdqu\t{%1, %0|%0, %1}";
+ else
+ return "vmovdqa\t{%1, %0|%0, %1}";
+ default:
+ gcc_unreachable ();
+ }
+}
+ [(set_attr "type" "sselog1,ssemov,ssemov")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "OI")])
+
(define_expand "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "nonimmediate_operand" ""))]
{
case 0:
if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
+ return "%vxorps\t%0, %d0";
else
- return "pxor\t%0, %0";
+ return "%vpxor\t%0, %d0";
case 1:
case 2:
/* TDmode values are passed as TImode on the stack. Moving them
to stack may result in unaligned memory access. */
if (misaligned_operand (operands[0], TImode)
|| misaligned_operand (operands[1], TImode))
- {
+ {
if (get_attr_mode (insn) == MODE_V4SF)
- return "movups\t{%1, %0|%0, %1}";
+ return "%vmovups\t{%1, %0|%0, %1}";
else
- return "movdqu\t{%1, %0|%0, %1}";
+ return "%vmovdqu\t{%1, %0|%0, %1}";
}
else
- {
+ {
if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
else
- return "movdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
}
default:
gcc_unreachable ();
}
}
[(set_attr "type" "sselog1,ssemov,ssemov")
+ (set_attr "prefix" "maybe_vex")
(set (attr "mode")
(cond [(ior (eq (symbol_ref "TARGET_SSE2") (const_int 0))
- (ne (symbol_ref "optimize_size") (const_int 0)))
+ (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0)))
(const_string "V4SF")
(and (eq_attr "alternative" "2")
(ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
(const_string "TI")))])
(define_insn "*movti_rex64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=!r,o,x,x,xm")
(match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
"TARGET_64BIT
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
return "#";
case 2:
if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
+ return "%vxorps\t%0, %d0";
else
- return "pxor\t%0, %0";
+ return "%vpxor\t%0, %d0";
case 3:
case 4:
/* TDmode values are passed as TImode on the stack. Moving them
to stack may result in unaligned memory access. */
if (misaligned_operand (operands[0], TImode)
|| misaligned_operand (operands[1], TImode))
- {
+ {
if (get_attr_mode (insn) == MODE_V4SF)
- return "movups\t{%1, %0|%0, %1}";
+ return "%vmovups\t{%1, %0|%0, %1}";
else
- return "movdqu\t{%1, %0|%0, %1}";
+ return "%vmovdqu\t{%1, %0|%0, %1}";
}
else
- {
+ {
if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
else
- return "movdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
}
default:
gcc_unreachable ();
}
}
[(set_attr "type" "*,*,sselog1,ssemov,ssemov")
+ (set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex")
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(if_then_else
- (ne (symbol_ref "optimize_size")
+ (ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(const_string "TI"))
(if_then_else
(ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
(const_int 0))
- (ne (symbol_ref "optimize_size")
+ (ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0)))
(const_string "V4SF")
(const_string "TI"))]
[(set (match_dup 0)
(match_dup 2))])
-
;; %%% Kill this when call knows how to work this out.
(define_split
[(set (match_operand:SF 0 "push_operand" "")
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
- || (!TARGET_SSE_MATH && optimize_size
+ || (!TARGET_SSE_MATH && optimize_function_for_size_p (cfun)
&& standard_80387_constant_p (operands[1]))
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], SFmode))"
return "mov{l}\t{%1, %0|%0, %1}";
case 5:
if (get_attr_mode (insn) == MODE_TI)
- return "pxor\t%0, %0";
+ return "%vpxor\t%0, %d0";
else
- return "xorps\t%0, %0";
+ return "%vxorps\t%0, %d0";
case 6:
if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
+ else
+ return "%vmovss\t{%1, %d0|%d0, %1}";
+ case 7:
+ if (TARGET_AVX)
+ return REG_P (operands[1]) ? "vmovss\t{%1, %0, %0|%0, %0, %1}"
+ : "vmovss\t{%1, %0|%0, %1}";
else
return "movss\t{%1, %0|%0, %1}";
- case 7: case 8:
- return "movss\t{%1, %0|%0, %1}";
+ case 8:
+ return "%vmovss\t{%1, %0|%0, %1}";
- case 9: case 10:
- case 12: case 13: case 14: case 15:
+ case 9: case 10: case 14: case 15:
return "movd\t{%1, %0|%0, %1}";
+ case 12: case 13:
+ return "%vmovd\t{%1, %0|%0, %1}";
case 11:
return "movq\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "fmov,fmov,fmov,imov,imov,sselog1,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov,ssemov,ssemov,mmxmov,mmxmov")
+ (set (attr "prefix")
+ (if_then_else (eq_attr "alternative" "5,6,7,8,12,13")
+ (const_string "maybe_vex")
+ (const_string "orig")))
(set (attr "mode")
(cond [(eq_attr "alternative" "3,4,9,10")
(const_string "SI")
(const_int 0))
(ne (symbol_ref "TARGET_SSE2")
(const_int 0)))
- (eq (symbol_ref "optimize_size")
+ (eq (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0)))
(const_string "TI")
(const_string "V4SF"))
(match_operand:DF 1 "general_operand"
"fm,f,G,*roF,*Fr,C ,Y2*x,mY2*x,Y2*x"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
- && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
+ && ((optimize_function_for_size_p (cfun)
+ || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
- || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
+ || (!(TARGET_SSE2 && TARGET_SSE_MATH)
+ && optimize_function_for_size_p (cfun)
&& !memory_operand (operands[0], DFmode)
&& standard_80387_constant_p (operands[1]))
|| GET_CODE (operands[1]) != CONST_DOUBLE
- || ((optimize_size
+ || ((optimize_function_for_size_p (cfun)
|| !TARGET_MEMORY_MISMATCH_STALL
|| reload_in_progress || reload_completed)
&& memory_operand (operands[0], DFmode)))"
switch (get_attr_mode (insn))
{
case MODE_V4SF:
- return "xorps\t%0, %0";
+ return "%vxorps\t%0, %d0";
case MODE_V2DF:
- return "xorpd\t%0, %0";
+ return "%vxorpd\t%0, %d0";
case MODE_TI:
- return "pxor\t%0, %0";
+ return "%vpxor\t%0, %d0";
default:
gcc_unreachable ();
}
switch (get_attr_mode (insn))
{
case MODE_V4SF:
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
- return "movapd\t{%1, %0|%0, %1}";
+ return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_TI:
- return "movdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_DI:
- return "movq\t{%1, %0|%0, %1}";
+ return "%vmovq\t{%1, %0|%0, %1}";
case MODE_DF:
- return "movsd\t{%1, %0|%0, %1}";
+ if (TARGET_AVX)
+ {
+ if (REG_P (operands[0]) && REG_P (operands[1]))
+ return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
+ else
+ return "vmovsd\t{%1, %0|%0, %1}";
+ }
+ else
+ return "movsd\t{%1, %0|%0, %1}";
case MODE_V1DF:
- return "movlpd\t{%1, %0|%0, %1}";
+ if (TARGET_AVX)
+ {
+ if (REG_P (operands[0]))
+ return "vmovlpd\t{%1, %0, %0|%0, %0, %1}";
+ else
+ return "vmovlpd\t{%1, %0|%0, %1}";
+ }
+ else
+ return "movlpd\t{%1, %0|%0, %1}";
case MODE_V2SF:
- return "movlps\t{%1, %0|%0, %1}";
+ if (TARGET_AVX)
+ {
+ if (REG_P (operands[0]))
+ return "vmovlps\t{%1, %0, %0|%0, %0, %1}";
+ else
+ return "vmovlps\t{%1, %0|%0, %1}";
+ }
+ else
+ return "movlps\t{%1, %0|%0, %1}";
default:
gcc_unreachable ();
}
}
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
+ (set (attr "prefix")
+ (if_then_else (eq_attr "alternative" "0,1,2,3,4")
+ (const_string "orig")
+ (const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
/* xorps is one byte shorter. */
(eq_attr "alternative" "5")
- (cond [(ne (symbol_ref "optimize_size")
+ (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
movaps encodes one byte shorter. */
(eq_attr "alternative" "6")
(cond
- [(ne (symbol_ref "optimize_size")
+ [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
- || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
+ || (!(TARGET_SSE2 && TARGET_SSE_MATH)
+ && optimize_function_for_size_p (cfun)
&& standard_80387_constant_p (operands[1]))
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], DFmode))"
switch (get_attr_mode (insn))
{
case MODE_V4SF:
- return "xorps\t%0, %0";
+ return "%vxorps\t%0, %d0";
case MODE_V2DF:
- return "xorpd\t%0, %0";
+ return "%vxorpd\t%0, %d0";
case MODE_TI:
- return "pxor\t%0, %0";
+ return "%vpxor\t%0, %d0";
default:
gcc_unreachable ();
}
switch (get_attr_mode (insn))
{
case MODE_V4SF:
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
- return "movapd\t{%1, %0|%0, %1}";
+ return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_TI:
- return "movdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_DI:
- return "movq\t{%1, %0|%0, %1}";
+ return "%vmovq\t{%1, %0|%0, %1}";
case MODE_DF:
- return "movsd\t{%1, %0|%0, %1}";
+ if (TARGET_AVX)
+ {
+ if (REG_P (operands[0]) && REG_P (operands[1]))
+ return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
+ else
+ return "vmovsd\t{%1, %0|%0, %1}";
+ }
+ else
+ return "movsd\t{%1, %0|%0, %1}";
case MODE_V1DF:
- return "movlpd\t{%1, %0|%0, %1}";
+ return "%vmovlpd\t{%1, %d0|%d0, %1}";
case MODE_V2SF:
- return "movlps\t{%1, %0|%0, %1}";
+ return "%vmovlps\t{%1, %d0|%d0, %1}";
default:
gcc_unreachable ();
}
case 9:
case 10:
- return "movd\t{%1, %0|%0, %1}";
+ return "%vmovd\t{%1, %0|%0, %1}";
default:
gcc_unreachable();
}
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov,ssemov,ssemov")
+ (set (attr "prefix")
+ (if_then_else (eq_attr "alternative" "0,1,2,3,4")
+ (const_string "orig")
+ (const_string "maybe_vex")))
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
/* xorps is one byte shorter. */
(eq_attr "alternative" "5")
- (cond [(ne (symbol_ref "optimize_size")
+ (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
movaps encodes one byte shorter. */
(eq_attr "alternative" "6")
(cond
- [(ne (symbol_ref "optimize_size")
+ [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(match_operand:DF 1 "general_operand"
"fm,f,G,roF,Fr,C ,Y2*x,m ,Y2*x"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
- && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
+ && optimize_function_for_speed_p (cfun)
+ && TARGET_INTEGER_DFMODE_MOVES
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
- || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
+ || (!(TARGET_SSE2 && TARGET_SSE_MATH)
+ && optimize_function_for_size_p (cfun)
&& standard_80387_constant_p (operands[1]))
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], DFmode))"
}
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "mode" "V1DF")
+ (const_string "1")
+ (const_string "*")))
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
/* xorps is one byte shorter. */
(eq_attr "alternative" "5")
- (cond [(ne (symbol_ref "optimize_size")
+ (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
movaps encodes one byte shorter. */
(eq_attr "alternative" "6")
(cond
- [(ne (symbol_ref "optimize_size")
+ [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(define_insn "*pushxf_nointeger"
[(set (match_operand:XF 0 "push_operand" "=X,X,X")
(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
- "optimize_size"
+ "optimize_function_for_size_p (cfun)"
{
/* This insn should be already split before reg-stack. */
gcc_unreachable ();
(define_insn "*pushxf_integer"
[(set (match_operand:XF 0 "push_operand" "=<,<")
(match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
- "!optimize_size"
+ "optimize_function_for_speed_p (cfun)"
{
/* This insn should be already split before reg-stack. */
gcc_unreachable ();
(define_insn "*movxf_nointeger"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
- "optimize_size
+ "optimize_function_for_size_p (cfun)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (reload_in_progress || reload_completed
- || (optimize_size && standard_80387_constant_p (operands[1]))
+ || standard_80387_constant_p (operands[1])
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], XFmode))"
{
(define_insn "*movxf_integer"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,r,o")
(match_operand:XF 1 "general_operand" "fm,f,G,roF,Fr"))]
- "!optimize_size
+ "optimize_function_for_speed_p (cfun)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (reload_in_progress || reload_completed
- || (optimize_size && standard_80387_constant_p (operands[1]))
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| memory_operand (operands[0], XFmode))"
{
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "nonimmediate_operand" ""))]
- "TARGET_64BIT"
+ "TARGET_SSE2"
{
ix86_expand_move (TFmode, operands);
DONE;
(define_insn "*movtf_internal"
[(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?r,?o")
(match_operand:TF 1 "general_operand" "xm,x,C,roF,Fr"))]
- "TARGET_64BIT
+ "TARGET_SSE2
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
case 0:
case 1:
if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
else
- return "movdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
case 2:
if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
+ return "%vxorps\t%0, %d0";
else
- return "pxor\t%0, %0";
+ return "%vpxor\t%0, %d0";
case 3:
case 4:
return "#";
}
}
[(set_attr "type" "ssemov,ssemov,sselog1,*,*")
+ (set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,*,*")
(set (attr "mode")
(cond [(eq_attr "alternative" "0,2")
(if_then_else
- (ne (symbol_ref "optimize_size")
+ (ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0))
(const_string "V4SF")
(const_string "TI"))
(if_then_else
(ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
(const_int 0))
- (ne (symbol_ref "optimize_size")
+ (ne (symbol_ref "optimize_function_for_size_p (cfun)")
(const_int 0)))
(const_string "V4SF")
(const_string "TI"))]
(const_string "DI")))])
+(define_insn "*pushtf_sse"
+ [(set (match_operand:TF 0 "push_operand" "=<,<,<")
+ (match_operand:TF 1 "general_no_elim_operand" "x,Fo,*r"))]
+ "TARGET_SSE2"
+{
+ /* This insn should be already split before reg-stack. */
+ gcc_unreachable ();
+}
+ [(set_attr "type" "multi")
+ (set_attr "unit" "sse,*,*")
+ (set_attr "mode" "TF,SI,SI")])
+
+(define_split
+ [(set (match_operand:TF 0 "push_operand" "")
+ (match_operand:TF 1 "general_operand" ""))]
+ "TARGET_SSE2 && reload_completed
+ && !SSE_REG_P (operands[1])"
+ [(const_int 0)]
+ "ix86_split_long_move (operands); DONE;")
+
+(define_split
+ [(set (match_operand:TF 0 "push_operand" "")
+ (match_operand:TF 1 "any_fp_register_operand" ""))]
+ "TARGET_SSE2"
+ [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16)))
+ (set (mem:TF (reg:P SP_REG)) (match_dup 1))]
+ "")
+
(define_split
[(set (match_operand 0 "nonimmediate_operand" "")
(match_operand 1 "general_operand" ""))]
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
""
{
- if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
+ if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
{
operands[1] = force_reg (HImode, operands[1]);
emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
+ "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "alu1")
(set_attr "mode" "SI")])
[(set (match_operand:SI 0 "register_operand" "")
(zero_extend:SI (match_operand:HI 1 "register_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
+ "reload_completed && TARGET_ZERO_EXTEND_WITH_AND
+ && optimize_function_for_speed_p (cfun)"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
(clobber (reg:CC FLAGS_REG))])]
"")
(define_insn "*zero_extendhisi2_movzwl"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
- "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
+ "!TARGET_ZERO_EXTEND_WITH_AND
+ || optimize_function_for_size_p (cfun)"
"movz{wl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
[(set (match_operand:HI 0 "register_operand" "=r,?&q")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
+ "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "alu1")
(set_attr "mode" "HI")])
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
+ "!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)"
"#"
[(set_attr "type" "imovx,alu1")
(set_attr "mode" "HI")])
(define_insn "*zero_extendqihi2_movzbl"
[(set (match_operand:HI 0 "register_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
- "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
+ "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
+ && reload_completed"
"movz{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
- && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
+ && (!TARGET_ZERO_EXTEND_WITH_AND
+ || optimize_function_for_size_p (cfun))
&& (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
- && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
+ && (TARGET_ZERO_EXTEND_WITH_AND
+ && optimize_function_for_speed_p (cfun))
&& !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0) (const_int 0))
- (set (strict_low_part (match_dup 2)) (match_dup 1))]
- "operands[2] = gen_lowpart (QImode, operands[0]);")
+ [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+{
+ operands[2] = gen_lowpart (QImode, operands[0]);
+ ix86_expand_clear (operands[0]);
+})
;; Rest is handled by single and.
(define_split
[(set (match_operand:SI 0 "register_operand" "=r,?&q")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
+ "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "alu1")
(set_attr "mode" "SI")])
-(define_insn "*zero_extendqisi2_movzbw_and"
+(define_insn "*zero_extendqisi2_movzbl_and"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
+ "!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)"
"#"
[(set_attr "type" "imovx,alu1")
(set_attr "mode" "SI")])
-(define_insn "*zero_extendqisi2_movzbw"
+(define_insn "*zero_extendqisi2_movzbl"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
- "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
+ "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
+ && reload_completed"
"movz{bl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
- && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
+ && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
&& (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
[(set (match_dup 0)
(zero_extend:SI (match_dup 1)))])
"reload_completed
&& ANY_QI_REG_P (operands[0])
&& (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
- && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
+ && (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
&& !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (match_dup 0) (const_int 0))
- (set (strict_low_part (match_dup 2)) (match_dup 1))]
- "operands[2] = gen_lowpart (QImode, operands[0]);")
+ [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+{
+ operands[2] = gen_lowpart (QImode, operands[0]);
+ ix86_expand_clear (operands[0]);
+})
;; Rest is handled by single and.
(define_split
#
movd\t{%1, %0|%0, %1}
movd\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}"
- [(set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")
- (set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")])
+ %vmovd\t{%1, %0|%0, %1}
+ %vmovd\t{%1, %0|%0, %1}"
+ [(set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")
+ (set_attr "prefix" "*,*,*,orig,orig,maybe_vex,maybe_vex")
+ (set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")])
(define_insn "zero_extendsidi2_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Y2")
#
movd\t{%1, %0|%0, %1}
movd\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}"
+ %vmovd\t{%1, %0|%0, %1}
+ %vmovd\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx,imov,mmxmov,mmxmov,ssemov,ssemov")
+ (set_attr "prefix" "orig,*,orig,orig,maybe_vex,maybe_vex")
+ (set_attr "prefix_0f" "0,*,*,*,*,*")
(set_attr "mode" "SI,DI,DI,DI,TI,TI")])
(define_split
"TARGET_64BIT"
"movz{wl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "SI")])
(define_insn "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=r")
"TARGET_64BIT"
"movz{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "SI")])
\f
;; Sign extension instructions
"TARGET_64BIT"
"@
{cltq|cdqe}
- movs{lq|x}\t{%1,%0|%0, %1}"
+ movs{lq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")
(set_attr "prefix_0f" "0")
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_64BIT"
- "movs{wq|x}\t{%1,%0|%0, %1}"
+ "movs{wq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"TARGET_64BIT"
- "movs{bq|x}\t{%1,%0|%0, %1}"
+ "movs{bq|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "DI")])
emit_move_insn (operands[3], operands[1]);
/* Generate a cltd if possible and doing so it profitable. */
- if ((optimize_size || TARGET_USE_CLTD)
+ if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
&& true_regnum (operands[1]) == AX_REG
&& true_regnum (operands[2]) == DX_REG)
{
emit_move_insn (operands[3], operands[1]);
/* Generate a cltd if possible and doing so it profitable. */
- if ((optimize_size || TARGET_USE_CLTD)
+ if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
&& true_regnum (operands[3]) == AX_REG)
{
emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
case 0:
return "{cwtl|cwde}";
default:
- return "movs{wl|x}\t{%1,%0|%0, %1}";
+ return "movs{wl|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
case 0:
return "{cwtl|cwde}";
default:
- return "movs{wl|x}\t{%1,%k0|%k0, %1}";
+ return "movs{wl|x}\t{%1, %k0|%k0, %1}";
}
}
[(set_attr "type" "imovx")
case 0:
return "{cbtw|cbw}";
default:
- return "movs{bw|x}\t{%1,%0|%0, %1}";
+ return "movs{bw|x}\t{%1, %0|%0, %1}";
}
}
[(set_attr "type" "imovx")
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
""
- "movs{bl|x}\t{%1,%0|%0, %1}"
+ "movs{bl|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(zero_extend:DI
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
"TARGET_64BIT"
- "movs{bl|x}\t{%1,%k0|%k0, %1}"
+ "movs{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
\f
[(set (match_operand:DF 0 "register_operand" "")
(float_extend:DF
(match_operand:SF 1 "nonimmediate_operand" "")))]
- "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
+ "TARGET_USE_VECTOR_FP_CONVERTS
+ && optimize_insn_for_speed_p ()
&& reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 2)
(float_extend:V2DF
return output_387_reg_move (insn, operands);
case 2:
- return "cvtss2sd\t{%1, %0|%0, %1}";
+ return "%vcvtss2sd\t{%1, %d0|%d0, %1}";
default:
gcc_unreachable ();
}
}
[(set_attr "type" "fmov,fmov,ssecvt")
+ (set_attr "prefix" "orig,orig,maybe_vex")
(set_attr "mode" "SF,XF,DF")])
(define_insn "*extendsfdf2_sse"
[(set (match_operand:DF 0 "nonimmediate_operand" "=x")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && TARGET_SSE_MATH"
- "cvtss2sd\t{%1, %0|%0, %1}"
+ "%vcvtss2sd\t{%1, %d0|%d0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "DF")])
(define_insn "*extendsfdf2_i387"
;
else
{
- int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
rtx temp = assign_386_stack_local (SFmode, slot);
emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
DONE;
[(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "")))]
- "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
+ "TARGET_USE_VECTOR_FP_CONVERTS
+ && optimize_insn_for_speed_p ()
&& reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 2)
(vec_concat:V4SF
case 0:
return output_387_reg_move (insn, operands);
case 1:
- return "cvtsd2ss\t{%1, %0|%0, %1}";
+ return "%vcvtsd2ss\t{%1, %d0|%d0, %1}";
default:
gcc_unreachable ();
}
}
[(set_attr "type" "fmov,ssecvt")
+ (set_attr "prefix" "orig,maybe_vex")
(set_attr "mode" "SF")])
;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2 && TARGET_SSE_MATH"
- "cvtsd2ss\t{%1, %0|%0, %1}"
+ "%vcvtsd2ss\t{%1, %d0|%d0, %1}"
[(set_attr "type" "ssecvt")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "SF")])
(define_insn "*truncdfsf_fast_i387"
(set_attr "mode" "SF")])
(define_insn "*truncdfsf_mixed"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y2")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,Y2 ,?f,?x,?*r")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Y2m")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))]
+ (match_operand:DF 1 "nonimmediate_operand" "f ,Y2m,f ,f ,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,X ,m ,m ,m"))]
"TARGET_MIX_SSE_I387"
{
switch (which_alternative)
{
case 0:
return output_387_reg_move (insn, operands);
-
case 1:
- return "#";
- case 2:
- return "cvtsd2ss\t{%1, %0|%0, %1}";
+ return "%vcvtsd2ss\t{%1, %d0|%d0, %1}";
+
default:
- gcc_unreachable ();
+ return "#";
}
}
- [(set_attr "type" "fmov,multi,ssecvt")
- (set_attr "unit" "*,i387,*")
+ [(set_attr "type" "fmov,ssecvt,multi,multi,multi")
+ (set_attr "unit" "*,*,i387,i387,i387")
+ (set_attr "prefix" "orig,maybe_vex,orig,orig,orig")
(set_attr "mode" "SF")])
(define_insn "*truncdfsf_i387"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "f,f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
+ (match_operand:DF 1 "nonimmediate_operand" "f ,f ,f ,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
"TARGET_80387"
{
switch (which_alternative)
case 0:
return output_387_reg_move (insn, operands);
- case 1:
- return "#";
default:
- gcc_unreachable ();
+ return "#";
}
}
- [(set_attr "type" "fmov,multi")
- (set_attr "unit" "*,i387")
+ [(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "SF")])
(define_insn "*truncdfsf2_i387_1"
}
else
{
- int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
operands[2] = assign_386_stack_local (<MODE>mode, slot);
}
})
(define_insn "*truncxfsf2_mixed"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
(float_truncate:SF
- (match_operand:XF 1 "register_operand" "f,f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
+ (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m ,m ,m"))]
"TARGET_80387"
{
gcc_assert (!which_alternative);
return output_387_reg_move (insn, operands);
}
- [(set_attr "type" "fmov,multi")
- (set_attr "unit" "*,i387")
+ [(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "SF")])
(define_insn "*truncxfdf2_mixed"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fY2*r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?Y2,?*r")
(float_truncate:DF
- (match_operand:XF 1 "register_operand" "f,f")))
- (clobber (match_operand:DF 2 "memory_operand" "=X,m"))]
+ (match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
+ (clobber (match_operand:DF 2 "memory_operand" "=X,m ,m ,m"))]
"TARGET_80387"
{
gcc_assert (!which_alternative);
return output_387_reg_move (insn, operands);
}
- [(set_attr "type" "fmov,multi")
- (set_attr "unit" "*,i387")
+ [(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "DF")])
(define_insn "truncxf<mode>2_i387_noop"
(use (match_dup 2))
(clobber (match_scratch:<ssevecmode> 3 ""))
(clobber (match_scratch:<ssevecmode> 4 ""))])]
- "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
+ "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
{
enum machine_mode mode = <MODE>mode;
enum machine_mode vecmode = <ssevecmode>mode;
REAL_VALUE_TYPE TWO31r;
rtx two31;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
real_ldexp (&TWO31r, &dconst1, 31);
two31 = const_double_from_real_value (TWO31r, mode);
two31 = ix86_build_const_vector (mode, true, two31);
(use (match_operand:<ssevecmode> 4 "nonimmediate_operand" "m,x"))
(clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
(clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
- "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
+ "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
+ && optimize_function_for_speed_p (cfun)"
"#"
"&& reload_completed"
[(const_int 0)]
(fix:DI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
"TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)
&& (!TARGET_FISTTP || TARGET_SSE_MATH)"
- "cvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
+ "%vcvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "prefix_rex" "1")
(set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
(fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
"SSE_FLOAT_MODE_P (<MODE>mode)
&& (!TARGET_FISTTP || TARGET_SSE_MATH)"
- "cvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}"
+ "%vcvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "double,vector")
(set_attr "amdfam10_decode" "double,double")])
[(match_scratch:DF 2 "Y2")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
- "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
+ "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
[(match_scratch:SF 2 "x")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
- "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
+ "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
&& !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& (TARGET_64BIT || <MODE>mode != DImode))
&& TARGET_SSE_MATH)
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
&& !TARGET_FISTTP
&& !(SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
&& (TARGET_64BIT || <MODE>mode != DImode))
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
"TARGET_80387"
"fnstcw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")])
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
"TARGET_80387"
"fldcw\t%0"
- [(set_attr "length" "2")
+ [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "HI")
(set_attr "unit" "i387")
(set_attr "athlon_decode" "vector")
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(parallel [(set (match_dup 0)
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)"
- "fild%z1\t%1"
+ "fild%Z1\t%1"
[(set_attr "type" "fmov")
(set_attr "mode" "<MODE>")
(set_attr "fp_int_src" "true")])
"TARGET_80387
|| ((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)"
- "")
+ "
+{
+ if (!((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
+ && SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
+ && !X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode))
+ {
+ rtx reg = gen_reg_rtx (XFmode);
+ rtx insn;
+
+ emit_insn (gen_float<SSEMODEI24:mode>xf2 (reg, operands[1]));
+
+ if (<X87MODEF:MODE>mode == SFmode)
+ insn = gen_truncxfsf2 (operands[0], reg);
+ else if (<X87MODEF:MODE>mode == DFmode)
+ insn = gen_truncxfdf2 (operands[0], reg);
+ else
+ gcc_unreachable ();
+
+ emit_insn (insn);
+ DONE;
+ }
+}")
;; Pre-reload splitter to add memory clobber to the pattern.
(define_insn_and_split "*float<SSEMODEI24:mode><X87MODEF:mode>2_1"
[(set (match_operand:X87MODEF 0 "register_operand" "")
(float:X87MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))]
"((TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
&& (!((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387))
|| ((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH
&& ((<SSEMODEI24:MODE>mode == SImode
- && TARGET_SSE2 && TARGET_USE_VECTOR_CONVERTS && !optimize_size
+ && TARGET_SSE2 && TARGET_USE_VECTOR_CONVERTS
+ && optimize_function_for_speed_p (cfun)
&& flag_trapping_math)
- || !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size))))
- && !(reload_completed || reload_in_progress)"
+ || !(TARGET_INTER_UNIT_CONVERSIONS
+ || optimize_function_for_size_p (cfun)))))
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(parallel [(set (match_dup 0) (float:X87MODEF (match_dup 1)))
/* Avoid store forwarding (partial memory) stall penalty
by passing DImode value through XMM registers. */
- if (<SSEMODEI24:MODE>mode == DImode && !TARGET_64BIT
- && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
- && !optimize_size)
+ if (<SSEMODEI24:MODE>mode == DImode && !TARGET_64BIT
+ && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
+ && optimize_function_for_speed_p (cfun))
{
emit_insn (gen_floatdi<X87MODEF:mode>2_i387_with_xmm (operands[0],
operands[1],
(match_operand:SI 1 "nonimmediate_operand" "m,?r,r,m,!x")))
(clobber (match_operand:SI 2 "memory_operand" "=X,m,m,X,m"))]
"TARGET_SSE2 && TARGET_MIX_SSE_I387
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt,sseicvt")
(set_attr "mode" "<MODE>,<MODE>,<MODE>,<MODE>,<ssevecmode>")
[(set (match_operand:MODEF 0 "register_operand" "=f,x")
(float:MODEF (match_operand:SI 1 "memory_operand" "m,m")))]
"TARGET_SSE2 && TARGET_MIX_SSE_I387
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
"@
- fild%z1\t%1
+ fild%Z1\t%1
#"
[(set_attr "type" "fmov,sseicvt")
(set_attr "mode" "<MODE>,<ssevecmode>")
(clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
"(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
- && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)
+ && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
(match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,r,m")))]
"(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
- && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
+ && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"@
- fild%z1\t%1
- cvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %0|%0, %1}
- cvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %0|%0, %1}"
+ fild%Z1\t%1
+ %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}
+ %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "fmov,sseicvt,sseicvt")
+ (set_attr "prefix" "orig,maybe_vex,maybe_vex")
(set_attr "mode" "<MODEF:MODE>")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "prefix" "maybe_vex")
+ (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+ (const_string "1")
+ (const_string "*")))
(set_attr "unit" "i387,*,*")
(set_attr "athlon_decode" "*,double,direct")
(set_attr "amdfam10_decode" "*,vector,double")
(match_operand:SSEMODEI24 1 "memory_operand" "m,m")))]
"(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
- && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
+ && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
"@
- fild%z1\t%1
- cvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %0|%0, %1}"
+ fild%Z1\t%1
+ %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "fmov,sseicvt")
+ (set_attr "prefix" "orig,maybe_vex")
(set_attr "mode" "<MODEF:MODE>")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "prefix" "maybe_vex")
+ (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+ (const_string "1")
+ (const_string "*")))
(set_attr "athlon_decode" "*,direct")
(set_attr "amdfam10_decode" "*,double")
(set_attr "fp_int_src" "true")])
(match_operand:SI 1 "nonimmediate_operand" "r,m,!x")))
(clobber (match_operand:SI 2 "memory_operand" "=m,X,m"))]
"TARGET_SSE2 && TARGET_SSE_MATH
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "sseicvt")
(set_attr "mode" "<MODE>,<MODE>,<ssevecmode>")
[(set (match_operand:MODEF 0 "register_operand" "=x")
(float:MODEF (match_operand:SI 1 "memory_operand" "m")))]
"TARGET_SSE2 && TARGET_SSE_MATH
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "sseicvt")
(set_attr "mode" "<MODE>")
(float:MODEF (match_operand:SI 1 "register_operand" "")))
(clobber (match_operand:SI 2 "memory_operand" ""))]
"TARGET_SSE2 && TARGET_SSE_MATH
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
(float:MODEF (match_operand:SI 1 "memory_operand" "")))
(clobber (match_operand:SI 2 "memory_operand" ""))]
"TARGET_SSE2 && TARGET_SSE_MATH
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
[(set (match_operand:MODEF 0 "register_operand" "")
(float:MODEF (match_operand:SI 1 "register_operand" "")))]
"TARGET_SSE2 && TARGET_SSE_MATH
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0);
else
gcc_unreachable ();
+ emit_insn
+ (gen_sse2_cvtdq2p<ssemodefsuffix> (operands[3], operands[4]));
+ DONE;
})
(define_split
[(set (match_operand:MODEF 0 "register_operand" "")
(float:MODEF (match_operand:SI 1 "memory_operand" "")))]
"TARGET_SSE2 && TARGET_SSE_MATH
- && TARGET_USE_VECTOR_CONVERTS && !optimize_size
+ && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
(match_operand:SSEMODEI24 1 "nonimmediate_operand" "r,m")))]
"(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
- && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
- "cvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %0|%0, %1}"
+ && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
+ "%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODEF:MODE>")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "prefix" "maybe_vex")
+ (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+ (const_string "1")
+ (const_string "*")))
(set_attr "athlon_decode" "double,direct")
(set_attr "amdfam10_decode" "vector,double")
(set_attr "fp_int_src" "true")])
(clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
"(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
- && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)
+ && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
(match_operand:SSEMODEI24 1 "memory_operand" "m")))]
"(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
- && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
- "cvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %0|%0, %1}"
+ && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
+ "%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sseicvt")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODEF:MODE>")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "prefix" "maybe_vex")
+ (ne (symbol_ref "<SSEMODEI24:MODE>mode == DImode") (const_int 0)))
+ (const_string "1")
+ (const_string "*")))
(set_attr "athlon_decode" "direct")
(set_attr "amdfam10_decode" "double")
(set_attr "fp_int_src" "true")])
(clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
"(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
- && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)
+ && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
&& reload_completed
&& (SSE_REG_P (operands[0])
|| (GET_CODE (operands[0]) == SUBREG
(float:X87MODEF
(match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,?r")))
(clobber (match_operand:SSEMODEI24 2 "memory_operand" "=X,m"))]
- "TARGET_80387"
+ "TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
"@
- fild%z1\t%1
+ fild%Z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "<X87MODEF:MODE>")
[(set (match_operand:X87MODEF 0 "register_operand" "=f")
(float:X87MODEF
(match_operand:SSEMODEI24 1 "memory_operand" "m")))]
- "TARGET_80387"
- "fild%z1\t%1"
+ "TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
+ "fild%Z1\t%1"
[(set_attr "type" "fmov")
(set_attr "mode" "<X87MODEF:MODE>")
(set_attr "fp_int_src" "true")])
(float:X87MODEF (match_operand:SSEMODEI24 1 "register_operand" "")))
(clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
"TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
&& reload_completed
&& FP_REG_P (operands[0])"
[(set (match_dup 2) (match_dup 1))
(float:X87MODEF (match_operand:SSEMODEI24 1 "memory_operand" "")))
(clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
"TARGET_80387
+ && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
&& reload_completed
&& FP_REG_P (operands[0])"
[(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
(clobber (match_scratch:V4SI 3 "=X,x"))
(clobber (match_scratch:V4SI 4 "=X,x"))
(clobber (match_operand:DI 2 "memory_operand" "=X,m"))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
- && !TARGET_64BIT && !optimize_size"
+ "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
+ && !TARGET_64BIT && optimize_function_for_speed_p (cfun)"
"#"
[(set_attr "type" "multi")
(set_attr "mode" "<X87MODEF:MODE>")
(clobber (match_scratch:V4SI 3 ""))
(clobber (match_scratch:V4SI 4 ""))
(clobber (match_operand:DI 2 "memory_operand" ""))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
- && !TARGET_64BIT && !optimize_size
+ "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
+ && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
&& reload_completed
&& FP_REG_P (operands[0])"
[(set (match_dup 2) (match_dup 3))
(clobber (match_scratch:V4SI 3 ""))
(clobber (match_scratch:V4SI 4 ""))
(clobber (match_operand:DI 2 "memory_operand" ""))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
- && !TARGET_64BIT && !optimize_size
+ "TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
+ && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
&& reload_completed
&& FP_REG_P (operands[0])"
[(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
(clobber (match_operand:DI 2 "memory_operand" "=m,m"))
(clobber (match_scratch:SI 3 "=X,x"))]
"!TARGET_64BIT
- && TARGET_80387 && TARGET_SSE"
+ && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE"
"#"
[(set_attr "type" "multi")
(set_attr "mode" "<MODE>")])
(clobber (match_operand:DI 2 "memory_operand" ""))
(clobber (match_scratch:SI 3 ""))]
"!TARGET_64BIT
- && TARGET_80387 && TARGET_SSE
+ && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE
&& reload_completed"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0)
(clobber (match_operand:DI 2 "memory_operand" ""))
(clobber (match_scratch:SI 3 ""))]
"!TARGET_64BIT
- && TARGET_80387 && TARGET_SSE
+ && TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE
&& reload_completed"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0)
(clobber (match_dup 2))
(clobber (match_scratch:SI 3 ""))])]
"!TARGET_64BIT
- && ((TARGET_80387 && TARGET_SSE)
+ && ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
+ && TARGET_SSE)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
}
else
{
- int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
operands[2] = assign_386_stack_local (DImode, slot);
}
})
\f
;; Add instructions
-;; %%% splits for addditi3
-
-(define_expand "addti3"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "ix86_expand_binary_operator (PLUS, TImode, operands); DONE;")
+(define_expand "add<mode>3"
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
+ (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
+ (match_operand:SDWIM 2 "<general_operand>" "")))]
+ ""
+ "ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;")
-(define_insn "*addti3_1"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
- (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0,0")
- (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
+(define_insn_and_split "*add<dwi>3_doubleword"
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
+ (plus:<DWI>
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
+ (match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, TImode, operands)"
- "#")
-
-(define_split
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
- UNSPEC_ADD_CARRY))
- (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))])
- (parallel [(set (match_dup 3)
- (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 4))
- (match_dup 5)))
- (clobber (reg:CC FLAGS_REG))])]
- "split_ti (&operands[0], 3, &operands[0], &operands[3]);")
-
-;; %%% splits for addsidi3
-; [(set (match_operand:DI 0 "nonimmediate_operand" "")
-; (plus:DI (match_operand:DI 1 "general_operand" "")
-; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
-
-(define_expand "adddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
-
-(define_insn "*adddi3_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "roiF,riF")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "#")
-
-(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
- UNSPEC_ADD_CARRY))
- (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
+ "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
+ "#"
+ "reload_completed"
+ [(parallel [(set (reg:CC FLAGS_REG)
+ (unspec:CC [(match_dup 1) (match_dup 2)]
+ UNSPEC_ADD_CARRY))
+ (set (match_dup 0)
+ (plus:DWIH (match_dup 1) (match_dup 2)))])
(parallel [(set (match_dup 3)
- (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 4))
- (match_dup 5)))
+ (plus:DWIH
+ (plus:DWIH
+ (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+ (match_dup 4))
+ (match_dup 5)))
(clobber (reg:CC FLAGS_REG))])]
- "split_di (&operands[0], 3, &operands[0], &operands[3]);")
+ "split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
-(define_insn "adddi3_carry_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
- (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
+(define_insn "add<mode>3_carry"
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (plus:SWI
+ (plus:SWI (match_operand:SWI 3 "ix86_carry_flag_operator" "")
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "adc{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "DI")])
-
-(define_insn "*adddi3_cc_rex64"
- [(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
- UNSPEC_ADD_CARRY))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
- "add{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
-
-(define_insn "*<plusminus_insn><mode>3_cc_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (plusminus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
- (match_dup 1)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
- (plusminus:SWI (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
- "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*add<mode>3_cconly_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (plus:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>m"))
- (match_dup 1)))
- (clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
- "add{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*sub<mode>3_cconly_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
- (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
- (match_dup 0)))]
- ""
- "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
- [(set_attr "type" "icmp")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (plusminus:SI (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
- (match_operand:SI 2 "general_operand" "g"))
- (match_dup 1)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
- "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "SI")])
-
-(define_insn "addqi3_carry"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
- (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:QI 2 "general_operand" "qi,qm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, QImode, operands)"
- "adc{b}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "QI")])
-
-(define_insn "addhi3_carry"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
- (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:HI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, HImode, operands)"
- "adc{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "HI")])
-
-(define_insn "addsi3_carry"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:SI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, SImode, operands)"
- "adc{l}\t{%2, %0|%0, %2}"
+ "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*addsi3_carry_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 1 "nonimmediate_operand" "%0"))
- (match_operand:SI 2 "general_operand" "g"))))
+ (zero_extend:DI
+ (plus:SI
+ (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
+ (match_operand:SI 1 "nonimmediate_operand" "%0"))
+ (match_operand:SI 2 "general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
"adc{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
-(define_insn "*addsi3_cc"
+(define_insn "*add<mode>3_cc"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")]
- UNSPEC_ADD_CARRY))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (plus:SI (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, SImode, operands)"
- "add{l}\t{%2, %0|%0, %2}"
+ (unspec:CC
+ [(match_operand:SWI48 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SWI48 2 "<general_operand>" "r<i>,rm")]
+ UNSPEC_ADD_CARRY))
+ (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
+ (plus:SWI48 (match_dup 1) (match_dup 2)))]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "addqi3_cc"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qi,qm")]
- UNSPEC_ADD_CARRY))
+ (unspec:CC
+ [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:QI 2 "general_operand" "qn,qm")]
+ UNSPEC_ADD_CARRY))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
(plus:QI (match_dup 1) (match_dup 2)))]
"ix86_binary_operator_ok (PLUS, QImode, operands)"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-(define_expand "addsi3"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- ""
- "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
+(define_insn "*add<mode>3_cconly_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (plus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "%0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>m"))
+ (match_dup 1)))
+ (clobber (match_scratch:SWI 0 "=<r>"))]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "add{<imodesuffix>}\t{%2, %0|%0, %2}"
+ [(set_attr "type" "alu")
+ (set_attr "mode" "<MODE>")])
(define_insn "*lea_1"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "no_seg_address_operand" "p"))]
- "!TARGET_64BIT"
- "lea{l}\t{%a1, %0|%0, %a1}"
+ [(set (match_operand:DWIH 0 "register_operand" "=r")
+ (match_operand:DWIH 1 "no_seg_address_operand" "p"))]
+ ""
+ "lea{<imodesuffix>}\t{%a1, %0|%0, %a1}"
[(set_attr "type" "lea")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*lea_1_rex64"
+(define_insn "*lea_2"
[(set (match_operand:SI 0 "register_operand" "=r")
(subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
"TARGET_64BIT"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
-(define_insn "*lea_1_zext"
+(define_insn "*lea_2_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
- (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
+ (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
"TARGET_64BIT"
"lea{l}\t{%a1, %k0|%k0, %a1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
-(define_insn "*lea_2_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (match_operand:DI 1 "no_seg_address_operand" "p"))]
- "TARGET_64BIT"
- "lea{q}\t{%a1, %0|%0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "DI")])
+(define_insn "*add<mode>_1"
+ [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
+ (plus:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r")
+ (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>,0,l<i>")))
+ (clobber (reg:CC FLAGS_REG))]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+{
+ switch (get_attr_type (insn))
+ {
+ case TYPE_LEA:
+ operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
+ return "lea{<imodesuffix>}\t{%a2, %0|%0, %a2}";
-;; The lea patterns for non-Pmodes needs to be matched by several
-;; insns converted to real lea by splitters.
+ case TYPE_INCDEC:
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ if (operands[2] == const1_rtx)
+ return "inc{<imodesuffix>}\t%0";
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{<imodesuffix>}\t%0";
+ }
-(define_insn_and_split "*lea_general_1"
- [(set (match_operand 0 "register_operand" "=r")
- (plus (plus (match_operand 1 "index_register_operand" "l")
- (match_operand 2 "register_operand" "r"))
- (match_operand 3 "immediate_operand" "i")))]
- "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
- || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE (operands[0]) == GET_MODE (operands[2])
- && (GET_MODE (operands[0]) == GET_MODE (operands[3])
- || GET_MODE (operands[3]) == VOIDmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx pat;
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
- operands[3]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
+ default:
+ /* Use add as much as possible to replace lea for AGU optimization. */
+ if (which_alternative == 2 && TARGET_OPT_AGU)
+ return "add{<imodesuffix>}\t{%1, %0|%0, %1}";
+
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
-(define_insn_and_split "*lea_general_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
- (match_operand:SI 2 "register_operand" "r"))
- (match_operand:SI 3 "immediate_operand" "i"))))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
- (match_dup 2))
- (match_dup 3)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
+ Exceptions: -128 encodes smaller than 128, so swap sign and op. */
+ if (CONST_INT_P (operands[2])
+ /* Avoid overflows. */
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
+ && (INTVAL (operands[2]) == 128
+ || (INTVAL (operands[2]) < 0
+ && INTVAL (operands[2]) != -128)))
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
+ }
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
+ }
}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
+ [(set (attr "type")
+ (cond [(and (eq_attr "alternative" "2")
+ (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
+ (const_string "lea")
+ (eq_attr "alternative" "3")
+ (const_string "lea")
+ ; Current assemblers are broken and do not allow @GOTOFF in
+ ; ought but a memory context.
+ (match_operand:SWI48 2 "pic_symbolic_operand" "")
+ (const_string "lea")
+ (match_operand:SWI48 2 "incdec_operand" "")
+ (const_string "incdec")
+ ]
+ (const_string "alu")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "<MODE>")])
-(define_insn_and_split "*lea_general_2"
- [(set (match_operand 0 "register_operand" "=r")
- (plus (mult (match_operand 1 "index_register_operand" "l")
- (match_operand 2 "const248_operand" "i"))
- (match_operand 3 "nonmemory_operand" "ri")))]
- "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
- || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && (GET_MODE (operands[0]) == GET_MODE (operands[3])
- || GET_MODE (operands[3]) == VOIDmode)"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx pat;
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
- operands[3]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
+;; It may seem that nonimmediate operand is proper one for operand 1.
+;; The addsi_1 pattern allows nonimmediate operand at that place and
+;; we take care in ix86_binary_operator_ok to not allow two memory
+;; operands so proper swapping will be done in reload. This allow
+;; patterns constructed from addsi_1 to match.
-(define_insn_and_split "*lea_general_2_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
+(define_insn "*addsi_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
- (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
- (match_operand:SI 2 "const248_operand" "n"))
- (match_operand:SI 3 "nonmemory_operand" "ri"))))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
- (match_dup 2))
- (match_dup 3)) 0)))]
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
+ (match_operand:SI 2 "general_operand" "g,li"))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea_general_3"
- [(set (match_operand 0 "register_operand" "=r")
- (plus (plus (mult (match_operand 1 "index_register_operand" "l")
- (match_operand 2 "const248_operand" "i"))
- (match_operand 3 "register_operand" "r"))
- (match_operand 4 "immediate_operand" "i")))]
- "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
- || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
- && GET_MODE (operands[0]) == GET_MODE (operands[1])
- && GET_MODE (operands[0]) == GET_MODE (operands[3])"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx pat;
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- operands[4] = gen_lowpart (Pmode, operands[4]);
- pat = gen_rtx_PLUS (Pmode,
- gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
- operands[2]),
- operands[3]),
- operands[4]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*lea_general_3_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (plus:SI (plus:SI (mult:SI
- (match_operand:SI 1 "index_register_operand" "l")
- (match_operand:SI 2 "const248_operand" "n"))
- (match_operand:SI 3 "register_operand" "r"))
- (match_operand:SI 4 "immediate_operand" "i"))))]
- "TARGET_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
- (match_dup 2))
- (match_dup 3))
- (match_dup 4)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[3] = gen_lowpart (Pmode, operands[3]);
- operands[4] = gen_lowpart (Pmode, operands[4]);
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
-(define_insn "*adddi_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_LEA:
- operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{q}\t{%a2, %0|%0, %a2}";
+ switch (get_attr_type (insn))
+ {
+ case TYPE_LEA:
+ operands[2] = XEXP (SET_SRC (XVECEXP (PATTERN (insn), 0, 0)), 0);
+ return "lea{l}\t{%a2, %k0|%k0, %a2}";
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
+ return "inc{l}\t%k0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
+ return "dec{l}\t%k0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
-
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
}
- return "add{q}\t{%2, %0|%0, %2}";
+ return "add{l}\t{%2, %k0|%k0, %2}";
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "2")
+ (cond [(eq_attr "alternative" "1")
(const_string "lea")
; Current assemblers are broken and do not allow @GOTOFF in
; ought but a memory context.
- (match_operand:DI 2 "pic_symbolic_operand" "")
+ (match_operand:SI 2 "pic_symbolic_operand" "")
(const_string "lea")
- (match_operand:DI 2 "incdec_operand" "")
+ (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
]
(const_string "alu")))
- (set_attr "mode" "DI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "SI")])
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
+(define_insn "*addhi_1"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:HI 2 "general_operand" "rn,rm")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
- [(set (match_dup 0)
- (plus:DI (match_dup 1)
- (match_dup 2)))]
- "")
-
-(define_insn "*adddi_2_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
- (plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, DImode, operands)
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+ "TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, HImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
+ return "inc{w}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
+ return "dec{w}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* ???? We ought to handle there the 32bit case too
- - do we need new constraint? */
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
- }
- return "add{q}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{w}\t{%2, %0|%0, %2}";
+ }
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "DI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "HI")])
-(define_insn "*adddi_3_rex64"
- [(set (reg FLAGS_REG)
- (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
- (match_operand:DI 1 "x86_64_general_operand" "%0")))
- (clobber (match_scratch:DI 0 "=r"))]
- "TARGET_64BIT
- && ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
+;; type optimizations enabled by define-splits. This is not important
+;; for PII, and in fact harmful because of partial register stalls.
+
+(define_insn "*addhi_1_lea"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
+ (match_operand:HI 2 "general_operand" "rn,rm,ln")))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, HImode, operands)"
{
switch (get_attr_type (insn))
{
+ case TYPE_LEA:
+ return "#";
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
+ return "inc{w}\t%0";
else
- {
+ {
gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
+ return "dec{w}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* ???? We ought to handle there the 32bit case too
- - do we need new constraint? */
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
- }
- return "add{q}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{w}\t{%2, %0|%0, %2}";
+ }
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "DI")])
+ (if_then_else (eq_attr "alternative" "2")
+ (const_string "lea")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu"))))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "HI,HI,SI")])
-; For comparisons against 1, -1 and 128, we may generate better code
-; by converting cmp to add, inc or dec as done by peephole2. This pattern
-; is matched then. We can't accept general immediate, because for
-; case of overflows, the result is messed up.
-; This pattern also don't hold of 0x8000000000000000, since the value overflows
-; when negated.
-; Also carry flag is reversed compared to cmp, so this conversion is valid
-; only for comparisons not depending on it.
-(define_insn "*adddi_4_rex64"
- [(set (reg FLAGS_REG)
- (compare (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:DI 2 "x86_64_immediate_operand" "e")))
- (clobber (match_scratch:DI 0 "=rm"))]
- "TARGET_64BIT
- && ix86_match_ccmode (insn, CCGCmode)"
+(define_insn "*addqi_1"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, QImode, operands)"
{
+ int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == constm1_rtx)
- return "inc{q}\t%0";
+ if (operands[2] == const1_rtx)
+ return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
else
- {
- gcc_assert (operands[2] == const1_rtx);
- return "dec{q}\t%0";
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if ((INTVAL (operands[2]) == -128
- || (INTVAL (operands[2]) > 0
- && INTVAL (operands[2]) != 128))
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
- return "sub{q}\t{%2, %0|%0, %2}";
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "add{q}\t{%2, %0|%0, %2}";
+ if (CONST_INT_P (operands[2])
+ && (INTVAL (operands[2]) == 128
+ || (INTVAL (operands[2]) < 0
+ && INTVAL (operands[2]) != -128)))
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ if (widen)
+ return "sub{l}\t{%2, %k0|%k0, %2}";
+ else
+ return "sub{b}\t{%2, %0|%0, %2}";
+ }
+ if (widen)
+ return "add{l}\t{%k2, %k0|%k0, %k2}";
+ else
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "DI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "QI,QI,SI")])
-(define_insn "*adddi_5_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
- (match_operand:DI 2 "x86_64_general_operand" "rme"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=r"))]
- "TARGET_64BIT
- && ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+;; %%% Potential partial reg stall on alternative 2. What to do?
+(define_insn "*addqi_1_lea"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL
+ && ix86_binary_operator_ok (PLUS, QImode, operands)"
{
+ int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
+ case TYPE_LEA:
+ return "#";
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{q}\t%0";
+ return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{q}\t%0";
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
- /* Avoid overflows. */
- && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{q}\t{%2, %0|%0, %2}";
- }
- return "add{q}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "DI")])
-
-
-(define_insn "*addsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:SI 2 "general_operand" "rmni,rni,lni")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, SImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_LEA:
- operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{l}\t{%a2, %0|%0, %a2}";
-
- case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
- else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ if (widen)
+ return "sub{l}\t{%2, %k0|%k0, %2}";
+ else
+ return "sub{b}\t{%2, %0|%0, %2}";
}
-
- default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
-
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
- }
- return "add{l}\t{%2, %0|%0, %2}";
+ if (widen)
+ return "add{l}\t{%k2, %k0|%k0, %k2}";
+ else
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "2")
- (const_string "lea")
- ; Current assemblers are broken and do not allow @GOTOFF in
- ; ought but a memory context.
- (match_operand:SI 2 "pic_symbolic_operand" "")
- (const_string "lea")
- (match_operand:SI 2 "incdec_operand" "")
- (const_string "incdec")
- ]
- (const_string "alu")))
- (set_attr "mode" "SI")])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (plus (match_operand 1 "register_operand" "")
- (match_operand 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
- [(const_int 0)]
-{
- rtx pat;
- /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
- may confuse gen_lowpart. */
- if (GET_MODE (operands[0]) != Pmode)
- {
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
- }
- operands[0] = gen_lowpart (SImode, operands[0]);
- pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-})
+ (if_then_else (eq_attr "alternative" "3")
+ (const_string "lea")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu"))))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "QI,QI,SI,SI")])
-;; It may seem that nonimmediate operand is proper one for operand 1.
-;; The addsi_1 pattern allows nonimmediate operand at that place and
-;; we take care in ix86_binary_operator_ok to not allow two memory
-;; operands so proper swapping will be done in reload. This allow
-;; patterns constructed from addsi_1 to match.
-(define_insn "addsi_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
- (match_operand:SI 2 "general_operand" "rmni,lni"))))
+(define_insn "*addqi_1_slp"
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
+ (plus:QI (match_dup 0)
+ (match_operand:QI 1 "general_operand" "qn,qnm")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (get_attr_type (insn))
{
- case TYPE_LEA:
- operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{l}\t{%a2, %k0|%k0, %a2}";
-
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{l}\t%k0";
+ if (operands[1] == const1_rtx)
+ return "inc{b}\t%0";
else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%k0";
+ {
+ gcc_assert (operands[1] == constm1_rtx);
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %k0|%k0, %2}";
- }
- return "add{l}\t{%2, %k0|%k0, %2}";
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
+ if (CONST_INT_P (operands[1])
+ && INTVAL (operands[1]) < 0)
+ {
+ operands[1] = GEN_INT (-INTVAL (operands[1]));
+ return "sub{b}\t{%1, %0|%0, %1}";
+ }
+ return "add{b}\t{%1, %0|%0, %1}";
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "1")
- (const_string "lea")
- ; Current assemblers are broken and do not allow @GOTOFF in
- ; ought but a memory context.
- (match_operand:SI 2 "pic_symbolic_operand" "")
- (const_string "lea")
- (match_operand:SI 2 "incdec_operand" "")
- (const_string "incdec")
- ]
- (const_string "alu")))
- (set_attr "mode" "SI")])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" ""))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_lowpart (Pmode, operands[2]);
-})
+ (if_then_else (match_operand:QI 1 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu1")))
+ (set (attr "memory")
+ (if_then_else (match_operand 1 "memory_operand" "")
+ (const_string "load")
+ (const_string "none")))
+ (set_attr "mode" "QI")])
-(define_insn "*addsi_2"
+(define_insn "*add<mode>_2"
[(set (reg FLAGS_REG)
(compare
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "rmni,rni"))
+ (plus:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>"))
(const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
- (plus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm")
+ (plus:SWI48 (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, SImode, operands)
+ && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
case TYPE_INCDEC:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
+ return "inc{<imodesuffix>}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ return "dec{<imodesuffix>}\t%0";
}
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* ???? In DImode, we ought to handle there the 32bit case too
+ - do we need new constraint? */
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
+ /* Avoid overflows. */
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
}
- return "add{l}\t{%2, %0|%0, %2}";
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "SI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "<MODE>")])
;; See comment for addsi_1_zext why we do use nonimmediate_operand
(define_insn "*addsi_2_zext"
[(set (reg FLAGS_REG)
(compare
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "rmni"))
+ (match_operand:SI 2 "general_operand" "g"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "SI")])
-(define_insn "*addsi_3"
+(define_insn "*addhi_2"
[(set (reg FLAGS_REG)
- (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
- (match_operand:SI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:SI 0 "=r"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+ (compare
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:HI 2 "general_operand" "rmn,rn"))
+ (const_int 0)))
+ (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
+ (plus:HI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (PLUS, HImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
+ return "inc{w}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ return "dec{w}\t%0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
- }
- return "add{l}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{w}\t{%2, %0|%0, %2}";
+ }
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "SI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "HI")])
-;; See comment for addsi_1_zext why we do use nonimmediate_operand
-(define_insn "*addsi_3_zext"
+(define_insn "*addqi_2"
[(set (reg FLAGS_REG)
- (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
- (match_operand:SI 1 "nonimmediate_operand" "%0")))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
- && ix86_binary_operator_ok (PLUS, SImode, operands)
- /* Current assemblers are broken and do not allow @GOTOFF in
- ought but a memory context. */
- && ! pic_symbolic_operand (operands[2], VOIDmode)"
+ (compare
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:QI 2 "general_operand" "qmn,qn"))
+ (const_int 0)))
+ (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
+ (plus:QI (match_dup 1) (match_dup 2)))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && ix86_binary_operator_ok (PLUS, QImode, operands)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return "inc{l}\t%k0";
+ return "inc{b}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%k0";
+ gcc_assert (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %k0|%k0, %2}";
- }
- return "add{l}\t{%2, %k0|%k0, %2}";
+ && INTVAL (operands[2]) < 0)
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{b}\t{%2, %0|%0, %2}";
+ }
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "QI")])
-; For comparisons against 1, -1 and 128, we may generate better code
-; by converting cmp to add, inc or dec as done by peephole2. This pattern
-; is matched then. We can't accept general immediate, because for
-; case of overflows, the result is messed up.
-; This pattern also don't hold of 0x80000000, since the value overflows
-; when negated.
-; Also carry flag is reversed compared to cmp, so this conversion is valid
-; only for comparisons not depending on it.
-(define_insn "*addsi_4"
+(define_insn "*add<mode>_3"
[(set (reg FLAGS_REG)
- (compare (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_scratch:SI 0 "=rm"))]
- "ix86_match_ccmode (insn, CCGCmode)
- && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
+ (compare
+ (neg:SWI48 (match_operand:SWI48 2 "<general_operand>" "<g>"))
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0")))
+ (clobber (match_scratch:SWI48 0 "=r"))]
+ "ix86_match_ccmode (insn, CCZmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ /* Current assemblers are broken and do not allow @GOTOFF in
+ ought but a memory context. */
+ && ! pic_symbolic_operand (operands[2], VOIDmode)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == constm1_rtx)
- return "inc{l}\t%0";
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ if (operands[2] == const1_rtx)
+ return "inc{<imodesuffix>}\t%0";
else
{
- gcc_assert (operands[2] == const1_rtx);
- return "dec{l}\t%0";
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{<imodesuffix>}\t%0";
}
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* ???? In DImode, we ought to handle there the 32bit case too
+ - do we need new constraint? */
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if ((INTVAL (operands[2]) == -128
- || (INTVAL (operands[2]) > 0
- && INTVAL (operands[2]) != 128)))
- return "sub{l}\t{%2, %0|%0, %2}";
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "add{l}\t{%2, %0|%0, %2}";
+ if (CONST_INT_P (operands[2])
+ /* Avoid overflows. */
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
+ && (INTVAL (operands[2]) == 128
+ || (INTVAL (operands[2]) < 0
+ && INTVAL (operands[2]) != -128)))
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
+ }
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "SI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "<MODE>")])
-(define_insn "*addsi_5"
+;; See comment for addsi_1_zext why we do use nonimmediate_operand
+(define_insn "*addsi_3_zext"
[(set (reg FLAGS_REG)
(compare
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "general_operand" "rmni"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ (neg:SI (match_operand:SI 2 "general_operand" "g"))
+ (match_operand:SI 1 "nonimmediate_operand" "%0")))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
+ && ix86_binary_operator_ok (PLUS, SImode, operands)
/* Current assemblers are broken and do not allow @GOTOFF in
ought but a memory context. */
&& ! pic_symbolic_operand (operands[2], VOIDmode)"
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return "inc{l}\t%0";
+ return "inc{l}\t%k0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return "dec{l}\t%0";
+ return "dec{l}\t%k0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{l}\t{%2, %0|%0, %2}";
+ return "sub{l}\t{%2, %k0|%k0, %2}";
}
- return "add{l}\t{%2, %0|%0, %2}";
+ return "add{l}\t{%2, %k0|%k0, %2}";
}
}
[(set (attr "type")
(if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "SI")])
-(define_expand "addhi3"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_HIMODE_MATH"
- "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
-
-;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
-;; type optimizations enabled by define-splits. This is not important
-;; for PII, and in fact harmful because of partial register stalls.
-
-(define_insn "*addhi_1_lea"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:HI 2 "general_operand" "ri,rm,lni")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, HImode, operands)"
+(define_insn "*addhi_3"
+ [(set (reg FLAGS_REG)
+ (compare
+ (neg:HI (match_operand:HI 2 "general_operand" "rmn"))
+ (match_operand:HI 1 "nonimmediate_operand" "%0")))
+ (clobber (match_scratch:HI 0 "=r"))]
+ "ix86_match_ccmode (insn, CCZmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
switch (get_attr_type (insn))
{
- case TYPE_LEA:
- return "#";
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{w}\t%0";
else
- {
+ {
gcc_assert (operands[2] == constm1_rtx);
return "dec{w}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
}
}
[(set (attr "type")
- (if_then_else (eq_attr "alternative" "2")
- (const_string "lea")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu"))))
- (set_attr "mode" "HI,HI,SI")])
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "HI")])
-(define_insn "*addhi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, HImode, operands)"
+(define_insn "*addqi_3"
+ [(set (reg FLAGS_REG)
+ (compare
+ (neg:QI (match_operand:QI 2 "general_operand" "qmn"))
+ (match_operand:QI 1 "nonimmediate_operand" "%0")))
+ (clobber (match_scratch:QI 0 "=q"))]
+ "ix86_match_ccmode (insn, CCZmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ return "inc{b}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
+ && INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
+ return "sub{b}\t{%2, %0|%0, %2}";
}
- return "add{w}\t{%2, %0|%0, %2}";
+ return "add{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "HI")])
+ (set_attr "mode" "QI")])
-(define_insn "*addhi_2"
+; For comparisons against 1, -1 and 128, we may generate better code
+; by converting cmp to add, inc or dec as done by peephole2. This pattern
+; is matched then. We can't accept general immediate, because for
+; case of overflows, the result is messed up.
+; This pattern also don't hold of 0x8000000000000000, since the value
+; overflows when negated.
+; Also carry flag is reversed compared to cmp, so this conversion is valid
+; only for comparisons not depending on it.
+
+(define_insn "*adddi_4"
[(set (reg FLAGS_REG)
(compare
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "rmni,rni"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
- (plus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, HImode, operands)"
+ (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:DI 2 "x86_64_immediate_operand" "e")))
+ (clobber (match_scratch:DI 0 "=rm"))]
+ "TARGET_64BIT
+ && ix86_match_ccmode (insn, CCGCmode)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ if (operands[2] == constm1_rtx)
+ return "inc{q}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{q}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
- }
- return "add{w}\t{%2, %0|%0, %2}";
+ if ((INTVAL (operands[2]) == -128
+ || (INTVAL (operands[2]) > 0
+ && INTVAL (operands[2]) != 128))
+ /* Avoid overflows. */
+ && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
+ return "sub{q}\t{%2, %0|%0, %2}";
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "add{q}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (if_then_else (match_operand:DI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "HI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "DI")])
-(define_insn "*addhi_3"
+; For comparisons against 1, -1 and 128, we may generate better code
+; by converting cmp to add, inc or dec as done by peephole2. This pattern
+; is matched then. We can't accept general immediate, because for
+; case of overflows, the result is messed up.
+; This pattern also don't hold of 0x80000000, since the value overflows
+; when negated.
+; Also carry flag is reversed compared to cmp, so this conversion is valid
+; only for comparisons not depending on it.
+
+(define_insn "*addsi_4"
[(set (reg FLAGS_REG)
- (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
- (match_operand:HI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:HI 0 "=r"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ (compare
+ (match_operand:SI 1 "nonimmediate_operand" "0")
+ (match_operand:SI 2 "const_int_operand" "n")))
+ (clobber (match_scratch:SI 0 "=rm"))]
+ "ix86_match_ccmode (insn, CCGCmode)
+ && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ if (operands[2] == constm1_rtx)
+ return "inc{l}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{l}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
- }
- return "add{w}\t{%2, %0|%0, %2}";
+ if ((INTVAL (operands[2]) == -128
+ || (INTVAL (operands[2]) > 0
+ && INTVAL (operands[2]) != 128)))
+ return "sub{l}\t{%2, %0|%0, %2}";
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "add{l}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "HI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "SI")])
; See comments above addsi_4 for details.
+
(define_insn "*addhi_4"
[(set (reg FLAGS_REG)
- (compare (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "const_int_operand" "n")))
+ (compare
+ (match_operand:HI 1 "nonimmediate_operand" "0")
+ (match_operand:HI 2 "const_int_operand" "n")))
(clobber (match_scratch:HI 0 "=rm"))]
"ix86_match_ccmode (insn, CCGCmode)
&& (INTVAL (operands[2]) & 0xffff) != 0x8000"
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if ((INTVAL (operands[2]) == -128
|| (INTVAL (operands[2]) > 0
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "SI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "HI")])
+; See comments above addsi_4 for details.
-(define_insn "*addhi_5"
+(define_insn "*addqi_4"
[(set (reg FLAGS_REG)
(compare
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
- (match_operand:HI 2 "general_operand" "rmni"))
- (const_int 0)))
- (clobber (match_scratch:HI 0 "=r"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ (match_operand:QI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "const_int_operand" "n")))
+ (clobber (match_scratch:QI 0 "=qm"))]
+ "ix86_match_ccmode (insn, CCGCmode)
+ && (INTVAL (operands[2]) & 0xff) != 0x80"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
+ if (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255))
+ return "inc{b}\t%0";
else
{
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
- Exceptions: -128 encodes smaller than 128, so swap sign and op. */
- if (CONST_INT_P (operands[2])
- && (INTVAL (operands[2]) == 128
- || (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{w}\t{%2, %0|%0, %2}";
- }
- return "add{w}\t{%2, %0|%0, %2}";
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ if (INTVAL (operands[2]) < 0)
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "add{b}\t{%2, %0|%0, %2}";
+ }
+ return "sub{b}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
(if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "HI")])
-
-(define_expand "addqi3"
- [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
+ (set_attr "mode" "QI")])
-;; %%% Potential partial reg stall on alternative 2. What to do?
-(define_insn "*addqi_1_lea"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
- (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, QImode, operands)"
+(define_insn "*add<mode>_5"
+ [(set (reg FLAGS_REG)
+ (compare
+ (plus:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0")
+ (match_operand:SWI48 2 "<general_operand>" "<g>"))
+ (const_int 0)))
+ (clobber (match_scratch:SWI48 0 "=r"))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ /* Current assemblers are broken and do not allow @GOTOFF in
+ ought but a memory context. */
+ && ! pic_symbolic_operand (operands[2], VOIDmode)"
{
- int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
- case TYPE_LEA:
- return "#";
case TYPE_INCDEC:
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
- return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
+ return "inc{<imodesuffix>}\t%0";
else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{<imodesuffix>}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
+ /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
+ /* Avoid overflows. */
+ && (<MODE>mode != DImode
+ || ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
&& (INTVAL (operands[2]) == 128
|| (INTVAL (operands[2]) < 0
&& INTVAL (operands[2]) != -128)))
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- if (widen)
- return "sub{l}\t{%2, %k0|%k0, %2}";
- else
- return "sub{b}\t{%2, %0|%0, %2}";
- }
- if (widen)
- return "add{l}\t{%k2, %k0|%k0, %k2}";
- else
- return "add{b}\t{%2, %0|%0, %2}";
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
+ }
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (eq_attr "alternative" "3")
- (const_string "lea")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu"))))
- (set_attr "mode" "QI,QI,SI,SI")])
+ (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
+ (const_string "incdec")
+ (const_string "alu")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "<MODE>")])
-(define_insn "*addqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (PLUS, QImode, operands)"
+(define_insn "*addhi_5"
+ [(set (reg FLAGS_REG)
+ (compare
+ (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
+ (match_operand:HI 2 "general_operand" "rmn"))
+ (const_int 0)))
+ (clobber (match_scratch:HI 0 "=r"))]
+ "ix86_match_ccmode (insn, CCGOCmode)
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
- int widen = (which_alternative == 2);
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
+ return "inc{w}\t%0";
else
{
gcc_assert (operands[2] == constm1_rtx);
- return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
+ return "dec{w}\t%0";
}
default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+ /* Make things pretty and `subw $4,%ax' rather than `addw $-4,%ax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 128
&& INTVAL (operands[2]) != -128)))
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
- if (widen)
- return "sub{l}\t{%2, %k0|%k0, %2}";
- else
- return "sub{b}\t{%2, %0|%0, %2}";
+ return "sub{w}\t{%2, %0|%0, %2}";
}
- if (widen)
- return "add{l}\t{%k2, %k0|%k0, %k2}";
- else
- return "add{b}\t{%2, %0|%0, %2}";
+ return "add{w}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:HI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
- (set_attr "mode" "QI,QI,SI")])
-
-(define_insn "*addqi_1_slp"
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
- (plus:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qn,qnm")))
- (clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[1] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[1] == constm1_rtx);
- return "dec{b}\t%0";
- }
-
- default:
- /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
- if (CONST_INT_P (operands[1])
- && INTVAL (operands[1]) < 0)
- {
- operands[1] = GEN_INT (-INTVAL (operands[1]));
- return "sub{b}\t{%1, %0|%0, %1}";
- }
- return "add{b}\t{%1, %0|%0, %1}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 1 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu1")))
- (set (attr "memory")
- (if_then_else (match_operand 1 "memory_operand" "")
- (const_string "load")
- (const_string "none")))
- (set_attr "mode" "QI")])
+ (set (attr "length_immediate")
+ (if_then_else
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "HI")])
-(define_insn "*addqi_2"
+(define_insn "*addqi_5"
[(set (reg FLAGS_REG)
(compare
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qmni,qni"))
+ (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
+ (match_operand:QI 2 "general_operand" "qmn"))
(const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
- (plus:QI (match_dup 1) (match_dup 2)))]
+ (clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, QImode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
switch (get_attr_type (insn))
{
{
gcc_assert (operands[2] == constm1_rtx
|| (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
+ && INTVAL (operands[2]) == 255));
return "dec{b}\t%0";
}
default:
- /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
+ /* Make things pretty and `subb $4,%al' rather than `addb $-4,%al'. */
if (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) < 0)
{
(const_string "alu")))
(set_attr "mode" "QI")])
-(define_insn "*addqi_3"
- [(set (reg FLAGS_REG)
- (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
- (match_operand:QI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:QI 0 "=q"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+(define_insn "*addqi_ext_1_rex64"
+ [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
+ (const_int 8)
+ (const_int 8))
+ (plus:SI
+ (zero_extract:SI
+ (match_operand 1 "ext_register_operand" "0")
+ (const_int 8)
+ (const_int 8))
+ (match_operand:QI 2 "nonmemory_operand" "Qn")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
+ return "inc{b}\t%h0";
else
{
gcc_assert (operands[2] == constm1_rtx
|| (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
+ return "dec{b}\t%h0";
+ }
default:
- /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
- if (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) < 0)
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{b}\t{%2, %0|%0, %2}";
- }
- return "add{b}\t{%2, %0|%0, %2}";
+ return "add{b}\t{%2, %h0|%h0, %2}";
}
}
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
-; See comments above addsi_4 for details.
-(define_insn "*addqi_4"
- [(set (reg FLAGS_REG)
- (compare (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_operand" "n")))
- (clobber (match_scratch:QI 0 "=qm"))]
- "ix86_match_ccmode (insn, CCGCmode)
- && (INTVAL (operands[2]) & 0xff) != 0x80"
+(define_insn "addqi_ext_1"
+ [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
+ (const_int 8)
+ (const_int 8))
+ (plus:SI
+ (zero_extract:SI
+ (match_operand 1 "ext_register_operand" "0")
+ (const_int 8)
+ (const_int 8))
+ (match_operand:QI 2 "general_operand" "Qmn")))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255))
- return "inc{b}\t%0";
+ if (operands[2] == const1_rtx)
+ return "inc{b}\t%h0";
else
- {
- gcc_assert (operands[2] == const1_rtx);
- return "dec{b}\t%0";
+ {
+ gcc_assert (operands[2] == constm1_rtx
+ || (CONST_INT_P (operands[2])
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%h0";
}
default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- if (INTVAL (operands[2]) < 0)
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "add{b}\t{%2, %0|%0, %2}";
- }
- return "sub{b}\t{%2, %0|%0, %2}";
+ return "add{b}\t{%2, %h0|%h0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
-
-(define_insn "*addqi_5"
- [(set (reg FLAGS_REG)
- (compare
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "general_operand" "qmni"))
- (const_int 0)))
- (clobber (match_scratch:QI 0 "=q"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
-
- default:
- /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
- if (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) < 0)
- {
- operands[2] = GEN_INT (-INTVAL (operands[2]));
- return "sub{b}\t{%2, %0|%0, %2}";
- }
- return "add{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
-
-(define_insn "addqi_ext_1"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
- (const_int 8)
- (const_int 8))
- (plus:SI
- (zero_extract:SI
- (match_operand 1 "ext_register_operand" "0")
- (const_int 8)
- (const_int 8))
- (match_operand:QI 2 "general_operand" "Qmn")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%h0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%h0";
- }
-
- default:
- return "add{b}\t{%2, %h0|%h0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
-(define_insn "*addqi_ext_1_rex64"
- [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
- (const_int 8)
- (const_int 8))
- (plus:SI
- (zero_extract:SI
- (match_operand 1 "ext_register_operand" "0")
- (const_int 8)
- (const_int 8))
- (match_operand:QI 2 "nonmemory_operand" "Qn")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%h0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%h0";
- }
-
- default:
- return "add{b}\t{%2, %h0|%h0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_2"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-;; The patterns that match these are at the end of this file.
-
-(define_expand "addxf3"
- [(set (match_operand:XF 0 "register_operand" "")
- (plus:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
- "TARGET_80387"
- "")
-
-(define_expand "add<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "")
- (plus:MODEF (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
- "")
-\f
-;; Subtract instructions
+;; The lea patterns for non-Pmodes needs to be matched by
+;; several insns converted to real lea by splitters.
-;; %%% splits for subditi3
+(define_insn_and_split "*lea_general_1"
+ [(set (match_operand 0 "register_operand" "=r")
+ (plus (plus (match_operand 1 "index_register_operand" "l")
+ (match_operand 2 "register_operand" "r"))
+ (match_operand 3 "immediate_operand" "i")))]
+ "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
+ || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE (operands[0]) == GET_MODE (operands[2])
+ && (GET_MODE (operands[0]) == GET_MODE (operands[3])
+ || GET_MODE (operands[3]) == VOIDmode)"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx pat;
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
+ operands[3]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_expand "subti3"
- [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+(define_insn_and_split "*lea_general_1_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (plus:SI (plus:SI
+ (match_operand:SI 1 "index_register_operand" "l")
+ (match_operand:SI 2 "register_operand" "r"))
+ (match_operand:SI 3 "immediate_operand" "i"))))]
"TARGET_64BIT"
- "ix86_expand_binary_operator (MINUS, TImode, operands); DONE;")
-
-(define_insn "*subti3_1"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
- (minus:TI (match_operand:TI 1 "nonimmediate_operand" "0,0")
- (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (MINUS, TImode, operands)"
- "#")
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_split
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
- (match_operand:TI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))])
- (parallel [(set (match_dup 3)
- (minus:DI (match_dup 4)
- (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 5))))
- (clobber (reg:CC FLAGS_REG))])]
- "split_ti (&operands[0], 3, &operands[0], &operands[3]);")
+(define_insn_and_split "*lea_general_2"
+ [(set (match_operand 0 "register_operand" "=r")
+ (plus (mult (match_operand 1 "index_register_operand" "l")
+ (match_operand 2 "const248_operand" "i"))
+ (match_operand 3 "nonmemory_operand" "ri")))]
+ "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
+ || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && (GET_MODE (operands[0]) == GET_MODE (operands[3])
+ || GET_MODE (operands[3]) == VOIDmode)"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx pat;
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
+ operands[3]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-;; %%% splits for subsidi3
+(define_insn_and_split "*lea_general_2_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (plus:SI (mult:SI
+ (match_operand:SI 1 "index_register_operand" "l")
+ (match_operand:SI 2 "const248_operand" "n"))
+ (match_operand:SI 3 "nonmemory_operand" "ri"))))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_expand "subdi3"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- ""
- "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
+(define_insn_and_split "*lea_general_3"
+ [(set (match_operand 0 "register_operand" "=r")
+ (plus (plus (mult (match_operand 1 "index_register_operand" "l")
+ (match_operand 2 "const248_operand" "i"))
+ (match_operand 3 "register_operand" "r"))
+ (match_operand 4 "immediate_operand" "i")))]
+ "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
+ || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && GET_MODE (operands[0]) == GET_MODE (operands[1])
+ && GET_MODE (operands[0]) == GET_MODE (operands[3])"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx pat;
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ operands[4] = gen_lowpart (Pmode, operands[4]);
+ pat = gen_rtx_PLUS (Pmode,
+ gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
+ operands[2]),
+ operands[3]),
+ operands[4]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
-(define_insn "*subdi3_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "general_operand" "roiF,riF")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "#")
+(define_insn_and_split "*lea_general_3_zext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (plus:SI (plus:SI
+ (mult:SI
+ (match_operand:SI 1 "index_register_operand" "l")
+ (match_operand:SI 2 "const248_operand" "n"))
+ (match_operand:SI 3 "register_operand" "r"))
+ (match_operand:SI 4 "immediate_operand" "i"))))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3))
+ (match_dup 4)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[3] = gen_lowpart (Pmode, operands[3]);
+ operands[4] = gen_lowpart (Pmode, operands[4]);
+}
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")])
+;; Convert lea to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && reload_completed"
- [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
- (parallel [(set (match_dup 3)
- (minus:SI (match_dup 4)
- (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
- (match_dup 5))))
- (clobber (reg:CC FLAGS_REG))])]
- "split_di (&operands[0], 3, &operands[0], &operands[3]);")
-
-(define_insn "subdi3_carry_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
+ [(set (match_operand:DI 0 "register_operand" "")
+ (plus:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sbb{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "DI")])
+ "TARGET_64BIT && reload_completed
+ && ix86_lea_for_add_ok (PLUS, insn, operands)"
+ [(set (match_dup 0)
+ (plus:DI (match_dup 1)
+ (match_dup 2)))]
+ "")
-(define_insn "*subdi_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
+;; Convert lea to the lea pattern to avoid flags dependency.
+(define_split
+ [(set (match_operand 0 "register_operand" "")
+ (plus (match_operand 1 "register_operand" "")
+ (match_operand 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sub{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
-
-(define_insn "*subdi_2_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, DImode, operands)"
- "sub{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
-
-(define_insn "*subdi_3_rex63"
- [(set (reg FLAGS_REG)
- (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (minus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "DI")])
+ "reload_completed && ix86_lea_for_add_ok (PLUS, insn, operands)"
+ [(const_int 0)]
+{
+ rtx pat;
+ /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
+ may confuse gen_lowpart. */
+ if (GET_MODE (operands[0]) != Pmode)
+ {
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+ }
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
+ if (Pmode != SImode)
+ pat = gen_rtx_SUBREG (SImode, pat, 0);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
+ DONE;
+})
-(define_insn "subqi3_carry"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
- (match_operand:QI 2 "general_operand" "qi,qm"))))
+;; Convert lea to the lea pattern to avoid flags dependency.
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (zero_extend:DI
+ (plus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" ""))))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sbb{b}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "QI")])
+ "TARGET_64BIT && reload_completed
+ && true_regnum (operands[0]) != true_regnum (operands[1])"
+ [(set (match_dup 0)
+ (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
+{
+ operands[1] = gen_lowpart (Pmode, operands[1]);
+ operands[2] = gen_lowpart (Pmode, operands[2]);
+})
+\f
+;; Subtract instructions
-(define_insn "subhi3_carry"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
- (match_operand:HI 2 "general_operand" "ri,rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sbb{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "mode" "HI")])
+(define_expand "sub<mode>3"
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
+ (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
+ (match_operand:SDWIM 2 "<general_operand>" "")))]
+ ""
+ "ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;")
-(define_insn "subsi3_carry"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
- (match_operand:SI 2 "general_operand" "ri,rm"))))
+(define_insn_and_split "*sub<dwi>3_doubleword"
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
+ (minus:<DWI>
+ (match_operand:<DWI> 1 "nonimmediate_operand" "0,0")
+ (match_operand:<DWI> 2 "<general_operand>" "ro<di>,r<di>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sbb{l}\t{%2, %0|%0, %2}"
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "#"
+ "reload_completed"
+ [(parallel [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (set (match_dup 0)
+ (minus:DWIH (match_dup 1) (match_dup 2)))])
+ (parallel [(set (match_dup 3)
+ (minus:DWIH
+ (match_dup 4)
+ (plus:DWIH
+ (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))
+ (match_dup 5))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
+
+(define_insn "sub<mode>3_carry"
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (plus:SWI
+ (match_operand:SWI 3 "ix86_carry_flag_operator" "")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))))
+ (clobber (reg:CC FLAGS_REG))]
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sbb{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "subsi3_carry_zext"
+(define_insn "*subsi3_carry_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 1 "register_operand" "0")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
-(define_expand "subsi3"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+(define_insn "*sub<mode>3_cconly_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (minus:SWI
+ (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
+ (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
+ (match_dup 0)))]
""
- "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
+ "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "icmp")
+ (set_attr "mode" "<MODE>")])
-(define_insn "*subsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")))
+(define_insn "*sub<mode>_1"
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %0|%0, %2}"
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*subsi_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*subsi_2"
+(define_insn "*subqi_1_slp"
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
+ (minus:QI (match_dup 0)
+ (match_operand:QI 1 "general_operand" "qn,qm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "sub{b}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")
+ (set_attr "mode" "QI")])
+
+(define_insn "*sub<mode>_2"
[(set (reg FLAGS_REG)
(compare
- (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm"))
+ (minus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
(const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_dup 1) (match_dup 2)))]
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*subsi_2_zext"
[(set (reg FLAGS_REG)
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*subsi_3"
+(define_insn "*sub<mode>_3"
[(set (reg FLAGS_REG)
- (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:SI 2 "general_operand" "ri,rm")))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (minus:SI (match_dup 1) (match_dup 2)))]
+ (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (minus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %0|%0, %2}"
+ && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*subsi_3_zext"
[(set (reg FLAGS_REG)
&& ix86_binary_operator_ok (MINUS, SImode, operands)"
"sub{l}\t{%2, %1|%1, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "DI")])
-
-(define_expand "subhi3"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_HIMODE_MATH"
- "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
-
-(define_insn "*subhi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (match_operand:HI 2 "general_operand" "ri,rm")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "HI")])
-
-(define_insn "*subhi_2"
- [(set (reg FLAGS_REG)
- (compare
- (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (match_operand:HI 2 "general_operand" "ri,rm"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "HI")])
-
-(define_insn "*subhi_3"
- [(set (reg FLAGS_REG)
- (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (match_operand:HI 2 "general_operand" "ri,rm")))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (minus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, HImode, operands)"
- "sub{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "HI")])
-
-(define_expand "subqi3"
- [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
-
-(define_insn "*subqi_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "general_operand" "qn,qmn")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "SI")])
-(define_insn "*subqi_1_slp"
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
- (minus:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qn,qmn")))
- (clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "sub{b}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "mode" "QI")])
-(define_insn "*subqi_2"
- [(set (reg FLAGS_REG)
- (compare
- (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "general_operand" "qi,qm"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
- (minus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\t{%2, %0|%0, %2}"
+(define_insn "*<plusminus_insn><mode>3_cc_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (plusminus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
+ (match_dup 1)))
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (plusminus:SWI (match_dup 1) (match_dup 2)))]
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "<plusminus_mnemonic>{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*subqi_3"
- [(set (reg FLAGS_REG)
- (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "general_operand" "qi,qm")))
- (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
- (minus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, QImode, operands)"
- "sub{b}\t{%2, %0|%0, %2}"
+(define_insn "*<plusminus_insn>si3_zext_cc_overflow"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (plusminus:SI
+ (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
+ (match_operand:SI 2 "general_operand" "g"))
+ (match_dup 1)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
+ "<plusminus_mnemonic>{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "alu")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "SI")])
;; The patterns that match these are at the end of this file.
-(define_expand "subxf3"
+(define_expand "<plusminus_insn>xf3"
[(set (match_operand:XF 0 "register_operand" "")
- (minus:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ (plusminus:XF
+ (match_operand:XF 1 "register_operand" "")
+ (match_operand:XF 2 "register_operand" "")))]
"TARGET_80387"
"")
-(define_expand "sub<mode>3"
+(define_expand "<plusminus_insn><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "")
- (minus:MODEF (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ (plusminus:MODEF
+ (match_operand:MODEF 1 "register_operand" "")
+ (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+ "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
\f
;; Multiply instructions
-(define_expand "muldi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))
+(define_expand "mul<mode>3"
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ (mult:SWIM248
+ (match_operand:SWIM248 1 "register_operand" "")
+ (match_operand:SWIM248 2 "<general_operand>" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
+ ""
"")
-;; On AMDFAM10
-;; IMUL reg64, reg64, imm8 Direct
-;; IMUL reg64, mem64, imm8 VectorPath
-;; IMUL reg64, reg64, imm32 Direct
-;; IMUL reg64, mem64, imm32 VectorPath
-;; IMUL reg64, reg64 Direct
-;; IMUL reg64, mem64 Direct
-
-(define_insn "*muldi3_1_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
- (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "@
- imul{q}\t{%2, %1, %0|%0, %1, %2}
- imul{q}\t{%2, %1, %0|%0, %1, %2}
- imul{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "imul")
- (set_attr "prefix_0f" "0,0,1")
- (set (attr "athlon_decode")
- (cond [(eq_attr "cpu" "athlon")
- (const_string "vector")
- (eq_attr "alternative" "1")
- (const_string "vector")
- (and (eq_attr "alternative" "2")
- (match_operand 1 "memory_operand" ""))
- (const_string "vector")]
- (const_string "direct")))
- (set (attr "amdfam10_decode")
- (cond [(and (eq_attr "alternative" "0,1")
- (match_operand 1 "memory_operand" ""))
- (const_string "vector")]
- (const_string "direct")))
- (set_attr "mode" "DI")])
-
-(define_expand "mulsi3"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "general_operand" "")))
+(define_expand "mulqi3"
+ [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ (mult:QI
+ (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "nonimmediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- ""
+ "TARGET_QIMODE_MATH"
"")
;; On AMDFAM10
-;; IMUL reg32, reg32, imm8 Direct
-;; IMUL reg32, mem32, imm8 VectorPath
-;; IMUL reg32, reg32, imm32 Direct
-;; IMUL reg32, mem32, imm32 VectorPath
-;; IMUL reg32, reg32 Direct
-;; IMUL reg32, mem32 Direct
-
-(define_insn "*mulsi3_1"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:SI 2 "general_operand" "K,i,mr")))
+;; IMUL reg32/64, reg32/64, imm8 Direct
+;; IMUL reg32/64, mem32/64, imm8 VectorPath
+;; IMUL reg32/64, reg32/64, imm32 Direct
+;; IMUL reg32/64, mem32/64, imm32 VectorPath
+;; IMUL reg32/64, reg32/64 Direct
+;; IMUL reg32/64, mem32/64 Direct
+
+(define_insn "*mul<mode>3_1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r,r,r")
+ (mult:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "%rm,rm,0")
+ (match_operand:SWI48 2 "<general_operand>" "K,<i>,mr")))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
- imul{l}\t{%2, %1, %0|%0, %1, %2}
- imul{l}\t{%2, %1, %0|%0, %1, %2}
- imul{l}\t{%2, %0|%0, %2}"
+ imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ imul{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
(match_operand 1 "memory_operand" ""))
(const_string "vector")]
(const_string "direct")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*mulsi3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
(const_string "direct")))
(set_attr "mode" "SI")])
-(define_expand "mulhi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
- (mult:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_HIMODE_MATH"
- "")
-
;; On AMDFAM10
;; IMUL reg16, reg16, imm8 VectorPath
;; IMUL reg16, mem16, imm8 VectorPath
;; IMUL reg16, mem16, imm16 VectorPath
;; IMUL reg16, reg16 Direct
;; IMUL reg16, mem16 Direct
+
(define_insn "*mulhi3_1"
[(set (match_operand:HI 0 "register_operand" "=r,r,r")
(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:HI 2 "general_operand" "K,i,mr")))
+ (match_operand:HI 2 "general_operand" "K,n,mr")))
(clobber (reg:CC FLAGS_REG))]
- "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ "TARGET_HIMODE_MATH
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
imul{w}\t{%2, %1, %0|%0, %1, %2}
imul{w}\t{%2, %1, %0|%0, %1, %2}
(const_string "direct")))
(set_attr "mode" "HI")])
-(define_expand "mulqi3"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
- (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "")
-
-;;On AMDFAM10
-;; MUL reg8 Direct
-;; MUL mem8 Direct
-
-(define_insn "*mulqi3_1"
- [(set (match_operand:QI 0 "register_operand" "=a")
- (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{b}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "direct")))
- (set_attr "amdfam10_decode" "direct")
- (set_attr "mode" "QI")])
-
-(define_expand "umulqihi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
- (mult:HI (zero_extend:HI
- (match_operand:QI 1 "nonimmediate_operand" ""))
- (zero_extend:HI
- (match_operand:QI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "")
-
-(define_insn "*umulqihi3_1"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
- (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{b}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "direct")))
- (set_attr "amdfam10_decode" "direct")
- (set_attr "mode" "QI")])
-
-(define_expand "mulqihi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
- (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
- (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_QIMODE_MATH"
- "")
-
-(define_insn "*mulqihi3_insn"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
- (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{b}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "direct")))
- (set_attr "amdfam10_decode" "direct")
- (set_attr "mode" "QI")])
-
-(define_expand "umulditi3"
- [(parallel [(set (match_operand:TI 0 "register_operand" "")
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (zero_extend:TI
- (match_operand:DI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
-
-(define_insn "*umulditi3_insn"
- [(set (match_operand:TI 0 "register_operand" "=A")
- (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
- (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{q}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "DI")])
-
-;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
-(define_expand "umulsidi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (zero_extend:DI
- (match_operand:SI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "!TARGET_64BIT"
- "")
-
-(define_insn "*umulsidi3_insn"
- [(set (match_operand:DI 0 "register_operand" "=A")
- (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
- (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{l}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
-
-(define_expand "mulditi3"
- [(parallel [(set (match_operand:TI 0 "register_operand" "")
- (mult:TI (sign_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (sign_extend:TI
- (match_operand:DI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
-
-(define_insn "*mulditi3_insn"
- [(set (match_operand:TI 0 "register_operand" "=A")
- (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
- (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{q}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "DI")])
-
-(define_expand "mulsidi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (sign_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (sign_extend:DI
- (match_operand:SI 2 "register_operand" ""))))
- (clobber (reg:CC FLAGS_REG))])]
- "!TARGET_64BIT"
- "")
-
-(define_insn "*mulsidi3_insn"
- [(set (match_operand:DI 0 "register_operand" "=A")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
- (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{l}\t%2"
- [(set_attr "type" "imul")
- (set_attr "length_immediate" "0")
- (set (attr "athlon_decode")
- (if_then_else (eq_attr "cpu" "athlon")
- (const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
-
-(define_expand "umuldi3_highpart"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (zero_extend:TI
- (match_operand:DI 2 "register_operand" "")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
+;;On AMDFAM10
+;; MUL reg8 Direct
+;; MUL mem8 Direct
-(define_insn "*umuldi3_highpart_rex64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (zero_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" "%a"))
- (zero_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 "=1"))
+(define_insn "*mulqi3_1"
+ [(set (match_operand:QI 0 "register_operand" "=a")
+ (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
+ (match_operand:QI 2 "nonimmediate_operand" "qm")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
+ "TARGET_QIMODE_MATH
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{q}\t%2"
+ "mul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "DI")])
+ (const_string "direct")))
+ (set_attr "amdfam10_decode" "direct")
+ (set_attr "mode" "QI")])
-(define_expand "umulsi3_highpart"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (zero_extend:DI
- (match_operand:SI 2 "register_operand" "")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 ""))
+(define_expand "<u>mul<mode><dwi>3"
+ [(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ (mult:<DWI>
+ (any_extend:<DWI>
+ (match_operand:DWIH 1 "nonimmediate_operand" ""))
+ (any_extend:<DWI>
+ (match_operand:DWIH 2 "register_operand" ""))))
(clobber (reg:CC FLAGS_REG))])]
""
"")
-(define_insn "*umulsi3_highpart_insn"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "%a"))
- (zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=1"))
+(define_expand "<u>mulqihi3"
+ [(parallel [(set (match_operand:HI 0 "register_operand" "")
+ (mult:HI
+ (any_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" ""))
+ (any_extend:HI
+ (match_operand:QI 2 "register_operand" ""))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_QIMODE_MATH"
+ "")
+
+(define_insn "*<u>mul<mode><dwi>3_1"
+ [(set (match_operand:<DWI> 0 "register_operand" "=A")
+ (mult:<DWI>
+ (any_extend:<DWI>
+ (match_operand:DWIH 1 "nonimmediate_operand" "%0"))
+ (any_extend:<DWI>
+ (match_operand:DWIH 2 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{l}\t%2"
+ "<sgnprefix>mul{<imodesuffix>}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(const_string "vector")
(const_string "double")))
(set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*umulsi3_highpart_zext"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (zero_extend:DI (truncate:SI
- (lshiftrt:DI
- (mult:DI (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "%a"))
- (zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (const_int 32)))))
- (clobber (match_scratch:SI 3 "=1"))
+(define_insn "*<u>mulqihi3_1"
+ [(set (match_operand:HI 0 "register_operand" "=a")
+ (mult:HI
+ (any_extend:HI
+ (match_operand:QI 1 "nonimmediate_operand" "%0"))
+ (any_extend:HI
+ (match_operand:QI 2 "nonimmediate_operand" "qm"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
+ "TARGET_QIMODE_MATH
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{l}\t%2"
+ "<sgnprefix>mul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
- (const_string "double")))
- (set_attr "amdfam10_decode" "double")
- (set_attr "mode" "SI")])
+ (const_string "direct")))
+ (set_attr "amdfam10_decode" "direct")
+ (set_attr "mode" "QI")])
-(define_expand "smuldi3_highpart"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (truncate:DI
- (lshiftrt:TI
- (mult:TI (sign_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" ""))
- (sign_extend:TI
- (match_operand:DI 2 "register_operand" "")))
- (const_int 64))))
- (clobber (match_scratch:DI 3 ""))
+(define_expand "<s>mul<mode>3_highpart"
+ [(parallel [(set (match_operand:SWI48 0 "register_operand" "")
+ (truncate:SWI48
+ (lshiftrt:<DWI>
+ (mult:<DWI>
+ (any_extend:<DWI>
+ (match_operand:SWI48 1 "nonimmediate_operand" ""))
+ (any_extend:<DWI>
+ (match_operand:SWI48 2 "register_operand" "")))
+ (match_dup 4))))
+ (clobber (match_scratch:SWI48 3 ""))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
+ ""
+ "operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
-(define_insn "*smuldi3_highpart_rex64"
+(define_insn "*<s>muldi3_highpart_1"
[(set (match_operand:DI 0 "register_operand" "=d")
(truncate:DI
(lshiftrt:TI
- (mult:TI (sign_extend:TI
- (match_operand:DI 1 "nonimmediate_operand" "%a"))
- (sign_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
+ (mult:TI
+ (any_extend:TI
+ (match_operand:DI 1 "nonimmediate_operand" "%a"))
+ (any_extend:TI
+ (match_operand:DI 2 "nonimmediate_operand" "rm")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=1"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{q}\t%2"
+ "<sgnprefix>mul{q}\t%2"
[(set_attr "type" "imul")
+ (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(set_attr "amdfam10_decode" "double")
(set_attr "mode" "DI")])
-(define_expand "smulsi3_highpart"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI (sign_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" ""))
- (sign_extend:DI
- (match_operand:SI 2 "register_operand" "")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC FLAGS_REG))])]
- ""
- "")
-
-(define_insn "*smulsi3_highpart_insn"
+(define_insn "*<s>mulsi3_highpart_1"
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
- (mult:DI (sign_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "%a"))
- (sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
+ (mult:DI
+ (any_extend:DI
+ (match_operand:SI 1 "nonimmediate_operand" "%a"))
+ (any_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=1"))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{l}\t%2"
+ "<sgnprefix>mul{l}\t%2"
[(set_attr "type" "imul")
+ (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(set_attr "amdfam10_decode" "double")
(set_attr "mode" "SI")])
-(define_insn "*smulsi3_highpart_zext"
+(define_insn "*<s>mulsi3_highpart_zext"
[(set (match_operand:DI 0 "register_operand" "=d")
(zero_extend:DI (truncate:SI
(lshiftrt:DI
- (mult:DI (sign_extend:DI
+ (mult:DI (any_extend:DI
(match_operand:SI 1 "nonimmediate_operand" "%a"))
- (sign_extend:DI
+ (any_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "rm")))
(const_int 32)))))
(clobber (match_scratch:SI 3 "=1"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "imul{l}\t%2"
+ "<sgnprefix>mul{l}\t%2"
[(set_attr "type" "imul")
+ (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
[(set (match_operand:MODEF 0 "register_operand" "")
(mult:MODEF (match_operand:MODEF 1 "register_operand" "")
(match_operand:MODEF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
-
-;; SSE5 scalar multiply/add instructions are defined in sse.md.
-
\f
;; Divide instructions
-(define_insn "divqi3"
- [(set (match_operand:QI 0 "register_operand" "=a")
- (div:QI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH"
- "idiv{b}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "QI")])
-
-(define_insn "udivqi3"
+(define_insn "<u>divqi3"
[(set (match_operand:QI 0 "register_operand" "=a")
- (udiv:QI (match_operand:HI 1 "register_operand" "0")
- (match_operand:QI 2 "nonimmediate_operand" "qm")))
+ (any_div:QI
+ (match_operand:HI 1 "register_operand" "0")
+ (match_operand:QI 2 "nonimmediate_operand" "qm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_QIMODE_MATH"
- "div{b}\t%2"
+ "<sgnprefix>div{b}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "QI")])
[(set (match_operand:DF 0 "register_operand" "")
(div:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
+ "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
+ || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "divsf3"
[(set (match_operand:SF 0 "register_operand" "")
(div:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE_MATH"
+ "(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
+ || TARGET_SSE_MATH"
{
- if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
+ if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations)
{
}
})
\f
-;; Remainder instructions.
-
-(define_expand "divmoddi4"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (div:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonimmediate_operand" "")))
- (set (match_operand:DI 3 "register_operand" "")
- (mod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
- "")
-
-;; Allow to come the parameter in eax or edx to avoid extra moves.
-;; Penalize eax case slightly because it results in worse scheduling
-;; of code.
-(define_insn "*divmoddi4_nocltd_rex64"
- [(set (match_operand:DI 0 "register_operand" "=&a,?a")
- (div:DI (match_operand:DI 2 "register_operand" "1,0")
- (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
- (set (match_operand:DI 1 "register_operand" "=&d,&d")
- (mod:DI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmoddi4_cltd_rex64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (div:DI (match_operand:DI 2 "register_operand" "a")
- (match_operand:DI 3 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 1 "register_operand" "=&d")
- (mod:DI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmoddi_noext_rex64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (div:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 3 "register_operand" "=d")
- (mod:DI (match_dup 1) (match_dup 2)))
- (use (match_operand:DI 4 "register_operand" "3"))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "idiv{q}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (div:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonimmediate_operand" "")))
- (set (match_operand:DI 3 "register_operand" "")
- (mod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(parallel [(set (match_dup 3)
- (ashiftrt:DI (match_dup 4) (const_int 63)))
- (clobber (reg:CC FLAGS_REG))])
- (parallel [(set (match_dup 0)
- (div:DI (reg:DI 0) (match_dup 2)))
- (set (match_dup 3)
- (mod:DI (reg:DI 0) (match_dup 2)))
- (use (match_dup 3))
- (clobber (reg:CC FLAGS_REG))])]
-{
- /* Avoid use of cltd in favor of a mov+shift. */
- if (!TARGET_USE_CLTD && !optimize_size)
- {
- if (true_regnum (operands[1]))
- emit_move_insn (operands[0], operands[1]);
- else
- emit_move_insn (operands[3], operands[1]);
- operands[4] = operands[3];
- }
- else
- {
- gcc_assert (!true_regnum (operands[1]));
- operands[4] = operands[1];
- }
-})
-
-
-(define_expand "divmodsi4"
- [(parallel [(set (match_operand:SI 0 "register_operand" "")
- (div:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
- (set (match_operand:SI 3 "register_operand" "")
- (mod:SI (match_dup 1) (match_dup 2)))
+;; Divmod instructions.
+
+(define_expand "divmod<mode>4"
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ (div:SWIM248
+ (match_operand:SWIM248 1 "register_operand" "")
+ (match_operand:SWIM248 2 "nonimmediate_operand" "")))
+ (set (match_operand:SWIM248 3 "register_operand" "")
+ (mod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
""
"")
-;; Allow to come the parameter in eax or edx to avoid extra moves.
-;; Penalize eax case slightly because it results in worse scheduling
-;; of code.
-(define_insn "*divmodsi4_nocltd"
- [(set (match_operand:SI 0 "register_operand" "=&a,?a")
- (div:SI (match_operand:SI 2 "register_operand" "1,0")
- (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
- (set (match_operand:SI 1 "register_operand" "=&d,&d")
- (mod:SI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "!optimize_size && !TARGET_USE_CLTD"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmodsi4_cltd"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (div:SI (match_operand:SI 2 "register_operand" "a")
- (match_operand:SI 3 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 1 "register_operand" "=&d")
- (mod:SI (match_dup 2) (match_dup 3)))
- (clobber (reg:CC FLAGS_REG))]
- "optimize_size || TARGET_USE_CLTD"
- "#"
- [(set_attr "type" "multi")])
-
-(define_insn "*divmodsi_noext"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (div:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 3 "register_operand" "=d")
- (mod:SI (match_dup 1) (match_dup 2)))
- (use (match_operand:SI 4 "register_operand" "3"))
+(define_insn_and_split "*divmod<mode>4"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=&d")
+ (mod:SWIM248 (match_dup 2) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))]
""
- "idiv{l}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (div:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
- (set (match_operand:SI 3 "register_operand" "")
- (mod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed"
- [(parallel [(set (match_dup 3)
- (ashiftrt:SI (match_dup 4) (const_int 31)))
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 1)
+ (ashiftrt:SWIM248 (match_dup 4) (match_dup 5)))
(clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_dup 0)
- (div:SI (reg:SI 0) (match_dup 2)))
- (set (match_dup 3)
- (mod:SI (reg:SI 0) (match_dup 2)))
- (use (match_dup 3))
+ (div:SWIM248 (match_dup 2) (match_dup 3)))
+ (set (match_dup 1)
+ (mod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_dup 1))
(clobber (reg:CC FLAGS_REG))])]
{
- /* Avoid use of cltd in favor of a mov+shift. */
- if (!TARGET_USE_CLTD && !optimize_size)
- {
- if (true_regnum (operands[1]))
- emit_move_insn (operands[0], operands[1]);
- else
- emit_move_insn (operands[3], operands[1]);
- operands[4] = operands[3];
- }
+ operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
+
+ if (<MODE>mode != HImode
+ && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
+ operands[4] = operands[2];
else
{
- gcc_assert (!true_regnum (operands[1]));
+ /* Avoid use of cltd in favor of a mov+shift. */
+ emit_move_insn (operands[1], operands[2]);
operands[4] = operands[1];
}
-})
-;; %%% Split me.
-(define_insn "divmodhi4"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (div:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:HI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:HI 3 "register_operand" "=&d")
- (mod:HI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_HIMODE_MATH"
- "cwtd\;idiv{w}\t%2"
- [(set_attr "type" "multi")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
-
-(define_insn "udivmoddi4"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (udiv:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 3 "register_operand" "=&d")
- (umod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "xor{q}\t%3, %3\;div{q}\t%2"
+}
[(set_attr "type" "multi")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*udivmoddi4_noext"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (udiv:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:DI 3 "register_operand" "=d")
- (umod:DI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
+(define_insn "*divmod<mode>4_noext"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=d")
+ (mod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_operand:SWIM248 4 "register_operand" "1"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "div{q}\t%2"
+ ""
+ "idiv{<imodesuffix>}\t%3"
[(set_attr "type" "idiv")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<MODE>")])
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (udiv:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonimmediate_operand" "")))
- (set (match_operand:DI 3 "register_operand" "")
- (umod:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
- [(set (match_dup 3) (const_int 0))
- (parallel [(set (match_dup 0)
- (udiv:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (umod:DI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
+(define_expand "udivmod<mode>4"
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ (udiv:SWIM248
+ (match_operand:SWIM248 1 "register_operand" "")
+ (match_operand:SWIM248 2 "nonimmediate_operand" "")))
+ (set (match_operand:SWIM248 3 "register_operand" "")
+ (umod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
- "")
-
-(define_insn "udivmodsi4"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (udiv:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 3 "register_operand" "=&d")
- (umod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
""
- "xor{l}\t%3, %3\;div{l}\t%2"
- [(set_attr "type" "multi")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
+ "")
-(define_insn "*udivmodsi4_noext"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (udiv:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:SI 3 "register_operand" "=d")
- (umod:SI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
+(define_insn_and_split "*udivmod<mode>4"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=&d")
+ (umod:SWIM248 (match_dup 2) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))]
""
- "div{l}\t%2"
- [(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (udiv:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
- (set (match_operand:SI 3 "register_operand" "")
- (umod:SI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed"
- [(set (match_dup 3) (const_int 0))
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 1) (const_int 0))
(parallel [(set (match_dup 0)
- (udiv:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (umod:SI (match_dup 1) (match_dup 2)))
- (use (match_dup 3))
- (clobber (reg:CC FLAGS_REG))])]
- "")
-
-(define_expand "udivmodhi4"
- [(set (match_dup 4) (const_int 0))
- (parallel [(set (match_operand:HI 0 "register_operand" "")
- (udiv:HI (match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "nonimmediate_operand" "")))
- (set (match_operand:HI 3 "register_operand" "")
- (umod:HI (match_dup 1) (match_dup 2)))
- (use (match_dup 4))
+ (udiv:SWIM248 (match_dup 2) (match_dup 3)))
+ (set (match_dup 1)
+ (umod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_dup 1))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_HIMODE_MATH"
- "operands[4] = gen_reg_rtx (HImode);")
+ ""
+ [(set_attr "type" "multi")
+ (set_attr "mode" "<MODE>")])
-(define_insn "*udivmodhi_noext"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (udiv:HI (match_operand:HI 1 "register_operand" "0")
- (match_operand:HI 2 "nonimmediate_operand" "rm")))
- (set (match_operand:HI 3 "register_operand" "=d")
- (umod:HI (match_dup 1) (match_dup 2)))
- (use (match_operand:HI 4 "register_operand" "3"))
+(define_insn "*udivmod<mode>4_noext"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=d")
+ (umod:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_operand:SWIM248 4 "register_operand" "1"))
(clobber (reg:CC FLAGS_REG))]
""
- "div{w}\t%2"
+ "div{<imodesuffix>}\t%3"
[(set_attr "type" "idiv")
- (set_attr "mode" "HI")])
+ (set_attr "mode" "<MODE>")])
;; We cannot use div/idiv for double division, because it causes
;; "division by zero" on the overflow and that's not what we expect
[(set (reg FLAGS_REG)
(compare
(and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
- (match_operand:SI 1 "general_operand" "in,in,rin"))
+ (match_operand:SI 1 "general_operand" "i,i,ri"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
[(set_attr "type" "test")
(set_attr "mode" "QI")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "pent_pair" "np")])
(define_insn "*testqi_ext_1"
else if (GET_CODE (val) == SUBREG
&& (submode = GET_MODE (SUBREG_REG (val)),
GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
- && pos + len <= GET_MODE_BITSIZE (submode))
+ && pos + len <= GET_MODE_BITSIZE (submode)
+ && GET_MODE_CLASS (submode) == MODE_INT)
{
/* Narrow a paradoxical subreg to prevent partial register stalls. */
mode = submode;
(define_expand "anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_szext_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:DI 2 "x86_64_szext_general_operand" "")))]
"TARGET_64BIT"
"ix86_expand_binary_operator (AND, DImode, operands); DONE;")
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return "movz{bq|x}\t{%1,%0|%0, %1}";
+ return "movz{bl|x}\t{%1, %k0|%k0, %1}";
else
- return "movz{wq|x}\t{%1,%0|%0, %1}";
+ return "movz{wl|x}\t{%1, %k0|%k0, %1}";
}
default:
}
[(set_attr "type" "alu,alu,alu,imovx")
(set_attr "length_immediate" "*,*,*,0")
- (set_attr "mode" "SI,DI,DI,DI")])
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (match_operand 1 "ext_QIreg_nomode_operand" "")))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "mode" "SI,DI,DI,SI")])
(define_insn "*anddi_2"
[(set (reg FLAGS_REG)
(define_expand "andsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:SI 2 "general_operand" "")))]
""
"ix86_expand_binary_operator (AND, SImode, operands); DONE;")
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
- return "movz{bl|x}\t{%1,%0|%0, %1}";
+ return "movz{bl|x}\t{%1, %0|%0, %1}";
else
- return "movz{wl|x}\t{%1,%0|%0, %1}";
+ return "movz{wl|x}\t{%1, %0|%0, %1}";
}
default:
}
}
[(set_attr "type" "alu,alu,imovx")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+ (match_operand 1 "ext_QIreg_nomode_operand" "")))
+ (const_string "1")
+ (const_string "*")))
(set_attr "length_immediate" "*,*,0")
(set_attr "mode" "SI")])
(and (match_dup 0)
(const_int -65536)))
(clobber (reg:CC FLAGS_REG))]
- "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
+ "optimize_function_for_size_p (cfun) || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (HImode, operands[0]);")
(and (match_dup 0)
(const_int -256)))
(clobber (reg:CC FLAGS_REG))]
- "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_REG_STALL) && reload_completed"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (QImode, operands[0]);")
(and (match_dup 0)
(const_int -65281)))
(clobber (reg:CC FLAGS_REG))]
- "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_REG_STALL) && reload_completed"
[(parallel [(set (zero_extract:SI (match_dup 0)
(const_int 8)
(const_int 8))
(define_expand "andhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:HI 2 "general_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (AND, HImode, operands); DONE;")
(define_insn "*andhi_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
- (match_operand:HI 2 "general_operand" "ri,rm,L")))
+ (match_operand:HI 2 "general_operand" "rn,rm,L")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, HImode, operands)"
{
}
[(set_attr "type" "alu,alu,imovx")
(set_attr "length_immediate" "*,*,0")
+ (set (attr "prefix_rex")
+ (if_then_else
+ (and (eq_attr "type" "imovx")
+ (match_operand 1 "ext_QIreg_nomode_operand" ""))
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "HI,HI,SI")])
(define_insn "*andhi_2"
[(set (reg FLAGS_REG)
(compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "g,ri"))
+ (match_operand:HI 2 "general_operand" "rmn,rn"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
(and:HI (match_dup 1) (match_dup 2)))]
(define_expand "andqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "general_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (AND, QImode, operands); DONE;")
(define_insn "*andqi_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (AND, QImode, operands)"
"@
(define_insn "*andqi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(and:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qi,qmi")))
+ (match_operand:QI 1 "general_operand" "qn,qmn")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"and{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
[(set (reg FLAGS_REG)
(compare (and:QI
(match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qim,qi,i"))
+ (match_operand:QI 2 "general_operand" "qmn,qn,n"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
(and:QI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare (and:QI
(match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qim,qi"))
+ (match_operand:QI 2 "general_operand" "qmn,qn"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
(and:QI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare (and:QI
(match_operand:QI 0 "nonimmediate_operand" "+q,qm")
- (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
+ (match_operand:QI 1 "nonimmediate_operand" "qmn,qn"))
(const_int 0)))
(set (strict_low_part (match_dup 0))
(and:QI (match_dup 0) (match_dup 1)))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"and{b}\t{%1, %0|%0, %1}"
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
;; Generated by peephole translating test to and. This shows up
"and{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*andqi_ext_1"
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(~INTVAL (operands[2]) & ~(255 << 8))
&& GET_MODE (operands[0]) != QImode"
[(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(~INTVAL (operands[2]) & ~255)
&& !(INTVAL (operands[2]) & 128)
&& GET_MODE (operands[0]) != QImode"
(define_expand "iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:DI 2 "x86_64_general_operand" "")))]
"TARGET_64BIT"
"ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
(define_expand "iorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:SI 2 "general_operand" "")))]
""
"ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
(define_expand "iorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:HI 2 "general_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
(define_insn "*iorhi_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
(ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "g,ri")))
+ (match_operand:HI 2 "general_operand" "rmn,rn")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (IOR, HImode, operands)"
"or{w}\t{%2, %0|%0, %2}"
(define_insn "*iorhi_2"
[(set (reg FLAGS_REG)
(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "g,ri"))
+ (match_operand:HI 2 "general_operand" "rmn,rn"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
(ior:HI (match_dup 1) (match_dup 2)))]
(define_insn "*iorhi_3"
[(set (reg FLAGS_REG)
(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
- (match_operand:HI 2 "general_operand" "g"))
+ (match_operand:HI 2 "general_operand" "rmn"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
(define_expand "iorqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "general_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
(define_insn "*iorqi_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
+ (match_operand:QI 2 "general_operand" "qmn,qn,rn")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (IOR, QImode, operands)"
"@
(define_insn "*iorqi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
(ior:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qmi,qi")))
+ (match_operand:QI 1 "general_operand" "qmn,qn")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"or{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(define_insn "*iorqi_2"
[(set (reg FLAGS_REG)
(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qim,qi"))
+ (match_operand:QI 2 "general_operand" "qmn,qn"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
(ior:QI (match_dup 1) (match_dup 2)))]
(define_insn "*iorqi_2_slp"
[(set (reg FLAGS_REG)
(compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
- (match_operand:QI 1 "general_operand" "qim,qi"))
+ (match_operand:QI 1 "general_operand" "qmn,qn"))
(const_int 0)))
(set (strict_low_part (match_dup 0))
(ior:QI (match_dup 0) (match_dup 1)))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"or{b}\t{%1, %0|%0, %1}"
(define_insn "*iorqi_3"
[(set (reg FLAGS_REG)
(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "general_operand" "qim"))
+ (match_operand:QI 2 "general_operand" "qmn"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCNOmode)
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-(define_insn "iorqi_ext_0"
+(define_insn "*iorqi_ext_0"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(const_int 8))
(match_operand 2 "const_int_operand" "n")))
(clobber (reg:CC FLAGS_REG))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"or{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*iorqi_ext_1"
(match_operand:QI 2 "general_operand" "Qm"))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"or{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(match_operand 2 "ext_register_operand" "Q"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"or{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(const_int 8)
(const_int 8))))
(clobber (reg:CC FLAGS_REG))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"ior{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(INTVAL (operands[2]) & ~(255 << 8))
&& GET_MODE (operands[0]) != QImode"
[(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(INTVAL (operands[2]) & ~255)
&& (INTVAL (operands[2]) & 128)
&& GET_MODE (operands[0]) != QImode"
(define_expand "xordi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:DI 2 "x86_64_general_operand" "")))]
"TARGET_64BIT"
"ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
(define_expand "xorsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:SI 2 "general_operand" "")))]
""
"ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
(define_expand "xorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:HI 2 "general_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
(define_insn "*xorhi_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
(xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "g,ri")))
+ (match_operand:HI 2 "general_operand" "rmn,rn")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (XOR, HImode, operands)"
"xor{w}\t{%2, %0|%0, %2}"
(define_insn "*xorhi_2"
[(set (reg FLAGS_REG)
(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "g,ri"))
+ (match_operand:HI 2 "general_operand" "rmn,rn"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
(xor:HI (match_dup 1) (match_dup 2)))]
(define_insn "*xorhi_3"
[(set (reg FLAGS_REG)
(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
- (match_operand:HI 2 "general_operand" "g"))
+ (match_operand:HI 2 "general_operand" "rmn"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCNOmode)
(define_expand "xorqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "general_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
(define_insn "*xorqi_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
+ (match_operand:QI 2 "general_operand" "qmn,qn,rn")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (XOR, QImode, operands)"
"@
(define_insn "*xorqi_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
(xor:QI (match_dup 0)
- (match_operand:QI 1 "general_operand" "qi,qmi")))
+ (match_operand:QI 1 "general_operand" "qn,qmn")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"xor{b}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
-(define_insn "xorqi_ext_0"
+(define_insn "*xorqi_ext_0"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(const_int 8))
(match_operand 2 "const_int_operand" "n")))
(clobber (reg:CC FLAGS_REG))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "1")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_ext_1"
(match_operand:QI 2 "general_operand" "Qm"))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(match_operand 2 "ext_register_operand" "Q"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(const_int 8)
(const_int 8))))
(clobber (reg:CC FLAGS_REG))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
+ "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
"xor{b}\t{%h2, %h0|%h0, %h2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
[(set (reg FLAGS_REG)
(compare
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qim,qi"))
+ (match_operand:QI 2 "general_operand" "qmn,qn"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
(xor:QI (match_dup 1) (match_dup 2)))]
(define_insn "*xorqi_2_slp"
[(set (reg FLAGS_REG)
(compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
- (match_operand:QI 1 "general_operand" "qim,qi"))
+ (match_operand:QI 1 "general_operand" "qmn,qn"))
(const_int 0)))
(set (strict_low_part (match_dup 0))
(xor:QI (match_dup 0) (match_dup 1)))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCNOmode)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"xor{b}\t{%1, %0|%0, %1}"
[(set (reg FLAGS_REG)
(compare
(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "general_operand" "qim"))
+ (match_operand:QI 2 "general_operand" "qmn"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCNOmode)
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_ext_1_rex64"
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
+ (set_attr "modrm" "1")
(set_attr "mode" "QI")])
(define_expand "xorqi_cc_ext_1"
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(INTVAL (operands[2]) & ~(255 << 8))
&& GET_MODE (operands[0]) != QImode"
[(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
- && (!TARGET_PARTIAL_REG_STALL || optimize_size)
+ && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(INTVAL (operands[2]) & ~255)
&& (INTVAL (operands[2]) & 128)
&& GET_MODE (operands[0]) != QImode"
;; Negation instructions
(define_expand "negti2"
- [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (neg:TI (match_operand:TI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (neg:TI (match_operand:TI 1 "nonimmediate_operand" "")))]
"TARGET_64BIT"
"ix86_expand_unary_operator (NEG, TImode, operands); DONE;")
"split_ti (&operands[0], 2, &operands[0], &operands[2]);")
(define_expand "negdi2"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
""
"ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
(define_expand "negsi2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
"ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
(set_attr "mode" "SI")])
(define_expand "neghi2"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "")
+ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
(set_attr "mode" "HI")])
(define_expand "negqi2"
- [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
(define_expand "<code>tf2"
[(set (match_operand:TF 0 "register_operand" "")
(absneg:TF (match_operand:TF 1 "register_operand" "")))]
- "TARGET_64BIT"
+ "TARGET_SSE2"
"ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
(define_insn "*absnegtf2_sse"
[(match_operand:TF 1 "register_operand" "0,x")]))
(use (match_operand:TF 2 "nonimmediate_operand" "xm,0"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
+ "TARGET_SSE2"
"#")
;; Splitters for fp abs and neg.
(match_operand:CSGNMODE 1 "nonmemory_operand" "")
(match_operand:CSGNMODE 2 "register_operand" "")]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_64BIT && (<MODE>mode == TFmode))"
+ || (TARGET_SSE2 && (<MODE>mode == TFmode))"
{
ix86_expand_copysign (operands);
DONE;
(match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "xm")]
UNSPEC_COPYSIGN))]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_64BIT && (<MODE>mode == TFmode))"
+ || (TARGET_SSE2 && (<MODE>mode == TFmode))"
"#"
"&& reload_completed"
[(const_int 0)]
UNSPEC_COPYSIGN))
(clobber (match_scratch:<CSGNVMODE> 1 "=x,x,x,x,x"))]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_64BIT && (<MODE>mode == TFmode))"
+ || (TARGET_SSE2 && (<MODE>mode == TFmode))"
"#")
(define_split
UNSPEC_COPYSIGN))
(clobber (match_scratch:<CSGNVMODE> 1 ""))]
"((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_64BIT && (<MODE>mode == TFmode)))
+ || (TARGET_SSE2 && (<MODE>mode == TFmode)))
&& reload_completed"
[(const_int 0)]
{
;; If the shift count is a constant, we need never emit more than one
;; shift pair, instead using moves and sign extension for counts greater
;; than 31.
-
-(define_expand "ashlti3"
- [(parallel [(set (match_operand:TI 0 "register_operand" "")
- (ashift:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_64BIT"
-{
- if (! immediate_operand (operands[2], QImode))
- {
- emit_insn (gen_ashlti3_1 (operands[0], operands[1], operands[2]));
- DONE;
- }
- ix86_expand_binary_operator (ASHIFT, TImode, operands);
- DONE;
-})
-
-(define_insn "ashlti3_1"
- [(set (match_operand:TI 0 "register_operand" "=r")
- (ashift:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:QI 2 "register_operand" "c")))
- (clobber (match_scratch:DI 3 "=&r"))
- (clobber (reg:CC FLAGS_REG))]
+
+(define_expand "ashlti3"
+ [(set (match_operand:TI 0 "register_operand" "")
+ (ashift:TI (match_operand:TI 1 "reg_or_pm1_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_64BIT"
- "#"
- [(set_attr "type" "multi")])
+ "ix86_expand_binary_operator (ASHIFT, TImode, operands); DONE;")
-;; This pattern must be defined before *ashlti3_2 to prevent
-;; combine pass from converting sse2_ashlti3 to *ashlti3_2.
+;; This pattern must be defined before *ashlti3_1 to prevent
+;; combine pass from converting sse2_ashlti3 to *ashlti3_1.
+
+(define_insn "*avx_ashlti3"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (ashift:TI (match_operand:TI 1 "register_operand" "x")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
+ "TARGET_AVX"
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
+ return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
+}
+ [(set_attr "type" "sseishft")
+ (set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
+ (set_attr "mode" "TI")])
(define_insn "sse2_ashlti3"
[(set (match_operand:TI 0 "register_operand" "=x")
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
-(define_insn "*ashlti3_2"
- [(set (match_operand:TI 0 "register_operand" "=r")
- (ashift:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "O")))
+(define_insn "*ashlti3_1"
+ [(set (match_operand:TI 0 "register_operand" "=&r,r")
+ (ashift:TI (match_operand:TI 1 "reg_or_pm1_operand" "n,0")
+ (match_operand:QI 2 "nonmemory_operand" "Oc,Oc")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"#"
[(set_attr "type" "multi")])
-(define_split
- [(set (match_operand:TI 0 "register_operand" "")
- (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
- (match_operand:QI 2 "register_operand" "")))
- (clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
+(define_peephole2
+ [(match_scratch:DI 3 "r")
+ (parallel [(set (match_operand:TI 0 "register_operand" "")
+ (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])
+ (match_dup 3)]
+ "TARGET_64BIT"
[(const_int 0)]
"ix86_split_ashl (operands, operands[3], TImode); DONE;")
(define_split
[(set (match_operand:TI 0 "register_operand" "")
- (ashift:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
+ (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
+ "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? epilogue_completed : reload_completed)"
[(const_int 0)]
"ix86_split_ashl (operands, NULL_RTX, TImode); DONE;")
(define_insn "x86_64_shld"
- [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
(ior:DI (ashift:DI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "J,c"))
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
+ (match_operand:QI 2 "nonmemory_operand" "Jc"))
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
(minus:QI (const_int 64) (match_dup 2)))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "@
- shld{q}\t{%2, %1, %0|%0, %1, %2}
- shld{q}\t{%s2%1, %0|%0, %1, %2}"
+ "shld{q}\t{%s2%1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "vector")])
-(define_expand "x86_64_shift_adj"
+(define_expand "x86_64_shift_adj_1"
[(set (reg:CCZ FLAGS_REG)
(compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
(const_int 64))
"TARGET_64BIT"
"")
+(define_expand "x86_64_shift_adj_2"
+ [(use (match_operand:DI 0 "register_operand" ""))
+ (use (match_operand:DI 1 "register_operand" ""))
+ (use (match_operand:QI 2 "register_operand" ""))]
+ "TARGET_64BIT"
+{
+ rtx label = gen_label_rtx ();
+ rtx tmp;
+
+ emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (64)));
+
+ tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
+ tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
+ tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
+ gen_rtx_LABEL_REF (VOIDmode, label),
+ pc_rtx);
+ tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
+ JUMP_LABEL (tmp) = label;
+
+ emit_move_insn (operands[0], operands[1]);
+ ix86_expand_clear (operands[1]);
+
+ emit_label (label);
+ LABEL_NUSES (label) = 1;
+
+ DONE;
+})
+
(define_expand "ashldi3"
[(set (match_operand:DI 0 "shiftdi_operand" "")
(ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
if (REG_P (operands[2]))
return "sal{q}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{q}\t%0";
else
return "sal{q}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "DI")])
;; Convert lea to the lea pattern to avoid flags dependency.
[(set (reg FLAGS_REG)
(compare
(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "e"))
+ (match_operand:QI 2 "const_1_to_63_operand" "J"))
(const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(ashift:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT
- && (optimize_size
+ && (optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{q}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{q}\t%0";
else
return "sal{q}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "DI")])
(define_insn "*ashldi3_cconly_rex64"
[(set (reg FLAGS_REG)
(compare
(ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "immediate_operand" "e"))
+ (match_operand:QI 2 "const_1_to_63_operand" "J"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT
- && (optimize_size
+ && (optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{q}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{q}\t%0";
else
return "sal{q}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "DI")])
(define_insn "*ashldi3_1"
[(const_int 0)]
"ix86_split_ashl (operands, NULL_RTX, DImode); DONE;")
-(define_insn "x86_shld_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
+(define_insn "x86_shld"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
(ior:SI (ashift:SI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "I,c"))
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:QI 2 "nonmemory_operand" "Ic"))
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
(minus:QI (const_int 32) (match_dup 2)))))
(clobber (reg:CC FLAGS_REG))]
""
- "@
- shld{l}\t{%2, %1, %0|%0, %1, %2}
- shld{l}\t{%s2%1, %0|%0, %1, %2}"
+ "shld{l}\t{%s2%1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "SI")
(define_expand "ashlsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
if (REG_P (operands[2]))
return "sal{l}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%0";
else
return "sal{l}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "SI")])
;; Convert lea to the lea pattern to avoid flags dependency.
if (REG_P (operands[2]))
return "sal{l}\t{%b2, %k0|%k0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%k0";
else
return "sal{l}\t{%2, %k0|%k0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "SI")])
;; Convert lea to the lea pattern to avoid flags dependency.
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashift:SI (match_dup 1) (match_dup 2)))]
- "(optimize_size
+ "(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{l}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%0";
else
return "sal{l}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "SI")])
(define_insn "*ashlsi3_cconly"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
- "(optimize_size
+ "(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{l}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%0";
else
return "sal{l}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "SI")])
(define_insn "*ashlsi3_cmp_zext"
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT
- && (optimize_size
+ && (optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{l}\t{%b2, %k0|%k0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%k0";
else
return "sal{l}\t{%2, %k0|%k0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "SI")])
(define_expand "ashlhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
if (REG_P (operands[2]))
return "sal{w}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "HI,SI")])
(define_insn "*ashlhi3_1"
if (REG_P (operands[2]))
return "sal{w}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "HI")])
;; This pattern can't accept a variable shift count, since shifts by
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashift:HI (match_dup 1) (match_dup 2)))]
- "(optimize_size
+ "(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{w}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "HI")])
(define_insn "*ashlhi3_cconly"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
- "(optimize_size
+ "(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{w}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "HI")])
(define_expand "ashlqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
return "sal{b}\t{%b2, %0|%0, %b2}";
}
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
return "sal{l}\t%0";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "QI,SI,SI")])
(define_insn "*ashlqi3_1"
return "sal{b}\t{%b2, %0|%0, %b2}";
}
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
return "sal{l}\t%0";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "QI,SI")])
;; This pattern can't accept a variable shift count, since shifts by
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashift:QI (match_dup 1) (match_dup 2)))]
- "(optimize_size
+ "(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{b}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{b}\t%0";
else
return "sal{b}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "QI")])
(define_insn "*ashlqi3_cconly"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
- "(optimize_size
+ "(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
if (REG_P (operands[2]))
return "sal{b}\t{%b2, %0|%0, %b2}";
else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_size))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{b}\t%0";
else
return "sal{b}\t{%2, %0|%0, %2}";
(const_string "alu")
]
(const_string "ishift")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift")
+ (and (match_operand 2 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
(set_attr "mode" "QI")])
;; See comment above `ashldi3' about how this works.
(define_expand "ashrti3"
- [(parallel [(set (match_operand:TI 0 "register_operand" "")
- (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+ [(set (match_operand:TI 0 "register_operand" "")
+ (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_64BIT"
-{
- if (! immediate_operand (operands[2], QImode))
- {
- emit_insn (gen_ashrti3_1 (operands[0], operands[1], operands[2]));
- DONE;
- }
- ix86_expand_binary_operator (ASHIFTRT, TImode, operands);
- DONE;
-})
+ "ix86_expand_binary_operator (ASHIFTRT, TImode, operands); DONE;")
-(define_insn "ashrti3_1"
+(define_insn "*ashrti3_1"
[(set (match_operand:TI 0 "register_operand" "=r")
(ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:QI 2 "register_operand" "c")))
- (clobber (match_scratch:DI 3 "=&r"))
+ (match_operand:QI 2 "nonmemory_operand" "Oc")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"#"
[(set_attr "type" "multi")])
-(define_insn "*ashrti3_2"
- [(set (match_operand:TI 0 "register_operand" "=r")
- (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "O")))
- (clobber (reg:CC FLAGS_REG))]
+(define_peephole2
+ [(match_scratch:DI 3 "r")
+ (parallel [(set (match_operand:TI 0 "register_operand" "")
+ (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])
+ (match_dup 3)]
"TARGET_64BIT"
- "#"
- [(set_attr "type" "multi")])
-
-(define_split
- [(set (match_operand:TI 0 "register_operand" "")
- (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "register_operand" "")))
- (clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
[(const_int 0)]
"ix86_split_ashr (operands, operands[3], TImode); DONE;")
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(ashiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
+ (match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
+ "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? epilogue_completed : reload_completed)"
[(const_int 0)]
"ix86_split_ashr (operands, NULL_RTX, TImode); DONE;")
(define_insn "x86_64_shrd"
- [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
(ior:DI (ashiftrt:DI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "J,c"))
- (ashift:DI (match_operand:DI 1 "register_operand" "r,r")
+ (match_operand:QI 2 "nonmemory_operand" "Jc"))
+ (ashift:DI (match_operand:DI 1 "register_operand" "r")
(minus:QI (const_int 64) (match_dup 2)))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "@
- shrd{q}\t{%2, %1, %0|%0, %1, %2}
- shrd{q}\t{%s2%1, %0|%0, %1, %2}"
+ "shrd{q}\t{%s2%1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "mode" "DI")
""
"ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
-(define_insn "*ashrdi3_63_rex64"
+(define_expand "x86_64_shift_adj_3"
+ [(use (match_operand:DI 0 "register_operand" ""))
+ (use (match_operand:DI 1 "register_operand" ""))
+ (use (match_operand:QI 2 "register_operand" ""))]
+ ""
+{
+ rtx label = gen_label_rtx ();
+ rtx tmp;
+
+ emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (64)));
+
+ tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
+ tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
+ tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
+ gen_rtx_LABEL_REF (VOIDmode, label),
+ pc_rtx);
+ tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
+ JUMP_LABEL (tmp) = label;
+
+ emit_move_insn (operands[0], operands[1]);
+ emit_insn (gen_ashrdi3_63_rex64 (operands[1], operands[1], GEN_INT (63)));
+
+ emit_label (label);
+ LABEL_NUSES (label) = 1;
+
+ DONE;
+})
+
+(define_insn "ashrdi3_63_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
(match_operand:DI 2 "const_int_operand" "i,i")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && INTVAL (operands[2]) == 63
- && (TARGET_USE_CLTD || optimize_size)
+ && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"@
{cqto|cqo}
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"sar{q}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:DI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
(define_insn "*ashrdi3_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"sar{q}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:DI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
(define_insn "*ashrdi3_one_bit_cconly_rex64"
[(set (reg FLAGS_REG)
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"sar{q}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
[(set (reg FLAGS_REG)
(compare
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_operand" "n"))
+ (match_operand:QI 2 "const_1_to_63_operand" "J"))
(const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT
- && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"sar{q}\t{%2, %0|%0, %2}"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_operand" "n"))
+ (match_operand:QI 2 "const_1_to_63_operand" "J"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT
- && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
"sar{q}\t{%2, %0|%0, %2}"
[(const_int 0)]
"ix86_split_ashr (operands, NULL_RTX, DImode); DONE;")
-(define_insn "x86_shrd_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
+(define_insn "x86_shrd"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
(ior:SI (ashiftrt:SI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "I,c"))
- (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:QI 2 "nonmemory_operand" "Ic"))
+ (ashift:SI (match_operand:SI 1 "register_operand" "r")
(minus:QI (const_int 32) (match_dup 2)))))
(clobber (reg:CC FLAGS_REG))]
""
- "@
- shrd{l}\t{%2, %1, %0|%0, %1, %2}
- shrd{l}\t{%s2%1, %0|%0, %1, %2}"
+ "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
(set_attr "pent_pair" "np")
DONE;
})
-(define_insn "ashrsi3_31"
+(define_expand "ashrsi3_31"
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
+ (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
+ (match_operand:SI 2 "const_int_operand" "i,i")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "")
+
+(define_insn "*ashrsi3_31"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
(match_operand:SI 2 "const_int_operand" "i,i")))
(clobber (reg:CC FLAGS_REG))]
- "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
+ "INTVAL (operands[2]) == 31
+ && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
{cltd|cdq}
(zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
(match_operand:SI 2 "const_int_operand" "i,i"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
+ "TARGET_64BIT && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
&& INTVAL (operands[2]) == 31
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"@
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*ashrsi3_1_one_bit_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:QI 2 "const1_operand" ""))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t%k0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*ashrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*ashrsi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*ashrsi3_one_bit_cmp_zext"
[(set (reg FLAGS_REG)
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t%k0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t{%2, %0|%0, %2}"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t{%2, %0|%0, %2}"
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT
- && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
"sar{l}\t{%2, %k0|%k0, %2}"
(define_expand "ashrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"sar{w}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
(define_insn "*ashrhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"sar{w}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
(define_insn "*ashrhi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"sar{w}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_dup 1) (match_dup 2)))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"sar{w}\t{%2, %0|%0, %2}"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
"sar{w}\t{%2, %0|%0, %2}"
(define_expand "ashrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*ashrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(ashiftrt:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && (TARGET_SHIFT1 || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t%0"
[(set_attr "type" "ishift1")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*ashrqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(ashiftrt:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
sar{b}\t{%1, %0|%0, %1}
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*ashrqi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(compare
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" "I"))
+ (match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t{%2, %0|%0, %2}"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
"sar{b}\t{%2, %0|%0, %2}"
;; See comment above `ashldi3' about how this works.
(define_expand "lshrti3"
- [(parallel [(set (match_operand:TI 0 "register_operand" "")
- (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+ [(set (match_operand:TI 0 "register_operand" "")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_64BIT"
-{
- if (! immediate_operand (operands[2], QImode))
- {
- emit_insn (gen_lshrti3_1 (operands[0], operands[1], operands[2]));
- DONE;
- }
- ix86_expand_binary_operator (LSHIFTRT, TImode, operands);
- DONE;
-})
+ "ix86_expand_binary_operator (LSHIFTRT, TImode, operands); DONE;")
-(define_insn "lshrti3_1"
- [(set (match_operand:TI 0 "register_operand" "=r")
- (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:QI 2 "register_operand" "c")))
- (clobber (match_scratch:DI 3 "=&r"))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "#"
- [(set_attr "type" "multi")])
+;; This pattern must be defined before *lshrti3_1 to prevent
+;; combine pass from converting sse2_lshrti3 to *lshrti3_1.
-;; This pattern must be defined before *lshrti3_2 to prevent
-;; combine pass from converting sse2_lshrti3 to *lshrti3_2.
+(define_insn "*avx_lshrti3"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "x")
+ (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
+ "TARGET_AVX"
+{
+ operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
+ return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
+}
+ [(set_attr "type" "sseishft")
+ (set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
+ (set_attr "mode" "TI")])
(define_insn "sse2_lshrti3"
[(set (match_operand:TI 0 "register_operand" "=x")
}
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
-(define_insn "*lshrti3_2"
+(define_insn "*lshrti3_1"
[(set (match_operand:TI 0 "register_operand" "=r")
(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:QI 2 "immediate_operand" "O")))
+ (match_operand:QI 2 "nonmemory_operand" "Oc")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"#"
[(set_attr "type" "multi")])
-(define_split
- [(set (match_operand:TI 0 "register_operand" "")
- (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "register_operand" "")))
- (clobber (match_scratch:DI 3 ""))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
+(define_peephole2
+ [(match_scratch:DI 3 "r")
+ (parallel [(set (match_operand:TI 0 "register_operand" "")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])
+ (match_dup 3)]
+ "TARGET_64BIT"
[(const_int 0)]
"ix86_split_lshr (operands, operands[3], TImode); DONE;")
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(lshiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
+ (match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed"
+ "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? epilogue_completed : reload_completed)"
[(const_int 0)]
"ix86_split_lshr (operands, NULL_RTX, TImode); DONE;")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{q}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:DI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
(define_insn "*lshrdi3_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(lshiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{q}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:DI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
(define_insn "*lshrdi3_cconly_one_bit_rex64"
[(set (reg FLAGS_REG)
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{q}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
[(set (reg FLAGS_REG)
(compare
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_operand" "e"))
+ (match_operand:QI 2 "const_1_to_63_operand" "J"))
(const_int 0)))
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(lshiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT
- && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{q}\t{%2, %0|%0, %2}"
[(set (reg FLAGS_REG)
(compare
(lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_operand" "e"))
+ (match_operand:QI 2 "const_1_to_63_operand" "J"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT
- && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{q}\t{%2, %0|%0, %2}"
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*lshrsi3_1_one_bit_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t%k0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*lshrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*lshrsi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*lshrsi3_cmp_one_bit_zext"
[(set (reg FLAGS_REG)
(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t%k0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t{%2, %0|%0, %2}"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t{%2, %0|%0, %2}"
(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT
- && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{l}\t{%2, %k0|%k0, %2}"
(define_expand "lshrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
- (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{w}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
(define_insn "*lshrhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{w}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
(define_insn "*lshrhi3_one_bit_cconly"
[(set (reg FLAGS_REG)
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{w}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_dup 1) (match_dup 2)))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{w}\t{%2, %0|%0, %2}"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
"shr{w}\t{%2, %0|%0, %2}"
(define_expand "lshrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"shr{b}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*lshrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(lshiftrt:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && (TARGET_SHIFT1 || optimize_size)"
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))"
"shr{b}\t%0"
[(set_attr "type" "ishift1")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*lshrqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(lshiftrt:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
shr{b}\t{%1, %0|%0, %1}
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(lshiftrt:QI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"shr{b}\t%0"
[(set_attr "type" "ishift")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*lshrqi2_one_bit_cconly"
[(set (reg FLAGS_REG)
(match_operand:QI 2 "const1_operand" ""))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"shr{b}\t%0"
[(set_attr "type" "ishift")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(lshiftrt:QI (match_dup 1) (match_dup 2)))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"shr{b}\t{%2, %0|%0, %2}"
(match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
- "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
+ "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
&& ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
"shr{b}\t{%2, %0|%0, %2}"
(define_expand "rotldi3"
[(set (match_operand:DI 0 "shiftdi_operand" "")
(rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
{
if (TARGET_64BIT)
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATE, DImode, operands)"
"rol{q}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand:DI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
(define_insn "*rotldi3_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(define_expand "rotlsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATE, SImode, operands)"
"rol{l}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*rotlsi3_1_one_bit_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:QI 2 "const1_operand" ""))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATE, SImode, operands)"
"rol{l}\t%k0"
[(set_attr "type" "rotate")
- (set_attr "length" "2")])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*rotlsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(define_expand "rotlhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATE, HImode, operands)"
"rol{w}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
(define_insn "*rotlhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(define_expand "rotlqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
(rotate:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && (TARGET_SHIFT1 || optimize_size)"
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))"
"rol{b}\t%0"
[(set_attr "type" "rotate1")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*rotlqi3_1_one_bit"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATE, QImode, operands)"
"rol{b}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*rotlqi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
(rotate:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
rol{b}\t{%1, %0|%0, %1}
(define_expand "rotrdi3"
[(set (match_operand:DI 0 "shiftdi_operand" "")
(rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
{
if (TARGET_64BIT)
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATERT, DImode, operands)"
"ror{q}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand:DI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "DI")])
(define_insn "*rotrdi3_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
(define_expand "rotrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATERT, SImode, operands)"
"ror{l}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*rotrsi3_1_one_bit_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:QI 2 "const1_operand" ""))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_size)
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATERT, SImode, operands)"
"ror{l}\t%k0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand:SI 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "SI")])
(define_insn "*rotrsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
(define_expand "rotrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_HIMODE_MATH"
"ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATERT, HImode, operands)"
"ror{w}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "HI")])
(define_insn "*rotrhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(define_expand "rotrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_QIMODE_MATH"
"ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
(match_operand:QI 2 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_size)
+ "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
&& ix86_binary_operator_ok (ROTATERT, QImode, operands)"
"ror{b}\t%0"
[(set_attr "type" "rotate")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*rotrqi3_1_one_bit_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(rotatert:QI (match_dup 0)
(match_operand:QI 1 "const1_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
- && (TARGET_SHIFT1 || optimize_size)"
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))"
"ror{b}\t%0"
[(set_attr "type" "rotate1")
- (set (attr "length")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "2")
- (const_string "*")))])
+ (set_attr "length_immediate" "0")
+ (set_attr "mode" "QI")])
(define_insn "*rotrqi3_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
(rotatert:QI (match_dup 0)
(match_operand:QI 1 "nonmemory_operand" "I,c")))
(clobber (reg:CC FLAGS_REG))]
- "(! TARGET_PARTIAL_REG_STALL || optimize_size)
+ "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
ror{b}\t{%1, %0|%0, %1}
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"bts{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btrq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btr{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btcq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
"btc{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
;; Allow Nocona to avoid these instructions if a register is available.
(const_int 1)
(match_operand:DI 1 "nonmemory_operand" "rN"))
(const_int 0)))]
- "TARGET_64BIT && (TARGET_USE_BT || optimize_size)"
+ "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
"bt{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "*btsi"
[(set (reg:CCC FLAGS_REG)
(const_int 1)
(match_operand:SI 1 "nonmemory_operand" "rN"))
(const_int 0)))]
- "TARGET_USE_BT || optimize_size"
+ "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"bt{l}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
\f
;; Store-flag instructions.
;; For all sCOND expanders, also expand the compare or test insn that
;; generates cc0. Generate an equality comparison if `seq' or `sne'.
-;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
-;; to avoid partial register stalls. Otherwise do things the setcc+movzx
-;; way, which can later delete the movzx if only QImode is needed.
+(define_insn_and_split "*setcc_di_1"
+ [(set (match_operand:DI 0 "register_operand" "=q")
+ (match_operator:DI 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))]
+ "TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (zero_extend:DI (match_dup 2)))]
+{
+ PUT_MODE (operands[1], QImode);
+ operands[2] = gen_lowpart (QImode, operands[0]);
+})
-(define_expand "s<code>"
- [(set (match_operand:QI 0 "register_operand" "")
- (int_cond:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (<CODE>, operands[0])) DONE; else FAIL;")
+(define_insn_and_split "*setcc_si_1_and"
+ [(set (match_operand:SI 0 "register_operand" "=q")
+ (match_operator:SI 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_PARTIAL_REG_STALL
+ && TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (parallel [(set (match_dup 0) (zero_extend:SI (match_dup 2)))
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ PUT_MODE (operands[1], QImode);
+ operands[2] = gen_lowpart (QImode, operands[0]);
+})
-(define_expand "s<code>"
- [(set (match_operand:QI 0 "register_operand" "")
- (fp_cond:QI (reg:CC FLAGS_REG) (const_int 0)))]
- "TARGET_80387 || TARGET_SSE"
- "if (ix86_expand_setcc (<CODE>, operands[0])) DONE; else FAIL;")
+(define_insn_and_split "*setcc_si_1_movzbl"
+ [(set (match_operand:SI 0 "register_operand" "=q")
+ (match_operator:SI 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))]
+ "!TARGET_PARTIAL_REG_STALL
+ && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
+{
+ PUT_MODE (operands[1], QImode);
+ operands[2] = gen_lowpart (QImode, operands[0]);
+})
-(define_insn "*setcc_1"
+(define_insn "*setcc_qi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(match_operator:QI 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))]
[(set_attr "type" "setcc")
(set_attr "mode" "QI")])
-(define_insn "*setcc_2"
+(define_insn "*setcc_qi_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
(match_operator:QI 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))]
;; 0xffffffff is NaN, but not in normalized form, so we can't represent
;; it directly.
-(define_insn "*sse_setcc<mode>"
+(define_insn "*avx_setcc<mode>"
[(set (match_operand:MODEF 0 "register_operand" "=x")
- (match_operator:MODEF 1 "sse_comparison_operator"
- [(match_operand:MODEF 2 "register_operand" "0")
+ (match_operator:MODEF 1 "avx_comparison_float_operator"
+ [(match_operand:MODEF 2 "register_operand" "x")
(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
- "cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
+ "TARGET_AVX"
+ "vcmp%D1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "type" "ssecmp")
+ (set_attr "prefix" "vex")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
-(define_insn "*sse5_setcc<mode>"
+(define_insn "*sse_setcc<mode>"
[(set (match_operand:MODEF 0 "register_operand" "=x")
- (match_operator:MODEF 1 "sse5_comparison_float_operator"
- [(match_operand:MODEF 2 "register_operand" "x")
+ (match_operator:MODEF 1 "sse_comparison_operator"
+ [(match_operand:MODEF 2 "register_operand" "0")
(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE5"
- "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sse4arg")
+ "SSE_FLOAT_MODE_P (<MODE>mode)"
+ "cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
+ [(set_attr "type" "ssecmp")
+ (set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
-
\f
;; Basic conditional jump instructions.
;; We ignore the overflow flag for signed branch instructions.
-;; For all bCOND expanders, also expand the compare or test insn that
-;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
-
-(define_expand "b<code>"
- [(set (pc)
- (if_then_else (int_cond:CC (reg:CC FLAGS_REG)
- (const_int 0))
- (label_ref (match_operand 0 ""))
- (pc)))]
- ""
- "ix86_expand_branch (<CODE>, operands[0]); DONE;")
-
-(define_expand "b<code>"
- [(set (pc)
- (if_then_else (fp_cond:CC (reg:CC FLAGS_REG)
- (const_int 0))
- (label_ref (match_operand 0 ""))
- (pc)))]
- "TARGET_80387 || TARGET_SSE_MATH"
- "ix86_expand_branch (<CODE>, operands[0]); DONE;")
-
(define_insn "*jcc_1"
[(set (pc)
(if_then_else (match_operator 1 "ix86_comparison_operator"
(const_int 2)
(const_int 6)))])
-;; ??? Handle alignment requirements for compare and branch fused macro-op;
-;; the branch instruction does not start at a 16-byte boundary or cross
-;; a 16-byte boundary.
-
-(define_insn "*jcc_fused_1"
- [(set (pc)
- (if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:SWI 2 "register_operand" "<r>")
- (match_operand:SWI 3 "const0_operand" "n")])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT"
-{
- return "test{<imodesuffix>}\t%2, %2\n\t"
- "%+j%E1\t%l0\t" ASM_COMMENT_START " fused";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*jcc_fused_2"
- [(set (pc)
- (if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:SWI 2 "register_operand" "<r>")
- (match_operand:SWI 3 "const0_operand" "n")])
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT"
-{
- return "test{<imodesuffix>}\t%2, %2\n\t"
- "%+j%e1\t%l0\t" ASM_COMMENT_START " fused";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*jcc_fused_3"
- [(set (pc)
- (if_then_else
- (match_operator 1 "ix86_comparison_uns_operator"
- [(match_operand:SWI 2 "nonimmediate_operand" "<r>,m,<r>")
- (match_operand:SWI 3 "<general_operand>" "<r><i>,<r>,m")])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT
- && !(MEM_P (operands[2])
- && (MEM_P (operands[3]) || CONST_INT_P (operands[3])))"
-{
- return "cmp{<imodesuffix>}\t{%3, %2|%2, %3}\n\t"
- "%+j%E1\t%l0\t" ASM_COMMENT_START " fused";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*jcc_fused_4"
- [(set (pc)
- (if_then_else
- (match_operator 1 "ix86_comparison_uns_operator"
- [(match_operand:SWI 2 "nonimmediate_operand" "<r>,m,<r>")
- (match_operand:SWI 3 "<general_operand>" "<r><i>,<r>,m")])
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "TARGET_FUSE_CMP_AND_BRANCH && !TARGET_64BIT
- && !(MEM_P (operands[2])
- && (MEM_P (operands[3]) || CONST_INT_P (operands[3])))"
-{
- return "cmp{<imodesuffix>}\t{%3, %2|%2, %3}\n\t"
- "%+j%e1\t%l0\t" ASM_COMMENT_START " fused";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "<MODE>")])
-
;; In general it is not safe to assume too much about CCmode registers,
;; so simplify-rtx stops when it sees a second one. Under certain
;; conditions this is safe on x86, so help combine not create
(match_operand:QI 2 "register_operand" "r")))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
- (pc)))]
- "TARGET_64BIT && (TARGET_USE_BT || optimize_size)"
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
(label_ref (match_operand 4 "" ""))
- (pc)))]
- "TARGET_64BIT && (TARGET_USE_BT || optimize_size)
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& (INTVAL (operands[3]) & 0x3f) == 0x3f"
"#"
"&& 1"
(match_operand:QI 2 "register_operand" "r")))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
- (pc)))]
- "TARGET_USE_BT || optimize_size"
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
(label_ref (match_operand 4 "" ""))
- (pc)))]
- "(TARGET_USE_BT || optimize_size)
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
+ "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
&& (INTVAL (operands[3]) & 0x1f) == 0x1f"
"#"
"&& 1"
(const_int 1))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
- (pc)))]
- "TARGET_USE_BT || optimize_size"
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
"#"
"&& 1"
[(set (reg:CCC FLAGS_REG)
(match_operator 0 "bt_comparison_operator"
[(and:SI
(lshiftrt:SI
- (match_operand:SI 1 "register_operand" "r")
- (subreg:QI
- (and:SI
- (match_operand:SI 2 "register_operand" "r")
- (match_operand:SI 3 "const_int_operand" "n")) 0))
- (const_int 1))
- (const_int 0)])
- (label_ref (match_operand 4 "" ""))
- (pc)))]
- "(TARGET_USE_BT || optimize_size)
- && (INTVAL (operands[3]) & 0x1f) == 0x1f"
- "#"
- "&& 1"
- [(set (reg:CCC FLAGS_REG)
- (compare:CCC
- (zero_extract:SI
- (match_dup 1)
- (const_int 1)
- (match_dup 2))
- (const_int 0)))
- (set (pc)
- (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
- (label_ref (match_dup 4))
- (pc)))]
- "PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
-
-;; Define combination compare-and-branch fp compare instructions to use
-;; during early optimization. Splitting the operation apart early makes
-;; for bad code when we want to reverse the operation.
-
-(define_insn "*fp_jcc_1_mixed"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f,x")
- (match_operand 2 "nonimmediate_operand" "f,xm")])
- (label_ref (match_operand 3 "" ""))
- (pc)))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_MIX_SSE_I387
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_1_sse"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "x")
- (match_operand 2 "nonimmediate_operand" "xm")])
- (label_ref (match_operand 3 "" ""))
- (pc)))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_SSE_MATH
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_1_387"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f")
- (match_operand 2 "register_operand" "f")])
- (label_ref (match_operand 3 "" ""))
- (pc)))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
- && TARGET_CMOVE
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_2_mixed"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f,x")
- (match_operand 2 "nonimmediate_operand" "f,xm")])
- (pc)
- (label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_MIX_SSE_I387
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
-
-(define_insn "*fp_jcc_2_sse"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "x")
- (match_operand 2 "nonimmediate_operand" "xm")])
- (pc)
- (label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "TARGET_SSE_MATH
- && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
+ (match_operand:SI 1 "register_operand" "r")
+ (subreg:QI
+ (and:SI
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "const_int_operand" "n")) 0))
+ (const_int 1))
+ (const_int 0)])
+ (label_ref (match_operand 4 "" ""))
+ (pc)))
+ (clobber (reg:CC FLAGS_REG))]
+ "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
+ && (INTVAL (operands[3]) & 0x1f) == 0x1f"
+ "#"
+ "&& 1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC
+ (zero_extract:SI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)))
+ (set (pc)
+ (if_then_else (match_op_dup 0 [(reg:CCC FLAGS_REG) (const_int 0)])
+ (label_ref (match_dup 4))
+ (pc)))]
+ "PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));")
-(define_insn "*fp_jcc_2_387"
- [(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
- [(match_operand 1 "register_operand" "f")
- (match_operand 2 "register_operand" "f")])
- (pc)
- (label_ref (match_operand 3 "" ""))))
- (clobber (reg:CCFP FPSR_REG))
- (clobber (reg:CCFP FLAGS_REG))]
- "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
- && TARGET_CMOVE
- && GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
- "#")
+;; Define combination compare-and-branch fp compare instructions to help
+;; combine.
(define_insn "*fp_jcc_3_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
(label_ref (match_operand 3 "" ""))
"TARGET_80387
&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
&& SELECT_CC_MODE (GET_CODE (operands[0]),
operands[1], operands[2]) == CCFPmode
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_4_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
(pc)
"TARGET_80387
&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
&& SELECT_CC_MODE (GET_CODE (operands[0]),
operands[1], operands[2]) == CCFPmode
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_5_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
(label_ref (match_operand 3 "" ""))
(clobber (match_scratch:HI 4 "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_6_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
(pc)
(clobber (match_scratch:HI 4 "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
(define_insn "*fp_jcc_7_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "X")])
+ (match_operand 2 "const0_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (match_scratch:HI 4 "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])
- && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
&& SELECT_CC_MODE (GET_CODE (operands[0]),
operands[1], operands[2]) == CCFPmode
- && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
+ && !TARGET_CMOVE"
"#")
;; The order of operands in *fp_jcc_8_387 is forced by combine in
(define_insn "*fp_jcc_8<mode>_387"
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operator 1 "float_operator"
[(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r")])
(match_operand 3 "register_operand" "f,f")])
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 5 "=a,a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[3]))
- && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
+ && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
&& GET_MODE (operands[1]) == GET_MODE (operands[3])
- && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
&& ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
- && ix86_fp_jump_nontrivial_p (swap_condition (GET_CODE (operands[0])))"
+ && !TARGET_CMOVE"
"#")
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "")
(match_operand 2 "nonimmediate_operand" "")])
(match_operand 3 "" "")
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "")
(match_operand 2 "general_operand" "")])
(match_operand 3 "" "")
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operator 1 "float_operator"
[(match_operand:X87MODEI12 2 "memory_operand" "")])
(match_operand 3 "register_operand" "")])
;; %%% Kill this when reload knows how to do it.
(define_split
[(set (pc)
- (if_then_else (match_operator 0 "comparison_operator"
+ (if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operator 1 "float_operator"
[(match_operand:X87MODEI12 2 "register_operand" "")])
(match_operand 3 "register_operand" "")])
}
[(set_attr "type" "call")])
-(define_insn "*call_pop_1"
+(define_insn "*call_pop_1_esp"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
(match_operand:SI 1 "" ""))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
- {
- if (SIBLING_CALL_P (insn))
- return "jmp\t%P0";
- else
- return "call\t%P0";
- }
- if (SIBLING_CALL_P (insn))
- return "jmp\t%A0";
- else
- return "call\t%A0";
+ return "call\t%P0";
+ return "call\t%A0";
+}
+ [(set_attr "type" "call")])
+
+(define_insn "*call_pop_1"
+ [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
+ (match_operand:SI 1 "" ""))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 2 "immediate_operand" "i")))]
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+ if (constant_call_address_operand (operands[0], Pmode))
+ return "call\t%P0";
+ return "call\t%A0";
}
[(set_attr "type" "call")])
+(define_insn "*sibcall_pop_1"
+ [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 1 "" ""))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 2 "immediate_operand" "i,i")))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P0
+ jmp\t%A0"
+ [(set_attr "type" "call")])
+
(define_expand "call"
[(call (match_operand:QI 0 "" "")
(match_operand 1 "" ""))
}
[(set_attr "type" "call")])
-(define_insn "*call_1"
+(define_insn "*call_1_esp"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
(match_operand 1 "" ""))]
- "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
return "call\t%P0";
}
[(set_attr "type" "call")])
-(define_insn "*sibcall_1"
- [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
+(define_insn "*call_1"
+ [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
(match_operand 1 "" ""))]
- "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[0], Pmode))
- return "jmp\t%P0";
- return "jmp\t%A0";
+ return "call\t%P0";
+ return "call\t%A0";
}
[(set_attr "type" "call")])
+(define_insn "*sibcall_1"
+ [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U"))
+ (match_operand 1 "" ""))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P0
+ jmp\t%A0"
+ [(set_attr "type" "call")])
+
(define_insn "*call_1_rex64"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
(match_operand 1 "" ""))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)
&& ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
{
if (constant_call_address_operand (operands[0], Pmode))
}
[(set_attr "type" "call")])
+(define_insn "*call_1_rex64_ms_sysv"
+ [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
+ (match_operand 1 "" ""))
+ (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
+ (clobber (reg:TI XMM6_REG))
+ (clobber (reg:TI XMM7_REG))
+ (clobber (reg:TI XMM8_REG))
+ (clobber (reg:TI XMM9_REG))
+ (clobber (reg:TI XMM10_REG))
+ (clobber (reg:TI XMM11_REG))
+ (clobber (reg:TI XMM12_REG))
+ (clobber (reg:TI XMM13_REG))
+ (clobber (reg:TI XMM14_REG))
+ (clobber (reg:TI XMM15_REG))
+ (clobber (reg:DI SI_REG))
+ (clobber (reg:DI DI_REG))]
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
+{
+ if (constant_call_address_operand (operands[0], Pmode))
+ return "call\t%P0";
+ return "call\t%A0";
+}
+ [(set_attr "type" "call")])
+
(define_insn "*call_1_rex64_large"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rm"))
(match_operand 1 "" ""))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
"call\t%A0"
[(set_attr "type" "call")])
(define_insn "*sibcall_1_rex64"
- [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
+ [(call (mem:QI (match_operand:DI 0 "sibcall_insn_operand" "s,U"))
(match_operand 1 "" ""))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t%P0"
- [(set_attr "type" "call")])
-
-(define_insn "*sibcall_1_rex64_v"
- [(call (mem:QI (reg:DI R11_REG))
- (match_operand 0 "" ""))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t{*%%}r11"
+ "TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P0
+ jmp\t%A0"
[(set_attr "type" "call")])
-
;; Call subroutine, returning value in operand 0
-
(define_expand "call_value_pop"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand:QI 1 "" "")
/* In order to give reg-stack an easier job in validating two
coprocessor registers as containing a possible return value,
simply pretend the untyped call returns a complex long double
- value. */
+ value.
+
+ We can't use SSE_REGPARM_MAX here since callee is unprototyped
+ and should have the default ABI. */
ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
operands[0], const0_rtx,
- GEN_INT ((DEFAULT_ABI == SYSV_ABI ? X86_64_SSE_REGPARM_MAX
- : X64_SSE_REGPARM_MAX)
+ GEN_INT ((TARGET_64BIT
+ ? (ix86_abi == SYSV_ABI
+ ? X86_64_SSE_REGPARM_MAX
+ : X86_64_MS_SSE_REGPARM_MAX)
+ : X86_32_SSE_REGPARM_MAX)
- 1),
NULL, 0);
""
[(set_attr "length" "0")])
+;; Do not schedule instructions accessing memory across this point.
+
+(define_expand "memory_blockage"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
+ ""
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+})
+
+(define_insn "*memory_blockage"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for PIC code
(define_insn "prologue_use"
"reload_completed"
"ret"
[(set_attr "length" "1")
+ (set_attr "atom_unit" "jeu")
(set_attr "length_immediate" "0")
(set_attr "modrm" "0")])
(unspec [(const_int 0)] UNSPEC_REP)]
"reload_completed"
"rep\;ret"
- [(set_attr "length" "1")
+ [(set_attr "length" "2")
+ (set_attr "atom_unit" "jeu")
(set_attr "length_immediate" "0")
(set_attr "prefix_rep" "1")
(set_attr "modrm" "0")])
"reload_completed"
"ret\t%0"
[(set_attr "length" "3")
+ (set_attr "atom_unit" "jeu")
(set_attr "length_immediate" "2")
(set_attr "modrm" "0")])
(set_attr "length_immediate" "0")
(set_attr "modrm" "0")])
-;; Align to 16-byte boundary, max skip in op0. Used to avoid
+(define_insn "vswapmov"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:SI 1 "register_operand" "r"))
+ (unspec_volatile [(const_int 0)] UNSPECV_VSWAPMOV)]
+ ""
+ "movl.s\t{%1, %0|%0, %1}"
+ [(set_attr "length" "2")
+ (set_attr "length_immediate" "0")
+ (set_attr "modrm" "0")])
+
+;; Pad to 16-byte boundary, max skip in op0. Used to avoid
;; branch prediction penalty for the third jump in a 16-byte
;; block on K8.
-(define_insn "align"
+(define_insn "pad"
[(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
""
{
-#ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
- ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
+#ifdef ASM_OUTPUT_MAX_SKIP_PAD
+ ASM_OUTPUT_MAX_SKIP_PAD (asm_out_file, 4, (int)INTVAL (operands[0]));
#else
/* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
The align insn is used to avoid 3 jump instructions in the row to improve
"TARGET_64BIT"
"lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
[(set_attr "type" "lea")
- (set_attr "length" "6")])
+ (set_attr "length_address" "4")
+ (set_attr "mode" "DI")])
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
+ (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))]
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
- (set_attr "length" "6")])
+ (set_attr "length_address" "4")
+ (set_attr "mode" "DI")])
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
+ (unspec:DI
+ [(label_ref (match_operand 1 "" ""))]
+ UNSPEC_SET_GOT_OFFSET))]
"TARGET_64BIT"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
[(set_attr "type" "imov")
- (set_attr "length" "11")])
+ (set_attr "length_immediate" "0")
+ (set_attr "length_address" "8")
+ (set_attr "mode" "DI")])
(define_expand "epilogue"
[(const_int 0)]
tmp = gen_rtx_MEM (Pmode, tmp);
emit_move_insn (tmp, ra);
- if (Pmode == SImode)
- emit_jump_insn (gen_eh_return_si (sa));
- else
- emit_jump_insn (gen_eh_return_di (sa));
+ emit_jump_insn (gen_eh_return_internal ());
emit_barrier ();
DONE;
})
-(define_insn_and_split "eh_return_<mode>"
- [(set (pc)
- (unspec [(match_operand:P 0 "register_operand" "c")]
- UNSPEC_EH_RETURN))]
+(define_insn_and_split "eh_return_internal"
+ [(eh_return)]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
"ix86_expand_epilogue (2); DONE;")
(define_expand "ffs_cmove"
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:SI 1 "register_operand" "")
+ (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "")
(const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "")
+ (set (match_operand:SI 0 "register_operand" "")
(ctz:SI (match_dup 1)))])
(set (match_dup 0) (if_then_else:SI
(eq (reg:CCZ FLAGS_REG) (const_int 0))
"operands[2] = gen_reg_rtx (SImode);")
(define_insn_and_split "*ffs_no_cmove"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "=r")
(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (match_scratch:SI 2 "=&q"))
(clobber (reg:CC FLAGS_REG))]
(ctz:SI (match_dup 1)))]
""
"bsf{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
(define_expand "ffsdi2"
[(set (match_dup 2) (const_int -1))
(parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_operand:DI 1 "register_operand" "")
+ (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "")
(const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "")
+ (set (match_operand:DI 0 "register_operand" "")
(ctz:DI (match_dup 1)))])
(set (match_dup 0) (if_then_else:DI
(eq (reg:CCZ FLAGS_REG) (const_int 0))
(ctz:DI (match_dup 1)))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_insn "ctzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clobber (reg:CC FLAGS_REG))]
""
"bsf{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")])
(define_insn "ctzdi2"
[(set (match_operand:DI 0 "register_operand" "=r")
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsf{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")])
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")])
(define_expand "clzsi2"
[(parallel
(define_insn "clzsi2_abm"
[(set (match_operand:SI 0 "register_operand" "=r")
- (clz:SI (match_operand:SI 1 "nonimmediate_operand" "")))
+ (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_ABM"
"lzcnt{l}\t{%1, %0|%0, %1}"
(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
-(define_insn "*bsr"
+(define_insn "bsr"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (const_int 31)
(clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
""
"bsr{l}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "SI")])
-(define_insn "popcountsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "")))
+(define_insn "popcount<mode>2"
+ [(set (match_operand:SWI248 0 "register_operand" "=r")
+ (popcount:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_POPCNT"
- "popcnt{l}\t{%1, %0|%0, %1}"
+{
+#if TARGET_MACHO
+ return "popcnt\t{%1, %0|%0, %1}";
+#else
+ return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+#endif
+}
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*popcountsi2_cmp"
+(define_insn "*popcount<mode>2_cmp"
[(set (reg FLAGS_REG)
(compare
- (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
+ (popcount:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand" "rm"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=r")
- (popcount:SI (match_dup 1)))]
+ (set (match_operand:SWI248 0 "register_operand" "=r")
+ (popcount:SWI248 (match_dup 1)))]
"TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{l}\t{%1, %0|%0, %1}"
+{
+#if TARGET_MACHO
+ return "popcnt\t{%1, %0|%0, %1}";
+#else
+ return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+#endif
+}
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*popcountsi2_cmp_zext"
[(set (reg FLAGS_REG)
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI(popcount:SI (match_dup 1))))]
"TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{l}\t{%1, %0|%0, %1}"
+{
+#if TARGET_MACHO
+ return "popcnt\t{%1, %0|%0, %1}";
+#else
+ return "popcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+#endif
+}
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
(bswap:SI (match_operand:SI 1 "register_operand" "")))]
""
{
- if (!TARGET_BSWAP)
+ if (!(TARGET_BSWAP || TARGET_MOVBE))
{
rtx x = operands[0];
}
})
+(define_insn "*bswapsi_movbe"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
+ (bswap:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,r")))]
+ "TARGET_MOVBE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "@
+ bswap\t%0
+ movbe\t{%1, %0|%0, %1}
+ movbe\t{%1, %0|%0, %1}"
+ [(set_attr "type" "*,imov,imov")
+ (set_attr "modrm" "*,1,1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_extra" "*,1,1")
+ (set_attr "length" "2,*,*")
+ (set_attr "mode" "SI")])
+
(define_insn "*bswapsi_1"
[(set (match_operand:SI 0 "register_operand" "=r")
(bswap:SI (match_operand:SI 1 "register_operand" "0")))]
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
(bswap:HI (match_dup 0)))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_USE_XCHGB || optimize_size"
+ "TARGET_USE_XCHGB || optimize_function_for_size_p (cfun)"
"@
xchg{b}\t{%h0, %b0|%b0, %h0}
rol{w}\t{$8, %0|%0, 8}"
[(set_attr "length" "4")
(set_attr "mode" "HI")])
-(define_insn "bswapdi2"
+(define_expand "bswapdi2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (bswap:DI (match_operand:DI 1 "register_operand" "")))]
+ "TARGET_64BIT"
+ "")
+
+(define_insn "*bswapdi_movbe"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
+ (bswap:DI (match_operand:DI 1 "nonimmediate_operand" "0,m,r")))]
+ "TARGET_64BIT && TARGET_MOVBE
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "@
+ bswap\t%0
+ movbe\t{%1, %0|%0, %1}
+ movbe\t{%1, %0|%0, %1}"
+ [(set_attr "type" "*,imov,imov")
+ (set_attr "modrm" "*,1,1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_extra" "*,1,1")
+ (set_attr "length" "3,*,*")
+ (set_attr "mode" "DI")])
+
+(define_insn "*bswapdi_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(bswap:DI (match_operand:DI 1 "register_operand" "0")))]
"TARGET_64BIT"
(define_insn "clzdi2_abm"
[(set (match_operand:DI 0 "register_operand" "=r")
- (clz:DI (match_operand:DI 1 "nonimmediate_operand" "")))
+ (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_ABM"
"lzcnt{q}\t{%1, %0|%0, %1}"
(set_attr "type" "bitmanip")
(set_attr "mode" "DI")])
-(define_insn "*bsr_rex64"
+(define_insn "bsr_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (const_int 63)
(clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
"bsr{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
- (set_attr "mode" "DI")])
-
-(define_insn "popcountdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_POPCNT"
- "popcnt{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "DI")])
-
-(define_insn "*popcountdi2_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (popcount:DI (match_dup 1)))]
- "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{q}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "DI")])
(define_expand "clzhi2"
(define_insn "clzhi2_abm"
[(set (match_operand:HI 0 "register_operand" "=r")
- (clz:HI (match_operand:HI 1 "nonimmediate_operand" "")))
+ (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_ABM"
"lzcnt{w}\t{%1, %0|%0, %1}"
(clobber (reg:CC FLAGS_REG))]
""
"bsr{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_0f" "1")
- (set_attr "mode" "HI")])
-
-(define_insn "popcounthi2"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_POPCNT"
- "popcnt{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "HI")])
-
-(define_insn "*popcounthi2_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))
- (const_int 0)))
- (set (match_operand:HI 0 "register_operand" "=r")
- (popcount:HI (match_dup 1)))]
- "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
- "popcnt{w}\t{%1, %0|%0, %1}"
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
(set_attr "mode" "HI")])
(define_expand "paritydi2"
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
UNSPEC_TLS_GD)]
"TARGET_64BIT"
- ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\;.word\t0x6666\;rex64\;call\t%P2"
+ { return ASM_BYTE "0x66\n\tlea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\n" ASM_SHORT "0x6666\n\trex64\n\tcall\t%P2"; }
[(set_attr "type" "multi")
(set_attr "length" "16")])
(clobber (reg:CC FLAGS_REG))])]
"!TARGET_64BIT && TARGET_GNU2_TLS"
{
- operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[3] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
ix86_tls_descriptor_calls_expanded_in_cfun = true;
})
""
[(set (match_dup 0) (match_dup 5))]
{
- operands[5] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[5] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
emit_insn (gen_tls_dynamic_gnu2_32 (operands[5], operands[1], operands[2]));
})
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && TARGET_GNU2_TLS"
{
- operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[2] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
ix86_tls_descriptor_calls_expanded_in_cfun = true;
})
""
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[4] = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : operands[0];
emit_insn (gen_tls_dynamic_gnu2_64 (operands[4], operands[1]));
})
;; Gcc is slightly more smart about handling normal two address instructions
;; so use special patterns for add and mull.
+(define_insn "*fop_<mode>_comm_mixed_avx"
+ [(set (match_operand:MODEF 0 "register_operand" "=f,x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
+ (match_operand:MODEF 2 "nonimmediate_operand" "fm,xm")]))]
+ "AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
+ && COMMUTATIVE_ARITH_P (operands[3])
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (eq_attr "alternative" "1")
+ (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (const_string "ssemul")
+ (const_string "sseadd"))
+ (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop"))))
+ (set_attr "prefix" "orig,maybe_vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*fop_<mode>_comm_mixed"
[(set (match_operand:MODEF 0 "register_operand" "=f,x")
(match_operator:MODEF 3 "binary_fp_operator"
(const_string "fop"))))
(set_attr "mode" "<MODE>")])
+(define_insn "*fop_<mode>_comm_avx"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "%x")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
+ "AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
+ && COMMUTATIVE_ARITH_P (operands[3])
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (const_string "ssemul")
+ (const_string "sseadd")))
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*fop_<mode>_comm_sse"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(match_operator:MODEF 3 "binary_fp_operator"
(match_operator:MODEF 3 "binary_fp_operator"
[(match_operand:MODEF 1 "nonimmediate_operand" "%0")
(match_operand:MODEF 2 "nonimmediate_operand" "fm")]))]
- "TARGET_80387
+ "TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)
&& COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
(const_string "fop")))
(set_attr "mode" "<MODE>")])
+(define_insn "*fop_<mode>_1_mixed_avx"
+ [(set (match_operand:MODEF 0 "register_operand" "=f,f,x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,x")
+ (match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm")]))]
+ "AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
+ && !COMMUTATIVE_ARITH_P (operands[3])
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(and (eq_attr "alternative" "2")
+ (match_operand:MODEF 3 "mult_operator" ""))
+ (const_string "ssemul")
+ (and (eq_attr "alternative" "2")
+ (match_operand:MODEF 3 "div_operator" ""))
+ (const_string "ssediv")
+ (eq_attr "alternative" "2")
+ (const_string "sseadd")
+ (match_operand:MODEF 3 "mult_operator" "")
+ (const_string "fmul")
+ (match_operand:MODEF 3 "div_operator" "")
+ (const_string "fdiv")
+ ]
+ (const_string "fop")))
+ (set_attr "prefix" "orig,orig,maybe_vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*fop_<mode>_1_mixed"
[(set (match_operand:MODEF 0 "register_operand" "=f,f,x")
(match_operator:MODEF 3 "binary_fp_operator"
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
UNSPEC_RCP))]
"TARGET_SSE_MATH"
- "rcpss\t{%1, %0|%0, %1}"
+ "%vrcpss\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "rcp")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "SF")])
+(define_insn "*fop_<mode>_1_avx"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (match_operator:MODEF 3 "binary_fp_operator"
+ [(match_operand:MODEF 1 "register_operand" "x")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
+ "AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
+ && !COMMUTATIVE_ARITH_P (operands[3])"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (const_string "ssemul")
+ (match_operand:MODEF 3 "div_operator" "")
+ (const_string "ssediv")
+ ]
+ (const_string "sseadd")))
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*fop_<mode>_1_sse"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(match_operator:MODEF 3 "binary_fp_operator"
(match_operator:MODEF 3 "binary_fp_operator"
[(match_operand:MODEF 1 "nonimmediate_operand" "0,fm")
(match_operand:MODEF 2 "nonimmediate_operand" "fm,0")]))]
- "TARGET_80387 && !TARGET_SSE_MATH
+ "TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode)
+ && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
&& !COMMUTATIVE_ARITH_P (operands[3])
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(float:MODEF
(match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
(match_operand:MODEF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && !TARGET_SSE_MATH
- && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_size)"
+ "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <X87MODEI12:MODE>mode)
+ && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
+ && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:MODEF 3 "mult_operator" "")
[(match_operand:MODEF 1 "register_operand" "0,0")
(float:MODEF
(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && !TARGET_SSE_MATH
- && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_size)"
+ "TARGET_80387 && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <X87MODEI12:MODE>mode)
+ && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
+ && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:MODEF 3 "mult_operator" "")
[(float_extend:DF
(match_operand:SF 1 "nonimmediate_operand" "fm,0"))
(match_operand:DF 2 "register_operand" "0,f")]))]
- "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
+ "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
[(match_operand:DF 1 "register_operand" "0,f")
(float_extend:DF
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
- "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
(match_operand:SF 1 "register_operand" "0,f"))
(float_extend:DF
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
- "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ "TARGET_80387 && X87_ENABLE_ARITH (DFmode)
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
[(float:XF
(match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
(match_operand:XF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)"
+ "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "")
[(match_operand:XF 1 "register_operand" "0,0")
(float:XF
(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)"
+ "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "")
[(float (match_operand:X87MODEI12 1 "register_operand" ""))
(match_operand 2 "register_operand" "")]))]
"reload_completed
- && X87_FLOAT_MODE_P (GET_MODE (operands[0]))"
+ && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[1]))"
[(const_int 0)]
{
operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
[(match_operand 1 "register_operand" "")
(float (match_operand:X87MODEI12 2 "register_operand" ""))]))]
"reload_completed
- && X87_FLOAT_MODE_P (GET_MODE (operands[0]))"
+ && X87_FLOAT_MODE_P (GET_MODE (operands[0]))
+ && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))"
[(const_int 0)]
{
operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
UNSPEC_RSQRT))]
"TARGET_SSE_MATH"
- "rsqrtss\t{%1, %0|%0, %1}"
+ "%vrsqrtss\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "rcp")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "SF")])
(define_expand "rsqrtsf2"
(sqrt:MODEF
(match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
- "sqrts<ssemodefsuffix>\t{%1, %0|%0, %1}"
+ "%vsqrts<ssemodefsuffix>\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "sqrt")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")
(set_attr "athlon_decode" "*")
(set_attr "amdfam10_decode" "*")])
[(set (match_operand:MODEF 0 "register_operand" "")
(sqrt:MODEF
(match_operand:MODEF 1 "nonimmediate_operand" "")))]
- "TARGET_USE_FANCY_MATH_387
+ "(TARGET_USE_FANCY_MATH_387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
if (<MODE>mode == SFmode
- && TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
+ && TARGET_SSE_MATH && TARGET_RECIP && !optimize_function_for_size_p (cfun)
&& flag_finite_math_only && !flag_trapping_math
&& flag_unsafe_math_optimizations)
{
rtx op1 = gen_reg_rtx (XFmode);
rtx op2 = gen_reg_rtx (XFmode);
- emit_move_insn (op1, operands[1]);
emit_move_insn (op2, operands[2]);
+ emit_move_insn (op1, operands[1]);
emit_label (label);
emit_insn (gen_fpremxf4_i387 (op1, op2, op1, op2));
rtx op1 = gen_reg_rtx (XFmode);
rtx op2 = gen_reg_rtx (XFmode);
- emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_label (label);
emit_insn (gen_fpremxf4_i387 (op1, op2, op1, op2));
rtx op1 = gen_reg_rtx (XFmode);
rtx op2 = gen_reg_rtx (XFmode);
- emit_move_insn (op1, operands[1]);
emit_move_insn (op2, operands[2]);
+ emit_move_insn (op1, operands[1]);
emit_label (label);
emit_insn (gen_fprem1xf4_i387 (op1, op2, op1, op2));
rtx op1 = gen_reg_rtx (XFmode);
rtx op2 = gen_reg_rtx (XFmode);
- emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_label (label);
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode);
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_asinxf2 (op0, op1));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 2; i < 6; i++)
operands[i] = gen_reg_rtx (XFmode);
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_acosxf2 (op0, op1));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
ix86_emit_i387_log1p (operands[0], operands[1]);
DONE;
})
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
+ rtx op0;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]);
[(use (match_operand:SI 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_fxtractxf3_i387 (op0, op1, operands[1]));
emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 3; i < 10; i++)
operands[i] = gen_reg_rtx (XFmode);
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op2 = gen_reg_rtx (XFmode);
emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */
emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_expxf2 (op0, op1));
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op2 = gen_reg_rtx (XFmode);
emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */
emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_exp10xf2 (op0, op1));
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op2 = gen_reg_rtx (XFmode);
emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_exp2xf2 (op0, op1));
(set (match_operand:XF 0 "register_operand" "")
(plus:XF (match_dup 12) (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
int i;
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
for (i = 2; i < 13; i++)
operands[i] = gen_reg_rtx (XFmode);
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_expm1xf2 (op0, op1));
(unspec:XF [(match_dup 1) (match_dup 3)]
UNSPEC_FSCALE_EXP))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
operands[3] = gen_reg_rtx (XFmode);
operands[4] = gen_reg_rtx (XFmode);
})
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
(unspec:XF [(match_dup 1) (match_dup 2)]
UNSPEC_FSCALE_EXP))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
operands[3] = gen_reg_rtx (XFmode);
})
(define_expand "scalb<mode>3"
[(use (match_operand:MODEF 0 "register_operand" ""))
(use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "register_operand" ""))]
+ (use (match_operand:MODEF 2 "general_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = gen_reg_rtx (XFmode);
+ rtx op0, op1, op2;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
+ op2 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
+
+(define_expand "significandxf2"
+ [(parallel [(set (match_operand:XF 0 "register_operand" "")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_XTRACT_FRACT))
+ (set (match_dup 2)
+ (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+{
+ operands[2] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "significand<mode>2"
+ [(use (match_operand:MODEF 0 "register_operand" ""))
+ (use (match_operand:MODEF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
+})
\f
(define_insn "sse4_1_round<mode>2"
(match_operand:SI 2 "const_0_to_15_operand" "n")]
UNSPEC_ROUND))]
"TARGET_ROUND"
- "rounds<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ "%vrounds<ssemodefsuffix>\t{%2, %1, %d0|%d0, %1, %2}"
[(set_attr "type" "ssecvt")
(set_attr "prefix_extra" "1")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "<MODE>")])
(define_insn "rintxf2"
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && !flag_trapping_math)
{
+ if (!TARGET_ROUND && optimize_insn_for_size_p ())
+ FAIL;
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x04)));
[(match_operand:MODEF 0 "register_operand" "")
(match_operand:MODEF 1 "nonimmediate_operand" "")]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math && !flag_rounding_math
- && !optimize_size"
+ && !flag_trapping_math && !flag_rounding_math"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
if (TARGET_64BIT || (<MODE>mode != DFmode))
ix86_expand_round (operand0, operand1);
else
(unspec:DI [(match_operand:XF 1 "register_operand" "")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
(match_operand:MODEF 1 "register_operand" "")]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)
- && !flag_trapping_math && !flag_rounding_math
- && !optimize_size"
+ && !flag_trapping_math && !flag_rounding_math"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
ix86_expand_lround (operand0, operand1);
DONE;
})
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
emit_insn (gen_frndintxf2_floor (operands[0], operands[1]));
DONE;
})
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size)
+ && flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && (TARGET_ROUND || optimize_insn_for_speed_p ()))
{
+ if (!TARGET_ROUND && optimize_insn_for_size_p ())
+ FAIL;
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x01)));
}
else
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_floor (op0, op1));
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
&& flag_unsafe_math_optimizations"
"")
-(define_expand "lfloor<mode>di2"
- [(match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
- && !flag_trapping_math
- && !optimize_size"
-{
- ix86_expand_lfloorceil (operand0, operand1, true);
- DONE;
-})
-
-(define_expand "lfloor<mode>si2"
- [(match_operand:SI 0 "nonimmediate_operand" "")
+(define_expand "lfloor<MODEF:mode><SWI48:mode>2"
+ [(match_operand:SWI48 0 "nonimmediate_operand" "")
(match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (!optimize_size || !TARGET_64BIT)"
+ "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
+ && !flag_trapping_math"
{
+ if (TARGET_64BIT && optimize_insn_for_size_p ())
+ FAIL;
ix86_expand_lfloorceil (operand0, operand1, true);
DONE;
})
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
emit_insn (gen_frndintxf2_ceil (operands[0], operands[1]));
DONE;
})
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size)
+ && flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && (TARGET_ROUND || optimize_insn_for_speed_p ()))
{
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x02)));
+ else if (optimize_insn_for_size_p ())
+ FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
ix86_expand_floorceil (operand0, operand1, false);
else
}
else
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_ceil (op0, op1));
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
&& flag_unsafe_math_optimizations"
"")
-(define_expand "lceil<mode>di2"
- [(match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
- && !flag_trapping_math"
-{
- ix86_expand_lfloorceil (operand0, operand1, false);
- DONE;
-})
-
-(define_expand "lceil<mode>si2"
- [(match_operand:SI 0 "nonimmediate_operand" "")
+(define_expand "lceil<MODEF:mode><SWI48:mode>2"
+ [(match_operand:SWI48 0 "nonimmediate_operand" "")
(match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
+ "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math"
{
ix86_expand_lfloorceil (operand0, operand1, false);
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations && !optimize_size"
+ && flag_unsafe_math_optimizations"
{
+ if (optimize_insn_for_size_p ())
+ FAIL;
emit_insn (gen_frndintxf2_trunc (operands[0], operands[1]));
DONE;
})
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations && !optimize_size)
+ && flag_unsafe_math_optimizations)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))"
+ && !flag_trapping_math)"
{
if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math
- && (TARGET_ROUND || !optimize_size))
+ && (TARGET_ROUND || optimize_insn_for_speed_p ()))
{
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
(operands[0], operands[1], GEN_INT (0x03)));
+ else if (optimize_insn_for_size_p ())
+ FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
ix86_expand_trunc (operand0, operand1);
else
}
else
{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
+ rtx op0, op1;
+
+ if (optimize_insn_for_size_p ())
+ FAIL;
+ op0 = gen_reg_rtx (XFmode);
+ op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_trunc (op0, op1));
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
- && !(reload_completed || reload_in_progress)"
+ && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
"TARGET_USE_FANCY_MATH_387"
"fxam\n\tfnstsw\t%0"
[(set_attr "type" "multi")
+ (set_attr "length" "4")
+ (set_attr "unit" "i387")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn_and_split "fxam<mode>2_i387_with_temp"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (unspec:HI
+ [(match_operand:MODEF 1 "memory_operand" "")]
+ UNSPEC_FXAM_MEM))]
+ "TARGET_USE_FANCY_MATH_387
+ && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(set (match_dup 2)(match_dup 1))
+ (set (match_dup 0)
+ (unspec:HI [(match_dup 2)] UNSPEC_FXAM))]
+{
+ operands[2] = gen_reg_rtx (<MODE>mode);
+
+ MEM_VOLATILE_P (operands[1]) = 1;
+}
+ [(set_attr "type" "multi")
(set_attr "unit" "i387")
(set_attr "mode" "<MODE>")])
+(define_expand "isinfxf2"
+ [(use (match_operand:SI 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && TARGET_C99_FUNCTIONS"
+{
+ rtx mask = GEN_INT (0x45);
+ rtx val = GEN_INT (0x05);
+
+ rtx cond;
+
+ rtx scratch = gen_reg_rtx (HImode);
+ rtx res = gen_reg_rtx (QImode);
+
+ emit_insn (gen_fxamxf2_i387 (scratch, operands[1]));
+
+ emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
+ emit_insn (gen_cmpqi_ext_3 (scratch, val));
+ cond = gen_rtx_fmt_ee (EQ, QImode,
+ gen_rtx_REG (CCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, res, cond));
+ emit_insn (gen_zero_extendqisi2 (operands[0], res));
+ DONE;
+})
+
(define_expand "isinf<mode>2"
[(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:X87MODEF 1 "register_operand" ""))]
+ (use (match_operand:MODEF 1 "nonimmediate_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& TARGET_C99_FUNCTIONS
&& !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
rtx scratch = gen_reg_rtx (HImode);
rtx res = gen_reg_rtx (QImode);
- emit_insn (gen_fxam<mode>2_i387 (scratch, operands[1]));
+ /* Remove excess precision by forcing value through memory. */
+ if (memory_operand (operands[1], VOIDmode))
+ emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, operands[1]));
+ else
+ {
+ enum ix86_stack_slot slot = (virtuals_instantiated
+ ? SLOT_TEMP
+ : SLOT_VIRTUAL);
+ rtx temp = assign_386_stack_local (<MODE>mode, slot);
+
+ emit_move_insn (temp, operands[1]);
+ emit_insn (gen_fxam<mode>2_i387_with_temp (scratch, temp));
+ }
+
emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
emit_insn (gen_cmpqi_ext_3 (scratch, val));
cond = gen_rtx_fmt_ee (EQ, QImode,
operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
/* Can't use this if the user has appropriated esi or edi. */
- if ((TARGET_SINGLE_STRINGOP || optimize_size)
+ if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG]))
{
emit_insn (gen_strmov_singleop (operands[0], operands[1],
(match_operand 4 "" ""))
(set (match_operand 2 "register_operand" "")
(match_operand 5 "" ""))])]
- "TARGET_SINGLE_STRINGOP || optimize_size"
+ ""
"ix86_current_function_needs_cld = 1;")
(define_insn "*strmovdi_rex_1"
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 8)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"movsq"
[(set_attr "type" "str")
(set_attr "mode" "DI")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 4)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT"
"movs{l|d}"
[(set_attr "type" "str")
(set_attr "mode" "SI")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 4)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"movs{l|d}"
[(set_attr "type" "str")
(set_attr "mode" "SI")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 2)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT"
"movsw"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 2)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"movsw"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set (match_operand:SI 1 "register_operand" "=S")
(plus:SI (match_dup 3)
(const_int 1)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT"
"movsb"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set (match_operand:DI 1 "register_operand" "=S")
(plus:DI (match_dup 3)
(const_int 1)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"movsb"
[(set_attr "type" "str")
(set_attr "memory" "both")
+ (set_attr "prefix_rex" "0")
(set_attr "mode" "QI")])
(define_expand "rep_mov"
operands[3] = gen_rtx_PLUS (Pmode, operands[0],
GEN_INT (GET_MODE_SIZE (GET_MODE
(operands[2]))));
- if (TARGET_SINGLE_STRINGOP || optimize_size)
+ if (TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ())
{
emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
operands[3]));
(match_operand 2 "register_operand" ""))
(set (match_operand 0 "register_operand" "")
(match_operand 3 "" ""))])]
- "TARGET_SINGLE_STRINGOP || optimize_size"
+ ""
"ix86_current_function_needs_cld = 1;")
(define_insn "*strsetdi_rex_1"
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 8)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"stosq"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 4)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT"
"stos{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 4)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"stos{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 2)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT"
"stosw"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 2)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"stosw"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:SI 0 "register_operand" "=D")
(plus:SI (match_dup 1)
(const_int 1)))]
- "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "!TARGET_64BIT"
"stosb"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (match_operand:DI 0 "register_operand" "=D")
(plus:DI (match_dup 1)
(const_int 1)))]
- "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
+ "TARGET_64BIT"
"stosb"
[(set_attr "type" "str")
(set_attr "memory" "store")
+ (set_attr "prefix_rex" "0")
(set_attr "mode" "QI")])
(define_expand "rep_stos"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
+ (set_attr "prefix_rex" "0")
(set_attr "mode" "QI")])
(define_expand "cmpstrnsi"
(match_operand:BLK 2 "general_operand" "")))
(use (match_operand 3 "general_operand" ""))
(use (match_operand 4 "immediate_operand" ""))]
- "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
+ ""
{
rtx addr1, addr2, out, outlow, count, countreg, align;
+ if (optimize_insn_for_size_p () && !TARGET_INLINE_ALL_STRINGOPS)
+ FAIL;
+
/* Can't use this if the user has appropriated esi or edi. */
if (fixed_regs[SI_REG] || fixed_regs[DI_REG])
FAIL;
"repz cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
+ (set_attr "prefix_rex" "0")
(set_attr "prefix_rep" "1")])
;; The same, but the count is not known to not be zero.
"repz cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
+ (set_attr "prefix_rex" "0")
(set_attr "prefix_rep" "1")])
(define_expand "strlensi"
"repnz scasb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
+ (set_attr "prefix_rex" "0")
(set_attr "prefix_rep" "1")])
;; Peephole optimizations to clean up after cmpstrn*. This should be
\f
;; Conditional move instructions.
-(define_expand "movdicc"
- [(set (match_operand:DI 0 "register_operand" "")
- (if_then_else:DI (match_operand 1 "comparison_operator" "")
- (match_operand:DI 2 "general_operand" "")
- (match_operand:DI 3 "general_operand" "")))]
- "TARGET_64BIT"
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
-
-(define_insn "x86_movdicc_0_m1_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int -1)
- (const_int 0)))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "sbb{q}\t%0, %0"
- ; Since we don't have the proper number of operands for an alu insn,
- ; fill in all the blanks.
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "memory" "none")
- (set_attr "imm_disp" "false")
- (set_attr "mode" "DI")
- (set_attr "length_immediate" "0")])
-
-(define_insn "*x86_movdicc_0_m1_se"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extract:DI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int 1)
- (const_int 0)))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "sbb{q}\t%0, %0"
- [(set_attr "type" "alu")
- (set_attr "pent_pair" "pu")
- (set_attr "memory" "none")
- (set_attr "imm_disp" "false")
- (set_attr "mode" "DI")
- (set_attr "length_immediate" "0")])
-
-(define_insn "*movdicc_c_rex64"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:DI 2 "nonimmediate_operand" "rm,0")
- (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_64BIT && TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
- "@
- cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
- (set_attr "mode" "DI")])
-
-(define_expand "movsicc"
- [(set (match_operand:SI 0 "register_operand" "")
- (if_then_else:SI (match_operand 1 "comparison_operator" "")
- (match_operand:SI 2 "general_operand" "")
- (match_operand:SI 3 "general_operand" "")))]
+(define_expand "mov<mode>cc"
+ [(set (match_operand:SWIM 0 "register_operand" "")
+ (if_then_else:SWIM (match_operand 1 "comparison_operator" "")
+ (match_operand:SWIM 2 "general_operand" "")
+ (match_operand:SWIM 3 "general_operand" "")))]
""
"if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
;; the register first winds up with `sbbl $0,reg', which is also weird.
;; So just document what we're doing explicitly.
-(define_insn "x86_movsicc_0_m1"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
+(define_insn "x86_mov<mode>cc_0_m1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (if_then_else:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
(const_int -1)
(const_int 0)))
(clobber (reg:CC FLAGS_REG))]
""
- "sbb{l}\t%0, %0"
+ "sbb{<imodesuffix>}\t%0, %0"
; Since we don't have the proper number of operands for an alu insn,
; fill in all the blanks.
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "SI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*x86_movsicc_0_m1_se"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extract:SI (match_operand 1 "ix86_carry_flag_operator" "")
- (const_int 1)
- (const_int 0)))
+(define_insn "*x86_mov<mode>cc_0_m1_se"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (sign_extract:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
+ (const_int 1)
+ (const_int 0)))
(clobber (reg:CC FLAGS_REG))]
""
- "sbb{l}\t%0, %0"
+ "sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "memory" "none")
(set_attr "imm_disp" "false")
- (set_attr "mode" "SI")
+ (set_attr "mode" "<MODE>")
(set_attr "length_immediate" "0")])
-(define_insn "*movsicc_noc"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:SI 2 "nonimmediate_operand" "rm,0")
- (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
- "@
- cmov%O2%C1\t{%2, %0|%0, %2}
- cmov%O2%c1\t{%3, %0|%0, %3}"
- [(set_attr "type" "icmov")
- (set_attr "mode" "SI")])
-
-(define_expand "movhicc"
- [(set (match_operand:HI 0 "register_operand" "")
- (if_then_else:HI (match_operand 1 "comparison_operator" "")
- (match_operand:HI 2 "general_operand" "")
- (match_operand:HI 3 "general_operand" "")))]
- "TARGET_HIMODE_MATH"
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
+(define_insn "*x86_mov<mode>cc_0_m1_neg"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (neg:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")))]
+ ""
+ "sbb{<imodesuffix>}\t%0, %0"
+ [(set_attr "type" "alu")
+ (set_attr "use_carry" "1")
+ (set_attr "pent_pair" "pu")
+ (set_attr "memory" "none")
+ (set_attr "imm_disp" "false")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length_immediate" "0")])
-(define_insn "*movhicc_noc"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand:HI 2 "nonimmediate_operand" "rm,0")
- (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
- "TARGET_CMOVE
- && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
+(define_insn "*mov<mode>cc_noc"
+ [(set (match_operand:SWI248 0 "register_operand" "=r,r")
+ (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)])
+ (match_operand:SWI248 2 "nonimmediate_operand" "rm,0")
+ (match_operand:SWI248 3 "nonimmediate_operand" "0,rm")))]
+ "TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
"@
cmov%O2%C1\t{%2, %0|%0, %2}
cmov%O2%c1\t{%3, %0|%0, %3}"
[(set_attr "type" "icmov")
- (set_attr "mode" "HI")])
-
-(define_expand "movqicc"
- [(set (match_operand:QI 0 "register_operand" "")
- (if_then_else:QI (match_operand 1 "comparison_operator" "")
- (match_operand:QI 2 "general_operand" "")
- (match_operand:QI 3 "general_operand" "")))]
- "TARGET_QIMODE_MATH"
- "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
+ (set_attr "mode" "<MODE>")])
(define_insn_and_split "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
- (const_int 0)])
+ [(match_operand 4 "flags_reg_operand" "")
+ (const_int 0)])
(match_operand:QI 2 "register_operand" "r,0")
(match_operand:QI 3 "register_operand" "0,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
(define_expand "mov<mode>cc"
[(set (match_operand:X87MODEF 0 "register_operand" "")
(if_then_else:X87MODEF
- (match_operand 1 "comparison_operator" "")
+ (match_operand 1 "ix86_fp_comparison_operator" "")
(match_operand:X87MODEF 2 "register_operand" "")
(match_operand:X87MODEF 3 "register_operand" "")))]
"(TARGET_80387 && TARGET_CMOVE)
[(set_attr "type" "fcmov")
(set_attr "mode" "XF")])
-;; All moves in SSE5 pcmov instructions are 128 bits and hence we restrict
-;; the scalar versions to have only XMM registers as operands.
-
-;; SSE5 conditional move
-(define_insn "*sse5_pcmov_<mode>"
- [(set (match_operand:MODEF 0 "register_operand" "=x,x")
- (if_then_else:MODEF
- (match_operand:MODEF 1 "register_operand" "x,0")
- (match_operand:MODEF 2 "register_operand" "0,x")
- (match_operand:MODEF 3 "register_operand" "x,x")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1)"
- "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
- [(set_attr "type" "sse4arg")])
-
;; These versions of the min/max patterns are intentionally ignorant of
;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
;; are undefined in this condition, we're certain this is correct.
+(define_insn "*avx_<code><mode>3"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (smaxmin:MODEF
+ (match_operand:MODEF 1 "nonimmediate_operand" "%x")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
+ "AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+ "v<maxminfprefix>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "sseadd")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "<code><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(smaxmin:MODEF
;; Their operands are not commutative, and thus they may be used in the
;; presence of -0.0 and NaN.
+(define_insn "*avx_ieee_smin<mode>3"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (unspec:MODEF
+ [(match_operand:MODEF 1 "register_operand" "x")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MIN))]
+ "AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+ "vmins<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "sseadd")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*ieee_smin<mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(unspec:MODEF
[(set_attr "type" "sseadd")
(set_attr "mode" "<MODE>")])
+(define_insn "*avx_ieee_smax<mode>3"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (unspec:MODEF
+ [(match_operand:MODEF 1 "register_operand" "0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MAX))]
+ "AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+ "vmaxs<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "sseadd")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*ieee_smax<mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(unspec:MODEF
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "0")
+ (cond [(and (eq_attr "alternative" "0")
+ (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
(const_string "alu")
(match_operand:SI 2 "const0_operand" "")
(const_string "imov")
]
(const_string "lea")))
+ (set (attr "length_immediate")
+ (cond [(eq_attr "type" "imov")
+ (const_string "0")
+ (and (eq_attr "type" "alu")
+ (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ ]
+ (const_string "*")))
(set_attr "mode" "SI")])
(define_insn "pro_epilogue_adjust_stack_rex64"
}
}
[(set (attr "type")
- (cond [(eq_attr "alternative" "0")
+ (cond [(and (eq_attr "alternative" "0")
+ (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
(const_string "alu")
(match_operand:DI 2 "const0_operand" "")
(const_string "imov")
]
(const_string "lea")))
+ (set (attr "length_immediate")
+ (cond [(eq_attr "type" "imov")
+ (const_string "0")
+ (and (eq_attr "type" "alu")
+ (match_operand 2 "const128_operand" ""))
+ (const_string "1")
+ ]
+ (const_string "*")))
(set_attr "mode" "DI")])
(define_insn "pro_epilogue_adjust_stack_rex64_2"
(set_attr "mode" "DI")])
(define_insn "allocate_stack_worker_32"
- [(set (match_operand:SI 0 "register_operand" "+a")
- (unspec_volatile:SI [(match_dup 0)] UNSPECV_STACK_PROBE))
- (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")]
+ UNSPECV_STACK_PROBE))
+ (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_STACK_PROBE"
"call\t___chkstk"
(set_attr "length" "5")])
(define_insn "allocate_stack_worker_64"
- [(set (match_operand:DI 0 "register_operand" "+a")
- (unspec_volatile:DI [(match_dup 0)] UNSPECV_STACK_PROBE))
- (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0")]
+ UNSPECV_STACK_PROBE))
+ (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 1)))
(clobber (reg:DI R10_REG))
(clobber (reg:DI R11_REG))
(clobber (reg:CC FLAGS_REG))]
{
x = copy_to_mode_reg (Pmode, operands[1]);
if (TARGET_64BIT)
- x = gen_allocate_stack_worker_64 (x);
+ x = gen_allocate_stack_worker_64 (x, x);
else
- x = gen_allocate_stack_worker_32 (x);
+ x = gen_allocate_stack_worker_32 (x, x);
emit_insn (x);
}
[(label_ref (match_operand 0 "" ""))]
"!TARGET_64BIT && flag_pic"
{
+#if TARGET_MACHO
if (TARGET_MACHO)
{
rtx xops[3];
rtx label_rtx = gen_label_rtx ();
emit_insn (gen_set_got_labelled (pic_offset_table_rtx, label_rtx));
xops[0] = xops[1] = picreg;
- xops[2] = gen_rtx_CONST (SImode,
- gen_rtx_MINUS (SImode,
- gen_rtx_LABEL_REF (SImode, label_rtx),
- gen_rtx_SYMBOL_REF (SImode, GOT_SYMBOL_NAME)));
+ xops[2] = machopic_gen_offset (gen_rtx_LABEL_REF (SImode, label_rtx));
ix86_expand_binary_operator (MINUS, SImode, xops);
}
else
+#endif
emit_insn (gen_set_got (pic_offset_table_rtx));
DONE;
})
(clobber (reg:CC FLAGS_REG))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& ((GET_MODE (operands[0]) == HImode
- && ((!optimize_size && !TARGET_FAST_PREFIX)
+ && ((optimize_function_for_speed_p (cfun) && !TARGET_FAST_PREFIX)
/* ??? next two lines just !satisfies_constraint_K (...) */
|| !CONST_INT_P (operands[2])
|| satisfies_constraint_K (operands[2])))
|| (GET_MODE (operands[0]) == QImode
- && (TARGET_PROMOTE_QImode || optimize_size)))"
+ && (TARGET_PROMOTE_QImode || optimize_function_for_size_p (cfun))))"
[(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))
(clobber (reg:CC FLAGS_REG))])]
(set (match_operand 1 "register_operand" "")
(and (match_dup 3) (match_dup 4)))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
- && ! optimize_size
+ && optimize_insn_for_speed_p ()
&& ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
|| (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))
/* Ensure that the operand will remain sign-extended immediate. */
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& ! TARGET_FAST_PREFIX
- && ! optimize_size
+ && optimize_insn_for_speed_p ()
/* Ensure that the operand will remain sign-extended immediate. */
&& ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)"
[(set (match_dup 0)
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
- && (TARGET_PROMOTE_QImode || optimize_size)))"
+ && (TARGET_PROMOTE_QImode
+ || optimize_insn_for_size_p ())))"
[(parallel [(set (match_dup 0)
(neg:SI (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
- && (TARGET_PROMOTE_QImode || optimize_size)))"
+ && (TARGET_PROMOTE_QImode
+ || optimize_insn_for_size_p ())))"
[(set (match_dup 0)
(not:SI (match_dup 1)))]
"operands[0] = gen_lowpart (SImode, operands[0]);
"! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
- && (TARGET_PROMOTE_QImode || optimize_size)))"
+ && (TARGET_PROMOTE_QImode
+ || optimize_insn_for_size_p ())))"
[(set (match_dup 0)
(if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
"operands[0] = gen_lowpart (SImode, operands[0]);
[(set (match_operand:SI 0 "push_operand" "")
(match_operand:SI 1 "memory_operand" ""))
(match_scratch:SI 2 "r")]
- "!optimize_size && !TARGET_PUSH_MEMORY
+ "optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
[(set (match_operand:DI 0 "push_operand" "")
(match_operand:DI 1 "memory_operand" ""))
(match_scratch:DI 2 "r")]
- "!optimize_size && !TARGET_PUSH_MEMORY
+ "optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
[(set (match_operand:SF 0 "push_operand" "")
(match_operand:SF 1 "memory_operand" ""))
(match_scratch:SF 2 "r")]
- "!optimize_size && !TARGET_PUSH_MEMORY
+ "optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
[(set (match_operand:HI 0 "push_operand" "")
(match_operand:HI 1 "memory_operand" ""))
(match_scratch:HI 2 "r")]
- "!optimize_size && !TARGET_PUSH_MEMORY
+ "optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
[(set (match_operand:QI 0 "push_operand" "")
(match_operand:QI 1 "memory_operand" ""))
(match_scratch:QI 2 "q")]
- "!optimize_size && !TARGET_PUSH_MEMORY
+ "optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
[(match_scratch:SI 1 "r")
(set (match_operand:SI 0 "memory_operand" "")
(const_int 0))]
- "! optimize_size
+ "optimize_insn_for_speed_p ()
&& ! TARGET_USE_MOV0
&& TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cost->large_insn
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 1) (const_int 0))
(clobber (reg:CC FLAGS_REG))])
[(match_scratch:HI 1 "r")
(set (match_operand:HI 0 "memory_operand" "")
(const_int 0))]
- "! optimize_size
+ "optimize_insn_for_speed_p ()
&& ! TARGET_USE_MOV0
&& TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cost->large_insn
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 2) (const_int 0))
(clobber (reg:CC FLAGS_REG))])
[(match_scratch:QI 1 "q")
(set (match_operand:QI 0 "memory_operand" "")
(const_int 0))]
- "! optimize_size
+ "optimize_insn_for_speed_p ()
&& ! TARGET_USE_MOV0
&& TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cost->large_insn
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 2) (const_int 0))
(clobber (reg:CC FLAGS_REG))])
[(match_scratch:SI 2 "r")
(set (match_operand:SI 0 "memory_operand" "")
(match_operand:SI 1 "immediate_operand" ""))]
- "! optimize_size
+ "optimize_insn_for_speed_p ()
&& TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cost->large_insn"
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
[(match_scratch:HI 2 "r")
(set (match_operand:HI 0 "memory_operand" "")
(match_operand:HI 1 "immediate_operand" ""))]
- "! optimize_size
+ "optimize_insn_for_speed_p ()
&& TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cost->large_insn"
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
[(match_scratch:QI 2 "q")
(set (match_operand:QI 0 "memory_operand" "")
(match_operand:QI 1 "immediate_operand" ""))]
- "! optimize_size
+ "optimize_insn_for_speed_p ()
&& TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cost->large_insn"
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
[(match_operand:SI 2 "memory_operand" "")
(const_int 0)]))
(match_scratch:SI 3 "r")]
- " ! optimize_size && ix86_match_ccmode (insn, CCNOmode)"
+ "optimize_insn_for_speed_p () && ix86_match_ccmode (insn, CCNOmode)"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
"")
(define_peephole2
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
- "!optimize_size
+ "optimize_insn_for_speed_p ()
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], SImode)))
(define_peephole2
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
- "!optimize_size
+ "optimize_insn_for_speed_p ()
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], HImode)))
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "!optimize_size
+ "optimize_insn_for_speed_p ()
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], QImode)))
[(match_dup 0)
(match_operand:SI 1 "memory_operand" "")]))
(clobber (reg:CC FLAGS_REG))])]
- "! optimize_size && ! TARGET_READ_MODIFY"
+ "optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY"
[(set (match_dup 2) (match_dup 1))
(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
[(match_operand:SI 1 "memory_operand" "")
(match_dup 0)]))
(clobber (reg:CC FLAGS_REG))])]
- "! optimize_size && ! TARGET_READ_MODIFY"
+ "optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY"
[(set (match_dup 2) (match_dup 1))
(parallel [(set (match_dup 0)
(match_op_dup 3 [(match_dup 2) (match_dup 0)]))
(clobber (reg:CC FLAGS_REG))])]
"")
+;; Prefer Load+RegOp to Mov+MemOp. Watch out for cases when the memory address
+;; refers to the destination of the load!
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand" "")
+ (match_operand:SI 1 "register_operand" ""))
+ (parallel [(set (match_dup 0)
+ (match_operator:SI 3 "commutative_operator"
+ [(match_dup 0)
+ (match_operand:SI 2 "memory_operand" "")]))
+ (clobber (reg:CC FLAGS_REG))])]
+ "REGNO (operands[0]) != REGNO (operands[1])
+ && GENERAL_REGNO_P (REGNO (operands[0]))
+ && GENERAL_REGNO_P (REGNO (operands[1]))"
+ [(set (match_dup 0) (match_dup 4))
+ (parallel [(set (match_dup 0)
+ (match_op_dup 3 [(match_dup 0) (match_dup 1)]))
+ (clobber (reg:CC FLAGS_REG))])]
+ "operands[4] = replace_rtx (operands[2], operands[0], operands[1]);")
+
+(define_peephole2
+ [(set (match_operand 0 "register_operand" "")
+ (match_operand 1 "register_operand" ""))
+ (set (match_dup 0)
+ (match_operator 3 "commutative_operator"
+ [(match_dup 0)
+ (match_operand 2 "memory_operand" "")]))]
+ "REGNO (operands[0]) != REGNO (operands[1])
+ && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
+ || (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 0)
+ (match_op_dup 3 [(match_dup 0) (match_dup 1)]))]
+ "")
+
; Don't do logical operations with memory outputs
;
; These two don't make sense for PPro/PII -- we're expanding a 4-uop
[(match_dup 0)
(match_operand:SI 1 "nonmemory_operand" "")]))
(clobber (reg:CC FLAGS_REG))])]
- "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
+ "optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY_WRITE"
[(set (match_dup 2) (match_dup 0))
(parallel [(set (match_dup 2)
(match_op_dup 3 [(match_dup 2) (match_dup 1)]))
[(match_operand:SI 1 "nonmemory_operand" "")
(match_dup 0)]))
(clobber (reg:CC FLAGS_REG))])]
- "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
+ "optimize_insn_for_speed_p () && ! TARGET_READ_MODIFY_WRITE"
[(set (match_dup 2) (match_dup 0))
(parallel [(set (match_dup 2)
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))
[(set (match_operand 0 "register_operand" "")
(match_operand 1 "const0_operand" ""))]
"GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
- && (! TARGET_USE_MOV0 || optimize_size)
+ && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
&& GENERAL_REG_P (operands[0])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int 0))
(const_int 0))]
"(GET_MODE (operands[0]) == QImode
|| GET_MODE (operands[0]) == HImode)
- && (! TARGET_USE_MOV0 || optimize_size)
+ && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
(clobber (reg:CC FLAGS_REG))])])
"(GET_MODE (operands[0]) == HImode
|| GET_MODE (operands[0]) == SImode
|| (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
- && (optimize_size || TARGET_MOVE_M1_VIA_OR)
+ && (optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int -1))
(clobber (reg:CC FLAGS_REG))])]
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_SUB_ESP_4"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
(parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
(clobber (mem:BLK (scratch)))])])
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_SUB_ESP_8"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
(parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
[(match_scratch:SI 0 "r")
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
(clobber (reg:CC FLAGS_REG))])]
- "optimize_size || !TARGET_SUB_ESP_4"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
[(match_scratch:SI 0 "r")
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
(clobber (reg:CC FLAGS_REG))])]
- "optimize_size || !TARGET_SUB_ESP_8"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_ADD_ESP_4"
+ "optimize_insn_for_size_p () || !TARGET_ADD_ESP_4"
[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (mem:BLK (scratch)))])]
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_ADD_ESP_8"
+ "optimize_insn_for_size_p () || !TARGET_ADD_ESP_8"
[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (mem:BLK (scratch)))])
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size"
+ "optimize_insn_for_size_p ()"
[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
(clobber (mem:BLK (scratch)))])
[(match_scratch:SI 0 "r")
(parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
(clobber (reg:CC FLAGS_REG))])]
- "optimize_size"
+ "optimize_insn_for_size_p ()"
[(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
"")
\f
;; Convert compares with 1 to shorter inc/dec operations when CF is not
-;; required and register dies. Similarly for 128 to plus -128.
+;; required and register dies. Similarly for 128 to -128.
(define_peephole2
[(set (match_operand 0 "flags_reg_operand" "")
(match_operator 1 "compare_operator"
[(match_operand 2 "register_operand" "")
(match_operand 3 "const_int_operand" "")]))]
- "(INTVAL (operands[3]) == -1
- || INTVAL (operands[3]) == 1
- || INTVAL (operands[3]) == 128)
+ "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ())
+ && incdec_operand (operands[3], GET_MODE (operands[3])))
+ || (!TARGET_FUSE_CMP_AND_BRANCH
+ && INTVAL (operands[3]) == 128))
&& ix86_match_ccmode (insn, CCGCmode)
&& peep2_reg_dead_p (1, operands[2])"
[(parallel [(set (match_dup 0)
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_SUB_ESP_4"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
(parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
(clobber (mem:BLK (scratch)))])])
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_SUB_ESP_8"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
(parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
[(match_scratch:DI 0 "r")
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
(clobber (reg:CC FLAGS_REG))])]
- "optimize_size || !TARGET_SUB_ESP_4"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_4"
[(clobber (match_dup 0))
(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
[(match_scratch:DI 0 "r")
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
(clobber (reg:CC FLAGS_REG))])]
- "optimize_size || !TARGET_SUB_ESP_8"
+ "optimize_insn_for_size_p () || !TARGET_SUB_ESP_8"
[(clobber (match_dup 0))
(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_ADD_ESP_4"
+ "optimize_insn_for_size_p () || !TARGET_ADD_ESP_4"
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (mem:BLK (scratch)))])]
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size || !TARGET_ADD_ESP_8"
+ "optimize_insn_for_size_p () || !TARGET_ADD_ESP_8"
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (mem:BLK (scratch)))])
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
- "optimize_size"
+ "optimize_insn_for_size_p ()"
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
(clobber (mem:BLK (scratch)))])
[(match_scratch:DI 0 "r")
(parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
(clobber (reg:CC FLAGS_REG))])]
- "optimize_size"
+ "optimize_insn_for_size_p ()"
[(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "!optimize_size
+ "optimize_insn_for_speed_p ()
&& (INTVAL (operands[2]) == 3
|| INTVAL (operands[2]) == 5
|| INTVAL (operands[2]) == 9)"
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT
- && !optimize_size
+ && optimize_insn_for_speed_p ()
&& (INTVAL (operands[2]) == 3
|| INTVAL (operands[2]) == 5
|| INTVAL (operands[2]) == 9)"
(mult:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
+ "TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
+ "TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
+ "TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:DI 3 "r")]
- "TARGET_SLOW_IMUL_IMM8 && !optimize_size
+ "TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()
&& satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:SI 3 "r")]
- "TARGET_SLOW_IMUL_IMM8 && !optimize_size
+ "TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()
&& satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
(match_operand:HI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:HI 3 "r")]
- "TARGET_SLOW_IMUL_IMM8 && !optimize_size"
+ "TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]
}
[(set_attr "type" "callv")])
-(define_insn "*call_value_pop_1"
+(define_insn "*call_value_pop_1_esp"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
(match_operand:SI 2 "" "")))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
- {
- if (SIBLING_CALL_P (insn))
- return "jmp\t%P1";
- else
- return "call\t%P1";
- }
- if (SIBLING_CALL_P (insn))
- return "jmp\t%A1";
- else
- return "call\t%A1";
+ return "call\t%P1";
+ return "call\t%A1";
+}
+ [(set_attr "type" "callv")])
+
+(define_insn "*call_value_pop_1"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
+ (match_operand:SI 2 "" "")))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i")))]
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
+{
+ if (constant_call_address_operand (operands[1], Pmode))
+ return "call\t%P1";
+ return "call\t%A1";
}
[(set_attr "type" "callv")])
+(define_insn "*sibcall_value_pop_1"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 2 "" "")))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i,i")))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P1
+ jmp\t%A1"
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_0"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
}
[(set_attr "type" "callv")])
-(define_insn "*call_value_1"
+(define_insn "*call_value_0_rex64_ms_sysv"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
+ (match_operand:DI 2 "const_int_operand" "")))
+ (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
+ (clobber (reg:TI XMM6_REG))
+ (clobber (reg:TI XMM7_REG))
+ (clobber (reg:TI XMM8_REG))
+ (clobber (reg:TI XMM9_REG))
+ (clobber (reg:TI XMM10_REG))
+ (clobber (reg:TI XMM11_REG))
+ (clobber (reg:TI XMM12_REG))
+ (clobber (reg:TI XMM13_REG))
+ (clobber (reg:TI XMM14_REG))
+ (clobber (reg:TI XMM15_REG))
+ (clobber (reg:DI SI_REG))
+ (clobber (reg:DI DI_REG))]
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
+{
+ if (SIBLING_CALL_P (insn))
+ return "jmp\t%P1";
+ else
+ return "call\t%P1";
+}
+ [(set_attr "type" "callv")])
+
+(define_insn "*call_value_1_esp"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
(match_operand:SI 2 "" "")))]
- "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
return "call\t%P1";
}
[(set_attr "type" "callv")])
-(define_insn "*sibcall_value_1"
+(define_insn "*call_value_1"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
+ (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
(match_operand:SI 2 "" "")))]
- "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
{
if (constant_call_address_operand (operands[1], Pmode))
- return "jmp\t%P1";
- return "jmp\t%A1";
+ return "call\t%P1";
+ return "call\t%A1";
}
[(set_attr "type" "callv")])
+(define_insn "*sibcall_value_1"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 2 "" "")))]
+ "!TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P1
+ jmp\t%A1"
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_1_rex64"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
(match_operand:DI 2 "" "")))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)
&& ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
{
if (constant_call_address_operand (operands[1], Pmode))
}
[(set_attr "type" "callv")])
+(define_insn "*call_value_1_rex64_ms_sysv"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
+ (match_operand:DI 2 "" "")))
+ (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
+ (clobber (reg:TI XMM6_REG))
+ (clobber (reg:TI XMM7_REG))
+ (clobber (reg:TI XMM8_REG))
+ (clobber (reg:TI XMM9_REG))
+ (clobber (reg:TI XMM10_REG))
+ (clobber (reg:TI XMM11_REG))
+ (clobber (reg:TI XMM12_REG))
+ (clobber (reg:TI XMM13_REG))
+ (clobber (reg:TI XMM14_REG))
+ (clobber (reg:TI XMM15_REG))
+ (clobber (reg:DI SI_REG))
+ (clobber (reg:DI DI_REG))]
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
+{
+ if (constant_call_address_operand (operands[1], Pmode))
+ return "call\t%P1";
+ return "call\t%A1";
+}
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_1_rex64_large"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rm"))
(match_operand:DI 2 "" "")))]
- "!SIBLING_CALL_P (insn) && TARGET_64BIT"
+ "TARGET_64BIT && !SIBLING_CALL_P (insn)"
"call\t%A1"
[(set_attr "type" "callv")])
(define_insn "*sibcall_value_1_rex64"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
+ (call (mem:QI (match_operand:DI 1 "sibcall_insn_operand" "s,U"))
(match_operand:DI 2 "" "")))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t%P1"
- [(set_attr "type" "callv")])
-
-(define_insn "*sibcall_value_1_rex64_v"
- [(set (match_operand 0 "" "")
- (call (mem:QI (reg:DI R11_REG))
- (match_operand:DI 1 "" "")))]
- "SIBLING_CALL_P (insn) && TARGET_64BIT"
- "jmp\t{*%%}r11"
+ "TARGET_64BIT && SIBLING_CALL_P (insn)"
+ "@
+ jmp\t%P1
+ jmp\t%A1"
[(set_attr "type" "callv")])
\f
;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
(define_expand "sse_prologue_save"
[(parallel [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(reg:DI 21)
- (reg:DI 22)
- (reg:DI 23)
- (reg:DI 24)
- (reg:DI 25)
- (reg:DI 26)
- (reg:DI 27)
- (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+ (unspec:BLK [(reg:DI XMM0_REG)
+ (reg:DI XMM1_REG)
+ (reg:DI XMM2_REG)
+ (reg:DI XMM3_REG)
+ (reg:DI XMM4_REG)
+ (reg:DI XMM5_REG)
+ (reg:DI XMM6_REG)
+ (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" ""))
(use (match_operand:DI 2 "immediate_operand" ""))
(use (label_ref:DI (match_operand 3 "" "")))])]
(define_insn "*sse_prologue_save_insn"
[(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
(match_operand:DI 4 "const_int_operand" "n")))
- (unspec:BLK [(reg:DI 21)
- (reg:DI 22)
- (reg:DI 23)
- (reg:DI 24)
- (reg:DI 25)
- (reg:DI 26)
- (reg:DI 27)
- (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+ (unspec:BLK [(reg:DI XMM0_REG)
+ (reg:DI XMM1_REG)
+ (reg:DI XMM2_REG)
+ (reg:DI XMM3_REG)
+ (reg:DI XMM4_REG)
+ (reg:DI XMM5_REG)
+ (reg:DI XMM6_REG)
+ (reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
(use (match_operand:DI 1 "register_operand" "r"))
(use (match_operand:DI 2 "const_int_operand" "i"))
(use (label_ref:DI (match_operand 3 "" "X")))]
int i;
operands[0] = gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode, operands[0], operands[4]));
+ /* VEX instruction with a REX prefix will #UD. */
+ if (TARGET_AVX && GET_CODE (XEXP (operands[0], 0)) != PLUS)
+ gcc_unreachable ();
+
output_asm_insn ("jmp\t%A1", operands);
for (i = X86_64_SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
{
PUT_MODE (operands[4], TImode);
if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
output_asm_insn ("rex", operands);
- output_asm_insn ("movaps\t{%5, %4|%4, %5}", operands);
+ output_asm_insn ("%vmovaps\t{%5, %4|%4, %5}", operands);
}
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (operands[3]));
[(set_attr "type" "other")
(set_attr "length_immediate" "0")
(set_attr "length_address" "0")
- (set_attr "length" "34")
+ (set (attr "length")
+ (if_then_else
+ (eq (symbol_ref "TARGET_AVX") (const_int 0))
+ (const_string "34")
+ (const_string "42")))
(set_attr "memory" "store")
(set_attr "modrm" "0")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "DI")])
(define_expand "prefetch"
return patterns[locality];
}
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "prefetch")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_sse_rex"
return patterns[locality];
}
[(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "prefetch")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow"
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_insn "*prefetch_3dnow_rex"
return "prefetchw\t%a0";
}
[(set_attr "type" "mmx")
+ (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
(set_attr "memory" "none")])
(define_expand "stack_protect_set"
""
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
- ix86_compare_op0 = operands[0];
- ix86_compare_op1 = operands[1];
- ix86_compare_emitted = flags;
#ifdef TARGET_THREAD_SSP_OFFSET
if (TARGET_64BIT)
else
emit_insn (gen_stack_protect_test_si (flags, operands[0], operands[1]));
#endif
- emit_jump_insn (gen_beq (operands[2]));
+
+ emit_jump_insn (gen_cbranchcc4 (gen_rtx_EQ (VOIDmode, flags, const0_rtx),
+ flags, const0_rtx, operands[2]));
DONE;
})
[(match_operand:SI 1 "register_operand" "0")
(match_operand:CRC32MODE 2 "nonimmediate_operand" "<crc32modeconstraint>")]
UNSPEC_CRC32))]
- "TARGET_SSE4_2"
+ "TARGET_SSE4_2 || TARGET_CRC32"
"crc32<crc32modesuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog1")
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
+ (set (attr "prefix_data16")
+ (if_then_else (match_operand:HI 2 "" "")
+ (const_string "1")
+ (const_string "*")))
+ (set (attr "prefix_rex")
+ (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
+ (const_string "1")
+ (const_string "*")))
(set_attr "mode" "SI")])
(define_insn "sse4_2_crc32di"
[(match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "nonimmediate_operand" "rm")]
UNSPEC_CRC32))]
- "TARGET_SSE4_2 && TARGET_64BIT"
+ "TARGET_64BIT && (TARGET_SSE4_2 || TARGET_CRC32)"
"crc32q\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog1")
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
(set_attr "mode" "DI")])
+(define_expand "rdpmc"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:SI 1 "register_operand" "")]
+ ""
+{
+ rtx reg = gen_reg_rtx (DImode);
+ rtx si;
+
+ /* Force operand 1 into ECX. */
+ rtx ecx = gen_rtx_REG (SImode, CX_REG);
+ emit_insn (gen_rtx_SET (VOIDmode, ecx, operands[1]));
+ si = gen_rtx_UNSPEC_VOLATILE (DImode, gen_rtvec (1, ecx),
+ UNSPECV_RDPMC);
+
+ if (TARGET_64BIT)
+ {
+ rtvec vec = rtvec_alloc (2);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ rtx upper = gen_reg_rtx (DImode);
+ rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDPMC);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, si);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di);
+ emit_insn (load);
+ upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
+ NULL, 1, OPTAB_DIRECT);
+ reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1,
+ OPTAB_DIRECT);
+ }
+ else
+ emit_insn (gen_rtx_SET (VOIDmode, reg, si));
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg));
+ DONE;
+})
+
+(define_insn "*rdpmc"
+ [(set (match_operand:DI 0 "register_operand" "=A")
+ (unspec_volatile:DI [(match_operand:SI 1 "register_operand" "c")]
+ UNSPECV_RDPMC))]
+ "!TARGET_64BIT"
+ "rdpmc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_insn "*rdpmc_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(match_operand:SI 2 "register_operand" "c")]
+ UNSPECV_RDPMC))
+ (set (match_operand:DI 1 "register_operand" "=d")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDPMC))]
+ "TARGET_64BIT"
+ "rdpmc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_expand "rdtsc"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
+ ""
+{
+ if (TARGET_64BIT)
+ {
+ rtvec vec = rtvec_alloc (2);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ rtx upper = gen_reg_rtx (DImode);
+ rtx lower = gen_reg_rtx (DImode);
+ rtx src = gen_rtx_UNSPEC_VOLATILE (DImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDTSC);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, lower, src);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, src);
+ emit_insn (load);
+ upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
+ NULL, 1, OPTAB_DIRECT);
+ lower = expand_simple_binop (DImode, IOR, lower, upper, lower, 1,
+ OPTAB_DIRECT);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], lower));
+ DONE;
+ }
+})
+
+(define_insn "*rdtsc"
+ [(set (match_operand:DI 0 "register_operand" "=A")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
+ "!TARGET_64BIT"
+ "rdtsc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_insn "*rdtsc_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))
+ (set (match_operand:DI 1 "register_operand" "=d")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
+ "TARGET_64BIT"
+ "rdtsc"
+ [(set_attr "type" "other")
+ (set_attr "length" "2")])
+
+(define_expand "rdtscp"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:SI 1 "memory_operand" "")]
+ ""
+{
+ rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDTSCP);
+ rtx si = gen_rtx_UNSPEC_VOLATILE (SImode,
+ gen_rtvec (1, const0_rtx),
+ UNSPECV_RDTSCP);
+ rtx reg = gen_reg_rtx (DImode);
+ rtx tmp = gen_reg_rtx (SImode);
+
+ if (TARGET_64BIT)
+ {
+ rtvec vec = rtvec_alloc (3);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ rtx upper = gen_reg_rtx (DImode);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, upper, di);
+ RTVEC_ELT (vec, 2) = gen_rtx_SET (VOIDmode, tmp, si);
+ emit_insn (load);
+ upper = expand_simple_binop (DImode, ASHIFT, upper, GEN_INT (32),
+ NULL, 1, OPTAB_DIRECT);
+ reg = expand_simple_binop (DImode, IOR, reg, upper, reg, 1,
+ OPTAB_DIRECT);
+ }
+ else
+ {
+ rtvec vec = rtvec_alloc (2);
+ rtx load = gen_rtx_PARALLEL (VOIDmode, vec);
+ RTVEC_ELT (vec, 0) = gen_rtx_SET (VOIDmode, reg, di);
+ RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, tmp, si);
+ emit_insn (load);
+ }
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], reg));
+ emit_insn (gen_rtx_SET (VOIDmode, operands[1], tmp));
+ DONE;
+})
+
+(define_insn "*rdtscp"
+ [(set (match_operand:DI 0 "register_operand" "=A")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
+ (set (match_operand:SI 1 "register_operand" "=c")
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_RDTSCP))]
+ "!TARGET_64BIT"
+ "rdtscp"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
+
+(define_insn "*rdtscp_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
+ (set (match_operand:DI 1 "register_operand" "=d")
+ (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSCP))
+ (set (match_operand:SI 2 "register_operand" "=c")
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_RDTSCP))]
+ "TARGET_64BIT"
+ "rdtscp"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
+
(include "mmx.md")
(include "sse.md")
(include "sync.md")
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