;;
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
-;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
-;; constraint letters.
-;;
;; The special asm out single letter directives following a '%' are:
;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
;; operands[1].
;; SSE asm suffix for floating point modes
(define_mode_attr ssemodefsuffix [(SF "s") (DF "d")])
+;; SSE vector mode corresponding to a scalar mode
+(define_mode_attr ssevecmode
+ [(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])
\f
;; Scheduling descriptions
(match_operand:DI 1 "const0_operand" "n,n")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"@
- test{q}\t{%0, %0|%0, %0}
+ test{q}\t%0, %0
cmp{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(match_operand:SI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
- test{l}\t{%0, %0|%0, %0}
+ test{l}\t%0, %0
cmp{l}\t{%1, %0|%0, %1}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(match_operand:HI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
- test{w}\t{%0, %0|%0, %0}
+ test{w}\t%0, %0
cmp{w}\t{%1, %0|%0, %1}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(match_operand:QI 1 "const0_operand" "n,n")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
- test{b}\t{%0, %0|%0, %0}
+ test{b}\t%0, %0
cmp{b}\t{$0, %0|%0, 0}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(match_operand:SI 1 "const0_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
- "xor{l}\t{%0, %0|%0, %0}"
+ "xor{l}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "SI")
(set_attr "length_immediate" "0")])
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
- "xor{w}\t{%0, %0|%0, %0}"
+ "xor{w}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "HI")
(set_attr "length_immediate" "0")])
(match_operand:QI 1 "const0_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
- "xor{b}\t{%0, %0|%0, %0}"
+ "xor{b}\t%0, %0"
[(set_attr "type" "alu1")
(set_attr "mode" "QI")
(set_attr "length_immediate" "0")])
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
&& reload_completed"
- "xor{l}\t{%k0, %k0|%k0, %k0}"
+ "xor{l}\t%k0, %k0";
[(set_attr "type" "alu1")
(set_attr "mode" "SI")
(set_attr "length_immediate" "0")])
}
})
+;; Unsigned conversion to SImode.
+
+(define_expand "fixuns_trunc<mode>si2"
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (unsigned_fix:SI
+ (match_operand:SSEMODEF 1 "nonimmediate_operand" "")))
+ (use (match_dup 2))
+ (clobber (match_scratch:<ssevecmode> 3 ""))
+ (clobber (match_scratch:<ssevecmode> 4 ""))])]
+ "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
+{
+ enum machine_mode mode = <MODE>mode;
+ enum machine_mode vecmode = <ssevecmode>mode;
+ REAL_VALUE_TYPE TWO31r;
+ rtx two31;
+
+ real_ldexp (&TWO31r, &dconst1, 31);
+ two31 = const_double_from_real_value (TWO31r, mode);
+ two31 = ix86_build_const_vector (mode, true, two31);
+ operands[2] = force_reg (vecmode, two31);
+})
+
+(define_insn_and_split "*fixuns_trunc<mode>_1"
+ [(set (match_operand:SI 0 "register_operand" "=&x,&x")
+ (unsigned_fix:SI
+ (match_operand:SSEMODEF 3 "nonimmediate_operand" "xm,xm")))
+ (use (match_operand:<ssevecmode> 4 "nonimmediate_operand" "m,x"))
+ (clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
+ (clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
+ "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ ix86_split_convert_uns_si_sse (operands);
+ DONE;
+})
+
+;; Unsigned conversion to HImode.
+;; Without these patterns, we'll try the unsigned SI conversion which
+;; is complex for SSE, rather than the signed SI conversion, which isn't.
+
+(define_expand "fixuns_truncsfhi2"
+ [(set (match_dup 2)
+ (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))
+ (set (match_operand:HI 0 "nonimmediate_operand" "")
+ (subreg:HI (match_dup 2) 0))]
+ "TARGET_SSE_MATH"
+ "operands[2] = gen_reg_rtx (SImode);")
+
+(define_expand "fixuns_truncdfhi2"
+ [(set (match_dup 2)
+ (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))
+ (set (match_operand:HI 0 "nonimmediate_operand" "")
+ (subreg:HI (match_dup 2) 0))]
+ "TARGET_SSE_MATH && TARGET_SSE2"
+ "operands[2] = gen_reg_rtx (SImode);")
+
;; When SSE is available, it is always faster to use it!
(define_insn "fix_truncsfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(define_expand "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
- "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
- "")
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
+{
+ if (!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)
+ {
+ ix86_expand_convert_sign_didf_sse (operands[0], operands[1]);
+ DONE;
+ }
+})
(define_insn "*floatdidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
(define_expand "floatunssisf2"
[(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:SI 1 "register_operand" ""))]
- "!TARGET_64BIT && TARGET_SSE_MATH"
- "x86_emit_floatuns (operands); DONE;")
+ (use (match_operand:SI 1 "nonimmediate_operand" ""))]
+ "!TARGET_64BIT"
+{
+ if (TARGET_SSE_MATH && TARGET_SSE2)
+ ix86_expand_convert_uns_sisf_sse (operands[0], operands[1]);
+ else
+ x86_emit_floatuns (operands);
+ DONE;
+})
+
+(define_expand "floatunssidf2"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:SI 1 "nonimmediate_operand" ""))]
+ "!TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE2"
+ "ix86_expand_convert_uns_sidf_sse (operands[0], operands[1]); DONE;")
(define_expand "floatunsdisf2"
[(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:DI 1 "register_operand" ""))]
+ (use (match_operand:DI 1 "nonimmediate_operand" ""))]
"TARGET_64BIT && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
[(use (match_operand:DF 0 "register_operand" ""))
- (use (match_operand:DI 1 "register_operand" ""))]
- "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
- "x86_emit_floatuns (operands); DONE;")
+ (use (match_operand:DI 1 "nonimmediate_operand" ""))]
+ "TARGET_SSE_MATH && TARGET_SSE2
+ && (TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)"
+{
+ if (TARGET_64BIT)
+ x86_emit_floatuns (operands);
+ else
+ ix86_expand_convert_uns_didf_sse (operands[0], operands[1]);
+ DONE;
+})
\f
;; SSE extract/set expanders
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- return "add{q}\t{%0, %0|%0, %0}";
+ return "add{q}\t%0, %0";
case TYPE_LEA:
gcc_assert (CONST_INT_P (operands[2]));
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{q}\t{%0, %0|%0, %0}";
+ return "add{q}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{q}\t{%0, %0|%0, %0}";
+ return "add{q}\t%0, %0";
default:
if (REG_P (operands[2]))
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- return "add{l}\t{%0, %0|%0, %0}";
+ return "add{l}\t%0, %0";
case TYPE_LEA:
return "#";
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t{%k0, %k0|%k0, %k0}";
+ return "add{l}\t%k0, %k0";
case TYPE_LEA:
return "#";
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t{%0, %0|%0, %0}";
+ return "add{l}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t{%0, %0|%0, %0}";
+ return "add{l}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t{%k0, %k0|%k0, %k0}";
+ return "add{l}\t%k0, %k0";
default:
if (REG_P (operands[2]))
return "#";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t{%0, %0|%0, %0}";
+ return "add{w}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t{%0, %0|%0, %0}";
+ return "add{w}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t{%0, %0|%0, %0}";
+ return "add{w}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t{%0, %0|%0, %0}";
+ return "add{w}\t%0, %0";
default:
if (REG_P (operands[2]))
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
- return "add{l}\t{%k0, %k0|%k0, %k0}";
+ return "add{l}\t%k0, %k0";
else
- return "add{b}\t{%0, %0|%0, %0}";
+ return "add{b}\t%0, %0";
default:
if (REG_P (operands[2]))
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
- return "add{l}\t{%k0, %k0|%k0, %k0}";
+ return "add{l}\t%k0, %k0";
else
- return "add{b}\t{%0, %0|%0, %0}";
+ return "add{b}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{b}\t{%0, %0|%0, %0}";
+ return "add{b}\t%0, %0";
default:
if (REG_P (operands[2]))
{
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
- return "add{b}\t{%0, %0|%0, %0}";
+ return "add{b}\t%0, %0";
default:
if (REG_P (operands[2]))
[(set_attr "type" "rotate")
(set_attr "mode" "HI")])
+(define_split
+ [(set (match_operand:HI 0 "register_operand" "")
+ (rotate:HI (match_dup 0) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))]
+ "reload_completed"
+ [(parallel [(set (strict_low_part (match_dup 0))
+ (bswap:HI (match_dup 0)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "")
+
(define_expand "rotlqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
(const_string "2")
(const_string "*")))])
-(define_insn "*rotrhi3"
+(define_insn "*rotrhi3_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "I,c")))
[(set_attr "type" "rotate")
(set_attr "mode" "HI")])
+(define_split
+ [(set (match_operand:HI 0 "register_operand" "")
+ (rotatert:HI (match_dup 0) (const_int 8)))
+ (clobber (reg:CC FLAGS_REG))]
+ "reload_completed"
+ [(parallel [(set (strict_low_part (match_dup 0))
+ (bswap:HI (match_dup 0)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "")
+
(define_expand "rotrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
-(define_insn "bswapsi2"
+(define_expand "bswapsi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (bswap:SI (match_operand:SI 1 "register_operand" "")))]
+ ""
+{
+ if (!TARGET_BSWAP)
+ {
+ rtx x = operands[0];
+
+ emit_move_insn (x, operands[1]);
+ emit_insn (gen_bswaphi_lowpart (gen_lowpart (HImode, x)));
+ emit_insn (gen_rotlsi3 (x, x, GEN_INT (16)));
+ emit_insn (gen_bswaphi_lowpart (gen_lowpart (HImode, x)));
+ DONE;
+ }
+})
+
+(define_insn "*bswapsi_1"
[(set (match_operand:SI 0 "register_operand" "=r")
- (bswap:SI (match_operand:SI 1 "register_operand" "0")))
- (clobber (reg:CC FLAGS_REG))]
+ (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
"TARGET_BSWAP"
- "bswap\t%k0"
+ "bswap\t%0"
[(set_attr "prefix_0f" "1")
(set_attr "length" "2")])
+(define_insn "*bswaphi_lowpart_1"
+ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
+ (bswap:HI (match_dup 0)))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_XCHGB || optimize_size"
+ "@
+ xchg{b}\t{%h0, %b0|%b0, %h0}
+ rol{w}\t{$8, %0|%0, 8}"
+ [(set_attr "length" "2,4")
+ (set_attr "mode" "QI,HI")])
+
+(define_insn "bswaphi_lowpart"
+ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
+ (bswap:HI (match_dup 0)))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "rol{w}\t{$8, %0|%0, 8}"
+ [(set_attr "length" "4")
+ (set_attr "mode" "HI")])
+
(define_insn "bswapdi2"
[(set (match_operand:DI 0 "register_operand" "=r")
- (bswap:DI (match_operand:DI 1 "register_operand" "0")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_BSWAP"
+ (bswap:DI (match_operand:DI 1 "register_operand" "0")))]
+ "TARGET_64BIT"
"bswap\t%0"
[(set_attr "prefix_0f" "1")
(set_attr "length" "3")])
[(set_attr "prefix_rep" "1")
(set_attr "type" "bitmanip")
(set_attr "mode" "HI")])
+
+(define_expand "paritydi2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (parity:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
+ "! TARGET_POPCNT"
+{
+ rtx scratch = gen_reg_rtx (QImode);
+ rtx cond;
+
+ emit_insn (gen_paritydi2_cmp (NULL_RTX, NULL_RTX,
+ NULL_RTX, operands[1]));
+
+ cond = gen_rtx_fmt_ee (ORDERED, QImode,
+ gen_rtx_REG (CCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
+
+ if (TARGET_64BIT)
+ emit_insn (gen_zero_extendqidi2 (operands[0], scratch));
+ else
+ {
+ rtx tmp = gen_reg_rtx (SImode);
+
+ emit_insn (gen_zero_extendqisi2 (tmp, scratch));
+ emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
+ }
+ DONE;
+})
+
+(define_insn_and_split "paritydi2_cmp"
+ [(set (reg:CC FLAGS_REG)
+ (parity:CC (match_operand:DI 3 "nonimmediate_operand" "0,m")))
+ (clobber (match_scratch:DI 0 "=r,X"))
+ (clobber (match_scratch:SI 1 "=r,r"))
+ (clobber (match_scratch:HI 2 "=Q,Q"))]
+ "! TARGET_POPCNT"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 1)
+ (xor:SI (match_dup 1) (match_dup 4)))
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel
+ [(set (reg:CC FLAGS_REG)
+ (parity:CC (match_dup 1)))
+ (clobber (match_dup 1))
+ (clobber (match_dup 2))])]
+{
+ operands[4] = gen_lowpart (SImode, operands[3]);
+
+ if (MEM_P (operands[3]))
+ emit_move_insn (operands[1], gen_highpart (SImode, operands[3]));
+ else if (! TARGET_64BIT)
+ operands[1] = gen_highpart (SImode, operands[3]);
+ else
+ {
+ emit_move_insn (operands[1], gen_lowpart (SImode, operands[3]));
+ emit_insn (gen_lshrdi3 (operands[3], operands[3], GEN_INT (32)));
+ }
+})
+
+(define_expand "paritysi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (parity:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
+ "! TARGET_POPCNT"
+{
+ rtx scratch = gen_reg_rtx (QImode);
+ rtx cond;
+
+ emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
+
+ cond = gen_rtx_fmt_ee (ORDERED, QImode,
+ gen_rtx_REG (CCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
+
+ emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
+ DONE;
+})
+
+(define_insn_and_split "paritysi2_cmp"
+ [(set (reg:CC FLAGS_REG)
+ (parity:CC (match_operand:SI 2 "nonimmediate_operand" "0,m")))
+ (clobber (match_scratch:SI 0 "=r,X"))
+ (clobber (match_scratch:HI 1 "=Q,Q"))]
+ "! TARGET_POPCNT"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 1)
+ (xor:HI (match_dup 1) (match_dup 3)))
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel
+ [(set (reg:CC FLAGS_REG)
+ (parity:CC (match_dup 1)))
+ (clobber (match_dup 1))])]
+{
+ operands[3] = gen_lowpart (HImode, operands[2]);
+
+ if (MEM_P (operands[2]))
+ emit_move_insn (operands[1], gen_highpart (HImode, operands[2]));
+ else
+ {
+ emit_move_insn (operands[1], gen_lowpart (HImode, operands[2]));
+ emit_insn (gen_lshrsi3 (operands[2], operands[2], GEN_INT (16)));
+ }
+})
+
+(define_insn "*parityhi2_cmp"
+ [(set (reg:CC FLAGS_REG)
+ (parity:CC (match_operand:HI 1 "register_operand" "0")))
+ (clobber (match_scratch:HI 0 "=Q"))]
+ "! TARGET_POPCNT"
+ "xor{b}\t{%h0, %b0|%b0, %h0}"
+ [(set_attr "length" "2")
+ (set_attr "mode" "HI")])
+
+(define_insn "*parityqi2_cmp"
+ [(set (reg:CC FLAGS_REG)
+ (parity:CC (match_operand:QI 0 "register_operand" "q")))]
+ "! TARGET_POPCNT"
+ "test{b}\t%0, %0"
+ [(set_attr "length" "2")
+ (set_attr "mode" "QI")])
\f
;; Thread-local storage patterns for ELF.
;;
(match_dup 2)))
(set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
(set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
+ (set (match_dup 9) (float_extend:XF (match_dup 13)))
(set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
(parallel [(set (match_dup 7)
(unspec:XF [(match_dup 6) (match_dup 4)]
UNSPEC_FSCALE_FRACT))
- (set (match_dup 8)
+ (set (match_dup 8)
(unspec:XF [(match_dup 6) (match_dup 4)]
UNSPEC_FSCALE_EXP))])
(parallel [(set (match_dup 10)
(set (match_dup 11)
(unspec:XF [(match_dup 9) (match_dup 8)]
UNSPEC_FSCALE_EXP))])
- (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
+ (set (match_dup 12) (minus:XF (match_dup 10)
+ (float_extend:XF (match_dup 13))))
(set (match_operand:XF 0 "register_operand" "")
(plus:XF (match_dup 12) (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
for (i = 2; i < 13; i++)
operands[i] = gen_reg_rtx (XFmode);
-
+
+ operands[13]
+ = validize_mem (force_const_mem (SFmode, CONST1_RTX (SFmode))); /* fld1 */
+
emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */
- emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
})
(define_expand "expm1<mode>2"
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
DONE;
})
+
+(define_expand "scalbxf3"
+ [(parallel [(set (match_operand:XF 0 " register_operand" "")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ (match_operand:XF 2 "register_operand" "")]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 3)
+ (unspec:XF [(match_dup 1) (match_dup 2)]
+ UNSPEC_FSCALE_EXP))])]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations && !optimize_size"
+{
+ operands[3] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "scalb<mode>3"
+ [(use (match_operand:X87MODEF12 0 "register_operand" ""))
+ (use (match_operand:X87MODEF12 1 "general_operand" ""))
+ (use (match_operand:X87MODEF12 2 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations && !optimize_size"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+ rtx op2 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
+ emit_insn (gen_scalbxf3 (op0, op1, op2));
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
+})
\f
(define_insn "frndintxf2"
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