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* config/i386/i386.md (ashr<mode>3): Macroize expander from
[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.md
index b125179..7fb307a 100644 (file)
 
 ;; See comment above `ashldi3' about how this works.
 
-(define_expand "ashrti3"
-  [(set (match_operand:TI 0 "register_operand" "")
-       (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
-                    (match_operand:QI 2 "nonmemory_operand" "")))]
-  "TARGET_64BIT"
-  "ix86_expand_binary_operator (ASHIFTRT, TImode, operands); DONE;")
+(define_expand "ashr<mode>3"
+  [(set (match_operand:SDWIM 0 "<shift_operand>" "")
+       (ashiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
+                       (match_operand:QI 2 "nonmemory_operand" "")))]
+  ""
+  "ix86_expand_binary_operator (ASHIFTRT, <MODE>mode, operands); DONE;")
 
-(define_insn "*ashrti3_1"
-  [(set (match_operand:TI 0 "register_operand" "=r")
-       (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
-                    (match_operand:QI 2 "nonmemory_operand" "Oc")))
+(define_insn_and_split "*ashr<mode>3_doubleword"
+  [(set (match_operand:DWI 0 "register_operand" "=r")
+       (ashiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
+                     (match_operand:QI 2 "nonmemory_operand" "<S>c")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT"
+  ""
   "#"
+  "(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
+  [(const_int 0)]
+  "ix86_split_ashr (operands, NULL_RTX, <MODE>mode); DONE;"
   [(set_attr "type" "multi")])
 
+;; By default we don't ask for a scratch register, because when DWImode
+;; values are manipulated, registers are already at a premium.  But if
+;; we have one handy, we won't turn it away.
+
 (define_peephole2
-  [(match_scratch:DI 3 "r")
-   (parallel [(set (match_operand:TI 0 "register_operand" "")
-                  (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
-                               (match_operand:QI 2 "nonmemory_operand" "")))
+  [(match_scratch:DWIH 3 "r")
+   (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+                  (ashiftrt:<DWI>
+                    (match_operand:<DWI> 1 "register_operand" "")
+                    (match_operand:QI 2 "nonmemory_operand" "")))
              (clobber (reg:CC FLAGS_REG))])
    (match_dup 3)]
-  "TARGET_64BIT"
-  [(const_int 0)]
-  "ix86_split_ashr (operands, operands[3], TImode); DONE;")
-
-(define_split
-  [(set (match_operand:TI 0 "register_operand" "")
-       (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
-                    (match_operand:QI 2 "nonmemory_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
-                   ? epilogue_completed : reload_completed)"
+  "TARGET_CMOVE"
   [(const_int 0)]
-  "ix86_split_ashr (operands, NULL_RTX, TImode); DONE;")
+  "ix86_split_ashr (operands, operands[3], <DWI>mode); DONE;")
 
 (define_insn "x86_64_shrd"
   [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "vector")])
 
-(define_expand "ashrdi3"
-  [(set (match_operand:DI 0 "shiftdi_operand" "")
-       (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
-                    (match_operand:QI 2 "nonmemory_operand" "")))]
+(define_insn "x86_shrd"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
+        (ior:SI (ashiftrt:SI (match_dup 0)
+                 (match_operand:QI 2 "nonmemory_operand" "Ic"))
+               (ashift:SI (match_operand:SI 1 "register_operand" "r")
+                 (minus:QI (const_int 32) (match_dup 2)))))
+   (clobber (reg:CC FLAGS_REG))]
   ""
-  "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
+  "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
+  [(set_attr "type" "ishift")
+   (set_attr "prefix_0f" "1")
+   (set_attr "pent_pair" "np")
+   (set_attr "mode" "SI")])
+
+(define_insn "ashrdi3_cvt"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
+       (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
+                    (match_operand:QI 2 "const_int_operand" "")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && INTVAL (operands[2]) == 63
+   && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
+   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+  "@
+   {cqto|cqo}
+   sar{q}\t{%2, %0|%0, %2}"
+  [(set_attr "type" "imovx,ishift")
+   (set_attr "prefix_0f" "0,*")
+   (set_attr "length_immediate" "0,*")
+   (set_attr "modrm" "0,1")
+   (set_attr "mode" "DI")])
+
+(define_insn "*ashrsi3_cvt_zext"
+  [(set (match_operand:DI 0 "register_operand" "=*d,r")
+       (zero_extend:DI
+         (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
+                      (match_operand:QI 2 "const_int_operand" ""))))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && INTVAL (operands[2]) == 31
+   && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+  "@
+   {cltd|cdq}
+   sar{l}\t{%2, %k0|%k0, %2}"
+  [(set_attr "type" "imovx,ishift")
+   (set_attr "prefix_0f" "0,*")
+   (set_attr "length_immediate" "0,*")
+   (set_attr "modrm" "0,1")
+   (set_attr "mode" "SI")])
+
+(define_insn "ashrsi3_cvt"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
+       (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
+                    (match_operand:QI 2 "const_int_operand" "")))
+   (clobber (reg:CC FLAGS_REG))]
+  "INTVAL (operands[2]) == 31
+   && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+  "@
+   {cltd|cdq}
+   sar{l}\t{%2, %0|%0, %2}"
+  [(set_attr "type" "imovx,ishift")
+   (set_attr "prefix_0f" "0,*")
+   (set_attr "length_immediate" "0,*")
+   (set_attr "modrm" "0,1")
+   (set_attr "mode" "SI")])
 
-(define_expand "x86_64_shift_adj_3"
-  [(use (match_operand:DI 0 "register_operand" ""))
-   (use (match_operand:DI 1 "register_operand" ""))
+(define_expand "x86_shift<mode>_adj_3"
+  [(use (match_operand:SWI48 0 "register_operand" ""))
+   (use (match_operand:SWI48 1 "register_operand" ""))
    (use (match_operand:QI 2 "register_operand" ""))]
   ""
 {
   rtx label = gen_label_rtx ();
   rtx tmp;
 
-  emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (64)));
+  emit_insn (gen_testqi_ccz_1 (operands[2],
+                              GEN_INT (GET_MODE_BITSIZE (<MODE>mode))));
 
   tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
   tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
   JUMP_LABEL (tmp) = label;
 
   emit_move_insn (operands[0], operands[1]);
-  emit_insn (gen_ashrdi3_63_rex64 (operands[1], operands[1], GEN_INT (63)));
-
+  emit_insn (gen_ashr<mode>3_cvt (operands[1], operands[1],
+                                 GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1)));
   emit_label (label);
   LABEL_NUSES (label) = 1;
 
   DONE;
 })
 
-(define_insn "ashrdi3_63_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
-       (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
-                    (match_operand:DI 2 "const_int_operand" "i,i")))
+(define_insn "*ashr<mode>3_1"
+  [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
+       (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
+                     (match_operand:QI 2 "nonmemory_operand" "c<S>")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && INTVAL (operands[2]) == 63
-   && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
-  "@
-   {cqto|cqo}
-   sar{q}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "imovx,ishift")
-   (set_attr "prefix_0f" "0,*")
-   (set_attr "length_immediate" "0,*")
-   (set_attr "modrm" "0,1")
-   (set_attr "mode" "DI")])
+  "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
+{
+  if (REG_P (operands[2]))
+    return "sar{<imodesuffix>}\t{%b2, %0|%0, %b2}";
+  else if (operands[2] == const1_rtx
+          && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+    return "sar{<imodesuffix>}\t%0";
+  else
+    return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
+}
+  [(set_attr "type" "ishift")
+   (set (attr "length_immediate")
+     (if_then_else
+       (and (match_operand 2 "const1_operand" "")
+           (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+               (const_int 0)))
+       (const_string "0")
+       (const_string "*")))
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "*ashrdi3_1_one_bit_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
-                    (match_operand:QI 2 "const1_operand" "")))
+(define_insn "*ashrsi3_1_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+                      (match_operand:QI 2 "nonmemory_operand" "cI"))))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
-   && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
-  "sar{q}\t%0"
+  "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+{
+  if (REG_P (operands[2]))
+    return "sar{l}\t{%b2, %k0|%k0, %b2}";
+  else if (operands[2] == const1_rtx
+          && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+    return "sar{l}\t%k0";
+  else
+    return "sar{l}\t{%2, %k0|%k0, %2}";
+}
   [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "DI")])
+   (set (attr "length_immediate")
+     (if_then_else
+       (and (match_operand 2 "const1_operand" "")
+           (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+               (const_int 0)))
+       (const_string "0")
+       (const_string "*")))
+   (set_attr "mode" "SI")])
 
-(define_insn "*ashrdi3_1_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
-       (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
-                    (match_operand:QI 2 "nonmemory_operand" "J,c")))
+(define_insn "*ashrqi3_1_slp"
+  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
+       (ashiftrt:QI (match_dup 0)
+                    (match_operand:QI 1 "nonmemory_operand" "cI")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
-  "@
-   sar{q}\t{%2, %0|%0, %2}
-   sar{q}\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "DI")])
+  "(optimize_function_for_size_p (cfun)
+    || !TARGET_PARTIAL_REG_STALL
+    || (operands[1] == const1_rtx
+       && TARGET_SHIFT1))"
+{
+  if (REG_P (operands[1]))
+    return "sar{b}\t{%b1, %0|%0, %b1}";
+  else if (operands[1] == const1_rtx
+          && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+    return "sar{b}\t%0";
+  else
+    return "sar{b}\t{%1, %0|%0, %1}";
+}
+  [(set_attr "type" "ishift1")
+   (set (attr "length_immediate")
+     (if_then_else
+       (and (match_operand 1 "const1_operand" "")
+           (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+               (const_int 0)))
+       (const_string "0")
+       (const_string "*")))
+   (set_attr "mode" "QI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
-(define_insn "*ashrdi3_one_bit_cmp_rex64"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
-         (const_int 0)))
-   (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT
-   && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
-  "sar{q}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "DI")])
-
-(define_insn "*ashrdi3_one_bit_cconly_rex64"
+(define_insn "*ashr<mode>3_cmp"
   [(set (reg FLAGS_REG)
        (compare
-         (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
+         (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
+                       (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
          (const_int 0)))
-   (clobber (match_scratch:DI 0 "=r"))]
-  "TARGET_64BIT
-   && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
+   (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
+       (ashiftrt:SWI (match_dup 1) (match_dup 2)))]
+  "(optimize_function_for_size_p (cfun)
+    || !TARGET_PARTIAL_FLAG_REG_STALL
+    || (operands[2] == const1_rtx
+       && TARGET_SHIFT1))
    && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
-  "sar{q}\t%0"
+   && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
+{
+  if (operands[2] == const1_rtx
+      && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+    return "sar{<imodesuffix>}\t%0";
+  else
+    return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
+}
   [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "DI")])
+   (set (attr "length_immediate")
+     (if_then_else
+       (and (match_operand 2 "const1_operand" "")
+           (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+               (const_int 0)))
+       (const_string "0")
+       (const_string "*")))
+   (set_attr "mode" "<MODE>")])
 
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags.  We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrdi3_cmp_rex64"
+(define_insn "*ashrsi3_cmp_zext"
   [(set (reg FLAGS_REG)
        (compare
-         (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_63_operand" "J"))
+         (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
+                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
          (const_int 0)))
-   (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:DI (match_dup 1) (match_dup 2)))]
+   (set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT
-   && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
+   && (optimize_function_for_size_p (cfun)
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && TARGET_SHIFT1))
    && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
-  "sar{q}\t{%2, %0|%0, %2}"
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+{
+  if (operands[2] == const1_rtx
+      && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+    return "sar{l}\t%k0";
+  else
+    return "sar{l}\t{%2, %k0|%k0, %2}";
+}
   [(set_attr "type" "ishift")
-   (set_attr "mode" "DI")])
+   (set (attr "length_immediate")
+     (if_then_else
+       (and (match_operand 2 "const1_operand" "")
+           (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+               (const_int 0)))
+       (const_string "0")
+       (const_string "*")))
+   (set_attr "mode" "SI")])
 
-(define_insn "*ashrdi3_cconly_rex64"
+(define_insn "*ashr<mode>3_cconly"
   [(set (reg FLAGS_REG)
        (compare
-         (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_63_operand" "J"))
+         (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
+                       (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
          (const_int 0)))
-   (clobber (match_scratch:DI 0 "=r"))]
-  "TARGET_64BIT
-   && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
+   (clobber (match_scratch:DI 0 "=<r>"))]
+  "(optimize_function_for_size_p (cfun)
+    || !TARGET_PARTIAL_FLAG_REG_STALL
+    || (operands[2] == const1_rtx
+       && TARGET_SHIFT1))
    && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
-  "sar{q}\t{%2, %0|%0, %2}"
+   && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
+{
+  if (operands[2] == const1_rtx
+      && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+    return "sar{<imodesuffix>}\t%0";
+  else
+    return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
+}
   [(set_attr "type" "ishift")
-   (set_attr "mode" "DI")])
-
-(define_insn "*ashrdi3_1"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-                    (match_operand:QI 2 "nonmemory_operand" "Jc")))
-   (clobber (reg:CC FLAGS_REG))]
-  "!TARGET_64BIT"
-  "#"
-  [(set_attr "type" "multi")])
-
-;; By default we don't ask for a scratch register, because when DImode
-;; values are manipulated, registers are already at a premium.  But if
-;; we have one handy, we won't turn it away.
-(define_peephole2
-  [(match_scratch:SI 3 "r")
-   (parallel [(set (match_operand:DI 0 "register_operand" "")
-                  (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-                               (match_operand:QI 2 "nonmemory_operand" "")))
-             (clobber (reg:CC FLAGS_REG))])
-   (match_dup 3)]
-  "!TARGET_64BIT && TARGET_CMOVE"
-  [(const_int 0)]
-  "ix86_split_ashr (operands, operands[3], DImode); DONE;")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-       (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
-                    (match_operand:QI 2 "nonmemory_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
-                    ? epilogue_completed : reload_completed)"
-  [(const_int 0)]
-  "ix86_split_ashr (operands, NULL_RTX, DImode); DONE;")
-
-(define_insn "x86_shrd"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
-        (ior:SI (ashiftrt:SI (match_dup 0)
-                 (match_operand:QI 2 "nonmemory_operand" "Ic"))
-               (ashift:SI (match_operand:SI 1 "register_operand" "r")
-                 (minus:QI (const_int 32) (match_dup 2)))))
-   (clobber (reg:CC FLAGS_REG))]
-  ""
-  "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "prefix_0f" "1")
-   (set_attr "pent_pair" "np")
-   (set_attr "mode" "SI")])
-
-(define_expand "x86_shift_adj_3"
-  [(use (match_operand:SI 0 "register_operand" ""))
-   (use (match_operand:SI 1 "register_operand" ""))
-   (use (match_operand:QI 2 "register_operand" ""))]
-  ""
-{
-  rtx label = gen_label_rtx ();
-  rtx tmp;
-
-  emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
-
-  tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
-  tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
-  tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
-                             gen_rtx_LABEL_REF (VOIDmode, label),
-                             pc_rtx);
-  tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
-  JUMP_LABEL (tmp) = label;
-
-  emit_move_insn (operands[0], operands[1]);
-  emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
-
-  emit_label (label);
-  LABEL_NUSES (label) = 1;
-
-  DONE;
-})
-
-(define_expand "ashrsi3_31"
-  [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
-                  (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
-                               (match_operand:SI 2 "const_int_operand" "i,i")))
-              (clobber (reg:CC FLAGS_REG))])]
-  "")
-
-(define_insn "*ashrsi3_31"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
-       (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
-                    (match_operand:SI 2 "const_int_operand" "i,i")))
-   (clobber (reg:CC FLAGS_REG))]
-  "INTVAL (operands[2]) == 31
-   && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "@
-   {cltd|cdq}
-   sar{l}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "imovx,ishift")
-   (set_attr "prefix_0f" "0,*")
-   (set_attr "length_immediate" "0,*")
-   (set_attr "modrm" "0,1")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_31_zext"
-  [(set (match_operand:DI 0 "register_operand" "=*d,r")
-       (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
-                                    (match_operand:SI 2 "const_int_operand" "i,i"))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
-   && INTVAL (operands[2]) == 31
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "@
-   {cltd|cdq}
-   sar{l}\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "imovx,ishift")
-   (set_attr "prefix_0f" "0,*")
-   (set_attr "length_immediate" "0,*")
-   (set_attr "modrm" "0,1")
-   (set_attr "mode" "SI")])
-
-(define_expand "ashrsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-       (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
-                    (match_operand:QI 2 "nonmemory_operand" "")))]
-  ""
-  "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
-
-(define_insn "*ashrsi3_1_one_bit"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                    (match_operand:QI 2 "const1_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_1_one_bit_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-                                    (match_operand:QI 2 "const1_operand" ""))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT
-   && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t%k0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_1"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
-       (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
-                    (match_operand:QI 2 "nonmemory_operand" "I,c")))
-   (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "@
-   sar{l}\t{%2, %0|%0, %2}
-   sar{l}\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_1_zext"
-  [(set (match_operand:DI 0 "register_operand" "=r,r")
-       (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
-                                    (match_operand:QI 2 "nonmemory_operand" "I,c"))))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "@
-   sar{l}\t{%2, %k0|%k0, %2}
-   sar{l}\t{%b2, %k0|%k0, %b2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "SI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags.  We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrsi3_one_bit_cmp"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
-         (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_one_bit_cconly"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
-         (const_int 0)))
-   (clobber (match_scratch:SI 0 "=r"))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_one_bit_cmp_zext"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
-         (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
-  "TARGET_64BIT
-   && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t%k0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "SI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags.  We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrsi3_cmp"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
-         (const_int 0)))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:SI (match_dup 1) (match_dup 2)))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_cconly"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
-         (const_int 0)))
-   (clobber (match_scratch:SI 0 "=r"))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_cmp_zext"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
-         (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-       (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
-  "TARGET_64BIT
-   && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "sar{l}\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "SI")])
-
-(define_expand "ashrhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-       (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
-                    (match_operand:QI 2 "nonmemory_operand" "")))]
-  "TARGET_HIMODE_MATH"
-  "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
-
-(define_insn "*ashrhi3_1_one_bit"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                    (match_operand:QI 2 "const1_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
-  "sar{w}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "HI")])
-
-(define_insn "*ashrhi3_1"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
-       (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
-                    (match_operand:QI 2 "nonmemory_operand" "I,c")))
-   (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
-  "@
-   sar{w}\t{%2, %0|%0, %2}
-   sar{w}\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "HI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags.  We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrhi3_one_bit_cmp"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
-         (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:HI (match_dup 1) (match_dup 2)))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
-  "sar{w}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "HI")])
-
-(define_insn "*ashrhi3_one_bit_cconly"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
-         (const_int 0)))
-   (clobber (match_scratch:HI 0 "=r"))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
-  "sar{w}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "HI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags.  We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrhi3_cmp"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
-         (const_int 0)))
-   (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
-       (ashiftrt:HI (match_dup 1) (match_dup 2)))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
-  "sar{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "HI")])
-
-(define_insn "*ashrhi3_cconly"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
-         (const_int 0)))
-   (clobber (match_scratch:HI 0 "=r"))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
-  "sar{w}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "HI")])
-
-(define_expand "ashrqi3"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "")
-       (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
-                    (match_operand:QI 2 "nonmemory_operand" "")))]
-  "TARGET_QIMODE_MATH"
-  "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
-
-(define_insn "*ashrqi3_1_one_bit"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-       (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                    (match_operand:QI 2 "const1_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
-  "sar{b}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "QI")])
-
-(define_insn "*ashrqi3_1_one_bit_slp"
-  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
-       (ashiftrt:QI (match_dup 0)
-                    (match_operand:QI 1 "const1_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
-   && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
-  "sar{b}\t%0"
-  [(set_attr "type" "ishift1")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "QI")])
-
-(define_insn "*ashrqi3_1"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
-       (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
-                    (match_operand:QI 2 "nonmemory_operand" "I,c")))
-   (clobber (reg:CC FLAGS_REG))]
-  "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
-  "@
-   sar{b}\t{%2, %0|%0, %2}
-   sar{b}\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "QI")])
-
-(define_insn "*ashrqi3_1_slp"
-  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
-       (ashiftrt:QI (match_dup 0)
-                    (match_operand:QI 1 "nonmemory_operand" "I,c")))
-   (clobber (reg:CC FLAGS_REG))]
-  "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
-   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "@
-   sar{b}\t{%1, %0|%0, %1}
-   sar{b}\t{%b1, %0|%0, %b1}"
-  [(set_attr "type" "ishift1")
-   (set_attr "mode" "QI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags.  We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrqi3_one_bit_cmp"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" "I"))
-         (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-       (ashiftrt:QI (match_dup 1) (match_dup 2)))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
-  "sar{b}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "QI")])
-
-(define_insn "*ashrqi3_one_bit_cconly"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const1_operand" ""))
-         (const_int 0)))
-   (clobber (match_scratch:QI 0 "=q"))]
-  "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
-  "sar{b}\t%0"
-  [(set_attr "type" "ishift")
-   (set_attr "length_immediate" "0")
-   (set_attr "mode" "QI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags.  We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrqi3_cmp"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
-         (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
-       (ashiftrt:QI (match_dup 1) (match_dup 2)))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
-  "sar{b}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "QI")])
-
-(define_insn "*ashrqi3_cconly"
-  [(set (reg FLAGS_REG)
-       (compare
-         (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-                      (match_operand:QI 2 "const_1_to_31_operand" "I"))
-         (const_int 0)))
-   (clobber (match_scratch:QI 0 "=q"))]
-  "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
-   && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
-  "sar{b}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")
-   (set_attr "mode" "QI")])
-
+   (set (attr "length_immediate")
+     (if_then_else
+       (and (match_operand 2 "const1_operand" "")
+           (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+               (const_int 0)))
+       (const_string "0")
+       (const_string "*")))
+   (set_attr "mode" "<MODE>")])
 \f
 ;; Logical shift instructions