;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004, 2005
+;; 2001, 2002, 2003, 2004, 2005, 2006
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA. */
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA. */
;;
;; The original PO technology requires these to be ordered by speed,
;; so that assigner will pick the fastest.
(UNSPEC_STACK_ALLOC 11)
(UNSPEC_SET_GOT 12)
(UNSPEC_SSE_PROLOGUE_SAVE 13)
+ (UNSPEC_REG_SAVE 14)
+ (UNSPEC_DEF_CFA 15)
; TLS support
- (UNSPEC_TP 15)
- (UNSPEC_TLS_GD 16)
- (UNSPEC_TLS_LD_BASE 17)
+ (UNSPEC_TP 16)
+ (UNSPEC_TLS_GD 17)
+ (UNSPEC_TLS_LD_BASE 18)
+ (UNSPEC_TLSDESC 19)
; Other random patterns
(UNSPEC_SCAS 20)
- (UNSPEC_SIN 21)
- (UNSPEC_COS 22)
- (UNSPEC_FNSTSW 24)
- (UNSPEC_SAHF 25)
- (UNSPEC_FSTCW 26)
- (UNSPEC_ADD_CARRY 27)
- (UNSPEC_FLDCW 28)
+ (UNSPEC_FNSTSW 21)
+ (UNSPEC_SAHF 22)
+ (UNSPEC_FSTCW 23)
+ (UNSPEC_ADD_CARRY 24)
+ (UNSPEC_FLDCW 25)
+ (UNSPEC_REP 26)
+ (UNSPEC_EH_RETURN 27)
+ (UNSPEC_LD_MPIC 28) ; load_macho_picbase
; For SSE/MMX support:
- (UNSPEC_FIX 30)
- (UNSPEC_FIX_NOTRUNC 31)
- (UNSPEC_MASKMOV 32)
- (UNSPEC_MOVMSK 33)
- (UNSPEC_MOVNT 34)
- (UNSPEC_MOVA 38)
- (UNSPEC_MOVU 39)
- (UNSPEC_SHUFFLE 41)
- (UNSPEC_RCP 42)
- (UNSPEC_RSQRT 43)
- (UNSPEC_SFENCE 44)
- (UNSPEC_NOP 45) ; prevents combiner cleverness
- (UNSPEC_PAVGUSB 49)
- (UNSPEC_PFRCP 50)
- (UNSPEC_PFRCPIT1 51)
- (UNSPEC_PFRCPIT2 52)
- (UNSPEC_PFRSQRT 53)
- (UNSPEC_PFRSQIT1 54)
- (UNSPEC_PSHUFLW 55)
- (UNSPEC_PSHUFHW 56)
- (UNSPEC_MFENCE 59)
- (UNSPEC_LFENCE 60)
- (UNSPEC_PSADBW 61)
- (UNSPEC_ADDSUB 71)
- (UNSPEC_HADD 72)
- (UNSPEC_HSUB 73)
- (UNSPEC_MOVSHDUP 74)
- (UNSPEC_MOVSLDUP 75)
- (UNSPEC_LDQQU 76)
- (UNSPEC_MOVDDUP 77)
+ (UNSPEC_FIX_NOTRUNC 30)
+ (UNSPEC_MASKMOV 31)
+ (UNSPEC_MOVMSK 32)
+ (UNSPEC_MOVNT 33)
+ (UNSPEC_MOVU 34)
+ (UNSPEC_RCP 35)
+ (UNSPEC_RSQRT 36)
+ (UNSPEC_SFENCE 37)
+ (UNSPEC_NOP 38) ; prevents combiner cleverness
+ (UNSPEC_PFRCP 39)
+ (UNSPEC_PFRCPIT1 40)
+ (UNSPEC_PFRCPIT2 41)
+ (UNSPEC_PFRSQRT 42)
+ (UNSPEC_PFRSQIT1 43)
+ (UNSPEC_MFENCE 44)
+ (UNSPEC_LFENCE 45)
+ (UNSPEC_PSADBW 46)
+ (UNSPEC_LDQQU 47)
+
+ ; Generic math support
+ (UNSPEC_COPYSIGN 50)
+ (UNSPEC_IEEE_MIN 51) ; not commutative
+ (UNSPEC_IEEE_MAX 52) ; not commutative
; x87 Floating point
- (UNSPEC_FPATAN 65)
- (UNSPEC_FYL2X 66)
- (UNSPEC_FYL2XP1 67)
- (UNSPEC_FRNDINT 68)
- (UNSPEC_F2XM1 69)
+ (UNSPEC_SIN 60)
+ (UNSPEC_COS 61)
+ (UNSPEC_FPATAN 62)
+ (UNSPEC_FYL2X 63)
+ (UNSPEC_FYL2XP1 64)
+ (UNSPEC_FRNDINT 65)
+ (UNSPEC_FIST 66)
+ (UNSPEC_F2XM1 67)
+
+ ; x87 Rounding
+ (UNSPEC_FRNDINT_FLOOR 70)
+ (UNSPEC_FRNDINT_CEIL 71)
+ (UNSPEC_FRNDINT_TRUNC 72)
+ (UNSPEC_FRNDINT_MASK_PM 73)
+ (UNSPEC_FIST_FLOOR 74)
+ (UNSPEC_FIST_CEIL 75)
; x87 Double output FP
(UNSPEC_SINCOS_COS 80)
(UNSPEC_FPREM1_F 90)
(UNSPEC_FPREM1_U 91)
- ; x87 Rounding
- (UNSPEC_FRNDINT_FLOOR 96)
- (UNSPEC_FRNDINT_CEIL 97)
- (UNSPEC_FRNDINT_TRUNC 98)
- (UNSPEC_FRNDINT_MASK_PM 99)
-
- ; REP instruction
- (UNSPEC_REP 75)
-
- (UNSPEC_EH_RETURN 76)
-
- (UNSPEC_COPYSIGN 100)
+ ; SSP patterns
+ (UNSPEC_SP_SET 100)
+ (UNSPEC_SP_TEST 101)
+ (UNSPEC_SP_TLS_SET 102)
+ (UNSPEC_SP_TLS_TEST 103)
])
(define_constants
[(UNSPECV_BLOCKAGE 0)
- (UNSPECV_STACK_PROBE 10)
- (UNSPECV_EMMS 31)
- (UNSPECV_LDMXCSR 37)
- (UNSPECV_STMXCSR 40)
- (UNSPECV_FEMMS 46)
- (UNSPECV_CLFLUSH 57)
- (UNSPECV_ALIGN 68)
- (UNSPECV_MONITOR 69)
- (UNSPECV_MWAIT 70)
+ (UNSPECV_STACK_PROBE 1)
+ (UNSPECV_EMMS 2)
+ (UNSPECV_LDMXCSR 3)
+ (UNSPECV_STMXCSR 4)
+ (UNSPECV_FEMMS 5)
+ (UNSPECV_CLFLUSH 6)
+ (UNSPECV_ALIGN 7)
+ (UNSPECV_MONITOR 8)
+ (UNSPECV_MWAIT 9)
+ (UNSPECV_CMPXCHG_1 10)
+ (UNSPECV_CMPXCHG_2 11)
+ (UNSPECV_XCHG 12)
+ (UNSPECV_LOCK 13)
])
;; Registers by name.
\f
;; Processor type. This attribute must exactly match the processor_type
;; enumeration in i386.h.
-(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
+(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona,generic32,generic64"
(const (symbol_ref "ix86_tune")))
;; A basic instruction type. Refinements due to arguments to be
icmp,test,ibr,setcc,icmov,
push,pop,call,callv,leave,
str,cld,
- fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
+ fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
sselog,sselog1,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
;; The CPU unit operations uses.
(define_attr "unit" "integer,i387,sse,mmx,unknown"
- (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
+ (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
(const_string "i387")
(eq_attr "type" "sselog,sselog1,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
(const_int 1)
]
(symbol_ref "/* Update immediate_length and other attributes! */
- abort(),1")))
+ gcc_unreachable (),1")))
;; The (bounding maximum) length of an instruction address.
(define_attr "length_address" ""
(not (match_operand 0 "memory_operand" "")))
(const_int 0)
(and (eq_attr "type" "imov")
- (and (match_operand 0 "register_operand" "")
- (match_operand 1 "immediate_operand" "")))
+ (ior (and (match_operand 0 "register_operand" "")
+ (match_operand 1 "immediate_operand" ""))
+ (ior (and (match_operand 0 "ax_reg_operand" "")
+ (match_operand 1 "memory_displacement_only_operand" ""))
+ (and (match_operand 0 "memory_displacement_only_operand" "")
+ (match_operand 1 "ax_reg_operand" "")))))
(const_int 0)
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand" ""))
;; Defines rounding mode of an FP operation.
-(define_attr "i387_cw" "floor,ceil,trunc,mask_pm,uninitialized,any"
+(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
(const_string "any"))
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "length" "128")
(set_attr "type" "multi")])
+
+;; All x87 floating point modes
+(define_mode_macro X87MODEF [SF DF XF])
+
+;; All integer modes handled by x87 fisttp operator.
+(define_mode_macro X87MODEI [HI SI DI])
+
+;; All integer modes handled by integer x87 operators.
+(define_mode_macro X87MODEI12 [HI SI])
+
+;; All SSE floating point modes
+(define_mode_macro SSEMODEF [SF DF])
+
+;; All integer modes handled by SSE cvtts?2si* operators.
+(define_mode_macro SSEMODEI24 [SI DI])
+
\f
;; Scheduling descriptions
;; actually generating RTL. The bCOND or sCOND (emitted immediately
;; after the cmp) will actually emit the cmpM.
+(define_expand "cmpti"
+ [(set (reg:CC FLAGS_REG)
+ (compare:CC (match_operand:TI 0 "nonimmediate_operand" "")
+ (match_operand:TI 1 "x86_64_general_operand" "")))]
+ "TARGET_64BIT"
+{
+ if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+ operands[0] = force_reg (TImode, operands[0]);
+ ix86_compare_op0 = operands[0];
+ ix86_compare_op1 = operands[1];
+ DONE;
+})
+
(define_expand "cmpdi"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
(define_expand "cmpxf"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
- (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
+ (compare:CC (match_operand:XF 0 "nonmemory_operand" "")
+ (match_operand:XF 1 "nonmemory_operand" "")))]
"TARGET_80387"
{
ix86_compare_op0 = operands[0];
;; We may not use "#" to split and emit these, since the REG_DEAD notes
;; used to manage the reg stack popping would not be preserved.
-(define_insn "*cmpfp_0_sf"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (unspec:HI
- [(compare:CCFP
- (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "const0_operand" "X"))]
- UNSPEC_FNSTSW))]
- "TARGET_80387"
- "* return output_fp_compare (insn, operands, 0, 0);"
- [(set_attr "type" "multi")
- (set_attr "mode" "SF")])
-
-(define_insn "*cmpfp_0_df"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (unspec:HI
- [(compare:CCFP
- (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "const0_operand" "X"))]
- UNSPEC_FNSTSW))]
- "TARGET_80387"
- "* return output_fp_compare (insn, operands, 0, 0);"
- [(set_attr "type" "multi")
- (set_attr "mode" "DF")])
-
-(define_insn "*cmpfp_0_xf"
+(define_insn "*cmpfp_0"
[(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI
[(compare:CCFP
- (match_operand:XF 1 "register_operand" "f")
- (match_operand:XF 2 "const0_operand" "X"))]
+ (match_operand 1 "register_operand" "f")
+ (match_operand 2 "const0_operand" "X"))]
UNSPEC_FNSTSW))]
- "TARGET_80387"
+ "TARGET_80387
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && GET_MODE (operands[1]) == GET_MODE (operands[2])"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "multi")
- (set_attr "mode" "XF")])
+ (set_attr "unit" "i387")
+ (set (attr "mode")
+ (cond [(match_operand:SF 1 "" "")
+ (const_string "SF")
+ (match_operand:DF 1 "" "")
+ (const_string "DF")
+ ]
+ (const_string "XF")))])
(define_insn "*cmpfp_sf"
[(set (match_operand:HI 0 "register_operand" "=a")
"TARGET_80387"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "multi")
+ (set_attr "unit" "i387")
(set_attr "mode" "SF")])
(define_insn "*cmpfp_df"
"TARGET_80387"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "multi")
+ (set_attr "unit" "i387")
(set_attr "mode" "DF")])
(define_insn "*cmpfp_xf"
"TARGET_80387"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "multi")
+ (set_attr "unit" "i387")
(set_attr "mode" "XF")])
(define_insn "*cmpfp_u"
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
"* return output_fp_compare (insn, operands, 0, 1);"
[(set_attr "type" "multi")
+ (set_attr "unit" "i387")
(set (attr "mode")
(cond [(match_operand:SF 1 "" "")
(const_string "SF")
]
(const_string "XF")))])
-(define_insn "*cmpfp_si"
+(define_insn "*cmpfp_<mode>"
[(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI
[(compare:CCFP
(match_operand 1 "register_operand" "f")
(match_operator 3 "float_operator"
- [(match_operand:SI 2 "memory_operand" "m")]))]
+ [(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
UNSPEC_FNSTSW))]
- "TARGET_80387 && TARGET_USE_FIOP
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
&& FLOAT_MODE_P (GET_MODE (operands[1]))
&& (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "multi")
+ (set_attr "unit" "i387")
(set_attr "fp_int_src" "true")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
;; FP compares, step 2
;; Move the fpsw to ax.
return "lea{l}\t{%1, %0|%0, %1}";
default:
- if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
- abort();
+ gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
return "mov{l}\t{%1, %0|%0, %1}";
}
}
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
- (const_string "mmx")
+ (const_string "mmxadd")
(eq_attr "alternative" "3,4,5")
(const_string "mmxmov")
(eq_attr "alternative" "6")
(const_string "sselog1")
(eq_attr "alternative" "7,8,9,10,11")
(const_string "ssemov")
- (and (ne (symbol_ref "flag_pic") (const_int 0))
- (match_operand:SI 1 "symbolic_operand" ""))
+ (match_operand:DI 1 "pic_32bit_operand" "")
(const_string "lea")
]
(const_string "imov")))
"ix86_expand_move (HImode, operands); DONE;")
(define_insn "*pushhi2"
- [(set (match_operand:HI 0 "push_operand" "=<,<")
- (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
+ [(set (match_operand:HI 0 "push_operand" "=X")
+ (match_operand:HI 1 "nonmemory_no_elim_operand" "rn"))]
"!TARGET_64BIT"
- "@
- push{w}\t{|WORD PTR }%1
- push{w}\t%1"
+ "push{l}\t%k1"
[(set_attr "type" "push")
- (set_attr "mode" "HI")])
+ (set_attr "mode" "SI")])
;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushhi2_rex64"
"TARGET_64BIT"
"push{q}\t%q1"
[(set_attr "type" "push")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "DI")])
(define_insn "*movhi_1"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
"ix86_expand_move (QImode, operands); DONE;")
;; emit_push_insn when it calls move_by_pieces requires an insn to
-;; "push a byte". But actually we use pushw, which has the effect
-;; of rounding the amount pushed up to a halfword.
+;; "push a byte". But actually we use pushl, which has the effect
+;; of rounding the amount pushed up to a word.
(define_insn "*pushqi2"
- [(set (match_operand:QI 0 "push_operand" "=X,X")
- (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
+ [(set (match_operand:QI 0 "push_operand" "=X")
+ (match_operand:QI 1 "nonmemory_no_elim_operand" "rn"))]
"!TARGET_64BIT"
- "@
- push{w}\t{|word ptr }%1
- push{w}\t%w1"
+ "push{l}\t%k1"
[(set_attr "type" "push")
- (set_attr "mode" "HI")])
+ (set_attr "mode" "SI")])
;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushqi2_rex64"
"TARGET_64BIT"
"push{q}\t%q1"
[(set_attr "type" "push")
- (set_attr "mode" "QI")])
+ (set_attr "mode" "DI")])
;; Situation is quite tricky about when to choose full sized (SImode) move
;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
- abort ();
+ gcc_assert (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM);
return "movz{bl|x}\t{%1, %k0|%k0, %1}";
default:
if (get_attr_mode (insn) == MODE_SI)
}
}
[(set (attr "type")
- (cond [(ne (symbol_ref "optimize_size") (const_int 0))
+ (cond [(and (eq_attr "alternative" "5")
+ (not (match_operand:QI 1 "aligned_operand" "")))
+ (const_string "imovx")
+ (ne (symbol_ref "optimize_size") (const_int 0))
(const_string "imov")
(and (eq_attr "alternative" "3")
(ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
(const_string "SI")
(and (eq_attr "type" "imov")
(and (eq_attr "alternative" "0,1")
- (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
- (const_int 0))))
+ (and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
+ (const_int 0))
+ (and (eq (symbol_ref "optimize_size")
+ (const_int 0))
+ (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
+ (const_int 0))))))
(const_string "SI")
;; Avoid partial register stalls when not using QImode arithmetic
(and (eq_attr "type" "imov")
rtx op0, op1, op2;
op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
- if (reg_overlap_mentioned_p (op2, op0))
- abort ();
+ gcc_assert (!reg_overlap_mentioned_p (op2, op0));
if (! q_regs_operand (op1, QImode))
{
emit_insn (gen_movqi (op2, op1));
(set_attr "memory" "load")
(set_attr "mode" "QI")])
+(define_insn "*movdi_extzv_1"
+ [(set (match_operand:DI 0 "register_operand" "=R")
+ (zero_extract:DI (match_operand 1 "ext_register_operand" "Q")
+ (const_int 8)
+ (const_int 8)))]
+ "TARGET_64BIT"
+ "movz{bl|x}\t{%h1, %k0|%k0, %h1}"
+ [(set_attr "type" "imovx")
+ (set_attr "mode" "DI")])
+
(define_insn "*movsi_extzv_1"
[(set (match_operand:SI 0 "register_operand" "=R")
(zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
(define_split
[(set (match_operand:DI 0 "push_operand" "")
(match_operand:DI 1 "immediate_operand" ""))]
- "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
+ "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? flow2_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 0) (match_dup 1))
case TYPE_LEA:
return "lea{q}\t{%a1, %0|%0, %a1}";
default:
- if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
- abort ();
+ gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
if (get_attr_mode (insn) == MODE_SI)
return "mov{l}\t{%k1, %k0|%k0, %k1}";
else if (which_alternative == 2)
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5")
- (const_string "mmx")
+ (const_string "mmxadd")
(eq_attr "alternative" "6,7,8")
(const_string "mmxmov")
(eq_attr "alternative" "9")
(const_string "ssecvt")
(eq_attr "alternative" "4")
(const_string "multi")
- (and (ne (symbol_ref "flag_pic") (const_int 0))
- (match_operand:DI 1 "symbolic_operand" ""))
+ (match_operand:DI 1 "pic_32bit_operand" "")
(const_string "lea")
]
(const_string "imov")))
(define_split
[(set (match_operand:DI 0 "memory_operand" "")
(match_operand:DI 1 "immediate_operand" ""))]
- "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
+ "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? flow2_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 2) (match_dup 3))
else
return "movdqa\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
}
- [(set_attr "type" "ssemov,ssemov,ssemov")
+ [(set_attr "type" "sselog1,ssemov,ssemov")
(set (attr "mode")
- (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
+ (cond [(ior (eq (symbol_ref "TARGET_SSE2") (const_int 0))
+ (ne (symbol_ref "optimize_size") (const_int 0)))
(const_string "V4SF")
-
- (eq_attr "alternative" "0,1")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "2")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "TI")))])
+ (and (eq_attr "alternative" "2")
+ (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
+ (const_int 0)))
+ (const_string "V4SF")]
+ (const_string "TI")))])
(define_insn "*movti_rex64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
else
return "movdqa\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
}
- [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
+ [(set_attr "type" "*,*,sselog1,ssemov,ssemov")
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(if_then_else
(match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
"!TARGET_64BIT"
{
- switch (which_alternative)
- {
- case 1:
- return "push{l}\t%1";
-
- default:
- /* This insn should be already split before reg-stack. */
- abort ();
- }
+ /* Anything else should be already split before reg-stack. */
+ gcc_assert (which_alternative == 1);
+ return "push{l}\t%1";
}
[(set_attr "type" "multi,push,multi")
+ (set_attr "unit" "i387,*,*")
(set_attr "mode" "SF,SI,SF")])
(define_insn "*pushsf_rex64"
(match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
"TARGET_64BIT"
{
- switch (which_alternative)
- {
- case 1:
- return "push{q}\t%q1";
-
- default:
- /* This insn should be already split before reg-stack. */
- abort ();
- }
+ /* Anything else should be already split before reg-stack. */
+ gcc_assert (which_alternative == 1);
+ return "push{q}\t%q1";
}
[(set_attr "type" "multi,push,multi")
+ (set_attr "unit" "i387,*,*")
(set_attr "mode" "SF,DI,SF")])
(define_split
(match_operand:SF 1 "memory_operand" ""))]
"reload_completed
&& GET_CODE (operands[1]) == MEM
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
- && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
+ && constant_pool_reference_p (operands[1])"
[(set (match_dup 0)
(match_dup 1))]
- "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
+ "operands[1] = avoid_constant_pool_reference (operands[1]);")
;; %%% Kill this when call knows how to work this out.
return "movq\t{%1, %0|%0, %1}";
default:
- abort();
+ gcc_unreachable ();
}
}
- [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
+ [(set_attr "type" "fmov,fmov,fmov,imov,imov,sselog1,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
(set (attr "mode")
(cond [(eq_attr "alternative" "3,4,9,10")
(const_string "SI")
"!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
{
/* This insn should be already split before reg-stack. */
- abort ();
+ gcc_unreachable ();
}
[(set_attr "type" "multi")
+ (set_attr "unit" "i387,*,*,*")
(set_attr "mode" "DF,SI,SI,DF")])
(define_insn "*pushdf_integer"
"TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
{
/* This insn should be already split before reg-stack. */
- abort ();
+ gcc_unreachable ();
}
[(set_attr "type" "multi")
+ (set_attr "unit" "i387,*,*")
(set_attr "mode" "DF,SI,DF")])
;; %%% Kill this when call knows how to work this out.
(define_insn "*movdf_nointeger"
[(set (match_operand:DF 0 "nonimmediate_operand"
- "=f#Y,m ,f#Y,*r ,o ,Y#f*x,Y#f*x,Y#f*x ,m ")
+ "=f#Y,m ,f#Y,*r ,o ,Y*x#f,Y*x#f,Y*x#f ,m ")
(match_operand:DF 1 "general_operand"
- "fm#Y,f#Y,G ,*roF,F*r,C ,Y#f*x,HmY#f*x,Y#f*x"))]
+ "fm#Y,f#Y,G ,*roF,F*r,C ,Y*x#f,HmY*x#f,Y*x#f"))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
&& (reload_in_progress || reload_completed
case MODE_TI:
return "pxor\t%0, %0";
default:
- abort ();
+ gcc_unreachable ();
}
case 6:
case 7:
case MODE_V2SF:
return "movlps\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
default:
- abort();
+ gcc_unreachable ();
}
}
- [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
+ [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
(define_insn "*movdf_integer"
[(set (match_operand:DF 0 "nonimmediate_operand"
- "=f#Yr,m ,f#Yr,r#Yf ,o ,Y#rf*x,Y#rf*x,Y#rf*x,m")
+ "=f#Yr,m ,f#Yr,r#Yf ,o ,Y*x#rf,Y*x#rf,Y*x#rf,m")
(match_operand:DF 1 "general_operand"
- "fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y#rf*x,m ,Y#rf*x"))]
+ "fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y*x#rf,m ,Y*x#rf"))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
&& (reload_in_progress || reload_completed
case MODE_TI:
return "pxor\t%0, %0";
default:
- abort ();
+ gcc_unreachable ();
}
case 6:
case 7:
case MODE_V2SF:
return "movlps\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
default:
- abort();
+ gcc_unreachable();
}
}
- [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
+ [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
(set (attr "mode")
(cond [(eq_attr "alternative" "0,1,2")
(const_string "DF")
"optimize_size"
{
/* This insn should be already split before reg-stack. */
- abort ();
+ gcc_unreachable ();
}
[(set_attr "type" "multi")
+ (set_attr "unit" "i387,*,*")
(set_attr "mode" "XF,SI,SI")])
(define_insn "*pushxf_integer"
"!optimize_size"
{
/* This insn should be already split before reg-stack. */
- abort ();
+ gcc_unreachable ();
}
[(set_attr "type" "multi")
+ (set_attr "unit" "i387,*")
(set_attr "mode" "XF,SI")])
(define_split
case 3: case 4:
return "#";
+ default:
+ gcc_unreachable ();
}
- abort();
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
case 3: case 4:
return "#";
+
+ default:
+ gcc_unreachable ();
}
- abort();
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
&& GET_CODE (operands[1]) == MEM
&& (GET_MODE (operands[0]) == XFmode
|| GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
- && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
+ && constant_pool_reference_p (operands[1])"
[(set (match_dup 0) (match_dup 1))]
{
- rtx c = get_pool_constant (XEXP (operands[1], 0));
+ rtx c = avoid_constant_pool_reference (operands[1]);
rtx r = operands[0];
if (GET_CODE (r) == SUBREG)
else
return "movdqa\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
}
- [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
+ [(set_attr "type" "*,*,sselog1,ssemov,ssemov")
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(if_then_else
[(set_attr "type" "imovx,alu1")
(set_attr "mode" "HI")])
-(define_insn "*zero_extendqihi2_movzbw"
+; zero extend to SImode here to avoid partial register stalls
+(define_insn "*zero_extendqihi2_movzbl"
[(set (match_operand:HI 0 "register_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
"(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
- "movz{bw|x}\t{%1, %0|%0, %1}"
+ "movz{bl|x}\t{%1, %k0|%k0, %k1}"
[(set_attr "type" "imovx")
- (set_attr "mode" "HI")])
+ (set_attr "mode" "SI")])
;; For the movzbw case strip only the clobber
(define_split
"split_di (&operands[0], 1, &operands[3], &operands[4]);")
(define_insn "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
"TARGET_64BIT"
- "@
- movz{wl|x}\t{%1, %k0|%k0, %1}
- movz{wq|x}\t{%1, %0|%0, %1}"
+ "movz{wl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
- (set_attr "mode" "SI,DI")])
+ (set_attr "mode" "DI")])
(define_insn "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
"TARGET_64BIT"
- "@
- movz{bl|x}\t{%1, %k0|%k0, %1}
- movz{bq|x}\t{%1, %0|%0, %1}"
+ "movz{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
- (set_attr "mode" "SI,DI")])
+ (set_attr "mode" "DI")])
\f
;; Sign extension instructions
/* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */
if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
+ {
+ if ((!TARGET_SSE2 || TARGET_MIX_SSE_I387)
+ && standard_80387_constant_p (operands[1]) > 0)
+ {
+ operands[1] = simplify_const_unary_operation
+ (FLOAT_EXTEND, DFmode, operands[1], SFmode);
+ emit_move_insn_1 (operands[0], operands[1]);
+ DONE;
+ }
+ operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
+ }
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
})
return "cvtss2sd\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "fmov,fmov,ssecvt")
return "fst%z0\t%y0";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "fmov")
/* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */
if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
+ {
+ if (standard_80387_constant_p (operands[1]) > 0)
+ {
+ operands[1] = simplify_const_unary_operation
+ (FLOAT_EXTEND, XFmode, operands[1], SFmode);
+ emit_move_insn_1 (operands[0], operands[1]);
+ DONE;
+ }
+ operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
+ }
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
})
return "fstp%z0\t%y0\n\tfld%z0\t%y0";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "fmov")
/* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */
if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
+ {
+ if (standard_80387_constant_p (operands[1]) > 0)
+ {
+ operands[1] = simplify_const_unary_operation
+ (FLOAT_EXTEND, XFmode, operands[1], DFmode);
+ emit_move_insn_1 (operands[0], operands[1]);
+ DONE;
+ }
+ operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
+ }
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (DFmode, operands[1]);
})
return "fstp%z0\t%y0";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "fmov")
;
else
{
- rtx temp = assign_386_stack_local (SFmode, 0);
+ rtx temp = assign_386_stack_local (SFmode, SLOT_TEMP);
emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
DONE;
}
case 2:
return "cvtsd2ss\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "fmov,fmov,ssecvt")
case 2:
return "cvtsd2ss\t{%1, %0|%0, %1}";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "fmov,multi,ssecvt")
+ (set_attr "unit" "*,i387,*")
(set_attr "mode" "SF")])
(define_insn "*truncdfsf_i387"
case 1:
return "#";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "fmov,multi")
+ (set_attr "unit" "*,i387")
+ (set_attr "mode" "SF")])
+
+(define_insn "*truncdfsf2_i387_1"
+ [(set (match_operand:SF 0 "memory_operand" "=m")
+ (float_truncate:SF
+ (match_operand:DF 1 "register_operand" "f")))]
+ "TARGET_80387
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)
+ && !TARGET_MIX_SSE_I387"
+{
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
+ else
+ return "fst%z0\t%y0";
+}
+ [(set_attr "type" "fmov")
(set_attr "mode" "SF")])
(define_split
DONE;
}
else
- operands[2] = assign_386_stack_local (SFmode, 0);
+ operands[2] = assign_386_stack_local (SFmode, SLOT_TEMP);
})
(define_insn "*truncxfsf2_mixed"
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_MIX_SSE_I387"
{
- switch (which_alternative)
- {
- case 0:
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0";
- else
- return "fst%z0\t%y0";
- default:
- abort();
- }
+ gcc_assert (!which_alternative);
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
+ else
+ return "fst%z0\t%y0";
}
[(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "SF")])
(define_insn "truncxfsf2_i387_noop"
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m"))]
"TARGET_80387"
{
- switch (which_alternative)
- {
- case 0:
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0";
- else
- return "fst%z0\t%y0";
- default:
- abort ();
- }
+ gcc_assert (!which_alternative);
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
+ else
+ return "fst%z0\t%y0";
}
[(set_attr "type" "fmov,multi,multi")
+ (set_attr "unit" "*,i387,i387")
(set_attr "mode" "SF")])
(define_insn "*truncxfsf2_i387_1"
DONE;
}
else
- operands[2] = assign_386_stack_local (DFmode, 0);
+ operands[2] = assign_386_stack_local (DFmode, SLOT_TEMP);
})
(define_insn "*truncxfdf2_mixed"
(clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_SSE2 && TARGET_MIX_SSE_I387"
{
- switch (which_alternative)
- {
- case 0:
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0";
- else
- return "fst%z0\t%y0";
- default:
- abort();
- }
- abort ();
+ gcc_assert (!which_alternative);
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
+ else
+ return "fst%z0\t%y0";
}
[(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "unit" "*,i387,i387,i387")
(set_attr "mode" "DF")])
(define_insn "truncxfdf2_i387_noop"
(clobber (match_operand:DF 2 "memory_operand" "=X,m,m"))]
"TARGET_80387"
{
- switch (which_alternative)
- {
- case 0:
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0";
- else
- return "fst%z0\t%y0";
- default:
- abort ();
- }
+ gcc_assert (!which_alternative);
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
+ else
+ return "fst%z0\t%y0";
}
[(set_attr "type" "fmov,multi,multi")
+ (set_attr "unit" "*,i387,i387")
(set_attr "mode" "DF")])
(define_insn "*truncxfdf2_i387_1"
[(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
"")
\f
-;; %%% Break up all these bad boys.
-
;; Signed conversion to DImode.
(define_expand "fix_truncxfdi2"
(fix:DI (match_operand:XF 1 "register_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
- "")
+{
+ if (TARGET_FISTTP)
+ {
+ emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
+ DONE;
+ }
+})
-(define_expand "fix_truncdfdi2"
+(define_expand "fix_trunc<mode>di2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (fix:DI (match_operand:DF 1 "register_operand" "")))
+ (fix:DI (match_operand:SSEMODEF 1 "register_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2)"
+ "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
{
- if (TARGET_64BIT && TARGET_SSE2)
+ if (TARGET_FISTTP
+ && !(TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
+ {
+ emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
+ DONE;
+ }
+ if (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))
{
rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
- emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
+ emit_insn (gen_fix_trunc<mode>di_sse (out, operands[1]));
if (out != operands[0])
emit_move_insn (operands[0], out);
DONE;
}
})
-(define_expand "fix_truncsfdi2"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (fix:DI (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 || (TARGET_64BIT && TARGET_SSE)"
+;; Signed conversion to SImode.
+
+(define_expand "fix_truncxfsi2"
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (fix:SI (match_operand:XF 1 "register_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_80387"
{
- if (TARGET_64BIT && TARGET_SSE)
+ if (TARGET_FISTTP)
{
- rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
- emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
+ emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
+ DONE;
+ }
+})
+
+(define_expand "fix_trunc<mode>si2"
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
+ (fix:SI (match_operand:SSEMODEF 1 "register_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
+{
+ if (TARGET_FISTTP
+ && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
+ {
+ emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
+ DONE;
+ }
+ if (SSE_FLOAT_MODE_P (<MODE>mode))
+ {
+ rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
+ emit_insn (gen_fix_trunc<mode>si_sse (out, operands[1]));
if (out != operands[0])
emit_move_insn (operands[0], out);
DONE;
}
})
-;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
-;; of the machinery.
-(define_insn_and_split "*fix_truncdi_i387"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
- (fix:DI (match_operand 1 "register_operand" "f,f")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && !reload_completed && !reload_in_progress
- && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- ix86_optimize_mode_switching = 1;
- operands[2] = assign_386_stack_local (HImode, 1);
- operands[3] = assign_386_stack_local (HImode, 2);
- if (memory_operand (operands[0], VOIDmode))
- emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
- operands[2], operands[3]));
- else
- {
- operands[4] = assign_386_stack_local (DImode, 0);
- emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
- }
- DONE;
-}
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "trunc")
- (set_attr "mode" "DI")])
+;; Signed conversion to HImode.
-(define_insn "fix_truncdi_nomemory"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
- (fix:DI (match_operand 1 "register_operand" "f,f")))
- (use (match_operand:HI 2 "memory_operand" "m,m"))
- (use (match_operand:HI 3 "memory_operand" "m,m"))
- (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
- (clobber (match_scratch:DF 5 "=&1f,&1f"))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
- "#"
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "trunc")
- (set_attr "mode" "DI")])
-
-(define_insn "fix_truncdi_memory"
- [(set (match_operand:DI 0 "memory_operand" "=m")
- (fix:DI (match_operand 1 "register_operand" "f")))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))
- (clobber (match_scratch:DF 4 "=&1f"))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
- "* return output_fix_trunc (insn, operands);"
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "trunc")
- (set_attr "mode" "DI")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
- (use (match_dup 2))
- (use (match_dup 3))
- (clobber (match_dup 5))])
- (set (match_dup 0) (match_dup 4))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (fix:DI (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
- (use (match_dup 2))
- (use (match_dup 3))
- (clobber (match_dup 5))])]
- "")
+(define_expand "fix_trunc<mode>hi2"
+ [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
+ (fix:HI (match_operand:X87MODEF 1 "register_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_80387
+ && !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))"
+{
+ if (TARGET_FISTTP)
+ {
+ emit_insn (gen_fix_trunchi_fisttp_i387_1 (operands[0], operands[1]));
+ DONE;
+ }
+})
-;; When SSE available, it is always faster to use it!
+;; When SSE is available, it is always faster to use it!
(define_insn "fix_truncsfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
- "TARGET_64BIT && TARGET_SSE"
+ "TARGET_64BIT && TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)"
"cvttss2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "SF")
(set_attr "athlon_decode" "double,vector")])
-;; Avoid vector decoded form of the instruction.
-(define_peephole2
- [(match_scratch:SF 2 "x")
- (set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:SF 1 "memory_operand" "")))]
- "TARGET_K8 && !optimize_size"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0) (fix:DI (match_dup 2)))]
- "")
-
(define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
- "TARGET_64BIT && TARGET_SSE2"
+ "TARGET_64BIT && TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
"cvttsd2si{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt,sseicvt")
+ [(set_attr "type" "sseicvt")
+ (set_attr "mode" "DF")
+ (set_attr "athlon_decode" "double,vector")])
+
+(define_insn "fix_truncsfsi_sse"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
+ "TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)"
+ "cvttss2si\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sseicvt")
+ (set_attr "mode" "DF")
+ (set_attr "athlon_decode" "double,vector")])
+
+(define_insn "fix_truncdfsi_sse"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
+ "TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
+ "cvttsd2si\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,vector")])
-;; Avoid vector decoded form of the instruction.
+;; Avoid vector decoded forms of the instruction.
(define_peephole2
[(match_scratch:DF 2 "Y")
- (set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand:DF 1 "memory_operand" "")))]
- "TARGET_K8 && !optimize_size"
+ (set (match_operand:SSEMODEI24 0 "register_operand" "")
+ (fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
[(set (match_dup 2) (match_dup 1))
- (set (match_dup 0) (fix:DI (match_dup 2)))]
+ (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
-;; Signed conversion to SImode.
-
-(define_expand "fix_truncxfsi2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (fix:SI (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387"
+(define_peephole2
+ [(match_scratch:SF 2 "x")
+ (set (match_operand:SSEMODEI24 0 "register_operand" "")
+ (fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
-(define_expand "fix_truncdfsi2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (fix:SI (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 || TARGET_SSE2"
+(define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
+ [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
+ (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))]
+ "TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
+ && (TARGET_64BIT || <MODE>mode != DImode))
+ && TARGET_SSE_MATH)
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
- if (TARGET_SSE2)
- {
- rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
- emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
- if (out != operands[0])
- emit_move_insn (operands[0], out);
- DONE;
- }
-})
+ if (memory_operand (operands[0], VOIDmode))
+ emit_insn (gen_fix_trunc<mode>_i387_fisttp (operands[0], operands[1]));
+ else
+ {
+ operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
+ emit_insn (gen_fix_trunc<mode>_i387_fisttp_with_temp (operands[0],
+ operands[1],
+ operands[2]));
+ }
+ DONE;
+}
+ [(set_attr "type" "fisttp")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fix_trunc<mode>_i387_fisttp"
+ [(set (match_operand:X87MODEI 0 "memory_operand" "=m")
+ (fix:X87MODEI (match_operand 1 "register_operand" "f")))
+ (clobber (match_scratch:XF 2 "=&1f"))]
+ "TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
+ && (TARGET_64BIT || <MODE>mode != DImode))
+ && TARGET_SSE_MATH)"
+ "* return output_fix_trunc (insn, operands, 1);"
+ [(set_attr "type" "fisttp")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fix_trunc<mode>_i387_fisttp_with_temp"
+ [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
+ (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))
+ (clobber (match_operand:X87MODEI 2 "memory_operand" "=m,m"))
+ (clobber (match_scratch:XF 3 "=&1f,&1f"))]
+ "TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
+ && (TARGET_64BIT || <MODE>mode != DImode))
+ && TARGET_SSE_MATH)"
+ "#"
+ [(set_attr "type" "fisttp")
+ (set_attr "mode" "<MODE>")])
-(define_expand "fix_truncsfsi2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (fix:SI (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 || TARGET_SSE"
-{
- if (TARGET_SSE)
- {
- rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
- emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
- if (out != operands[0])
- emit_move_insn (operands[0], out);
- DONE;
- }
-})
+(define_split
+ [(set (match_operand:X87MODEI 0 "register_operand" "")
+ (fix:X87MODEI (match_operand 1 "register_operand" "")))
+ (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
+ (clobber (match_scratch 3 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 2) (fix:X87MODEI (match_dup 1)))
+ (clobber (match_dup 3))])
+ (set (match_dup 0) (match_dup 2))]
+ "")
+
+(define_split
+ [(set (match_operand:X87MODEI 0 "memory_operand" "")
+ (fix:X87MODEI (match_operand 1 "register_operand" "")))
+ (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
+ (clobber (match_scratch 3 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (fix:X87MODEI (match_dup 1)))
+ (clobber (match_dup 3))])]
+ "")
;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
-;; of the machinery.
-(define_insn_and_split "*fix_truncsi_i387"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
- (fix:SI (match_operand 1 "register_operand" "f,f")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && !reload_completed && !reload_in_progress
- && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
+;; of the machinery. Please note the clobber of FLAGS_REG. In i387 control
+;; word calculation (inserted by LCM in mode switching pass) a FLAGS_REG
+;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
+;; function in i386.c.
+(define_insn_and_split "*fix_trunc<mode>_i387_1"
+ [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
+ (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_80387 && !TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && !(SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
+ && (TARGET_64BIT || <MODE>mode != DImode))
+ && !(reload_completed || reload_in_progress)"
"#"
"&& 1"
[(const_int 0)]
{
- ix86_optimize_mode_switching = 1;
- operands[2] = assign_386_stack_local (HImode, 1);
- operands[3] = assign_386_stack_local (HImode, 2);
+ ix86_optimize_mode_switching[I387_TRUNC] = 1;
+
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
if (memory_operand (operands[0], VOIDmode))
- emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
- operands[2], operands[3]));
+ emit_insn (gen_fix_trunc<mode>_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
else
{
- operands[4] = assign_386_stack_local (SImode, 0);
- emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
+ operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
+ emit_insn (gen_fix_trunc<mode>_i387_with_temp (operands[0], operands[1],
+ operands[2], operands[3],
+ operands[4]));
}
DONE;
}
[(set_attr "type" "fistp")
(set_attr "i387_cw" "trunc")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "fix_truncsi_nomemory"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
- (fix:SI (match_operand 1 "register_operand" "f,f")))
- (use (match_operand:HI 2 "memory_operand" "m,m"))
- (use (match_operand:HI 3 "memory_operand" "m,m"))
- (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
- "#"
+(define_insn "fix_truncdi_i387"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (fix:DI (match_operand 1 "register_operand" "f")))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))
+ (clobber (match_scratch:XF 4 "=&1f"))]
+ "TARGET_80387 && !TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
+ "* return output_fix_trunc (insn, operands, 0);"
[(set_attr "type" "fistp")
(set_attr "i387_cw" "trunc")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "DI")])
-(define_insn "fix_truncsi_memory"
- [(set (match_operand:SI 0 "memory_operand" "=m")
- (fix:SI (match_operand 1 "register_operand" "f")))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
- "* return output_fix_trunc (insn, operands);"
+(define_insn "fix_truncdi_i387_with_temp"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
+ (fix:DI (match_operand 1 "register_operand" "f,f")))
+ (use (match_operand:HI 2 "memory_operand" "m,m"))
+ (use (match_operand:HI 3 "memory_operand" "m,m"))
+ (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
+ (clobber (match_scratch:XF 5 "=&1f,&1f"))]
+ "TARGET_80387 && !TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
+ && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
+ "#"
[(set_attr "type" "fistp")
(set_attr "i387_cw" "trunc")
- (set_attr "mode" "SI")])
-
-;; When SSE available, it is always faster to use it!
-(define_insn "fix_truncsfsi_sse"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
- "TARGET_SSE"
- "cvttss2si\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
- (set_attr "athlon_decode" "double,vector")])
-
-;; Avoid vector decoded form of the instruction.
-(define_peephole2
- [(match_scratch:SF 2 "x")
- (set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand:SF 1 "memory_operand" "")))]
- "TARGET_K8 && !optimize_size"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0) (fix:SI (match_dup 2)))]
- "")
-
-(define_insn "fix_truncdfsi_sse"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
- "TARGET_SSE2"
- "cvttsd2si\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
- (set_attr "athlon_decode" "double,vector")])
-
-;; Avoid vector decoded form of the instruction.
-(define_peephole2
- [(match_scratch:DF 2 "Y")
- (set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand:DF 1 "memory_operand" "")))]
- "TARGET_K8 && !optimize_size"
- [(set (match_dup 2) (match_dup 1))
- (set (match_dup 0) (fix:SI (match_dup 2)))]
- "")
+ (set_attr "mode" "DI")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (fix:SI (match_operand 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "register_operand" "")
+ (fix:DI (match_operand 1 "register_operand" "")))
(use (match_operand:HI 2 "memory_operand" ""))
(use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SI 4 "memory_operand" ""))]
+ (clobber (match_operand:DI 4 "memory_operand" ""))
+ (clobber (match_scratch 5 ""))]
"reload_completed"
- [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
+ [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
(use (match_dup 2))
- (use (match_dup 3))])
+ (use (match_dup 3))
+ (clobber (match_dup 5))])
(set (match_dup 0) (match_dup 4))]
"")
(define_split
- [(set (match_operand:SI 0 "memory_operand" "")
- (fix:SI (match_operand 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "memory_operand" "")
+ (fix:DI (match_operand 1 "register_operand" "")))
(use (match_operand:HI 2 "memory_operand" ""))
(use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SI 4 "memory_operand" ""))]
+ (clobber (match_operand:DI 4 "memory_operand" ""))
+ (clobber (match_scratch 5 ""))]
"reload_completed"
- [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
+ [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
(use (match_dup 2))
- (use (match_dup 3))])]
- "")
-
-;; Signed conversion to HImode.
-
-(define_expand "fix_truncxfhi2"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (fix:HI (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387"
- "")
-
-(define_expand "fix_truncdfhi2"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (fix:HI (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 && !TARGET_SSE2"
- "")
-
-(define_expand "fix_truncsfhi2"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (fix:HI (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 && !TARGET_SSE"
+ (use (match_dup 3))
+ (clobber (match_dup 5))])]
"")
-;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
-;; of the machinery.
-(define_insn_and_split "*fix_trunchi_i387"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
- (fix:HI (match_operand 1 "register_operand" "f,f")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && !reload_completed && !reload_in_progress
+(define_insn "fix_trunc<mode>_i387"
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
+ (fix:X87MODEI12 (match_operand 1 "register_operand" "f")))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
+ "TARGET_80387 && !TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- ix86_optimize_mode_switching = 1;
- operands[2] = assign_386_stack_local (HImode, 1);
- operands[3] = assign_386_stack_local (HImode, 2);
- if (memory_operand (operands[0], VOIDmode))
- emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
- operands[2], operands[3]));
- else
- {
- operands[4] = assign_386_stack_local (HImode, 0);
- emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
- }
- DONE;
-}
+ "* return output_fix_trunc (insn, operands, 0);"
[(set_attr "type" "fistp")
(set_attr "i387_cw" "trunc")
- (set_attr "mode" "HI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "fix_trunchi_nomemory"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
- (fix:HI (match_operand 1 "register_operand" "f,f")))
+(define_insn "fix_trunc<mode>_i387_with_temp"
+ [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
+ (fix:X87MODEI12 (match_operand 1 "register_operand" "f,f")))
(use (match_operand:HI 2 "memory_operand" "m,m"))
(use (match_operand:HI 3 "memory_operand" "m,m"))
- (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
+ "TARGET_80387 && !TARGET_FISTTP
+ && FLOAT_MODE_P (GET_MODE (operands[1]))
&& !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
"#"
[(set_attr "type" "fistp")
(set_attr "i387_cw" "trunc")
- (set_attr "mode" "HI")])
-
-(define_insn "fix_trunchi_memory"
- [(set (match_operand:HI 0 "memory_operand" "=m")
- (fix:HI (match_operand 1 "register_operand" "f")))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))]
- "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
- && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
- "* return output_fix_trunc (insn, operands);"
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "trunc")
- (set_attr "mode" "HI")])
+ (set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:HI 0 "memory_operand" "")
- (fix:HI (match_operand 1 "register_operand" "")))
+ [(set (match_operand:X87MODEI12 0 "register_operand" "")
+ (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
(use (match_operand:HI 2 "memory_operand" ""))
(use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:HI 4 "memory_operand" ""))]
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
"reload_completed"
- [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
+ [(parallel [(set (match_dup 4) (fix:X87MODEI12 (match_dup 1)))
(use (match_dup 2))
- (use (match_dup 3))])]
+ (use (match_dup 3))])
+ (set (match_dup 0) (match_dup 4))]
"")
(define_split
- [(set (match_operand:HI 0 "register_operand" "")
- (fix:HI (match_operand 1 "register_operand" "")))
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "")
+ (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
(use (match_operand:HI 2 "memory_operand" ""))
(use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:HI 4 "memory_operand" ""))]
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
"reload_completed"
- [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
+ [(parallel [(set (match_dup 0) (fix:X87MODEI12 (match_dup 1)))
(use (match_dup 2))
- (use (match_dup 3))
- (clobber (match_dup 4))])
- (set (match_dup 0) (match_dup 4))]
+ (use (match_dup 3))])]
"")
(define_insn "x86_fnstcw_1"
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "SF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floatsisf2"
cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "SF")
+ (set_attr "unit" "*,i387,*,*")
(set_attr "athlon_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")])
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "SF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floatdisf2"
cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "SF")
+ (set_attr "unit" "*,i387,*,*")
(set_attr "athlon_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")])
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "SF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floathidf2"
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "DF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floatsidf2"
cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "DF")
+ (set_attr "unit" "*,i387,*,*")
(set_attr "athlon_decode" "*,*,double,direct")
(set_attr "fp_int_src" "true")])
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "DF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_expand "floatdidf2"
cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "DF")
+ (set_attr "unit" "*,i387,*,*")
(set_attr "athlon_decode" "*,*,double,direct")
(set_attr "fp_int_src" "true")])
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "DF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_insn "floathixf2"
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_insn "floatsixf2"
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
(define_insn "floatdixf2"
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
+ (set_attr "unit" "*,i387")
(set_attr "fp_int_src" "true")])
;; %%% Kill these when reload knows how to do it.
\f
;; Add instructions
-;; %%% splits for addsidi3
-; [(set (match_operand:DI 0 "nonimmediate_operand" "")
-; (plus:DI (match_operand:DI 1 "general_operand" "")
-; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
+;; %%% splits for addditi3
-(define_expand "adddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "x86_64_general_operand" "")))
+(define_expand "addti3"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
+ (match_operand:TI 2 "x86_64_general_operand" "")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "ix86_expand_binary_operator (PLUS, TImode, operands); DONE;")
+
+(define_insn "*addti3_1"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
+ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:TI 2 "general_operand" "roiF,riF")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, TImode, operands)"
+ "#")
+
+(define_split
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
+ (match_operand:TI 2 "general_operand" "")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
+ UNSPEC_ADD_CARRY))
+ (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))])
+ (parallel [(set (match_dup 3)
+ (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
+ (match_dup 4))
+ (match_dup 5)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_ti (operands+0, 1, operands+0, operands+3);
+ split_ti (operands+1, 1, operands+1, operands+4);
+ split_ti (operands+2, 1, operands+2, operands+5);")
+
+;; %%% splits for addsidi3
+; [(set (match_operand:DI 0 "nonimmediate_operand" "")
+; (plus:DI (match_operand:DI 1 "general_operand" "")
+; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
+
+(define_expand "adddi3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ (match_operand:DI 2 "x86_64_general_operand" "")))
(clobber (reg:CC FLAGS_REG))]
""
"ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
return "lea{q}\t{%a2, %0|%0, %a2}";
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{q}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{q}\t%0";
else
- abort ();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{q}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{q}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{q}\t%0";
else
- abort ();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{q}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* ???? We ought to handle there the 32bit case too
- do we need new constraint? */
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{q}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{q}\t%0";
else
- abort ();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{q}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* ???? We ought to handle there the 32bit case too
- do we need new constraint? */
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == constm1_rtx)
return "inc{q}\t%0";
- else if (operands[2] == const1_rtx)
- return "dec{q}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{q}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if ((INTVAL (operands[2]) == -128
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{q}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{q}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{q}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
return "lea{l}\t{%a2, %0|%0, %a2}";
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{l}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{l}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{l}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{l}\t%k0";
- else if (operands[2] == constm1_rtx)
- return "dec{l}\t%k0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{l}\t%k0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{l}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{l}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{l}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{l}\t%k0";
- else if (operands[2] == constm1_rtx)
- return "dec{l}\t%k0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{l}\t%k0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{l}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{l}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{l}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{l}\t%k0";
- else if (operands[2] == constm1_rtx)
- return "dec{l}\t%k0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{l}\t%k0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == constm1_rtx)
return "inc{l}\t%0";
- else if (operands[2] == const1_rtx)
- return "dec{l}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{l}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if ((INTVAL (operands[2]) == -128
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (operands[2] == const1_rtx)
return "inc{l}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{l}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{l}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if (GET_CODE (operands[2]) == CONST_INT
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{w}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{w}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{w}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{w}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{w}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{w}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{w}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{w}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{w}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{w}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{w}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{w}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == constm1_rtx)
return "inc{w}\t%0";
- else if (operands[2] == const1_rtx)
- return "dec{w}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{w}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
Exceptions: -128 encodes smaller than 128, so swap sign and op. */
if ((INTVAL (operands[2]) == -128
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{w}\t%0";
- else if (operands[2] == constm1_rtx)
- return "dec{w}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return "dec{w}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
- else if (operands[2] == constm1_rtx)
- return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
- else if (operands[2] == constm1_rtx)
- return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx);
+ return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
case TYPE_INCDEC:
if (operands[1] == const1_rtx)
return "inc{b}\t%0";
- else if (operands[1] == constm1_rtx)
- return "dec{b}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[1] == constm1_rtx);
+ return "dec{b}\t%0";
+ }
default:
/* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{b}\t%0";
- else if (operands[2] == constm1_rtx
- || (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == 255))
- return "dec{b}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx
+ || (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%0";
+ }
default:
/* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{b}\t%0";
- else if (operands[2] == constm1_rtx
- || (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == 255))
- return "dec{b}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx
+ || (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%0";
+ }
default:
/* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
return "inc{b}\t%0";
- else if (operands[2] == const1_rtx)
- return "dec{b}\t%0";
else
- abort();
+ {
+ gcc_assert (operands[2] == const1_rtx);
+ return "dec{b}\t%0";
+ }
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{b}\t%0";
- else if (operands[2] == constm1_rtx
- || (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == 255))
- return "dec{b}\t%0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx
+ || (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%0";
+ }
default:
/* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{b}\t%h0";
- else if (operands[2] == constm1_rtx
- || (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == 255))
- return "dec{b}\t%h0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx
+ || (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%h0";
+ }
default:
return "add{b}\t{%2, %h0|%h0, %2}";
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return "inc{b}\t%h0";
- else if (operands[2] == constm1_rtx
- || (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) == 255))
- return "dec{b}\t%h0";
- abort();
+ else
+ {
+ gcc_assert (operands[2] == constm1_rtx
+ || (GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == 255));
+ return "dec{b}\t%h0";
+ }
default:
return "add{b}\t{%2, %h0|%h0, %2}";
\f
;; Subtract instructions
+;; %%% splits for subditi3
+
+(define_expand "subti3"
+ [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
+ (match_operand:TI 2 "x86_64_general_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT"
+ "ix86_expand_binary_operator (MINUS, TImode, operands); DONE;")
+
+(define_insn "*subti3_1"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
+ (minus:TI (match_operand:TI 1 "nonimmediate_operand" "0,0")
+ (match_operand:TI 2 "general_operand" "roiF,riF")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && ix86_binary_operator_ok (MINUS, TImode, operands)"
+ "#")
+
+(define_split
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
+ (match_operand:TI 2 "general_operand" "")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
+ (set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))])
+ (parallel [(set (match_dup 3)
+ (minus:DI (match_dup 4)
+ (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
+ (match_dup 5))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_ti (operands+0, 1, operands+0, operands+3);
+ split_ti (operands+1, 1, operands+1, operands+4);
+ split_ti (operands+2, 1, operands+2, operands+5);")
+
;; %%% splits for subsidi3
(define_expand "subdi3"
}
else
{
- if (true_regnum (operands[1]))
- abort();
+ gcc_assert (!true_regnum (operands[1]));
operands[4] = operands[1];
}
})
}
else
{
- if (true_regnum (operands[1]))
- abort();
+ gcc_assert (!true_regnum (operands[1]));
operands[4] = operands[1];
}
})
(match_operand:SI 2 "const_int_operand" ""))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)
+ && INTVAL (operands[1]) > 0
+ && INTVAL (operands[2]) >= 0
+ && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
&& (GET_MODE (operands[0]) == SImode
|| (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
|| GET_MODE (operands[0]) == HImode
(const_int 0)))]
"TARGET_64BIT
&& ix86_match_ccmode (insn, CCNOmode)
- /* The code below cannot deal with constants outside HOST_WIDE_INT. */
- && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
+ && INTVAL (operands[1]) > 0
+ && INTVAL (operands[2]) >= 0
/* Ensure that resulting mask is zero or sign extended operand. */
&& (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
|| (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
val = gen_lowpart (QImode, val);
}
- mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
- mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
+ if (len == HOST_BITS_PER_WIDE_INT)
+ mask = -1;
+ else
+ mask = ((HOST_WIDE_INT)1 << len) - 1;
+ mask <<= pos;
operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
})
{
enum machine_mode mode;
- if (GET_CODE (operands[2]) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
if (INTVAL (operands[2]) == 0xff)
mode = QImode;
- else if (INTVAL (operands[2]) == 0xffff)
- mode = HImode;
else
- abort ();
+ {
+ gcc_assert (INTVAL (operands[2]) == 0xffff);
+ mode = HImode;
+ }
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
}
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (get_attr_mode (insn) == MODE_SI)
return "and{l}\t{%k2, %k0|%k0, %k2}";
else
{
enum machine_mode mode;
- if (GET_CODE (operands[2]) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
if (INTVAL (operands[2]) == 0xff)
mode = QImode;
- else if (INTVAL (operands[2]) == 0xffff)
- mode = HImode;
else
- abort ();
+ {
+ gcc_assert (INTVAL (operands[2]) == 0xffff);
+ mode = HImode;
+ }
operands[1] = gen_lowpart (mode, operands[1]);
if (mode == QImode)
}
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "and{l}\t{%2, %0|%0, %2}";
}
}
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- if (GET_CODE (operands[2]) != CONST_INT)
- abort ();
- if (INTVAL (operands[2]) == 0xff)
- return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
- abort ();
+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+ gcc_assert (INTVAL (operands[2]) == 0xff);
+ return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
default:
- if (! rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "and{w}\t{%2, %0|%0, %2}";
}
\f
;; Negation instructions
+(define_expand "negti2"
+ [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (neg:TI (match_operand:TI 1 "nonimmediate_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT"
+ "ix86_expand_unary_operator (NEG, TImode, operands); DONE;")
+
+(define_insn "*negti2_1"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=ro")
+ (neg:TI (match_operand:TI 1 "general_operand" "0")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT
+ && ix86_unary_operator_ok (NEG, TImode, operands)"
+ "#")
+
+(define_split
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (neg:TI (match_operand:TI 1 "general_operand" "")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(parallel
+ [(set (reg:CCZ FLAGS_REG)
+ (compare:CCZ (neg:DI (match_dup 2)) (const_int 0)))
+ (set (match_dup 0) (neg:DI (match_dup 2)))])
+ (parallel
+ [(set (match_dup 1)
+ (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
+ (match_dup 3))
+ (const_int 0)))
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel
+ [(set (match_dup 1)
+ (neg:DI (match_dup 1)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_ti (operands+1, 1, operands+2, operands+3);
+ split_ti (operands+0, 1, operands+0, operands+1);")
+
(define_expand "negdi2"
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
"ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
(define_insn "*absnegsf2_mixed"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=x#f,x#f,f#x,rm")
(match_operator:SF 3 "absneg_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#fr,0 ,0")]))
- (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X ,X"))
+ [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#f,0 ,0")]))
+ (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X ,X"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
"#")
(define_insn "*absnegsf2_sse"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x#r,x#r,rm#x")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,rm")
(match_operator:SF 3 "absneg_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#r,0")]))
- (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X"))
+ [(match_operand:SF 1 "nonimmediate_operand" "0 ,x,0")]))
+ (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,X"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_SSE_MATH
&& ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
"#")
(define_insn "*absnegsf2_i387"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,rm")
(match_operator:SF 3 "absneg_operator"
[(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
(use (match_operand 2 "" ""))
"#")
(define_expand "copysignsf3"
- [(parallel [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_operand:SF 1 "register_operand" "")
- (match_dup 4)
- (match_operand:SF 2 "register_operand" "")
- (match_dup 5)]
- UNSPEC_COPYSIGN))
- (clobber (match_scratch:V4SF 3 ""))])]
+ [(match_operand:SF 0 "register_operand" "")
+ (match_operand:SF 1 "nonmemory_operand" "")
+ (match_operand:SF 2 "register_operand" "")]
+ "TARGET_SSE_MATH"
+{
+ ix86_expand_copysign (operands);
+ DONE;
+})
+
+(define_insn_and_split "copysignsf3_const"
+ [(set (match_operand:SF 0 "register_operand" "=x")
+ (unspec:SF
+ [(match_operand:V4SF 1 "vector_move_operand" "xmC")
+ (match_operand:SF 2 "register_operand" "0")
+ (match_operand:V4SF 3 "nonimmediate_operand" "xm")]
+ UNSPEC_COPYSIGN))]
"TARGET_SSE_MATH"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
{
- operands[4] = ix86_build_signbit_mask (SFmode, 0, 1);
- operands[5] = ix86_build_signbit_mask (SFmode, 0, 0);
+ ix86_split_copysign_const (operands);
+ DONE;
})
-(define_insn_and_split "*copysignsf3"
+(define_insn "copysignsf3_var"
[(set (match_operand:SF 0 "register_operand" "=x, x, x, x,x")
(unspec:SF
[(match_operand:SF 2 "register_operand" " x, 0, 0, x,x")
- (match_operand:V4SF 3 "nonimmediate_operand" " X,xm,xm, 0,0")
- (match_operand:SF 4 "register_operand" " 1, 1, x, 1,x")
+ (match_operand:SF 3 "register_operand" " 1, 1, x, 1,x")
+ (match_operand:V4SF 4 "nonimmediate_operand" " X,xm,xm, 0,0")
(match_operand:V4SF 5 "nonimmediate_operand" " 0,xm, 1,xm,1")]
UNSPEC_COPYSIGN))
(clobber (match_scratch:V4SF 1 "=x, x, x, x,x"))]
"TARGET_SSE_MATH"
- "#"
- "&& reload_completed"
+ "#")
+
+(define_split
+ [(set (match_operand:SF 0 "register_operand" "")
+ (unspec:SF
+ [(match_operand:SF 2 "register_operand" "")
+ (match_operand:SF 3 "register_operand" "")
+ (match_operand:V4SF 4 "" "")
+ (match_operand:V4SF 5 "" "")]
+ UNSPEC_COPYSIGN))
+ (clobber (match_scratch:V4SF 1 ""))]
+ "TARGET_SSE_MATH && reload_completed"
[(const_int 0)]
{
- ix86_split_copysign (operands);
+ ix86_split_copysign_var (operands);
DONE;
})
"ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
(define_insn "*absnegdf2_mixed"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,f#Y,rm")
(match_operator:DF 3 "absneg_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#fr,0 ,0")]))
- (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X ,X"))
+ [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#f,0 ,0")]))
+ (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X ,X"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
"#")
(define_insn "*absnegdf2_sse"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#r,Y#r,rm#Y")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,Y,rm")
(match_operator:DF 3 "absneg_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#r,0")]))
- (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X"))
+ [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y,0")]))
+ (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,X"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
"#")
(define_insn "*absnegdf2_i387"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,rm")
(match_operator:DF 3 "absneg_operator"
[(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
(use (match_operand 2 "" ""))
"#")
(define_expand "copysigndf3"
- [(parallel [(set (match_operand:DF 0 "register_operand" "")
- (unspec:DF [(match_operand:DF 1 "register_operand" "")
- (match_dup 4)
- (match_operand:DF 2 "register_operand" "")
- (match_dup 5)]
- UNSPEC_COPYSIGN))
- (clobber (match_scratch:V2DF 3 ""))])]
+ [(match_operand:DF 0 "register_operand" "")
+ (match_operand:DF 1 "nonmemory_operand" "")
+ (match_operand:DF 2 "register_operand" "")]
+ "TARGET_SSE2 && TARGET_SSE_MATH"
+{
+ ix86_expand_copysign (operands);
+ DONE;
+})
+
+(define_insn_and_split "copysigndf3_const"
+ [(set (match_operand:DF 0 "register_operand" "=x")
+ (unspec:DF
+ [(match_operand:V2DF 1 "vector_move_operand" "xmC")
+ (match_operand:DF 2 "register_operand" "0")
+ (match_operand:V2DF 3 "nonimmediate_operand" "xm")]
+ UNSPEC_COPYSIGN))]
"TARGET_SSE2 && TARGET_SSE_MATH"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
{
- operands[4] = ix86_build_signbit_mask (DFmode, 0, 1);
- operands[5] = ix86_build_signbit_mask (DFmode, 0, 0);
+ ix86_split_copysign_const (operands);
+ DONE;
})
-(define_insn_and_split "*copysigndf3"
+(define_insn "copysigndf3_var"
[(set (match_operand:DF 0 "register_operand" "=x, x, x, x,x")
(unspec:DF
[(match_operand:DF 2 "register_operand" " x, 0, 0, x,x")
- (match_operand:V2DF 3 "nonimmediate_operand" " X,xm,xm, 0,0")
- (match_operand:DF 4 "register_operand" " 1, 1, x, 1,x")
+ (match_operand:DF 3 "register_operand" " 1, 1, x, 1,x")
+ (match_operand:V2DF 4 "nonimmediate_operand" " X,xm,xm, 0,0")
(match_operand:V2DF 5 "nonimmediate_operand" " 0,xm, 1,xm,1")]
UNSPEC_COPYSIGN))
(clobber (match_scratch:V2DF 1 "=x, x, x, x,x"))]
"TARGET_SSE2 && TARGET_SSE_MATH"
- "#"
- "&& reload_completed"
+ "#")
+
+(define_split
+ [(set (match_operand:DF 0 "register_operand" "")
+ (unspec:DF
+ [(match_operand:DF 2 "register_operand" "")
+ (match_operand:DF 3 "register_operand" "")
+ (match_operand:V2DF 4 "" "")
+ (match_operand:V2DF 5 "" "")]
+ UNSPEC_COPYSIGN))
+ (clobber (match_scratch:V2DF 1 ""))]
+ "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
[(const_int 0)]
{
- ix86_split_copysign (operands);
+ ix86_split_copysign_var (operands);
DONE;
})
(define_expand "absxf2"
[(set (match_operand:XF 0 "nonimmediate_operand" "")
- (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
+ (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
"TARGET_80387"
"ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
(define_insn "*absnegxf2_i387"
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
+ [(set (match_operand:XF 0 "nonimmediate_operand" "=f,?rm")
(match_operator:XF 3 "absneg_operator"
[(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
(use (match_operand 2 "" ""))
;; shift pair, instead using moves and sign extension for counts greater
;; than 31.
+(define_expand "ashlti3"
+ [(parallel [(set (match_operand:TI 0 "register_operand" "")
+ (ashift:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT"
+{
+ if (! immediate_operand (operands[2], QImode))
+ {
+ emit_insn (gen_ashlti3_1 (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ ix86_expand_binary_operator (ASHIFT, TImode, operands);
+ DONE;
+})
+
+(define_insn "ashlti3_1"
+ [(set (match_operand:TI 0 "register_operand" "=r")
+ (ashift:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:QI 2 "register_operand" "c")))
+ (clobber (match_scratch:DI 3 "=&r"))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "#"
+ [(set_attr "type" "multi")])
+
+(define_insn "*ashlti3_2"
+ [(set (match_operand:TI 0 "register_operand" "=r")
+ (ashift:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "O")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "#"
+ [(set_attr "type" "multi")])
+
+(define_split
+ [(set (match_operand:TI 0 "register_operand" "")
+ (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
+ (match_operand:QI 2 "register_operand" "")))
+ (clobber (match_scratch:DI 3 ""))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(const_int 0)]
+ "ix86_split_ashl (operands, operands[3], TImode); DONE;")
+
+(define_split
+ [(set (match_operand:TI 0 "register_operand" "")
+ (ashift:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "immediate_operand" "")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(const_int 0)]
+ "ix86_split_ashl (operands, NULL_RTX, TImode); DONE;")
+
+(define_insn "x86_64_shld"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
+ (ior:DI (ashift:DI (match_dup 0)
+ (match_operand:QI 2 "nonmemory_operand" "J,c"))
+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
+ (minus:QI (const_int 64) (match_dup 2)))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "@
+ shld{q}\t{%2, %1, %0|%0, %1, %2}
+ shld{q}\t{%s2%1, %0|%0, %1, %2}"
+ [(set_attr "type" "ishift")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")
+ (set_attr "athlon_decode" "vector")])
+
+(define_expand "x86_64_shift_adj"
+ [(set (reg:CCZ FLAGS_REG)
+ (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
+ (const_int 64))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "")
+ (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
+ (match_operand:DI 1 "register_operand" "")
+ (match_dup 0)))
+ (set (match_dup 1)
+ (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
+ (match_operand:DI 3 "register_operand" "r")
+ (match_dup 1)))]
+ "TARGET_64BIT"
+ "")
+
(define_expand "ashldi3"
[(set (match_operand:DI 0 "shiftdi_operand" "")
(ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
- if (!rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "add{q}\t{%0, %0|%0, %0}";
case TYPE_LEA:
- if (GET_CODE (operands[2]) != CONST_INT
- || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
- abort ();
+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+ gcc_assert ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) <= 3);
operands[1] = gen_rtx_MULT (DImode, operands[1],
GEN_INT (1 << INTVAL (operands[2])));
return "lea{q}\t{%a1, %0|%0, %a1}";
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{q}\t{%0, %0|%0, %0}";
default:
(match_dup 3)]
"!TARGET_64BIT && TARGET_CMOVE"
[(const_int 0)]
- "ix86_split_ashldi (operands, operands[3]); DONE;")
+ "ix86_split_ashl (operands, operands[3], DImode); DONE;")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
+ "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? flow2_completed : reload_completed)"
[(const_int 0)]
- "ix86_split_ashldi (operands, NULL_RTX); DONE;")
+ "ix86_split_ashl (operands, NULL_RTX, DImode); DONE;")
(define_insn "x86_shld_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
- if (!rtx_equal_p (operands[0], operands[1]))
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "add{l}\t{%0, %0|%0, %0}";
case TYPE_LEA:
[(const_int 0)]
{
rtx pat, clob;
- emit_move_insn (operands[1], operands[0]);
+ emit_move_insn (operands[0], operands[1]);
pat = gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_ASHIFT (GET_MODE (operands[0]),
operands[0], operands[2]));
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{l}\t{%k0, %k0|%k0, %k0}";
case TYPE_LEA:
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{l}\t{%0, %0|%0, %0}";
default:
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{l}\t{%k0, %k0|%k0, %k0}";
default:
case TYPE_LEA:
return "#";
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{w}\t{%0, %0|%0, %0}";
default:
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{w}\t{%0, %0|%0, %0}";
default:
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{w}\t{%0, %0|%0, %0}";
default:
case TYPE_LEA:
return "#";
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
return "add{l}\t{%k0, %k0|%k0, %k0}";
else
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
return "add{l}\t{%k0, %k0|%k0, %k0}";
else
switch (get_attr_type (insn))
{
case TYPE_ALU:
- if (operands[2] != const1_rtx)
- abort ();
+ gcc_assert (operands[2] == const1_rtx);
return "add{b}\t{%0, %0|%0, %0}";
default:
;; See comment above `ashldi3' about how this works.
-(define_expand "ashrdi3"
- [(set (match_operand:DI 0 "shiftdi_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- ""
- "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
+(define_expand "ashrti3"
+ [(parallel [(set (match_operand:TI 0 "register_operand" "")
+ (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT"
+{
+ if (! immediate_operand (operands[2], QImode))
+ {
+ emit_insn (gen_ashrti3_1 (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ ix86_expand_binary_operator (ASHIFTRT, TImode, operands);
+ DONE;
+})
-(define_insn "*ashrdi3_63_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
- (match_operand:DI 2 "const_int_operand" "i,i")))
+(define_insn "ashrti3_1"
+ [(set (match_operand:TI 0 "register_operand" "=r")
+ (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:QI 2 "register_operand" "c")))
+ (clobber (match_scratch:DI 3 "=&r"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && INTVAL (operands[2]) == 63
- && (TARGET_USE_CLTD || optimize_size)
- && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "@
- {cqto|cqo}
- sar{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "imovx,ishift")
- (set_attr "prefix_0f" "0,*")
- (set_attr "length_immediate" "0,*")
- (set_attr "modrm" "0,1")
+ "TARGET_64BIT"
+ "#"
+ [(set_attr "type" "multi")])
+
+(define_insn "*ashrti3_2"
+ [(set (match_operand:TI 0 "register_operand" "=r")
+ (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "O")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "#"
+ [(set_attr "type" "multi")])
+
+(define_split
+ [(set (match_operand:TI 0 "register_operand" "")
+ (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "register_operand" "")))
+ (clobber (match_scratch:DI 3 ""))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(const_int 0)]
+ "ix86_split_ashr (operands, operands[3], TImode); DONE;")
+
+(define_split
+ [(set (match_operand:TI 0 "register_operand" "")
+ (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "immediate_operand" "")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(const_int 0)]
+ "ix86_split_ashr (operands, NULL_RTX, TImode); DONE;")
+
+(define_insn "x86_64_shrd"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
+ (ior:DI (ashiftrt:DI (match_dup 0)
+ (match_operand:QI 2 "nonmemory_operand" "J,c"))
+ (ashift:DI (match_operand:DI 1 "register_operand" "r,r")
+ (minus:QI (const_int 64) (match_dup 2)))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "@
+ shrd{q}\t{%2, %1, %0|%0, %1, %2}
+ shrd{q}\t{%s2%1, %0|%0, %1, %2}"
+ [(set_attr "type" "ishift")
+ (set_attr "prefix_0f" "1")
+ (set_attr "mode" "DI")
+ (set_attr "athlon_decode" "vector")])
+
+(define_expand "ashrdi3"
+ [(set (match_operand:DI 0 "shiftdi_operand" "")
+ (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ ""
+ "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
+
+(define_insn "*ashrdi3_63_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
+ (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
+ (match_operand:DI 2 "const_int_operand" "i,i")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && INTVAL (operands[2]) == 63
+ && (TARGET_USE_CLTD || optimize_size)
+ && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+ "@
+ {cqto|cqo}
+ sar{q}\t{%2, %0|%0, %2}"
+ [(set_attr "type" "imovx,ishift")
+ (set_attr "prefix_0f" "0,*")
+ (set_attr "length_immediate" "0,*")
+ (set_attr "modrm" "0,1")
(set_attr "mode" "DI")])
(define_insn "*ashrdi3_1_one_bit_rex64"
(match_dup 3)]
"!TARGET_64BIT && TARGET_CMOVE"
[(const_int 0)]
- "ix86_split_ashrdi (operands, operands[3]); DONE;")
+ "ix86_split_ashr (operands, operands[3], DImode); DONE;")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
+ "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? flow2_completed : reload_completed)"
[(const_int 0)]
- "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
+ "ix86_split_ashr (operands, NULL_RTX, DImode); DONE;")
(define_insn "x86_shrd_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
;; See comment above `ashldi3' about how this works.
+(define_expand "lshrti3"
+ [(parallel [(set (match_operand:TI 0 "register_operand" "")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT"
+{
+ if (! immediate_operand (operands[2], QImode))
+ {
+ emit_insn (gen_lshrti3_1 (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+ ix86_expand_binary_operator (LSHIFTRT, TImode, operands);
+ DONE;
+})
+
+(define_insn "lshrti3_1"
+ [(set (match_operand:TI 0 "register_operand" "=r")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:QI 2 "register_operand" "c")))
+ (clobber (match_scratch:DI 3 "=&r"))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "#"
+ [(set_attr "type" "multi")])
+
+(define_insn "*lshrti3_2"
+ [(set (match_operand:TI 0 "register_operand" "=r")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "O")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "#"
+ [(set_attr "type" "multi")])
+
+(define_split
+ [(set (match_operand:TI 0 "register_operand" "")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "register_operand" "")))
+ (clobber (match_scratch:DI 3 ""))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(const_int 0)]
+ "ix86_split_lshr (operands, operands[3], TImode); DONE;")
+
+(define_split
+ [(set (match_operand:TI 0 "register_operand" "")
+ (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:QI 2 "immediate_operand" "")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && reload_completed"
+ [(const_int 0)]
+ "ix86_split_lshr (operands, NULL_RTX, TImode); DONE;")
+
(define_expand "lshrdi3"
[(set (match_operand:DI 0 "shiftdi_operand" "")
(lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
(match_dup 3)]
"!TARGET_64BIT && TARGET_CMOVE"
[(const_int 0)]
- "ix86_split_lshrdi (operands, operands[3]); DONE;")
+ "ix86_split_lshr (operands, operands[3], DImode); DONE;")
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
+ "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
+ ? flow2_completed : reload_completed)"
[(const_int 0)]
- "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
+ "ix86_split_lshr (operands, NULL_RTX, DImode); DONE;")
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
;; Rotate instructions
(define_expand "rotldi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
+ [(set (match_operand:DI 0 "shiftdi_operand" "")
+ (rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
+ ""
+{
+ if (TARGET_64BIT)
+ {
+ ix86_expand_binary_operator (ROTATE, DImode, operands);
+ DONE;
+ }
+ if (!const_1_to_31_operand (operands[2], VOIDmode))
+ FAIL;
+ emit_insn (gen_ix86_rotldi3 (operands[0], operands[1], operands[2]));
+ DONE;
+})
+;; Implement rotation using two double-precision shift instructions
+;; and a scratch register.
+(define_insn_and_split "ix86_rotldi3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (rotate:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_1_to_31_operand" "I")))
+ (clobber (reg:CC FLAGS_REG))
+ (clobber (match_scratch:SI 3 "=&r"))]
+ "!TARGET_64BIT"
+ ""
+ "&& reload_completed"
+ [(set (match_dup 3) (match_dup 4))
+ (parallel
+ [(set (match_dup 4)
+ (ior:SI (ashift:SI (match_dup 4) (match_dup 2))
+ (lshiftrt:SI (match_dup 5)
+ (minus:QI (const_int 32) (match_dup 2)))))
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel
+ [(set (match_dup 5)
+ (ior:SI (ashift:SI (match_dup 5) (match_dup 2))
+ (lshiftrt:SI (match_dup 3)
+ (minus:QI (const_int 32) (match_dup 2)))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_di (operands, 1, operands + 4, operands + 5);")
+
(define_insn "*rotlsi3_1_one_bit_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(set_attr "mode" "QI")])
(define_expand "rotrdi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ [(set (match_operand:DI 0 "shiftdi_operand" "")
+ (rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
+ ""
+{
+ if (TARGET_64BIT)
+ {
+ ix86_expand_binary_operator (ROTATERT, DImode, operands);
+ DONE;
+ }
+ if (!const_1_to_31_operand (operands[2], VOIDmode))
+ FAIL;
+ emit_insn (gen_ix86_rotrdi3 (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+;; Implement rotation using two double-precision shift instructions
+;; and a scratch register.
+(define_insn_and_split "ix86_rotrdi3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (rotatert:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_1_to_31_operand" "I")))
+ (clobber (reg:CC FLAGS_REG))
+ (clobber (match_scratch:SI 3 "=&r"))]
+ "!TARGET_64BIT"
+ ""
+ "&& reload_completed"
+ [(set (match_dup 3) (match_dup 4))
+ (parallel
+ [(set (match_dup 4)
+ (ior:SI (ashiftrt:SI (match_dup 4) (match_dup 2))
+ (ashift:SI (match_dup 5)
+ (minus:QI (const_int 32) (match_dup 2)))))
+ (clobber (reg:CC FLAGS_REG))])
+ (parallel
+ [(set (match_dup 5)
+ (ior:SI (ashiftrt:SI (match_dup 5) (match_dup 2))
+ (ashift:SI (match_dup 3)
+ (minus:QI (const_int 32) (match_dup 2)))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "split_di (operands, 1, operands + 4, operands + 5);")
(define_insn "*rotrdi3_1_one_bit_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
;; subsequent logical operations are used to imitate conditional moves.
;; 0xffffffff is NaN, but not in normalized form, so we can't represent
-;; it directly. Further holding this value in pseudo register might bring
-;; problem in implicit normalization in spill code.
-;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
-;; instructions after reload by splitting the conditional move patterns.
+;; it directly.
(define_insn "*sse_setccsf"
[(set (match_operand:SF 0 "register_operand" "=x")
(match_operator:SF 1 "sse_comparison_operator"
[(match_operand:SF 2 "register_operand" "0")
(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE && reload_completed"
+ "TARGET_SSE"
"cmp%D1ss\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
(set_attr "mode" "SF")])
(match_operator:DF 1 "sse_comparison_operator"
[(match_operand:DF 2 "register_operand" "0")
(match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
- "TARGET_SSE2 && reload_completed"
+ "TARGET_SSE2"
"cmp%D1sd\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
(set_attr "mode" "DF")])
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(match_operand 1 "register_operand" "f")
- (match_operand 2 "const_double_operand" "C")])
+ (match_operand 2 "const0_operand" "X")])
(label_ref (match_operand 3 "" ""))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (match_scratch:HI 4 "=a"))]
"TARGET_80387
&& FLOAT_MODE_P (GET_MODE (operands[1]))
- && operands[2] == CONST0_RTX (GET_MODE (operands[1]))
+ && GET_MODE (operands[1]) == GET_MODE (operands[2])
&& !ix86_use_fcomi_compare (GET_CODE (operands[0]))
&& SELECT_CC_MODE (GET_CODE (operands[0]),
operands[1], operands[2]) == CCFPmode
&& ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
"#")
-;; The order of operands in *fp_jcc_8 is forced by combine in
+;; The order of operands in *fp_jcc_8_387 is forced by combine in
;; simplify_comparison () function. Float operator is treated as RTX_OBJ
;; with a precedence over other operators and is always put in the first
;; place. Swap condition and operands to match ficom instruction.
-(define_insn "*fp_jcc_8_387"
+(define_insn "*fp_jcc_8<mode>_387"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(match_operator 1 "float_operator"
- [(match_operand:SI 2 "nonimmediate_operand" "m,?r")])
+ [(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r")])
(match_operand 3 "register_operand" "f,f")])
(label_ref (match_operand 4 "" ""))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 5 "=a,a"))]
- "TARGET_80387 && TARGET_USE_FIOP
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
&& FLOAT_MODE_P (GET_MODE (operands[3]))
&& GET_MODE (operands[1]) == GET_MODE (operands[3])
&& !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(match_operator 1 "float_operator"
- [(match_operand:SI 2 "memory_operand" "")])
+ [(match_operand:X87MODEI12 2 "memory_operand" "")])
(match_operand 3 "register_operand" "")])
(match_operand 4 "" "")
(match_operand 5 "" "")))
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator"
[(match_operator 1 "float_operator"
- [(match_operand:SI 2 "register_operand" "")])
+ [(match_operand:X87MODEI12 2 "register_operand" "")])
(match_operand 3 "register_operand" "")])
(match_operand 4 "" "")
(match_operand 5 "" "")))
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
\f
-;; Loop instruction
-;;
-;; This is all complicated by the fact that since this is a jump insn
-;; we must handle our own reloads.
-
-(define_expand "doloop_end"
- [(use (match_operand 0 "" "")) ; loop pseudo
- (use (match_operand 1 "" "")) ; iterations; zero if unknown
- (use (match_operand 2 "" "")) ; max iterations
- (use (match_operand 3 "" "")) ; loop level
- (use (match_operand 4 "" ""))] ; label
- "!TARGET_64BIT && TARGET_USE_LOOP"
- "
-{
- /* Only use cloop on innermost loops. */
- if (INTVAL (operands[3]) > 1)
- FAIL;
- if (GET_MODE (operands[0]) != SImode)
- FAIL;
- emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
- operands[0]));
- DONE;
-}")
-
-(define_insn "doloop_end_internal"
- [(set (pc)
- (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
- (const_int 1))
- (label_ref (match_operand 0 "" ""))
- (pc)))
- (set (match_operand:SI 2 "nonimmediate_operand" "=1,1,*m*r")
- (plus:SI (match_dup 1)
- (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,X,r"))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_USE_LOOP
- && (reload_in_progress || reload_completed
- || register_operand (operands[2], VOIDmode))"
-{
- if (which_alternative != 0)
- return "#";
- if (get_attr_length (insn) == 2)
- return "%+loop\t%l0";
- else
- return "dec{l}\t%1\;%+jne\t%l0";
-}
- [(set (attr "length")
- (if_then_else (and (eq_attr "alternative" "0")
- (and (ge (minus (match_dup 0) (pc))
- (const_int -126))
- (lt (minus (match_dup 0) (pc))
- (const_int 128))))
- (const_int 2)
- (const_int 16)))
- ;; We don't know the type before shorten branches. Optimistically expect
- ;; the loop instruction to match.
- (set (attr "type") (const_string "ibr"))])
-
-(define_split
- [(set (pc)
- (if_then_else (ne (match_operand:SI 1 "register_operand" "")
- (const_int 1))
- (match_operand 0 "" "")
- (pc)))
- (set (match_dup 1)
- (plus:SI (match_dup 1)
- (const_int -1)))
- (clobber (match_scratch:SI 2 ""))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_USE_LOOP
- && reload_completed
- && REGNO (operands[1]) != 2"
- [(parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
- (const_int 0)))
- (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
- (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_dup 0)
- (pc)))]
- "")
-
-(define_split
- [(set (pc)
- (if_then_else (ne (match_operand:SI 1 "register_operand" "")
- (const_int 1))
- (match_operand 0 "" "")
- (pc)))
- (set (match_operand:SI 2 "nonimmediate_operand" "")
- (plus:SI (match_dup 1)
- (const_int -1)))
- (clobber (match_scratch:SI 3 ""))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_USE_LOOP
- && reload_completed
- && (! REG_P (operands[2])
- || ! rtx_equal_p (operands[1], operands[2]))"
- [(set (match_dup 3) (match_dup 1))
- (parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
- (const_int 0)))
- (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
- (set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_dup 0)
- (pc)))]
- "")
-
;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
(define_peephole2
(set (strict_low_part (match_dup 5))
(match_dup 2))]
{
- operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
+ operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
operands[5] = gen_lowpart (QImode, operands[3]);
ix86_expand_clear (operands[3]);
})
(set (strict_low_part (match_dup 5))
(match_dup 2))]
{
- operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
+ operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
operands[5] = gen_lowpart (QImode, operands[3]);
ix86_expand_clear (operands[3]);
})
(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
- { return output_set_got (operands[0]); }
+ { return output_set_got (operands[0], NULL_RTX); }
[(set_attr "type" "multi")
(set_attr "length" "12")])
+(define_insn "set_got_labelled"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(label_ref (match_operand 1 "" ""))]
+ UNSPEC_SET_GOT))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT"
+ { return output_set_got (operands[0], operands[1]); }
+ [(set_attr "type" "multi")
+ (set_attr "length" "12")])
+
+(define_insn "set_got_rex64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
+ "TARGET_64BIT"
+ "lea{q}\t_GLOBAL_OFFSET_TABLE_(%%rip), %0"
+ [(set_attr "type" "lea")
+ (set_attr "length" "6")])
+
(define_expand "epilogue"
[(const_int 1)]
""
operands[2] = gen_reg_rtx (Pmode);
emit_insn (gen_set_got (operands[2]));
}
+ if (TARGET_GNU2_TLS)
+ {
+ emit_insn (gen_tls_dynamic_gnu2_32
+ (operands[0], operands[1], operands[2]));
+ DONE;
+ }
operands[3] = ix86_tls_get_addr ();
})
(define_insn "*tls_global_dynamic_64"
[(set (match_operand:DI 0 "register_operand" "=a")
- (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
- (match_operand:DI 3 "" "")))
+ (call:DI (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
+ (match_operand:DI 3 "" "")))
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
UNSPEC_TLS_GD)]
"TARGET_64BIT"
(define_expand "tls_global_dynamic_64"
[(parallel [(set (match_operand:DI 0 "register_operand" "")
- (call (mem:QI (match_dup 2)) (const_int 0)))
+ (call:DI (mem:QI (match_dup 2)) (const_int 0)))
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
UNSPEC_TLS_GD)])]
""
{
+ if (TARGET_GNU2_TLS)
+ {
+ emit_insn (gen_tls_dynamic_gnu2_64
+ (operands[0], operands[1]));
+ DONE;
+ }
operands[2] = ix86_tls_get_addr ();
})
operands[1] = gen_reg_rtx (Pmode);
emit_insn (gen_set_got (operands[1]));
}
+ if (TARGET_GNU2_TLS)
+ {
+ emit_insn (gen_tls_dynamic_gnu2_32
+ (operands[0], ix86_tls_module_base (), operands[1]));
+ DONE;
+ }
operands[2] = ix86_tls_get_addr ();
})
(define_insn "*tls_local_dynamic_base_64"
[(set (match_operand:DI 0 "register_operand" "=a")
- (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
- (match_operand:DI 2 "" "")))
+ (call:DI (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
+ (match_operand:DI 2 "" "")))
(unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
"TARGET_64BIT"
"lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
(define_expand "tls_local_dynamic_base_64"
[(parallel [(set (match_operand:DI 0 "register_operand" "")
- (call (mem:QI (match_dup 1)) (const_int 0)))
+ (call:DI (mem:QI (match_dup 1)) (const_int 0)))
(unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
""
{
+ if (TARGET_GNU2_TLS)
+ {
+ emit_insn (gen_tls_dynamic_gnu2_64
+ (operands[0], ix86_tls_module_base ()));
+ DONE;
+ }
operands[1] = ix86_tls_get_addr ();
})
(set_attr "length" "7")
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
+
+;; GNU2 TLS patterns can be split.
+
+(define_expand "tls_dynamic_gnu2_32"
+ [(set (match_dup 3)
+ (plus:SI (match_operand:SI 2 "register_operand" "")
+ (const:SI
+ (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")]
+ UNSPEC_TLSDESC))))
+ (parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (unspec:SI [(match_dup 1) (match_dup 3)
+ (match_dup 2) (reg:SI SP_REG)]
+ UNSPEC_TLSDESC))
+ (clobber (reg:CC FLAGS_REG))])]
+ "!TARGET_64BIT && TARGET_GNU2_TLS"
+{
+ operands[3] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+ ix86_tls_descriptor_calls_expanded_in_cfun = true;
+})
+
+(define_insn "*tls_dynamic_lea_32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (match_operand:SI 1 "register_operand" "b")
+ (const:SI
+ (unspec:SI [(match_operand:SI 2 "tls_symbolic_operand" "")]
+ UNSPEC_TLSDESC))))]
+ "!TARGET_64BIT && TARGET_GNU2_TLS"
+ "lea{l}\t{%a2@TLSDESC(%1), %0|%0, %a2@TLSDESC[%1]}"
+ [(set_attr "type" "lea")
+ (set_attr "mode" "SI")
+ (set_attr "length" "6")
+ (set_attr "length_address" "4")])
+
+(define_insn "*tls_dynamic_call_32"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")
+ (match_operand:SI 2 "register_operand" "0")
+ ;; we have to make sure %ebx still points to the GOT
+ (match_operand:SI 3 "register_operand" "b")
+ (reg:SI SP_REG)]
+ UNSPEC_TLSDESC))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT && TARGET_GNU2_TLS"
+ "call\t{*%a1@TLSCALL(%2)|[DWORD PTR [%2+%a1@TLSCALL]]}"
+ [(set_attr "type" "call")
+ (set_attr "length" "2")
+ (set_attr "length_address" "0")])
+
+(define_insn_and_split "*tls_dynamic_gnu2_combine_32"
+ [(set (match_operand:SI 0 "register_operand" "=&a")
+ (plus:SI
+ (plus:SI (match_operand:SI 3 "tp_or_register_operand" "ir")
+ (unspec:SI [(match_operand:SI 4 "tls_modbase_operand" "")
+ (match_operand:SI 5 "" "")
+ (match_operand:SI 2 "register_operand" "b")
+ (reg:SI SP_REG)]
+ UNSPEC_TLSDESC))
+ (const:SI (unspec:SI
+ [(match_operand:SI 1 "tls_symbolic_operand" "")]
+ UNSPEC_DTPOFF))))
+ (clobber (reg:CC FLAGS_REG))]
+ "!TARGET_64BIT && TARGET_GNU2_TLS"
+ "#"
+ ""
+ [(parallel
+ [(set (match_dup 0)
+ (plus:SI (match_dup 3)
+ (match_dup 5)))
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ operands[5] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+ emit_insn (gen_tls_dynamic_gnu2_32 (operands[5], operands[1], operands[2]));
+})
+
+(define_expand "tls_dynamic_gnu2_64"
+ [(set (match_dup 2)
+ (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
+ UNSPEC_TLSDESC))
+ (parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_dup 1) (match_dup 2) (reg:DI SP_REG)]
+ UNSPEC_TLSDESC))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT && TARGET_GNU2_TLS"
+{
+ operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+ ix86_tls_descriptor_calls_expanded_in_cfun = true;
+})
+
+(define_insn "*tls_dynamic_lea_64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
+ UNSPEC_TLSDESC))]
+ "TARGET_64BIT && TARGET_GNU2_TLS"
+ "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[%%rip]}"
+ [(set_attr "type" "lea")
+ (set_attr "mode" "DI")
+ (set_attr "length" "7")
+ (set_attr "length_address" "4")])
+
+(define_insn "*tls_dynamic_call_64"
+ [(set (match_operand:DI 0 "register_operand" "=a")
+ (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")
+ (match_operand:DI 2 "register_operand" "0")
+ (reg:DI SP_REG)]
+ UNSPEC_TLSDESC))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && TARGET_GNU2_TLS"
+ "call\t{*%a1@TLSCALL(%2)|[QWORD PTR [%2+%a1@TLSCALL]]}"
+ [(set_attr "type" "call")
+ (set_attr "length" "2")
+ (set_attr "length_address" "0")])
+
+(define_insn_and_split "*tls_dynamic_gnu2_combine_64"
+ [(set (match_operand:DI 0 "register_operand" "=&a")
+ (plus:DI
+ (plus:DI (match_operand:DI 2 "tp_or_register_operand" "ir")
+ (unspec:DI [(match_operand:DI 3 "tls_modbase_operand" "")
+ (match_operand:DI 4 "" "")
+ (reg:DI SP_REG)]
+ UNSPEC_TLSDESC))
+ (const:DI (unspec:DI
+ [(match_operand:DI 1 "tls_symbolic_operand" "")]
+ UNSPEC_DTPOFF))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && TARGET_GNU2_TLS"
+ "#"
+ ""
+ [(parallel
+ [(set (match_dup 0)
+ (plus:DI (match_dup 2)
+ (match_dup 4)))
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ operands[4] = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+ emit_insn (gen_tls_dynamic_gnu2_64 (operands[4], operands[1]));
+})
+
+;;
\f
;; These patterns match the binary 387 instructions for addM3, subM3,
;; mulM3 and divM3. There are three patterns for each of DFmode and
(const_string "fop")))
(set_attr "mode" "SF")])
-
;; ??? Add SSE splitters for these!
-(define_insn "*fop_sf_2_i387"
+(define_insn "*fop_sf_2<mode>_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(match_operator:SF 3 "binary_fp_operator"
- [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
+ [(float:SF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
(match_operand:SF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*fop_sf_3_i387"
+(define_insn "*fop_sf_3<mode>_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0,0")
- (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
+ (float:SF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*fop_df_comm_mixed"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(set_attr "mode" "DF")])
;; ??? Add SSE splitters for these!
-(define_insn "*fop_df_2_i387"
+(define_insn "*fop_df_2<mode>_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
- [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
+ [(float:DF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
(match_operand:DF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*fop_df_3_i387"
+(define_insn "*fop_df_3<mode>_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0,0")
- (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ (float:DF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
+ && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*fop_df_4_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(const_string "fop")))
(set_attr "mode" "XF")])
-(define_insn "*fop_xf_2_i387"
+(define_insn "*fop_xf_2<mode>_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
- [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
+ [(float:XF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
(match_operand:XF 2 "register_operand" "0,0")]))]
- "TARGET_80387 && TARGET_USE_FIOP"
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*fop_xf_3_i387"
+(define_insn "*fop_xf_3<mode>_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,0")
- (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
- "TARGET_80387 && TARGET_USE_FIOP"
+ (float:XF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
+ "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*fop_xf_4_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(define_split
[(set (match_operand 0 "register_operand" "")
(match_operator 3 "binary_fp_operator"
- [(float (match_operand:SI 1 "register_operand" ""))
+ [(float (match_operand:X87MODEI12 1 "register_operand" ""))
(match_operand 2 "register_operand" "")]))]
"TARGET_80387 && reload_completed
&& FLOAT_MODE_P (GET_MODE (operands[0]))"
[(set (match_operand 0 "register_operand" "")
(match_operator 3 "binary_fp_operator"
[(match_operand 1 "register_operand" "")
- (float (match_operand:SI 2 "register_operand" ""))]))]
+ (float (match_operand:X87MODEI12 2 "register_operand" ""))]))]
"TARGET_80387 && reload_completed
&& FLOAT_MODE_P (GET_MODE (operands[0]))"
[(const_int 0)]
emit_move_insn (operands[2], temp);
emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
})
+
+(define_expand "ldexpdf3"
+ [(set (match_dup 3)
+ (float_extend:XF (match_operand:DF 1 "register_operand" "")))
+ (set (match_dup 4)
+ (float:XF (match_operand:SI 2 "register_operand" "")))
+ (parallel [(set (match_dup 5)
+ (unspec:XF [(match_dup 3) (match_dup 4)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 6)
+ (unspec:XF [(match_dup 3) (match_dup 4)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:DF 0 "register_operand" "")
+ (float_truncate:DF (match_dup 5)))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=3; i<7; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "ldexpsf3"
+ [(set (match_dup 3)
+ (float_extend:XF (match_operand:SF 1 "register_operand" "")))
+ (set (match_dup 4)
+ (float:XF (match_operand:SI 2 "register_operand" "")))
+ (parallel [(set (match_dup 5)
+ (unspec:XF [(match_dup 3) (match_dup 4)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 6)
+ (unspec:XF [(match_dup 3) (match_dup 4)]
+ UNSPEC_FSCALE_EXP))])
+ (set (match_operand:SF 0 "register_operand" "")
+ (float_truncate:SF (match_dup 5)))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=3; i<7; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+})
+
+(define_expand "ldexpxf3"
+ [(set (match_dup 3)
+ (float:XF (match_operand:SI 2 "register_operand" "")))
+ (parallel [(set (match_operand:XF 0 " register_operand" "")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ (match_dup 3)]
+ UNSPEC_FSCALE_FRACT))
+ (set (match_dup 4)
+ (unspec:XF [(match_dup 1) (match_dup 3)]
+ UNSPEC_FSCALE_EXP))])]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+{
+ int i;
+
+ for (i=3; i<5; i++)
+ operands[i] = gen_reg_rtx (XFmode);
+})
\f
(define_insn "frndintxf2"
DONE;
})
-(define_insn "frndintxf2_floor"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_FRNDINT_FLOOR))
+(define_insn_and_split "*fistdi2_1"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ if (memory_operand (operands[0], VOIDmode))
+ emit_insn (gen_fistdi2 (operands[0], operands[1]));
+ else
+ {
+ operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
+ emit_insn (gen_fistdi2_with_temp (operands[0], operands[1],
+ operands[2]));
+ }
+ DONE;
+}
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "DI")])
+
+(define_insn "fistdi2"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST))
+ (clobber (match_scratch:XF 2 "=&1f"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "* return output_fix_trunc (insn, operands, 0);"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "DI")])
+
+(define_insn "fistdi2_with_temp"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST))
+ (clobber (match_operand:DI 2 "memory_operand" "=m,m"))
+ (clobber (match_scratch:XF 3 "=&1f,&1f"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "#"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "DI")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST))
+ (clobber (match_operand:DI 2 "memory_operand" ""))
+ (clobber (match_scratch 3 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
+ (clobber (match_dup 3))])
+ (set (match_dup 0) (match_dup 2))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "memory_operand" "")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST))
+ (clobber (match_operand:DI 2 "memory_operand" ""))
+ (clobber (match_scratch 3 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
+ (clobber (match_dup 3))])]
+ "")
+
+(define_insn_and_split "*fist<mode>2_1"
+ [(set (match_operand:X87MODEI12 0 "register_operand" "=r")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
+ emit_insn (gen_fist<mode>2_with_temp (operands[0], operands[1],
+ operands[2]));
+ DONE;
+}
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fist<mode>2"
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "* return output_fix_trunc (insn, operands, 0);"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fist<mode>2_with_temp"
+ [(set (match_operand:X87MODEI12 0 "register_operand" "=r")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST))
+ (clobber (match_operand:X87MODEI12 2 "memory_operand" "=m"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "#"
+ [(set_attr "type" "fpspc")
+ (set_attr "mode" "<MODE>")])
+
+(define_split
+ [(set (match_operand:X87MODEI12 0 "register_operand" "")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST))
+ (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
+ "reload_completed"
+ [(set (match_dup 2) (unspec:X87MODEI12 [(match_dup 1)]
+ UNSPEC_FIST))
+ (set (match_dup 0) (match_dup 2))]
+ "")
+
+(define_split
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST))
+ (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
+ "reload_completed"
+ [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
+ UNSPEC_FIST))]
+ "")
+
+(define_expand "lrint<mode>2"
+ [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
+ (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations"
+ "")
+
+;; Rounding mode control word calculation could clobber FLAGS_REG.
+(define_insn_and_split "frndintxf2_floor"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_FLOOR))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ ix86_optimize_mode_switching[I387_FLOOR] = 1;
+
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
+
+ emit_insn (gen_frndintxf2_floor_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
+ DONE;
+}
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "floor")
+ (set_attr "mode" "XF")])
+
+(define_insn "frndintxf2_floor_i387"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_FLOOR))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
"TARGET_USE_FANCY_MATH_387
(set_attr "i387_cw" "floor")
(set_attr "mode" "XF")])
+(define_expand "floorxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+{
+ emit_insn (gen_frndintxf2_floor (operands[0], operands[1]));
+ DONE;
+})
+
(define_expand "floordf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
emit_insn (gen_extenddfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
+ emit_insn (gen_frndintxf2_floor (op0, op1));
emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
emit_insn (gen_extendsfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
+ emit_insn (gen_frndintxf2_floor (op0, op1));
emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
-(define_expand "floorxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+(define_insn_and_split "*fist<mode>2_floor_1"
+ [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
+ (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST_FLOOR))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ ix86_optimize_mode_switching[I387_FLOOR] = 1;
+
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
+ if (memory_operand (operands[0], VOIDmode))
+ emit_insn (gen_fist<mode>2_floor (operands[0], operands[1],
+ operands[2], operands[3]));
+ else
+ {
+ operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
+ emit_insn (gen_fist<mode>2_floor_with_temp (operands[0], operands[1],
+ operands[2], operands[3],
+ operands[4]));
+ }
+ DONE;
+}
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "floor")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fistdi2_floor"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))
+ (clobber (match_scratch:XF 4 "=&1f"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "* return output_fix_trunc (insn, operands, 0);"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "floor")
+ (set_attr "mode" "DI")])
+
+(define_insn "fistdi2_floor_with_temp"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" "m,m"))
+ (use (match_operand:HI 3 "memory_operand" "m,m"))
+ (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
+ (clobber (match_scratch:XF 5 "=&1f,&1f"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "#"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "floor")
+ (set_attr "mode" "DI")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:DI 4 "memory_operand" ""))
+ (clobber (match_scratch 5 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (match_dup 5))])
+ (set (match_dup 0) (match_dup 4))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "memory_operand" "")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:DI 4 "memory_operand" ""))
+ (clobber (match_scratch 5 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (match_dup 5))])]
+ "")
+
+(define_insn "fist<mode>2_floor"
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "* return output_fix_trunc (insn, operands, 0);"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "floor")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fist<mode>2_floor_with_temp"
+ [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" "m,m"))
+ (use (match_operand:HI 3 "memory_operand" "m,m"))
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "#"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "floor")
+ (set_attr "mode" "<MODE>")])
+
+(define_split
+ [(set (match_operand:X87MODEI12 0 "register_operand" "")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
+ UNSPEC_FIST_FLOOR))
+ (use (match_dup 2))
+ (use (match_dup 3))])
+ (set (match_dup 0) (match_dup 4))]
+ "")
+
+(define_split
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_FLOOR))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
+ UNSPEC_FIST_FLOOR))
+ (use (match_dup 2))
+ (use (match_dup 3))])]
+ "")
+
+(define_expand "lfloor<mode>2"
+ [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
+ (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_FLOOR))
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
+ "")
+
+;; Rounding mode control word calculation could clobber FLAGS_REG.
+(define_insn_and_split "frndintxf2_ceil"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_CEIL))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
+ ix86_optimize_mode_switching[I387_CEIL] = 1;
+
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
- emit_insn (gen_frndintxf2_floor (operands[0], operands[1], op2, op3));
+ emit_insn (gen_frndintxf2_ceil_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
DONE;
-})
+}
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "ceil")
+ (set_attr "mode" "XF")])
-(define_insn "frndintxf2_ceil"
+(define_insn "frndintxf2_ceil_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT_CEIL))
(set_attr "i387_cw" "ceil")
(set_attr "mode" "XF")])
+(define_expand "ceilxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+{
+ emit_insn (gen_frndintxf2_ceil (operands[0], operands[1]));
+ DONE;
+})
+
(define_expand "ceildf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
emit_insn (gen_extenddfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
+ emit_insn (gen_frndintxf2_ceil (op0, op1));
+
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
+ DONE;
+})
+
+(define_expand "ceilsf2"
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extendsfxf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_ceil (op0, op1));
+
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
+ DONE;
+})
+
+(define_insn_and_split "*fist<mode>2_ceil_1"
+ [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
+ (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST_CEIL))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ ix86_optimize_mode_switching[I387_CEIL] = 1;
+
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
+ if (memory_operand (operands[0], VOIDmode))
+ emit_insn (gen_fist<mode>2_ceil (operands[0], operands[1],
+ operands[2], operands[3]));
+ else
+ {
+ operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
+ emit_insn (gen_fist<mode>2_ceil_with_temp (operands[0], operands[1],
+ operands[2], operands[3],
+ operands[4]));
+ }
+ DONE;
+}
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "ceil")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fistdi2_ceil"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))
+ (clobber (match_scratch:XF 4 "=&1f"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "* return output_fix_trunc (insn, operands, 0);"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "ceil")
+ (set_attr "mode" "DI")])
+
+(define_insn "fistdi2_ceil_with_temp"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" "m,m"))
+ (use (match_operand:HI 3 "memory_operand" "m,m"))
+ (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
+ (clobber (match_scratch:XF 5 "=&1f,&1f"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "#"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "ceil")
+ (set_attr "mode" "DI")])
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:DI 4 "memory_operand" ""))
+ (clobber (match_scratch 5 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (match_dup 5))])
+ (set (match_dup 0) (match_dup 4))]
+ "")
+
+(define_split
+ [(set (match_operand:DI 0 "memory_operand" "")
+ (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:DI 4 "memory_operand" ""))
+ (clobber (match_scratch 5 ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (match_dup 5))])]
+ "")
+
+(define_insn "fist<mode>2_ceil"
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "* return output_fix_trunc (insn, operands, 0);"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "ceil")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "fist<mode>2_ceil_with_temp"
+ [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" "m,m"))
+ (use (match_operand:HI 3 "memory_operand" "m,m"))
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "#"
+ [(set_attr "type" "fistp")
+ (set_attr "i387_cw" "ceil")
+ (set_attr "mode" "<MODE>")])
+
+(define_split
+ [(set (match_operand:X87MODEI12 0 "register_operand" "")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
+ UNSPEC_FIST_CEIL))
+ (use (match_dup 2))
+ (use (match_dup 3))])
+ (set (match_dup 0) (match_dup 4))]
+ "")
- emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
- DONE;
-})
+(define_split
+ [(set (match_operand:X87MODEI12 0 "memory_operand" "")
+ (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_CEIL))
+ (use (match_operand:HI 2 "memory_operand" ""))
+ (use (match_operand:HI 3 "memory_operand" ""))
+ (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
+ UNSPEC_FIST_CEIL))
+ (use (match_dup 2))
+ (use (match_dup 3))])]
+ "")
-(define_expand "ceilsf2"
- [(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:SF 1 "register_operand" ""))]
+(define_expand "lceil<mode>2"
+ [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
+ (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
+ UNSPEC_FIST_CEIL))
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_USE_FANCY_MATH_387
&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
-{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
-
- emit_insn (gen_extendsfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
-
- emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
- DONE;
-})
+ "")
-(define_expand "ceilxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+;; Rounding mode control word calculation could clobber FLAGS_REG.
+(define_insn_and_split "frndintxf2_trunc"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_TRUNC))
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
+ ix86_optimize_mode_switching[I387_TRUNC] = 1;
- emit_insn (gen_frndintxf2_ceil (operands[0], operands[1], op2, op3));
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
+
+ emit_insn (gen_frndintxf2_trunc_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
DONE;
-})
+}
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "trunc")
+ (set_attr "mode" "XF")])
-(define_insn "frndintxf2_trunc"
+(define_insn "frndintxf2_trunc_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT_TRUNC))
(set_attr "i387_cw" "trunc")
(set_attr "mode" "XF")])
+(define_expand "btruncxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+{
+ emit_insn (gen_frndintxf2_trunc (operands[0], operands[1]));
+ DONE;
+})
+
(define_expand "btruncdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
emit_insn (gen_extenddfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
+ emit_insn (gen_frndintxf2_trunc (op0, op1));
emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
emit_insn (gen_extendsfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
+ emit_insn (gen_frndintxf2_trunc (op0, op1));
emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
-(define_expand "btruncxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+;; Rounding mode control word calculation could clobber FLAGS_REG.
+(define_insn_and_split "frndintxf2_mask_pm"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_MASK_PM))
+ (clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
+ && flag_unsafe_math_optimizations
+ && !(reload_completed || reload_in_progress)"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
+ ix86_optimize_mode_switching[I387_MASK_PM] = 1;
+
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_MASK_PM);
- emit_insn (gen_frndintxf2_trunc (operands[0], operands[1], op2, op3));
+ emit_insn (gen_frndintxf2_mask_pm_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
DONE;
-})
+}
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "mask_pm")
+ (set_attr "mode" "XF")])
-(define_insn "frndintxf2_mask_pm"
+(define_insn "frndintxf2_mask_pm_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT_MASK_PM))
(set_attr "i387_cw" "mask_pm")
(set_attr "mode" "XF")])
+(define_expand "nearbyintxf2"
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+{
+ emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1]));
+
+ DONE;
+})
+
(define_expand "nearbyintdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
emit_insn (gen_extenddfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
+ emit_insn (gen_frndintxf2_mask_pm (op0, op1));
emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
{
rtx op0 = gen_reg_rtx (XFmode);
rtx op1 = gen_reg_rtx (XFmode);
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
emit_insn (gen_extendsfxf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
+ emit_insn (gen_frndintxf2_mask_pm (op0, op1));
emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
-(define_expand "nearbyintxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
-{
- rtx op2 = assign_386_stack_local (HImode, 1);
- rtx op3 = assign_386_stack_local (HImode, 2);
-
- ix86_optimize_mode_switching = 1;
-
- emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1],
- op2, op3));
- DONE;
-})
-
\f
;; Block operation instructions
(use (match_operand:BLK 1 "memory_operand" ""))
(use (match_operand:SI 2 "nonmemory_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))]
- "! optimize_size"
+ "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
{
if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
DONE;
(set_attr "memory" "both")
(set_attr "mode" "SI")])
-(define_expand "clrmemsi"
+(define_expand "setmemsi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:SI 1 "nonmemory_operand" ""))
- (use (match_operand 2 "const_int_operand" ""))]
+ (use (match_operand 2 "const_int_operand" ""))
+ (use (match_operand 3 "const_int_operand" ""))]
""
{
- if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
+ /* If value to set is not zero, use the library routine. */
+ if (operands[2] != const0_rtx)
+ FAIL;
+
+ if (ix86_expand_clrmem (operands[0], operands[1], operands[3]))
DONE;
else
FAIL;
})
-(define_expand "clrmemdi"
+(define_expand "setmemdi"
[(use (match_operand:BLK 0 "memory_operand" ""))
(use (match_operand:DI 1 "nonmemory_operand" ""))
- (use (match_operand 2 "const_int_operand" ""))]
+ (use (match_operand 2 "const_int_operand" ""))
+ (use (match_operand 3 "const_int_operand" ""))]
"TARGET_64BIT"
{
- if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
+ /* If value to set is not zero, use the library routine. */
+ if (operands[2] != const0_rtx)
+ FAIL;
+
+ if (ix86_expand_clrmem (operands[0], operands[1], operands[3]))
DONE;
else
FAIL;
(set_attr "memory" "store")
(set_attr "mode" "QI")])
-(define_expand "cmpstrsi"
+(define_expand "cmpstrnsi"
[(set (match_operand:SI 0 "register_operand" "")
(compare:SI (match_operand:BLK 1 "general_operand" "")
(match_operand:BLK 2 "general_operand" "")))
emit_move_insn (operands[0], const0_rtx);
DONE;
}
- emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
- operands[1], operands[2]));
+ emit_insn (gen_cmpstrnqi_nz_1 (addr1, addr2, countreg, align,
+ operands[1], operands[2]));
}
else
{
emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
else
emit_insn (gen_cmpsi_1 (countreg, countreg));
- emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
- operands[1], operands[2]));
+ emit_insn (gen_cmpstrnqi_1 (addr1, addr2, countreg, align,
+ operands[1], operands[2]));
}
outlow = gen_lowpart (QImode, out);
;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
;; zero. Emit extra code to make sure that a zero-length compare is EQ.
-(define_expand "cmpstrqi_nz_1"
+(define_expand "cmpstrnqi_nz_1"
[(parallel [(set (reg:CC FLAGS_REG)
(compare:CC (match_operand 4 "memory_operand" "")
(match_operand 5 "memory_operand" "")))
""
"")
-(define_insn "*cmpstrqi_nz_1"
+(define_insn "*cmpstrnqi_nz_1"
[(set (reg:CC FLAGS_REG)
(compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
(mem:BLK (match_operand:SI 5 "register_operand" "1"))))
(set_attr "mode" "QI")
(set_attr "prefix_rep" "1")])
-(define_insn "*cmpstrqi_nz_rex_1"
+(define_insn "*cmpstrnqi_nz_rex_1"
[(set (reg:CC FLAGS_REG)
(compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
(mem:BLK (match_operand:DI 5 "register_operand" "1"))))
;; The same, but the count is not known to not be zero.
-(define_expand "cmpstrqi_1"
+(define_expand "cmpstrnqi_1"
[(parallel [(set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_operand 2 "register_operand" "")
(const_int 0))
""
"")
-(define_insn "*cmpstrqi_1"
+(define_insn "*cmpstrnqi_1"
[(set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
(const_int 0))
(set_attr "mode" "QI")
(set_attr "prefix_rep" "1")])
-(define_insn "*cmpstrqi_rex_1"
+(define_insn "*cmpstrnqi_rex_1"
[(set (reg:CC FLAGS_REG)
(if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
(const_int 0))
(set_attr "mode" "QI")
(set_attr "prefix_rep" "1")])
-;; Peephole optimizations to clean up after cmpstr*. This should be
+;; Peephole optimizations to clean up after cmpstrn*. This should be
;; handled in combine, but it is not currently up to the task.
-;; When used for their truth value, the cmpstr* expanders generate
+;; When used for their truth value, the cmpstrn* expanders generate
;; code like this:
;;
;; repz cmpsb
;;
;; The intermediate three instructions are unnecessary.
-;; This one handles cmpstr*_nz_1...
+;; This one handles cmpstrn*_nz_1...
(define_peephole2
[(parallel[
(set (reg:CC FLAGS_REG)
(clobber (match_dup 2))])]
"")
-;; ...and this one handles cmpstr*_1.
+;; ...and this one handles cmpstrn*_1.
(define_peephole2
[(parallel[
(set (reg:CC FLAGS_REG)
"(TARGET_80387 && TARGET_CMOVE) || TARGET_SSE_MATH"
"if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-;; These versions of min/max are aware of the instruction's behavior
-;; wrt -0.0 and NaN inputs. If we don't care about either, then we
-;; should have used the smin/smax expanders in the first place.
-(define_insn "*movsfcc_1_sse_min"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (if_then_else:SF
- (lt:SF (match_operand:SF 1 "register_operand" "0")
- (match_operand:SF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (match_dup 2)))]
- "TARGET_SSE_MATH"
- "minss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-(define_insn "*movsfcc_1_sse_max"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (if_then_else:SF
- (lt:SF (match_operand:SF 2 "nonimmediate_operand" "xm")
- (match_operand:SF 1 "nonimmediate_operand" "0"))
- (match_dup 1)
- (match_dup 2)))]
- "TARGET_SSE_MATH"
- "maxss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-(define_insn_and_split "*movsfcc_1_sse"
- [(set (match_operand:SF 0 "register_operand" "=x,x,x")
- (if_then_else:SF
- (match_operator:SF 4 "sse_comparison_operator"
- [(match_operand:SF 5 "register_operand" "0,0,0")
- (match_operand:SF 6 "nonimmediate_operand" "xm,xm,xm")])
- (match_operand:SF 2 "reg_or_0_operand" "C,x,x")
- (match_operand:SF 3 "reg_or_0_operand" "x,C,x")))
- (clobber (match_scratch:V4SF 1 "=&x,&x,&x"))]
- "TARGET_SSE_MATH"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- ix86_split_sse_movcc (operands);
- DONE;
-})
-
(define_insn "*movsfcc_1_387"
[(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
"(TARGET_80387 && TARGET_CMOVE) || (TARGET_SSE2 && TARGET_SSE_MATH)"
"if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-;; These versions of min/max are aware of the instruction's behavior
-;; wrt -0.0 and NaN inputs. If we don't care about either, then we
-;; should have used the smin/smax expanders in the first place.
-(define_insn "*movdfcc_1_sse_min"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (if_then_else:DF
- (lt:DF (match_operand:DF 1 "register_operand" "0")
- (match_operand:DF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (match_dup 2)))]
- "TARGET_SSE2 && TARGET_SSE_MATH"
- "minsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
-
-(define_insn "*movdfcc_1_sse_max"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (if_then_else:DF
- (lt:DF (match_operand:DF 2 "nonimmediate_operand" "xm")
- (match_operand:DF 1 "nonimmediate_operand" "0"))
- (match_dup 1)
- (match_dup 2)))]
- "TARGET_SSE2 && TARGET_SSE_MATH"
- "maxsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
-
-(define_insn_and_split "*movdfcc_1_sse"
- [(set (match_operand:DF 0 "register_operand" "=x,x,x")
- (if_then_else:DF
- (match_operator:DF 4 "sse_comparison_operator"
- [(match_operand:DF 5 "register_operand" "0,0,0")
- (match_operand:DF 6 "nonimmediate_operand" "xm,xm,xm")])
- (match_operand:DF 2 "reg_or_0_operand" "C,x,x")
- (match_operand:DF 3 "reg_or_0_operand" "x,C,x")))
- (clobber (match_scratch:V2DF 1 "=&x,&x,&x"))]
- "TARGET_SSE2 && TARGET_SSE_MATH"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- ix86_split_sse_movcc (operands);
- DONE;
-})
-
(define_insn "*movdfcc_1"
[(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
[(set_attr "type" "sseadd")
(set_attr "mode" "DF")])
+;; These versions of the min/max patterns implement exactly the operations
+;; min = (op1 < op2 ? op1 : op2)
+;; max = (!(op1 < op2) ? op1 : op2)
+;; Their operands are not commutative, and thus they may be used in the
+;; presence of -0.0 and NaN.
+
+(define_insn "*ieee_sminsf3"
+ [(set (match_operand:SF 0 "register_operand" "=x")
+ (unspec:SF [(match_operand:SF 1 "register_operand" "0")
+ (match_operand:SF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MIN))]
+ "TARGET_SSE_MATH"
+ "minss\t{%2, %0|%0, %2}"
+ [(set_attr "type" "sseadd")
+ (set_attr "mode" "SF")])
+
+(define_insn "*ieee_smaxsf3"
+ [(set (match_operand:SF 0 "register_operand" "=x")
+ (unspec:SF [(match_operand:SF 1 "register_operand" "0")
+ (match_operand:SF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MAX))]
+ "TARGET_SSE_MATH"
+ "maxss\t{%2, %0|%0, %2}"
+ [(set_attr "type" "sseadd")
+ (set_attr "mode" "SF")])
+
+(define_insn "*ieee_smindf3"
+ [(set (match_operand:DF 0 "register_operand" "=x")
+ (unspec:DF [(match_operand:DF 1 "register_operand" "0")
+ (match_operand:DF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MIN))]
+ "TARGET_SSE2 && TARGET_SSE_MATH"
+ "minsd\t{%2, %0|%0, %2}"
+ [(set_attr "type" "sseadd")
+ (set_attr "mode" "DF")])
+
+(define_insn "*ieee_smaxdf3"
+ [(set (match_operand:DF 0 "register_operand" "=x")
+ (unspec:DF [(match_operand:DF 1 "register_operand" "0")
+ (match_operand:DF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MAX))]
+ "TARGET_SSE2 && TARGET_SSE_MATH"
+ "maxsd\t{%2, %0|%0, %2}"
+ [(set_attr "type" "sseadd")
+ (set_attr "mode" "DF")])
+
;; Conditional addition patterns
(define_expand "addqicc"
[(match_operand:QI 0 "register_operand" "")
return "lea{l}\t{%a2, %0|%0, %a2}";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set (attr "type")
return "lea{q}\t{%a2, %0|%0, %a2}";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set (attr "type")
return "lea{q}\t{%a2, %0|%0, %a2}";
default:
- abort ();
+ gcc_unreachable ();
}
}
[(set_attr "type" "alu,lea")
[(label_ref (match_operand 0 "" ""))]
"!TARGET_64BIT && flag_pic"
{
- emit_insn (gen_set_got (pic_offset_table_rtx));
+ if (TARGET_MACHO)
+ {
+ rtx xops[3];
+ rtx picreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
+ rtx label_rtx = gen_label_rtx ();
+ emit_insn (gen_set_got_labelled (pic_offset_table_rtx, label_rtx));
+ xops[0] = xops[1] = picreg;
+ xops[2] = gen_rtx_CONST (SImode,
+ gen_rtx_MINUS (SImode,
+ gen_rtx_LABEL_REF (SImode, label_rtx),
+ gen_rtx_SYMBOL_REF (SImode, GOT_SYMBOL_NAME)));
+ ix86_expand_binary_operator (MINUS, SImode, xops);
+ }
+ else
+ emit_insn (gen_set_got (pic_offset_table_rtx));
DONE;
})
\f
[(set (match_operand:SI 0 "push_operand" "")
(match_operand:SI 1 "memory_operand" ""))
(match_scratch:SI 2 "r")]
- "! optimize_size && ! TARGET_PUSH_MEMORY"
+ "!optimize_size && !TARGET_PUSH_MEMORY
+ && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
[(set (match_operand:DI 0 "push_operand" "")
(match_operand:DI 1 "memory_operand" ""))
(match_scratch:DI 2 "r")]
- "! optimize_size && ! TARGET_PUSH_MEMORY"
+ "!optimize_size && !TARGET_PUSH_MEMORY
+ && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
[(set (match_operand:SF 0 "push_operand" "")
(match_operand:SF 1 "memory_operand" ""))
(match_scratch:SF 2 "r")]
- "! optimize_size && ! TARGET_PUSH_MEMORY"
+ "!optimize_size && !TARGET_PUSH_MEMORY
+ && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
[(set (match_operand:HI 0 "push_operand" "")
(match_operand:HI 1 "memory_operand" ""))
(match_scratch:HI 2 "r")]
- "! optimize_size && ! TARGET_PUSH_MEMORY"
+ "!optimize_size && !TARGET_PUSH_MEMORY
+ && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
[(set (match_operand:QI 0 "push_operand" "")
(match_operand:QI 1 "memory_operand" ""))
(match_scratch:QI 2 "q")]
- "! optimize_size && ! TARGET_PUSH_MEMORY"
+ "!optimize_size && !TARGET_PUSH_MEMORY
+ && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
"")
;; Attempt to always use XOR for zeroing registers.
(define_peephole2
[(set (match_operand 0 "register_operand" "")
- (const_int 0))]
- "(GET_MODE (operands[0]) == QImode
- || GET_MODE (operands[0]) == HImode
- || GET_MODE (operands[0]) == SImode
- || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
+ (match_operand 1 "const0_operand" ""))]
+ "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
&& (! TARGET_USE_MOV0 || optimize_size)
&& GENERAL_REG_P (operands[0])
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int 0))
(clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
- operands[0]);")
+{
+ operands[0] = gen_lowpart (word_mode, operands[0]);
+})
(define_peephole2
[(set (strict_low_part (match_operand 0 "register_operand" ""))
(mult:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_K8 && !optimize_size
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_K8 && !optimize_size
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_K8 && !optimize_size
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:DI 3 "r")]
- "TARGET_K8 && !optimize_size
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:SI 3 "r")]
- "TARGET_K8 && !optimize_size
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
(match_operand:HI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:HI 3 "r")]
- "TARGET_K8 && !optimize_size"
+ "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]
if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);
})
+
+;; After splitting up read-modify operations, array accesses with memory
+;; operands might end up in form:
+;; sall $2, %eax
+;; movl 4(%esp), %edx
+;; addl %edx, %eax
+;; instead of pre-splitting:
+;; sall $2, %eax
+;; addl 4(%esp), %eax
+;; Turn it into:
+;; movl 4(%esp), %edx
+;; leal (%edx,%eax,4), %eax
+
+(define_peephole2
+ [(parallel [(set (match_operand 0 "register_operand" "")
+ (ashift (match_operand 1 "register_operand" "")
+ (match_operand 2 "const_int_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])
+ (set (match_operand 3 "register_operand")
+ (match_operand 4 "x86_64_general_operand" ""))
+ (parallel [(set (match_operand 5 "register_operand" "")
+ (plus (match_operand 6 "register_operand" "")
+ (match_operand 7 "register_operand" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
+ /* Validate MODE for lea. */
+ && ((!TARGET_PARTIAL_REG_STALL
+ && (GET_MODE (operands[0]) == QImode
+ || GET_MODE (operands[0]) == HImode))
+ || GET_MODE (operands[0]) == SImode
+ || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
+ /* We reorder load and the shift. */
+ && !rtx_equal_p (operands[1], operands[3])
+ && !reg_overlap_mentioned_p (operands[0], operands[4])
+ /* Last PLUS must consist of operand 0 and 3. */
+ && !rtx_equal_p (operands[0], operands[3])
+ && (rtx_equal_p (operands[3], operands[6])
+ || rtx_equal_p (operands[3], operands[7]))
+ && (rtx_equal_p (operands[0], operands[6])
+ || rtx_equal_p (operands[0], operands[7]))
+ /* The intermediate operand 0 must die or be same as output. */
+ && (rtx_equal_p (operands[0], operands[5])
+ || peep2_reg_dead_p (3, operands[0]))"
+ [(set (match_dup 3) (match_dup 4))
+ (set (match_dup 0) (match_dup 1))]
+{
+ enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode;
+ int scale = 1 << INTVAL (operands[2]);
+ rtx index = gen_lowpart (Pmode, operands[1]);
+ rtx base = gen_lowpart (Pmode, operands[3]);
+ rtx dest = gen_lowpart (mode, operands[5]);
+
+ operands[1] = gen_rtx_PLUS (Pmode, base,
+ gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
+ if (mode != Pmode)
+ operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
+ operands[0] = dest;
+})
\f
;; Call-value patterns last so that the wildcard operand does not
;; disrupt insn-recog's switch tables.
"jmp\t*%%r11"
[(set_attr "type" "callv")])
\f
+;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
+;; That, however, is usually mapped by the OS to SIGSEGV, which is often
+;; caught for use by garbage collectors and the like. Using an insn that
+;; maps to SIGILL makes it more likely the program will rightfully die.
+;; Keeping with tradition, "6" is in honor of #UD.
(define_insn "trap"
- [(trap_if (const_int 1) (const_int 5))]
- ""
- "int\t$5")
-
-;;; ix86 doesn't have conditional trap instructions, but we fake them
-;;; for the sake of bounds checking. By emitting bounds checks as
-;;; conditional traps rather than as conditional jumps around
-;;; unconditional traps we avoid introducing spurious basic-block
-;;; boundaries and facilitate elimination of redundant checks. In
-;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
-;;; interrupt 5.
-;;;
-;;; FIXME: Static branch prediction rules for ix86 are such that
-;;; forward conditional branches predict as untaken. As implemented
-;;; below, pseudo conditional traps violate that rule. We should use
-;;; .pushsection/.popsection to place all of the `int 5's in a special
-;;; section loaded at the end of the text segment and branch forward
-;;; there on bounds-failure, and then jump back immediately (in case
-;;; the system chooses to ignore bounds violations, or to report
-;;; violations and continue execution).
-
-(define_expand "conditional_trap"
- [(trap_if (match_operator 0 "comparison_operator"
- [(match_dup 2) (const_int 0)])
- (match_operand 1 "const_int_operand" ""))]
- ""
-{
- emit_insn (gen_rtx_TRAP_IF (VOIDmode,
- ix86_expand_compare (GET_CODE (operands[0]),
- NULL, NULL),
- operands[1]));
- DONE;
-})
-
-(define_insn "*conditional_trap_1"
- [(trap_if (match_operator 0 "comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand 1 "const_int_operand" ""))]
+ [(trap_if (const_int 1) (const_int 6))]
""
-{
- operands[2] = gen_label_rtx ();
- output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
- (*targetm.asm_out.internal_label) (asm_out_file, "L",
- CODE_LABEL_NUMBER (operands[2]));
- RET;
-})
+ ".word\t0x0b0f"
+ [(set_attr "length" "2")])
(define_expand "sse_prologue_save"
[(parallel [(set (match_operand:BLK 0 "" "")
int rw = INTVAL (operands[1]);
int locality = INTVAL (operands[2]);
- if (rw != 0 && rw != 1)
- abort ();
- if (locality < 0 || locality > 3)
- abort ();
- if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
- abort ();
+ gcc_assert (rw == 0 || rw == 1);
+ gcc_assert (locality >= 0 && locality <= 3);
+ gcc_assert (GET_MODE (operands[0]) == Pmode
+ || GET_MODE (operands[0]) == VOIDmode);
/* Use 3dNOW prefetch in case we are asking for write prefetch not
- suported by SSE counterpart or the SSE prefetch is not available
+ supported by SSE counterpart or the SSE prefetch is not available
(K6 machines). Otherwise use SSE prefetch as it allows specifying
of locality. */
if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
};
int locality = INTVAL (operands[1]);
- if (locality < 0 || locality > 3)
- abort ();
+ gcc_assert (locality >= 0 && locality <= 3);
return patterns[locality];
}
};
int locality = INTVAL (operands[1]);
- if (locality < 0 || locality > 3)
- abort ();
+ gcc_assert (locality >= 0 && locality <= 3);
return patterns[locality];
}
[(set_attr "type" "mmx")
(set_attr "memory" "none")])
+(define_expand "stack_protect_set"
+ [(match_operand 0 "memory_operand" "")
+ (match_operand 1 "memory_operand" "")]
+ ""
+{
+#ifdef TARGET_THREAD_SSP_OFFSET
+ if (TARGET_64BIT)
+ emit_insn (gen_stack_tls_protect_set_di (operands[0],
+ GEN_INT (TARGET_THREAD_SSP_OFFSET)));
+ else
+ emit_insn (gen_stack_tls_protect_set_si (operands[0],
+ GEN_INT (TARGET_THREAD_SSP_OFFSET)));
+#else
+ if (TARGET_64BIT)
+ emit_insn (gen_stack_protect_set_di (operands[0], operands[1]));
+ else
+ emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
+#endif
+ DONE;
+})
+
+(define_insn "stack_protect_set_si"
+ [(set (match_operand:SI 0 "memory_operand" "=m")
+ (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+ (set (match_scratch:SI 2 "=&r") (const_int 0))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "mov{l}\t{%1, %2|%2, %1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
+ [(set_attr "type" "multi")])
+
+(define_insn "stack_protect_set_di"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
+ (set (match_scratch:DI 2 "=&r") (const_int 0))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "mov{q}\t{%1, %2|%2, %1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
+ [(set_attr "type" "multi")])
+
+(define_insn "stack_tls_protect_set_si"
+ [(set (match_operand:SI 0 "memory_operand" "=m")
+ (unspec:SI [(match_operand:SI 1 "const_int_operand" "i")] UNSPEC_SP_TLS_SET))
+ (set (match_scratch:SI 2 "=&r") (const_int 0))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR %%gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
+ [(set_attr "type" "multi")])
+
+(define_insn "stack_tls_protect_set_di"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (unspec:DI [(match_operand:DI 1 "const_int_operand" "i")] UNSPEC_SP_TLS_SET))
+ (set (match_scratch:DI 2 "=&r") (const_int 0))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
+ [(set_attr "type" "multi")])
+
+(define_expand "stack_protect_test"
+ [(match_operand 0 "memory_operand" "")
+ (match_operand 1 "memory_operand" "")
+ (match_operand 2 "" "")]
+ ""
+{
+ rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
+ ix86_compare_op0 = operands[0];
+ ix86_compare_op1 = operands[1];
+ ix86_compare_emitted = flags;
+
+#ifdef TARGET_THREAD_SSP_OFFSET
+ if (TARGET_64BIT)
+ emit_insn (gen_stack_tls_protect_test_di (flags, operands[0],
+ GEN_INT (TARGET_THREAD_SSP_OFFSET)));
+ else
+ emit_insn (gen_stack_tls_protect_test_si (flags, operands[0],
+ GEN_INT (TARGET_THREAD_SSP_OFFSET)));
+#else
+ if (TARGET_64BIT)
+ emit_insn (gen_stack_protect_test_di (flags, operands[0], operands[1]));
+ else
+ emit_insn (gen_stack_protect_test_si (flags, operands[0], operands[1]));
+#endif
+ emit_jump_insn (gen_beq (operands[2]));
+ DONE;
+})
+
+(define_insn "stack_protect_test_si"
+ [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ (unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
+ (match_operand:SI 2 "memory_operand" "m")]
+ UNSPEC_SP_TEST))
+ (clobber (match_scratch:SI 3 "=&r"))]
+ ""
+ "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%2, %3|%3, %2}"
+ [(set_attr "type" "multi")])
+
+(define_insn "stack_protect_test_di"
+ [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ (unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
+ (match_operand:DI 2 "memory_operand" "m")]
+ UNSPEC_SP_TEST))
+ (clobber (match_scratch:DI 3 "=&r"))]
+ "TARGET_64BIT"
+ "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%2, %3|%3, %2}"
+ [(set_attr "type" "multi")])
+
+(define_insn "stack_tls_protect_test_si"
+ [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ (unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
+ (match_operand:SI 2 "const_int_operand" "i")]
+ UNSPEC_SP_TLS_TEST))
+ (clobber (match_scratch:SI 3 "=r"))]
+ ""
+ "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR %%gs:%P2}"
+ [(set_attr "type" "multi")])
+
+(define_insn "stack_tls_protect_test_di"
+ [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ (unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
+ (match_operand:DI 2 "const_int_operand" "i")]
+ UNSPEC_SP_TLS_TEST))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_64BIT"
+ "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}"
+ [(set_attr "type" "multi")])
+
(include "sse.md")
(include "mmx.md")
+(include "sync.md")
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