\f
;; Processor type.
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
- generic64,amdfam10,bdver1"
+ generic64,amdfam10"
(const (symbol_ref "ix86_schedule")))
;; A basic instruction type. Refinements due to arguments to be
&& !x86_64_immediate_operand (operands[1], DImode) && 1"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))]
-{
- split_di (&operands[1], 1, &operands[2], &operands[3]);
-
- operands[1] = gen_lowpart (DImode, operands[2]);
- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
- GEN_INT (4)));
-})
+ "split_di (&operands[1], 1, &operands[2], &operands[3]);
+ operands[1] = gen_lowpart (DImode, operands[2]);
+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
+ GEN_INT (4)));
+ ")
(define_split
[(set (match_operand:DI 0 "push_operand" "")
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))]
-{
- split_di (&operands[1], 1, &operands[2], &operands[3]);
-
- operands[1] = gen_lowpart (DImode, operands[2]);
- operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
- GEN_INT (4)));
-})
+ "split_di (&operands[1], 1, &operands[2], &operands[3]);
+ operands[1] = gen_lowpart (DImode, operands[2]);
+ operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
+ GEN_INT (4)));
+ ")
(define_insn "*pushdi2_prologue_rex64"
[(set (match_operand:DI 0 "push_operand" "=<")
case MODE_V4SF:
return "%vxorps\t%0, %d0";
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vxorps\t%0, %d0";
- else
- return "%vxorpd\t%0, %d0";
+ return "%vxorpd\t%0, %d0";
case MODE_TI:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vxorps\t%0, %d0";
- else
- return "%vpxor\t%0, %d0";
+ return "%vpxor\t%0, %d0";
default:
gcc_unreachable ();
}
case MODE_V4SF:
return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovaps\t{%1, %0|%0, %1}";
- else
- return "%vmovapd\t{%1, %0|%0, %1}";
+ return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_TI:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovaps\t{%1, %0|%0, %1}";
- else
- return "%vmovdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_DI:
return "%vmovq\t{%1, %0|%0, %1}";
case MODE_DF:
case MODE_V4SF:
return "%vxorps\t%0, %d0";
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vxorps\t%0, %d0";
- else
- return "%vxorpd\t%0, %d0";
+ return "%vxorpd\t%0, %d0";
case MODE_TI:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vxorps\t%0, %d0";
- else
- return "%vpxor\t%0, %d0";
+ return "%vpxor\t%0, %d0";
default:
gcc_unreachable ();
}
case MODE_V4SF:
return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovaps\t{%1, %0|%0, %1}";
- else
- return "%vmovapd\t{%1, %0|%0, %1}";
+ return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_TI:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovaps\t{%1, %0|%0, %1}";
- else
- return "%vmovdqa\t{%1, %0|%0, %1}";
+ return "%vmovdqa\t{%1, %0|%0, %1}";
case MODE_DI:
return "%vmovq\t{%1, %0|%0, %1}";
case MODE_DF:
case MODE_V4SF:
return "xorps\t%0, %0";
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "xorps\t%0, %0";
- else
- return "xorpd\t%0, %0";
+ return "xorpd\t%0, %0";
case MODE_TI:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
+ return "pxor\t%0, %0";
default:
gcc_unreachable ();
}
case MODE_V4SF:
return "movaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movapd\t{%1, %0|%0, %1}";
+ return "movapd\t{%1, %0|%0, %1}";
case MODE_TI:
- if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
+ return "movdqa\t{%1, %0|%0, %1}";
case MODE_DI:
return "movq\t{%1, %0|%0, %1}";
case MODE_DF:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "add{<imodesuffix>}\t%0, %0";
- case TYPE_LEA:
- return "#";
-
default:
- if (REG_P (operands[2]))
- return "sal{<imodesuffix>}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{<imodesuffix>}\t%0";
else
return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
gcc_assert (operands[2] == const1_rtx);
return "add{l}\t%k0, %k0";
- case TYPE_LEA:
- return "#";
-
default:
- if (REG_P (operands[2]))
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%k0";
else
return "sal{l}\t{%2, %k0|%k0, %2}";
return "add{w}\t%0, %0";
default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
{
case TYPE_LEA:
return "#";
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t%0, %0";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{w}\t%0, %0";
default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
return "add{b}\t%0, %0";
default:
- if (REG_P (operands[2]))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else
- return "sal{b}\t{%b2, %0|%0, %b2}";
- }
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t%0";
+ return "sal{l}\t%k0";
else
return "sal{b}\t%0";
}
{
case TYPE_LEA:
return "#";
+
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
return "add{b}\t%0, %0";
default:
- if (REG_P (operands[2]))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else
- return "sal{b}\t{%b2, %0|%0, %b2}";
- }
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t%0";
+ return "sal{l}\t%k0";
else
return "sal{b}\t%0";
}
(const_string "*")))
(set_attr "mode" "QI,SI,SI")])
+(define_insn "*ashlqi3_1_slp"
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
+ (ashift:QI (match_dup 0)
+ (match_operand:QI 1 "nonmemory_operand" "cI")))
+ (clobber (reg:CC FLAGS_REG))]
+ "(optimize_function_for_size_p (cfun)
+ || !TARGET_PARTIAL_FLAG_REG_STALL
+ || (operands[1] == const1_rtx
+ && (TARGET_SHIFT1
+ || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
+{
+ switch (get_attr_type (insn))
+ {
+ case TYPE_ALU:
+ gcc_assert (operands[1] == const1_rtx);
+ return "add{b}\t%0, %0";
+
+ default:
+ if (operands[1] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ return "sal{b}\t%0";
+ else
+ return "sal{b}\t{%1, %0|%0, %1}";
+ }
+}
+ [(set (attr "type")
+ (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
+ (const_int 0))
+ (match_operand 0 "register_operand" ""))
+ (match_operand 1 "const1_operand" ""))
+ (const_string "alu")
+ ]
+ (const_string "ishift1")))
+ (set (attr "length_immediate")
+ (if_then_else
+ (ior (eq_attr "type" "alu")
+ (and (eq_attr "type" "ishift1")
+ (and (match_operand 1 "const1_operand" "")
+ (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
+ (const_int 0)))))
+ (const_string "0")
+ (const_string "*")))
+ (set_attr "mode" "QI")])
+
;; Convert lea to the lea pattern to avoid flags dependency.
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(const_string "*")))
(set_attr "mode" "<MODE>")])
-;; See comment above `ashldi3' about how this works.
+;; See comment above `ashl<mode>3' about how this works.
-(define_expand "ashr<mode>3"
+(define_expand "<shiftrt_insn><mode>3"
[(set (match_operand:SDWIM 0 "<shift_operand>" "")
- (ashiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
- "ix86_expand_binary_operator (ASHIFTRT, <MODE>mode, operands); DONE;")
+ "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
-(define_insn_and_split "*ashr<mode>3_doubleword"
+(define_insn_and_split "*<shiftrt_insn><mode>3_doubleword"
[(set (match_operand:DWI 0 "register_operand" "=r")
- (ashiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "<S>c")))
+ (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
+ (match_operand:QI 2 "nonmemory_operand" "<S>c")))
(clobber (reg:CC FLAGS_REG))]
""
"#"
"(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
[(const_int 0)]
- "ix86_split_ashr (operands, NULL_RTX, <MODE>mode); DONE;"
+ "ix86_split_<shiftrt_insn> (operands, NULL_RTX, <MODE>mode); DONE;"
[(set_attr "type" "multi")])
;; By default we don't ask for a scratch register, because when DWImode
(define_peephole2
[(match_scratch:DWIH 3 "r")
(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
- (ashiftrt:<DWI>
+ (any_shiftrt:<DWI>
(match_operand:<DWI> 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_dup 3)]
"TARGET_CMOVE"
[(const_int 0)]
- "ix86_split_ashr (operands, operands[3], <DWI>mode); DONE;")
+ "ix86_split_<shiftrt_insn> (operands, operands[3], <DWI>mode); DONE;")
(define_insn "x86_64_shrd"
[(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
"shrd{l}\t{%s2%1, %0|%0, %1, %2}"
[(set_attr "type" "ishift")
(set_attr "prefix_0f" "1")
+ (set_attr "mode" "SI")
(set_attr "pent_pair" "np")
- (set_attr "mode" "SI")])
+ (set_attr "athlon_decode" "vector")
+ (set_attr "amdfam10_decode" "vector")])
(define_insn "ashrdi3_cvt"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
DONE;
})
-(define_insn "*ashr<mode>3_1"
+(define_insn "*<shiftrt_insn><mode>3_1"
[(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
- (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "c<S>")))
+ (any_shiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "nonmemory_operand" "c<S>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
-{
- if (REG_P (operands[2]))
- return "sar{<imodesuffix>}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{<imodesuffix>}\t%0";
- else
- return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*ashrsi3_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "cI"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-{
- if (REG_P (operands[2]))
- return "sar{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{l}\t%k0";
- else
- return "sar{l}\t{%2, %k0|%k0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrqi3_1_slp"
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
- (ashiftrt:QI (match_dup 0)
- (match_operand:QI 1 "nonmemory_operand" "cI")))
- (clobber (reg:CC FLAGS_REG))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_REG_STALL
- || (operands[1] == const1_rtx
- && TARGET_SHIFT1))"
-{
- if (REG_P (operands[1]))
- return "sar{b}\t{%b1, %0|%0, %b1}";
- else if (operands[1] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{b}\t%0";
- else
- return "sar{b}\t{%1, %0|%0, %1}";
-}
- [(set_attr "type" "ishift1")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 1 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "QI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashr<mode>3_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
- (const_int 0)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
- (ashiftrt:SWI (match_dup 1) (match_dup 2)))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && TARGET_SHIFT1))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
-{
- if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{<imodesuffix>}\t%0";
- else
- return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*ashrsi3_cmp_zext"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && TARGET_SHIFT1))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-{
- if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{l}\t%k0";
- else
- return "sar{l}\t{%2, %k0|%k0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-(define_insn "*ashr<mode>3_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
- (const_int 0)))
- (clobber (match_scratch:SWI 0 "=<r>"))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && TARGET_SHIFT1))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
+ "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sar{<imodesuffix>}\t%0";
- else
- return "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ishift")
- (set (attr "length_immediate")
- (if_then_else
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "<MODE>")])
-\f
-;; Logical shift instructions
-
-;; See comment above `ashldi3' about how this works.
-
-(define_expand "lshr<mode>3"
- [(set (match_operand:SDWIM 0 "<shift_operand>" "")
- (lshiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- ""
- "ix86_expand_binary_operator (LSHIFTRT, <MODE>mode, operands); DONE;")
-
-(define_insn_and_split "*lshr<mode>3_doubleword"
- [(set (match_operand:DWI 0 "register_operand" "=r")
- (lshiftrt:DWI (match_operand:DWI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "<S>c")))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "#"
- "(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
- [(const_int 0)]
- "ix86_split_lshr (operands, NULL_RTX, <MODE>mode); DONE;"
- [(set_attr "type" "multi")])
-
-;; By default we don't ask for a scratch register, because when DWImode
-;; values are manipulated, registers are already at a premium. But if
-;; we have one handy, we won't turn it away.
-
-(define_peephole2
- [(match_scratch:DWIH 3 "r")
- (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
- (lshiftrt:<DWI>
- (match_operand:<DWI> 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])
- (match_dup 3)]
- "TARGET_CMOVE"
- [(const_int 0)]
- "ix86_split_lshr (operands, operands[3], <DWI>mode); DONE;")
-
-(define_insn "*lshr<mode>3_1"
- [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
- (lshiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands)"
-{
- if (REG_P (operands[2]))
- return "shr{<imodesuffix>}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "shr{<imodesuffix>}\t%0";
+ return "<shiftrt>{<imodesuffix>}\t%0";
else
- return "shr{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*lshrsi3_1_zext"
+(define_insn "*<shiftrt_insn>si3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "cI"))))
+ (any_shiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "nonmemory_operand" "cI"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, SImode, operands)"
+ "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
- if (REG_P (operands[2]))
- return "shr{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "shr{l}\t%k0";
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ return "<shiftrt>{l}\t%k0";
else
- return "shr{l}\t{%2, %k0|%k0, %2}";
+ return "<shiftrt>{l}\t{%2, %k0|%k0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(const_string "*")))
(set_attr "mode" "SI")])
-(define_insn "*lshrqi3_1_slp"
+(define_insn "*<shiftrt_insn>qi3_1_slp"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
- (lshiftrt:QI (match_dup 0)
- (match_operand:QI 1 "nonmemory_operand" "cI")))
+ (any_shiftrt:QI (match_dup 0)
+ (match_operand:QI 1 "nonmemory_operand" "cI")))
(clobber (reg:CC FLAGS_REG))]
"(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_REG_STALL
|| (operands[1] == const1_rtx
&& TARGET_SHIFT1))"
{
- if (REG_P (operands[1]))
- return "shr{b}\t{%b1, %0|%0, %b1}";
- else if (operands[1] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "shr{b}\t%0";
+ if (operands[1] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ return "<shiftrt>{b}\t%0";
else
- return "shr{b}\t{%1, %0|%0, %1}";
+ return "<shiftrt>{b}\t{%1, %0|%0, %1}";
}
[(set_attr "type" "ishift1")
(set (attr "length_immediate")
;; This pattern can't accept a variable shift count, since shifts by
;; zero don't affect the flags. We assume that shifts by constant
;; zero are optimized away.
-(define_insn "*lshr<mode>3_cmp"
+(define_insn "*<shiftrt_insn><mode>3_cmp"
[(set (reg FLAGS_REG)
(compare
- (lshiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
+ (any_shiftrt:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
(const_int 0)))
(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
- (lshiftrt:SWI (match_dup 1) (match_dup 2)))]
+ (any_shiftrt:SWI (match_dup 1) (match_dup 2)))]
"(optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& TARGET_SHIFT1))
&& ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands)"
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "shr{<imodesuffix>}\t%0";
+ return "<shiftrt>{<imodesuffix>}\t%0";
else
- return "shr{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*lshrsi3_cmp_zext"
+(define_insn "*<shiftrt_insn>si3_cmp_zext"
[(set (reg FLAGS_REG)
(compare
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
+ (any_shiftrt:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (lshiftrt:SI (match_dup 1) (match_dup 2))))]
+ (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT
&& (optimize_function_for_size_p (cfun)
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& TARGET_SHIFT1))
&& ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (LSHIFTRT, SImode, operands)"
+ && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "shr{l}\t%k0";
+ return "<shiftrt>{l}\t%k0";
else
- return "shr{l}\t{%2, %k0|%k0, %2}";
+ return "<shiftrt>{l}\t{%2, %k0|%k0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(const_string "*")))
(set_attr "mode" "SI")])
-(define_insn "*lshr<mode>3_cconly"
+(define_insn "*<shiftrt_insn><mode>3_cconly"
[(set (reg FLAGS_REG)
(compare
- (lshiftrt:SWI (match_operand:SWI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
+ (any_shiftrt:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "0")
+ (match_operand:QI 2 "<shift_immediate_operand>" "<S>"))
(const_int 0)))
(clobber (match_scratch:SWI 0 "=<r>"))]
"(optimize_function_for_size_p (cfun)
|| (operands[2] == const1_rtx
&& TARGET_SHIFT1))
&& ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands)"
+ && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "shr{<imodesuffix>}\t%0";
+ return "<shiftrt>{<imodesuffix>}\t%0";
else
- return "shr{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "type" "ishift")
(set (attr "length_immediate")
[(const_int 0)]
{
operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
-
ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
operands[3], operands[7],
operands[4], operands[5], operands[6], NULL_RTX);
{
operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
-
ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
operands[3], operands[7],
operands[4], operands[5], operands[6], operands[2]);
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"TARGET_64BIT"
- "rep{%;} movsq"
+ "rep movsq"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"!TARGET_64BIT"
- "rep{%;} movs{l|d}"
+ "rep movs{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"TARGET_64BIT"
- "rep{%;} movs{l|d}"
+ "rep movs{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"!TARGET_64BIT"
- "rep{%;} movsb"
+ "rep movsb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"TARGET_64BIT"
- "rep{%;} movsb"
+ "rep movsb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(use (match_operand:DI 2 "register_operand" "a"))
(use (match_dup 4))]
"TARGET_64BIT"
- "rep{%;} stosq"
+ "rep stosq"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(use (match_operand:SI 2 "register_operand" "a"))
(use (match_dup 4))]
"!TARGET_64BIT"
- "rep{%;} stos{l|d}"
+ "rep stos{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(use (match_operand:SI 2 "register_operand" "a"))
(use (match_dup 4))]
"TARGET_64BIT"
- "rep{%;} stos{l|d}"
+ "rep stos{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(use (match_operand:QI 2 "register_operand" "a"))
(use (match_dup 4))]
"!TARGET_64BIT"
- "rep{%;} stosb"
+ "rep stosb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(use (match_operand:QI 2 "register_operand" "a"))
(use (match_dup 4))]
"TARGET_64BIT"
- "rep{%;} stosb"
+ "rep stosb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (match_operand:SI 2 "register_operand" "=c"))]
"!TARGET_64BIT"
- "repz{%;} cmpsb"
+ "repz cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set_attr "prefix_rep" "1")])
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (match_operand:DI 2 "register_operand" "=c"))]
"TARGET_64BIT"
- "repz{%;} cmpsb"
+ "repz cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set_attr "prefix_rex" "0")
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (match_operand:SI 2 "register_operand" "=c"))]
"!TARGET_64BIT"
- "repz{%;} cmpsb"
+ "repz cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set_attr "prefix_rep" "1")])
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (match_operand:DI 2 "register_operand" "=c"))]
"TARGET_64BIT"
- "repz{%;} cmpsb"
+ "repz cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set_attr "prefix_rex" "0")
(clobber (match_operand:SI 1 "register_operand" "=D"))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
- "repnz{%;} scasb"
+ "repnz scasb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set_attr "prefix_rep" "1")])
(clobber (match_operand:DI 1 "register_operand" "=D"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "repnz{%;} scasb"
+ "repnz scasb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set_attr "prefix_rex" "0")
(if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
(match_dup 7)
(match_dup 8)))]
-{
- split_di (&operands[2], 2, &operands[5], &operands[7]);
- split_di (&operands[0], 1, &operands[2], &operands[3]);
-})
+ "split_di (&operands[2], 2, &operands[5], &operands[7]);
+ split_di (&operands[0], 1, &operands[2], &operands[3]);")
(define_insn "*movxfcc_1"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(reg:DI XMM5_REG)
(reg:DI XMM6_REG)
(reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
- (clobber (reg:CC FLAGS_REG))
(clobber (match_operand:DI 1 "register_operand" ""))
(use (match_operand:DI 2 "immediate_operand" ""))
(use (label_ref:DI (match_operand 3 "" "")))
(reg:DI XMM5_REG)
(reg:DI XMM6_REG)
(reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
- (clobber (reg:CC FLAGS_REG))
(clobber (match_operand:DI 1 "register_operand" "=r"))
(use (match_operand:DI 2 "const_int_operand" "i"))
(use (label_ref:DI (match_operand 3 "" "X")))
(reg:DI XMM5_REG)
(reg:DI XMM6_REG)
(reg:DI XMM7_REG)] UNSPEC_SSE_PROLOGUE_SAVE))
- (clobber (reg:CC FLAGS_REG))
(clobber (match_operand:DI 1 "register_operand" ""))
(use (match_operand:DI 2 "const_int_operand" ""))
(use (match_operand 3 "" ""))
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