(UNSPEC_RCP 45)
(UNSPEC_RSQRT 46)
(UNSPEC_SFENCE 47)
- (UNSPEC_NOP 48) ; prevents combiner cleverness
(UNSPEC_PFRCP 49)
(UNSPEC_PFRCPIT1 40)
(UNSPEC_PFRCPIT2 41)
[(set (match_operand:DF 0 "nonimmediate_operand"
"=f,m,f,*r ,o ,Y2*x,Y2*x,Y2*x ,m ")
(match_operand:DF 1 "general_operand"
- "fm,f,G,*roF,F*r,C ,Y2*x,mY2*x,Y2*x"))]
+ "fm,f,G,*roF,*Fr,C ,Y2*x,mY2*x,Y2*x"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
&& (reload_in_progress || reload_completed
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
+ && !memory_operand (operands[0], DFmode)
&& standard_80387_constant_p (operands[1]))
|| GET_CODE (operands[1]) != CONST_DOUBLE
- || memory_operand (operands[0], DFmode))"
+ || ((optimize_size
+ || !TARGET_MEMORY_MISMATCH_STALL
+ || reload_in_progress || reload_completed)
+ && memory_operand (operands[0], DFmode)))"
{
switch (which_alternative)
{
DONE;
})
-(define_expand "floatunssisf2"
- [(use (match_operand:SF 0 "register_operand" ""))
+(define_expand "floatunssi<mode>2"
+ [(use (match_operand:MODEF 0 "register_operand" ""))
(use (match_operand:SI 1 "nonimmediate_operand" ""))]
- "!TARGET_64BIT && TARGET_SSE_MATH"
+ "!TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
{
- if (TARGET_SSE2)
- ix86_expand_convert_uns_sisf_sse (operands[0], operands[1]);
- else
- x86_emit_floatuns (operands);
+ ix86_expand_convert_uns_si<mode>_sse (operands[0], operands[1]);
DONE;
})
-(define_expand "floatunssidf2"
- [(use (match_operand:DF 0 "register_operand" ""))
- (use (match_operand:SI 1 "nonimmediate_operand" ""))]
- "!TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE2"
- "ix86_expand_convert_uns_sidf_sse (operands[0], operands[1]); DONE;")
-
(define_expand "floatunsdisf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:DI 1 "nonimmediate_operand" ""))]
(define_expand "floatunsdidf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DI 1 "nonimmediate_operand" ""))]
- "TARGET_SSE_MATH && TARGET_SSE2
- && (TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)"
+ "(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)
+ && TARGET_SSE2 && TARGET_SSE_MATH"
{
if (TARGET_64BIT)
x86_emit_floatuns (operands);
;; 0xffffffff is NaN, but not in normalized form, so we can't represent
;; it directly.
-(define_insn "*sse_setccsf"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (match_operator:SF 1 "sse_comparison_operator"
- [(match_operand:SF 2 "register_operand" "0")
- (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE && !TARGET_SSE5"
- "cmp%D1ss\t{%3, %0|%0, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "SF")])
-
-(define_insn "*sse_setccdf"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (match_operator:DF 1 "sse_comparison_operator"
- [(match_operand:DF 2 "register_operand" "0")
- (match_operand:DF 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE2 && !TARGET_SSE5"
- "cmp%D1sd\t{%3, %0|%0, %3}"
+(define_insn "*sse_setcc<mode>"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (match_operator:MODEF 1 "sse_comparison_operator"
+ [(match_operand:MODEF 2 "register_operand" "0")
+ (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
+ "cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<MODE>")])
(define_insn "*sse5_setcc<mode>"
[(set (match_operand:MODEF 0 "register_operand" "=x")
(define_expand "paritydi2"
[(set (match_operand:DI 0 "register_operand" "")
- (parity:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
+ (parity:DI (match_operand:DI 1 "register_operand" "")))]
"! TARGET_POPCNT"
{
rtx scratch = gen_reg_rtx (QImode);
(define_insn_and_split "paritydi2_cmp"
[(set (reg:CC FLAGS_REG)
- (parity:CC (match_operand:DI 3 "nonimmediate_operand" "0,m")))
- (clobber (match_scratch:DI 0 "=r,X"))
- (clobber (match_scratch:SI 1 "=r,r"))
- (clobber (match_scratch:HI 2 "=Q,Q"))]
+ (parity:CC (match_operand:DI 3 "register_operand" "0")))
+ (clobber (match_scratch:DI 0 "=r"))
+ (clobber (match_scratch:SI 1 "=&r"))
+ (clobber (match_scratch:HI 2 "=Q"))]
"! TARGET_POPCNT"
"#"
"&& reload_completed"
{
operands[4] = gen_lowpart (SImode, operands[3]);
- if (MEM_P (operands[3]))
- emit_move_insn (operands[1], gen_highpart (SImode, operands[3]));
- else if (! TARGET_64BIT)
- operands[1] = gen_highpart (SImode, operands[3]);
- else
+ if (TARGET_64BIT)
{
emit_move_insn (operands[1], gen_lowpart (SImode, operands[3]));
emit_insn (gen_lshrdi3 (operands[3], operands[3], GEN_INT (32)));
}
+ else
+ operands[1] = gen_highpart (SImode, operands[3]);
})
(define_expand "paritysi2"
[(set (match_operand:SI 0 "register_operand" "")
- (parity:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
+ (parity:SI (match_operand:SI 1 "register_operand" "")))]
"! TARGET_POPCNT"
{
rtx scratch = gen_reg_rtx (QImode);
(define_insn_and_split "paritysi2_cmp"
[(set (reg:CC FLAGS_REG)
- (parity:CC (match_operand:SI 2 "nonimmediate_operand" "0,m")))
- (clobber (match_scratch:SI 0 "=r,X"))
- (clobber (match_scratch:HI 1 "=Q,Q"))]
+ (parity:CC (match_operand:SI 2 "register_operand" "0")))
+ (clobber (match_scratch:SI 0 "=r"))
+ (clobber (match_scratch:HI 1 "=&Q"))]
"! TARGET_POPCNT"
"#"
"&& reload_completed"
{
operands[3] = gen_lowpart (HImode, operands[2]);
- if (MEM_P (operands[2]))
- emit_move_insn (operands[1], gen_highpart (HImode, operands[2]));
- else
- {
- emit_move_insn (operands[1], gen_lowpart (HImode, operands[2]));
- emit_insn (gen_lshrsi3 (operands[2], operands[2], GEN_INT (16)));
- }
+ emit_move_insn (operands[1], gen_lowpart (HImode, operands[2]));
+ emit_insn (gen_lshrsi3 (operands[2], operands[2], GEN_INT (16)));
})
(define_insn "*parityhi2_cmp"
(match_operand:DI 2 "general_operand" "")
(match_operand:DI 3 "general_operand" "")))]
"TARGET_64BIT"
- "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
(define_insn "x86_movdicc_0_m1_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(set_attr "mode" "DI")
(set_attr "length_immediate" "0")])
+(define_insn "*x86_movdicc_0_m1_se"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extract:DI (match_operand 1 "ix86_carry_flag_operator" "")
+ (const_int 1)
+ (const_int 0)))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "sbb{q}\t%0, %0"
+ [(set_attr "type" "alu")
+ (set_attr "pent_pair" "pu")
+ (set_attr "memory" "none")
+ (set_attr "imm_disp" "false")
+ (set_attr "mode" "DI")
+ (set_attr "length_immediate" "0")])
+
(define_insn "*movdicc_c_rex64"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
(match_operand:SI 2 "general_operand" "")
(match_operand:SI 3 "general_operand" "")))]
""
- "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
;; the register first winds up with `sbbl $0,reg', which is also weird.
(set_attr "mode" "SI")
(set_attr "length_immediate" "0")])
+(define_insn "*x86_movsicc_0_m1_se"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (sign_extract:SI (match_operand 1 "ix86_carry_flag_operator" "")
+ (const_int 1)
+ (const_int 0)))
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+ "sbb{l}\t%0, %0"
+ [(set_attr "type" "alu")
+ (set_attr "pent_pair" "pu")
+ (set_attr "memory" "none")
+ (set_attr "imm_disp" "false")
+ (set_attr "mode" "SI")
+ (set_attr "length_immediate" "0")])
+
(define_insn "*movsicc_noc"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
(match_operand:HI 2 "general_operand" "")
(match_operand:HI 3 "general_operand" "")))]
"TARGET_HIMODE_MATH"
- "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
(define_insn "*movhicc_noc"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(match_operand:QI 2 "general_operand" "")
(match_operand:QI 3 "general_operand" "")))]
"TARGET_QIMODE_MATH"
- "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
(define_insn_and_split "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
[(set_attr "type" "icmov")
(set_attr "mode" "SI")])
-(define_expand "movsfcc"
- [(set (match_operand:SF 0 "register_operand" "")
- (if_then_else:SF (match_operand 1 "comparison_operator" "")
- (match_operand:SF 2 "register_operand" "")
- (match_operand:SF 3 "register_operand" "")))]
- "(TARGET_80387 && TARGET_CMOVE) || TARGET_SSE_MATH"
- "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
+(define_expand "mov<mode>cc"
+ [(set (match_operand:X87MODEF 0 "register_operand" "")
+ (if_then_else:X87MODEF
+ (match_operand 1 "comparison_operator" "")
+ (match_operand:X87MODEF 2 "register_operand" "")
+ (match_operand:X87MODEF 3 "register_operand" "")))]
+ "(TARGET_80387 && TARGET_CMOVE)
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ "if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;")
(define_insn "*movsfcc_1_387"
[(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
[(set_attr "type" "fcmov,fcmov,icmov,icmov")
(set_attr "mode" "SF,SF,SI,SI")])
-(define_expand "movdfcc"
- [(set (match_operand:DF 0 "register_operand" "")
- (if_then_else:DF (match_operand 1 "comparison_operator" "")
- (match_operand:DF 2 "register_operand" "")
- (match_operand:DF 3 "register_operand" "")))]
- "(TARGET_80387 && TARGET_CMOVE) || (TARGET_SSE2 && TARGET_SSE_MATH)"
- "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-
(define_insn "*movdfcc_1"
[(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
split_di (operands+3, 1, operands+7, operands+8);
split_di (operands, 1, operands+2, operands+3);")
-(define_expand "movxfcc"
- [(set (match_operand:XF 0 "register_operand" "")
- (if_then_else:XF (match_operand 1 "comparison_operator" "")
- (match_operand:XF 2 "register_operand" "")
- (match_operand:XF 3 "register_operand" "")))]
- "TARGET_80387 && TARGET_CMOVE"
- "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-
(define_insn "*movxfcc_1"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
;; are undefined in this condition, we're certain this is correct.
-(define_insn "sminsf3"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (smin:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
- (match_operand:SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE_MATH"
- "minss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-(define_insn "smaxsf3"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (smax:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
- (match_operand:SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE_MATH"
- "maxss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-(define_insn "smindf3"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (smin:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
- (match_operand:DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && TARGET_SSE_MATH"
- "minsd\t{%2, %0|%0, %2}"
+(define_insn "smin<mode>3"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (smin:MODEF
+ (match_operand:MODEF 1 "nonimmediate_operand" "%0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+ "mins<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "smaxdf3"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (smax:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
- (match_operand:DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && TARGET_SSE_MATH"
- "maxsd\t{%2, %0|%0, %2}"
+(define_insn "smax<mode>3"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (smax:MODEF
+ (match_operand:MODEF 1 "nonimmediate_operand" "%0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+ "maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<MODE>")])
;; These versions of the min/max patterns implement exactly the operations
;; min = (op1 < op2 ? op1 : op2)
;; Their operands are not commutative, and thus they may be used in the
;; presence of -0.0 and NaN.
-(define_insn "*ieee_sminsf3"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (unspec:SF [(match_operand:SF 1 "register_operand" "0")
- (match_operand:SF 2 "nonimmediate_operand" "xm")]
- UNSPEC_IEEE_MIN))]
- "TARGET_SSE_MATH"
- "minss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-(define_insn "*ieee_smaxsf3"
- [(set (match_operand:SF 0 "register_operand" "=x")
- (unspec:SF [(match_operand:SF 1 "register_operand" "0")
- (match_operand:SF 2 "nonimmediate_operand" "xm")]
- UNSPEC_IEEE_MAX))]
- "TARGET_SSE_MATH"
- "maxss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-(define_insn "*ieee_smindf3"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (unspec:DF [(match_operand:DF 1 "register_operand" "0")
- (match_operand:DF 2 "nonimmediate_operand" "xm")]
- UNSPEC_IEEE_MIN))]
- "TARGET_SSE2 && TARGET_SSE_MATH"
- "minsd\t{%2, %0|%0, %2}"
+(define_insn "*ieee_smin<mode>3"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (unspec:MODEF
+ [(match_operand:MODEF 1 "register_operand" "0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MIN))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+ "mins<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<MODE>")])
-(define_insn "*ieee_smaxdf3"
- [(set (match_operand:DF 0 "register_operand" "=x")
- (unspec:DF [(match_operand:DF 1 "register_operand" "0")
- (match_operand:DF 2 "nonimmediate_operand" "xm")]
- UNSPEC_IEEE_MAX))]
- "TARGET_SSE2 && TARGET_SSE_MATH"
- "maxsd\t{%2, %0|%0, %2}"
+(define_insn "*ieee_smax<mode>3"
+ [(set (match_operand:MODEF 0 "register_operand" "=x")
+ (unspec:MODEF
+ [(match_operand:MODEF 1 "register_operand" "0")
+ (match_operand:MODEF 2 "nonimmediate_operand" "xm")]
+ UNSPEC_IEEE_MAX))]
+ "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
+ "maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
[(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
+ (set_attr "mode" "<MODE>")])
;; Make two stack loads independent:
;; fld aa fld aa
(match_operand:QI 2 "register_operand" "")
(match_operand:QI 3 "const_int_operand" "")]
""
- "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
(define_expand "addhicc"
[(match_operand:HI 0 "register_operand" "")
(match_operand:HI 2 "register_operand" "")
(match_operand:HI 3 "const_int_operand" "")]
""
- "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
(define_expand "addsicc"
[(match_operand:SI 0 "register_operand" "")
(match_operand:SI 2 "register_operand" "")
(match_operand:SI 3 "const_int_operand" "")]
""
- "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
(define_expand "adddicc"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 2 "register_operand" "")
(match_operand:DI 3 "const_int_operand" "")]
"TARGET_64BIT"
- "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
+ "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
\f
;; Misc patterns (?)
(set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_STACK_PROBE"
- "call\t__alloca"
+ "call\t___chkstk"
[(set_attr "type" "multi")
(set_attr "length" "5")])
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