/* Definitions of target machine for GCC for IA-32.
Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
Free Software Foundation, Inc.
This file is part of GCC.
/* Redefines for option macros. */
#define TARGET_64BIT OPTION_ISA_64BIT
+#define TARGET_X32 OPTION_ISA_X32
#define TARGET_MMX OPTION_ISA_MMX
#define TARGET_3DNOW OPTION_ISA_3DNOW
#define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
#define TARGET_SSE4_1 OPTION_ISA_SSE4_1
#define TARGET_SSE4_2 OPTION_ISA_SSE4_2
#define TARGET_AVX OPTION_ISA_AVX
+#define TARGET_AVX2 OPTION_ISA_AVX2
#define TARGET_FMA OPTION_ISA_FMA
#define TARGET_SSE4A OPTION_ISA_SSE4A
#define TARGET_FMA4 OPTION_ISA_FMA4
#define TARGET_LWP OPTION_ISA_LWP
#define TARGET_ROUND OPTION_ISA_ROUND
#define TARGET_ABM OPTION_ISA_ABM
+#define TARGET_BMI OPTION_ISA_BMI
+#define TARGET_BMI2 OPTION_ISA_BMI2
+#define TARGET_LZCNT OPTION_ISA_LZCNT
+#define TARGET_TBM OPTION_ISA_TBM
#define TARGET_POPCNT OPTION_ISA_POPCNT
#define TARGET_SAHF OPTION_ISA_SAHF
#define TARGET_MOVBE OPTION_ISA_MOVBE
#define TARGET_RDRND OPTION_ISA_RDRND
#define TARGET_F16C OPTION_ISA_F16C
+#define TARGET_LP64 (TARGET_64BIT && !TARGET_X32)
/* SSE4.1 defines round instructions */
#define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
#include "config/vxworks-dummy.h"
-/* Algorithm to expand string function with. */
-enum stringop_alg
-{
- no_stringop,
- libcall,
- rep_prefix_1_byte,
- rep_prefix_4_byte,
- rep_prefix_8_byte,
- loop_1_byte,
- loop,
- unrolled_loop
-};
+#include "config/i386/i386-opts.h"
#define MAX_STRINGOP_ALGS 4
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
-#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
+#define TARGET_CORE2_32 (ix86_tune == PROCESSOR_CORE2_32)
+#define TARGET_CORE2_64 (ix86_tune == PROCESSOR_CORE2_64)
+#define TARGET_CORE2 (TARGET_CORE2_32 || TARGET_CORE2_64)
#define TARGET_COREI7_32 (ix86_tune == PROCESSOR_COREI7_32)
#define TARGET_COREI7_64 (ix86_tune == PROCESSOR_COREI7_64)
#define TARGET_COREI7 (TARGET_COREI7_32 || TARGET_COREI7_64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
+#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
+#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
/* Feature tests against the various tunings. */
X86_TUNE_PUSH_MEMORY,
X86_TUNE_ZERO_EXTEND_WITH_AND,
X86_TUNE_UNROLL_STRLEN,
- X86_TUNE_DEEP_BRANCH_PREDICTION,
X86_TUNE_BRANCH_PREDICTION_HINTS,
X86_TUNE_DOUBLE_WITH_ADD,
X86_TUNE_USE_SAHF,
X86_TUNE_FUSE_CMP_AND_BRANCH,
X86_TUNE_OPT_AGU,
X86_TUNE_VECTORIZE_DOUBLE,
+ X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL,
+ X86_TUNE_AVX128_OPTIMAL,
+ X86_TUNE_REASSOC_INT_TO_PARALLEL,
+ X86_TUNE_REASSOC_FP_TO_PARALLEL,
X86_TUNE_LAST
};
#define TARGET_ZERO_EXTEND_WITH_AND \
ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
-#define TARGET_DEEP_BRANCH_PREDICTION \
- ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
#define TARGET_BRANCH_PREDICTION_HINTS \
ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
#define TARGET_VECTORIZE_DOUBLE \
ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
+#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
+ ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
+#define TARGET_AVX128_OPTIMAL \
+ ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
+#define TARGET_REASSOC_INT_TO_PARALLEL \
+ ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL]
+#define TARGET_REASSOC_FP_TO_PARALLEL \
+ ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL]
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {
#define TARGET_SUBTARGET64_DEFAULT 0
#define TARGET_SUBTARGET64_ISA_DEFAULT 0
-/* This is not really a target flag, but is done this way so that
- it's analogous to similar code for Mach-O on PowerPC. darwin.h
- redefines this to 1. */
+/* Replace MACH-O, ifdefs by in-line tests, where possible.
+ (a) Macros defined in config/i386/darwin.h */
#define TARGET_MACHO 0
-
-/* Branch island 'stubs' are emitted for earlier versions of darwin.
- This provides a default (over-ridden in darwin.h.) */
-#ifndef TARGET_MACHO_BRANCH_ISLANDS
#define TARGET_MACHO_BRANCH_ISLANDS 0
-#endif
+#define MACHOPIC_ATT_STUB 0
+/* (b) Macros defined in config/darwin.h */
+#define MACHO_DYNAMIC_NO_PIC_P 0
+#define MACHOPIC_INDIRECT 0
+#define MACHOPIC_PURE 0
/* For the Windows 64-bit ABI. */
#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
+/* For the Windows 32-bit ABI. */
+#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
+
/* This is re-defined by cygming.h. */
#define TARGET_SEH 0
-/* Available call abi. */
-enum calling_abi
-{
- SYSV_ABI = 0,
- MS_ABI = 1
-};
-
-/* The abi used by target. */
-extern enum calling_abi ix86_abi;
-
/* The default abi used by target. */
#define DEFAULT_ABI SYSV_ABI
#define OPT_ARCH64 "!m32"
#define OPT_ARCH32 "m32"
#else
-#define OPT_ARCH64 "m64"
-#define OPT_ARCH32 "!m64"
+#define OPT_ARCH64 "m64|mx32"
+#define OPT_ARCH32 "m64|mx32:;"
#endif
/* Support for configure-time defaults of some command line options.
/* Specs for the compiler proper */
#ifndef CC1_CPU_SPEC
-#define CC1_CPU_SPEC_1 "\
-%{msse5:-mavx \
-%n'-msse5' was removed.\n}"
+#define CC1_CPU_SPEC_1 ""
#ifndef HAVE_LOCAL_CPU_DETECT
#define CC1_CPU_SPEC CC1_CPU_SPEC_1
#else
#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
-"%{march=native:%<march=native %:local_cpu_detect(arch) \
- %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
-%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
+"%{march=native:%>march=native %:local_cpu_detect(arch) \
+ %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
+%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
#endif
#endif
\f
TARGET_CPU_DEFAULT_prescott,
TARGET_CPU_DEFAULT_nocona,
TARGET_CPU_DEFAULT_core2,
+ TARGET_CPU_DEFAULT_corei7,
TARGET_CPU_DEFAULT_atom,
TARGET_CPU_DEFAULT_geode,
TARGET_CPU_DEFAULT_k8,
TARGET_CPU_DEFAULT_amdfam10,
TARGET_CPU_DEFAULT_bdver1,
+ TARGET_CPU_DEFAULT_bdver2,
+ TARGET_CPU_DEFAULT_btver1,
TARGET_CPU_DEFAULT_max
};
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE 32
+#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
+#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
ix86_minimum_alignment (EXP, MODE, ALIGN)
-/* If defined, a C expression that gives the alignment boundary, in
- bits, of an argument with the specified mode and type. If it is
- not defined, `PARM_BOUNDARY' is used for all arguments. */
-
-#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
- ix86_function_arg_boundary ((MODE), (TYPE))
-
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 0
|| ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \
|| (MODE) == XFmode)
-/* Cover class containing the stack registers. */
-#define STACK_REG_COVER_CLASS FLOAT_REGS
-
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
64 bit targets, one if the register if fixed on both 32 and 64
bit targets, two if it is only fixed on 32bit targets and three
if its only fixed on 64bit targets.
- Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
+ Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
*/
#define FIXED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
64 bit targets, one if the register if call used on both 32 and 64
bit targets, two if it is only call used on 32bit targets and three
if its only call used on 64bit targets.
- Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
+ Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE.
*/
#define CALL_USED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
-/* Macro to conditionally modify fixed_regs/call_used_regs. */
-#define CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage ()
-
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
#define VALID_AVX256_REG_MODE(MODE) \
((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
- || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
+ || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
+ || (MODE) == V4DFmode)
#define VALID_SSE2_REG_MODE(MODE) \
((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
|| (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
|| (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
|| (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
- || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
+ || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
+ || (MODE) == V2TImode)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
/* This is overridden by <cygwin.h>. */
#define MS_AGGREGATE_RETURN 0
-/* This is overridden by <netware.h>. */
#define KEEP_AGGREGATE_RETURN_POINTER 0
\f
/* Define the classes of registers for register constraints in the
for a vector of HARD_REG_SET of length N_REG_CLASSES.
Note that the default setting of CLOBBERED_REGS is for 32-bit; this
- is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect. */
+ is adjusted by TARGET_CONDITIONAL_REGISTER_USAGE for the 64-bit ABI
+ in effect. */
#define REG_CLASS_CONTENTS \
{ { 0x00, 0x0 }, \
{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
-{ 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
+{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
{ 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
#define SSE_FLOAT_MODE_P(MODE) \
((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
-#define SSE_VEC_FLOAT_MODE_P(MODE) \
- ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
-
-#define AVX_FLOAT_MODE_P(MODE) \
- (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode))
-
-#define AVX128_VEC_FLOAT_MODE_P(MODE) \
- (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode))
-
-#define AVX256_VEC_FLOAT_MODE_P(MODE) \
- (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode))
-
-#define AVX_VEC_FLOAT_MODE_P(MODE) \
- (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \
- || (MODE) == V8SFmode || (MODE) == V4DFmode))
-
#define FMA4_VEC_FLOAT_MODE_P(MODE) \
(TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
|| (MODE) == V8SFmode || (MODE) == V4DFmode))
? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
: MODE)
-/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS. */
-/* On the 80386, this is the size of MODE in words,
- except in the FP regs, where a single reg is always enough. */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- (MAYBE_INTEGER_CLASS_P (CLASS) \
- ? ((MODE) == XFmode \
- ? (TARGET_64BIT ? 2 : 3) \
- : (MODE) == XCmode \
- ? (TARGET_64BIT ? 4 : 6) \
- : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
- : (COMPLEX_MODE_P (MODE) ? 2 : 1))
-
/* Return a class of registers that cannot change FROM mode to TO mode. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
No space will be pushed onto the stack for each call; instead, the
function prologue should increase the stack frame size by this amount.
- MS ABI seem to require 16 byte alignment everywhere except for function
- prologue and apilogue. This is not possible without
+ 64-bit MS ABI seem to require 16 byte alignment everywhere except for
+ function prologue and apilogue. This is not possible without
ACCUMULATE_OUTGOING_ARGS. */
#define ACCUMULATE_OUTGOING_ARGS \
- (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI)
+ (TARGET_ACCUMULATE_OUTGOING_ARGS || TARGET_64BIT_MS_ABI)
/* If defined, a C expression whose value is nonzero when we want to use PUSH
instructions to pass outgoing arguments. */
#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
- (ix86_function_type_abi (FNTYPE) == MS_ABI)
+ (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-
-#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
-
/* If defined, a C expression to determine the base term of address X.
This macro is used in only one place: `find_base_term' in alias.c.
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE \
- (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
+ (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
between pointers and any other objects of this machine mode. */
#define Pmode (TARGET_64BIT ? DImode : SImode)
+/* A C expression whose value is zero if pointers that need to be extended
+ from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
+ greater then zero if they are zero-extended and less then zero if the
+ ptr_extend instruction should be used. */
+
+#define POINTERS_EXTEND_UNSIGNED 1
+
/* A function address in a call instruction
is a byte address (for indexing purposes)
so give the MEM rtx a byte's mode. */
PROCESSOR_PENTIUM4,
PROCESSOR_K8,
PROCESSOR_NOCONA,
- PROCESSOR_CORE2,
+ PROCESSOR_CORE2_32,
+ PROCESSOR_CORE2_64,
PROCESSOR_COREI7_32,
PROCESSOR_COREI7_64,
PROCESSOR_GENERIC32,
PROCESSOR_GENERIC64,
PROCESSOR_AMDFAM10,
PROCESSOR_BDVER1,
+ PROCESSOR_BDVER2,
+ PROCESSOR_BTVER1,
PROCESSOR_ATOM,
PROCESSOR_max
};
extern enum processor_type ix86_tune;
extern enum processor_type ix86_arch;
-enum fpmath_unit
-{
- FPMATH_387 = 1,
- FPMATH_SSE = 2
-};
-
-extern enum fpmath_unit ix86_fpmath;
-
-enum tls_dialect
-{
- TLS_DIALECT_GNU,
- TLS_DIALECT_GNU2,
- TLS_DIALECT_SUN
-};
-
-extern enum tls_dialect ix86_tls_dialect;
-
-enum cmodel {
- CM_32, /* The traditional 32-bit ABI. */
- CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
- CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
- CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
- CM_LARGE, /* No assumptions. */
- CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
- CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
- CM_LARGE_PIC /* No assumptions. */
-};
-
-extern enum cmodel ix86_cmodel;
-
/* Size of the RED_ZONE area. */
#define RED_ZONE_SIZE 128
/* Reserved area of the red zone for temporaries. */
#define RED_ZONE_RESERVE 8
-enum asm_dialect {
- ASM_ATT,
- ASM_INTEL
-};
-
-extern enum asm_dialect ix86_asm_dialect;
extern unsigned int ix86_preferred_stack_boundary;
extern unsigned int ix86_incoming_stack_boundary;
-extern int ix86_branch_cost, ix86_section_threshold;
/* Smallest class containing REGNO. */
extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
stack below the return address. */
BOOL_BITFIELD static_chain_on_stack : 1;
- /* Nonzero if the current function uses vzeroupper. */
- BOOL_BITFIELD use_vzeroupper_p : 1;
-
- /* Nonzero if the current function uses 256bit AVX regisers. */
- BOOL_BITFIELD use_avx256_p : 1;
-
/* Nonzero if caller passes 256bit AVX modes. */
BOOL_BITFIELD caller_pass_avx256_p : 1;
/* Nonzero if the current callee returns 256bit AVX modes. */
BOOL_BITFIELD callee_return_avx256_p : 1;
+ /* Nonzero if rescan vzerouppers in the current function is needed. */
+ BOOL_BITFIELD rescan_vzeroupper_p : 1;
+
/* During prologue/epilogue generation, the current frame state.
Otherwise, the frame state at the end of the prologue. */
struct machine_frame_state fs;
extern void debug_ready_dispatch (void);
extern void debug_dispatch_window (int);
+/* The value at zero is only defined for the BMI instructions
+ LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+ ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+ ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT)
+
+
+/* Flags returned by ix86_get_callcvt (). */
+#define IX86_CALLCVT_CDECL 0x1
+#define IX86_CALLCVT_STDCALL 0x2
+#define IX86_CALLCVT_FASTCALL 0x4
+#define IX86_CALLCVT_THISCALL 0x8
+#define IX86_CALLCVT_REGPARM 0x10
+#define IX86_CALLCVT_SSEREGPARM 0x20
+
+#define IX86_BASE_CALLCVT(FLAGS) \
+ ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
+ | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
+
+#define RECIP_MASK_NONE 0x00
+#define RECIP_MASK_DIV 0x01
+#define RECIP_MASK_SQRT 0x02
+#define RECIP_MASK_VEC_DIV 0x04
+#define RECIP_MASK_VEC_SQRT 0x08
+#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
+ | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
+#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
+
+#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
+#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
+#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
+#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
+
/*
Local variables:
version-control: t
OSDN Git Service
