2003-06-25 H.J. Lu <hongjiu.lu@intel.com>

[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.h

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 25b9acf..5f390f0 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -121,12 +121,13 @@ extern int target_flags;
 #define MASK_MMX               0x00002000      /* Support MMX regs/builtins */
 #define MASK_SSE               0x00004000      /* Support SSE regs/builtins */
 #define MASK_SSE2              0x00008000      /* Support SSE2 regs/builtins */
-#define MASK_3DNOW             0x00010000      /* Support 3Dnow builtins */
-#define MASK_3DNOW_A           0x00020000      /* Support Athlon 3Dnow builtins */
-#define MASK_128BIT_LONG_DOUBLE 0x00040000     /* long double size is 128bit */
-#define MASK_64BIT             0x00080000      /* Produce 64bit code */
-#define MASK_MS_BITFIELD_LAYOUT 0x00100000     /* Use native (MS) bitfield layout */
-#define MASK_TLS_DIRECT_SEG_REFS 0x00200000    /* Avoid adding %gs:0  */
+#define MASK_PNI               0x00010000      /* Support PNI regs/builtins */
+#define MASK_3DNOW             0x00020000      /* Support 3Dnow builtins */
+#define MASK_3DNOW_A           0x00040000      /* Support Athlon 3Dnow builtins */
+#define MASK_128BIT_LONG_DOUBLE 0x00080000     /* long double size is 128bit */
+#define MASK_64BIT             0x00100000      /* Produce 64bit code */
+#define MASK_MS_BITFIELD_LAYOUT 0x00200000     /* Use native (MS) bitfield layout */
+#define MASK_TLS_DIRECT_SEG_REFS 0x00400000    /* Avoid adding %gs:0  */
 
 /* Unused:                     0x03e0000       */
 
@@ -302,6 +303,7 @@ extern int x86_prefetch_sse;
 
 #define TARGET_SSE ((target_flags & MASK_SSE) != 0)
 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
+#define TARGET_PNI ((target_flags & MASK_PNI) != 0)
 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
                             && (ix86_fpmath & FPMATH_387))
@@ -393,10 +395,14 @@ extern int x86_prefetch_sse;
     N_("Support MMX and SSE built-in functions and code generation") },              \
   { "no-sse",                   -MASK_SSE,                                   \
     N_("Do not support MMX and SSE built-in functions and code generation") },\
-  { "sse2",                     (MASK_SSE2|MASK_SSE),                        \
+  { "sse2",                     MASK_SSE2,                                   \
     N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
   { "no-sse2",                  -MASK_SSE2,                                  \
     N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") },    \
+  { "pni",                      MASK_PNI,                                    \
+    N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
+  { "no-pni",                   -MASK_PNI,                                   \
+    N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
   { "128bit-long-double",       MASK_128BIT_LONG_DOUBLE,                     \
     N_("sizeof(long double) is 16") },                                       \
   { "96bit-long-double",       -MASK_128BIT_LONG_DOUBLE,                     \
@@ -611,6 +617,8 @@ extern int x86_prefetch_sse;
        builtin_define ("__SSE__");                             \
       if (TARGET_SSE2)                                         \
        builtin_define ("__SSE2__");                            \
+      if (TARGET_PNI)                                          \
+       builtin_define ("__PNI__");                             \
       if (TARGET_SSE_MATH && TARGET_SSE)                       \
        builtin_define ("__SSE_MATH__");                        \
       if (TARGET_SSE_MATH && TARGET_SSE2)                      \
@@ -2516,6 +2524,22 @@ enum ix86_builtins
   IX86_BUILTIN_MFENCE,
   IX86_BUILTIN_LFENCE,
 
+  /* Prescott New Instructions.  */
+  IX86_BUILTIN_ADDSUBPS,
+  IX86_BUILTIN_HADDPS,
+  IX86_BUILTIN_HSUBPS,
+  IX86_BUILTIN_MOVSHDUP,
+  IX86_BUILTIN_MOVSLDUP,
+  IX86_BUILTIN_ADDSUBPD,
+  IX86_BUILTIN_HADDPD,
+  IX86_BUILTIN_HSUBPD,
+  IX86_BUILTIN_LOADDDUP,
+  IX86_BUILTIN_MOVDDUP,
+  IX86_BUILTIN_LDDQU,
+
+  IX86_BUILTIN_MONITOR,
+  IX86_BUILTIN_MWAIT,
+
   IX86_BUILTIN_MAX
 };
 \f