#define EXTRA_SPECS \
{ "cc1_cpu", CC1_CPU_SPEC }, \
SUBTARGET_EXTRA_SPECS
+
+#define LINK_GCC_MATH_SPEC "%{msselibm:-lgcc-math}"
\f
/* target machine storage layout */
#define STACK_REGS
#define IS_STACK_MODE(MODE) \
- ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \
+ (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
+ || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
+ || (MODE) == XFmode)
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
#define INDEX_REG_CLASS INDEX_REGS
#define BASE_REG_CLASS GENERAL_REGS
-/* Unused letters:
- B TU W
- h jk vw z
-*/
-
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'r' ? GENERAL_REGS : \
- (C) == 'R' ? LEGACY_REGS : \
- (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
- (C) == 'Q' ? Q_REGS : \
- (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
- ? FLOAT_REGS \
- : NO_REGS) : \
- (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
- ? FP_TOP_REG \
- : NO_REGS) : \
- (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
- ? FP_SECOND_REG \
- : NO_REGS) : \
- (C) == 'a' ? AREG : \
- (C) == 'b' ? BREG : \
- (C) == 'c' ? CREG : \
- (C) == 'd' ? DREG : \
- (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
- (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
- (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
- (C) == 'A' ? AD_REGS : \
- (C) == 'D' ? DIREG : \
- (C) == 'S' ? SIREG : \
- (C) == 'l' ? INDEX_REGS : \
- NO_REGS)
-
-/* The letters I, J, K, L, M, N, and O in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- I is for non-DImode shifts.
- J is for DImode shifts.
- K is for signed imm8 operands.
- L is for andsi as zero-extending move.
- M is for shifts that can be executed by the "lea" opcode.
- N is for immediate operands for out/in instructions (0-255)
- O is for TImode shifts.
- */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
- : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
- : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
- : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
- : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
- : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
- : (C) == 'O' ? (VALUE) >= 0 && (VALUE) <= 127 \
- : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
- TARGET_387 isn't set, because the stack register converter may need to
- load 0.0 into the function value register. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? standard_80387_constant_p (VALUE) \
- : 0)
-
-/* A C expression that defines the optional machine-dependent
- constraint letters that can be used to segregate specific types of
- operands, usually memory references, for the target machine. Any
- letter that is not elsewhere defined and not matched by
- `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
- be defined.
-
- If it is required for a particular target machine, it should
- return 1 if VALUE corresponds to the operand type represented by
- the constraint letter C. If C is not defined as an extra
- constraint, the value returned should be 0 regardless of VALUE. */
-
-#define EXTRA_CONSTRAINT(VALUE, D) \
- ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \
- : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \
- : (D) == 'C' ? standard_sse_constant_p (VALUE) \
- : 0)
-
/* Place additional restrictions on the register class to use when it
is necessary to be able to hold a value of mode MODE in a reload
register for which class CLASS would ordinarily be used. */
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
ix86_preferred_reload_class ((X), (CLASS))
+/* Discourage putting floating-point values in SSE registers unless
+ SSE math is being used, and likewise for the 387 registers. */
+
+#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
+ ix86_preferred_output_reload_class ((X), (CLASS))
+
/* If we are copying between general and FP registers, we need a memory
location. The same is true for SSE and MMX registers. */
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
#define DBX_REGISTER_NUMBER(N) \
(TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
-extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
-extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
-extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
+extern int const dbx_register_map[FIRST_PSEUDO_REGISTER+1];
+extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER+1];
+extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER+1];
/* Before the prologue, RA is at 0(%esp). */
#define INCOMING_RETURN_ADDR_RTX \
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