Pizza-lize :-)

[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / driver-i386.c

diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 5f14c76..1c005f8 100644 (file)
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -24,7 +24,7 @@ along with GCC; see the file COPYING3.  If not see
 
 const char *host_detect_local_cpu (int argc, const char **argv);
 
-#ifdef __GNUC__
+#if defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
 #include "cpuid.h"
 
 struct cache_desc
@@ -350,7 +350,10 @@ detect_caches_intel (bool xeon_mp, unsigned max_level,
 enum vendor_signatures
 {
   SIG_INTEL =  0x756e6547 /* Genu */,
-  SIG_AMD =    0x68747541 /* Auth */
+  SIG_AMD =    0x68747541 /* Auth */,
+  SIG_CENTAUR =        0x746e6543 /* Cent */,
+  SIG_CYRIX =  0x69727943 /* Cyri */,
+  SIG_NSC =    0x646f6547 /* Geod */
 };
 
 enum processor_signatures
@@ -397,6 +400,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
+  unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
+  unsigned int has_osxsave = 0;
 
   bool arch;
 
@@ -438,12 +443,15 @@ const char *host_detect_local_cpu (int argc, const char **argv)
   has_sse4_1 = ecx & bit_SSE4_1;
   has_sse4_2 = ecx & bit_SSE4_2;
   has_avx = ecx & bit_AVX;
+  has_osxsave = ecx & bit_OSXSAVE;
   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
   has_movbe = ecx & bit_MOVBE;
   has_popcnt = ecx & bit_POPCNT;
   has_aes = ecx & bit_AES;
   has_pclmul = ecx & bit_PCLMUL;
   has_fma = ecx & bit_FMA;
+  has_f16c = ecx & bit_F16C;
+  has_rdrnd = ecx & bit_RDRND;
 
   has_cmpxchg8b = edx & bit_CMPXCHG8B;
   has_cmov = edx & bit_CMOV;
@@ -458,6 +466,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_bmi = ebx & bit_BMI;
       has_avx2 = ebx & bit_AVX2;
       has_bmi2 = ebx & bit_BMI2;
+      has_fsgsbase = ebx & bit_FSGSBASE;
     }
 
   /* Check cpuid level of extended features.  */
@@ -481,9 +490,34 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       has_3dnow = edx & bit_3DNOW;
     }
 
+  /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
+#define XCR_XFEATURE_ENABLED_MASK      0x0
+#define XSTATE_FP                      0x1
+#define XSTATE_SSE                     0x2
+#define XSTATE_YMM                     0x4
+  if (has_osxsave)
+    asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
+        : "=a" (eax), "=d" (edx)
+        : "c" (XCR_XFEATURE_ENABLED_MASK));
+
+  /* Check if SSE and YMM states are supported.  */
+  if (!has_osxsave
+      || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
+    {
+      has_avx = 0;
+      has_avx2 = 0;
+      has_fma = 0;
+      has_fma4 = 0;
+      has_f16c = 0;
+      has_xop = 0;
+    }
+
   if (!arch)
     {
-      if (vendor == SIG_AMD)
+      if (vendor == SIG_AMD
+         || vendor == SIG_CENTAUR
+         || vendor == SIG_CYRIX
+         || vendor == SIG_NSC)
        cache = detect_caches_amd (ext_level);
       else if (vendor == SIG_INTEL)
        {
@@ -515,13 +549,44 @@ const char *host_detect_local_cpu (int argc, const char **argv)
        processor = PROCESSOR_AMDFAM10;
       else if (has_sse2 || has_longmode)
        processor = PROCESSOR_K8;
-      else if (has_3dnowp)
+      else if (has_3dnowp && family == 6)
        processor = PROCESSOR_ATHLON;
       else if (has_mmx)
        processor = PROCESSOR_K6;
       else
        processor = PROCESSOR_PENTIUM;
     }
+  else if (vendor == SIG_CENTAUR)
+    {
+      if (arch)
+       {
+         switch (family)
+           {
+           case 6:
+             if (model > 9)
+               /* Use the default detection procedure.  */
+               processor = PROCESSOR_GENERIC32;
+             else if (model == 9)
+               cpu = "c3-2";
+             else if (model >= 6)
+               cpu = "c3";
+             else
+               processor = PROCESSOR_GENERIC32;
+             break;
+           case 5:
+             if (has_3dnow)
+               cpu = "winchip2";
+             else if (has_mmx)
+               cpu = "winchip2-c6";
+             else
+               processor = PROCESSOR_GENERIC32;
+             break;
+           default:
+             /* We have no idea.  */
+             processor = PROCESSOR_GENERIC32;
+           }
+       }
+    }
   else
     {
       switch (family)
@@ -566,13 +631,18 @@ const char *host_detect_local_cpu (int argc, const char **argv)
          /* Atom.  */
          cpu = "atom";
          break;
+       case 0x0f:
+         /* Merom.  */
+       case 0x17:
+       case 0x1d:
+         /* Penryn.  */
+         cpu = "core2";
+         break;
        case 0x1a:
        case 0x1e:
        case 0x1f:
        case 0x2e:
          /* Nehalem.  */
-         cpu = "corei7";
-         break;
        case 0x25:
        case 0x2c:
        case 0x2f:
@@ -584,14 +654,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
          /* Sandy Bridge.  */
          cpu = "corei7-avx";
          break;
-       case 0x17:
-       case 0x1d:
-         /* Penryn.  */
-         cpu = "core2";
-         break;
-       case 0x0f:
-         /* Merom.  */
-         cpu = "core2";
+       case 0x3a:
+       case 0x3e:
+         /* Ivy Bridge.  */
+         cpu = "core-avx-i";
          break;
        default:
          if (arch)
@@ -726,10 +792,14 @@ const char *host_detect_local_cpu (int argc, const char **argv)
       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
+      const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
+      const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
+      const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 
       options = concat (options, cx16, sahf, movbe, ase, pclmul,
                        popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
-                       tbm, avx, avx2, sse4_2, sse4_1, lzcnt, NULL);
+                       tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rdrnd,
+                       f16c, fsgsbase, NULL);
     }
 
 done: