/* Subroutines for the gcc driver.
- Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
+ Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc.
This file is part of GCC.
#include "system.h"
#include "coretypes.h"
#include "tm.h"
-#include <stdlib.h>
const char *host_detect_local_cpu (int argc, const char **argv);
-#ifdef __GNUC__
+#if defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
#include "cpuid.h"
struct cache_desc
enum vendor_signatures
{
SIG_INTEL = 0x756e6547 /* Genu */,
- SIG_AMD = 0x68747541 /* Auth */
+ SIG_AMD = 0x68747541 /* Auth */,
+ SIG_CENTAUR = 0x746e6543 /* Cent */,
+ SIG_CYRIX = 0x69727943 /* Cyri */,
+ SIG_NSC = 0x646f6547 /* Geod */
};
enum processor_signatures
unsigned int has_lahf_lm = 0, has_sse4a = 0;
unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
- unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
+ unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
+ unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
+ unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
+ unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
+ unsigned int has_osxsave = 0;
bool arch;
has_sse4_1 = ecx & bit_SSE4_1;
has_sse4_2 = ecx & bit_SSE4_2;
has_avx = ecx & bit_AVX;
+ has_osxsave = ecx & bit_OSXSAVE;
has_cmpxchg16b = ecx & bit_CMPXCHG16B;
has_movbe = ecx & bit_MOVBE;
has_popcnt = ecx & bit_POPCNT;
has_aes = ecx & bit_AES;
has_pclmul = ecx & bit_PCLMUL;
+ has_fma = ecx & bit_FMA;
+ has_f16c = ecx & bit_F16C;
+ has_rdrnd = ecx & bit_RDRND;
has_cmpxchg8b = edx & bit_CMPXCHG8B;
has_cmov = edx & bit_CMOV;
has_sse = edx & bit_SSE;
has_sse2 = edx & bit_SSE2;
+ if (max_level >= 7)
+ {
+ __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+ has_bmi = ebx & bit_BMI;
+ has_avx2 = ebx & bit_AVX2;
+ has_bmi2 = ebx & bit_BMI2;
+ has_fsgsbase = ebx & bit_FSGSBASE;
+ }
+
/* Check cpuid level of extended features. */
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
has_sse4a = ecx & bit_SSE4a;
has_abm = ecx & bit_ABM;
has_lwp = ecx & bit_LWP;
+ has_fma4 = ecx & bit_FMA4;
+ has_xop = ecx & bit_XOP;
+ has_tbm = ecx & bit_TBM;
+ has_lzcnt = ecx & bit_LZCNT;
has_longmode = edx & bit_LM;
has_3dnowp = edx & bit_3DNOWP;
has_3dnow = edx & bit_3DNOW;
}
+ /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
+#define XCR_XFEATURE_ENABLED_MASK 0x0
+#define XSTATE_FP 0x1
+#define XSTATE_SSE 0x2
+#define XSTATE_YMM 0x4
+ if (has_osxsave)
+ asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
+ : "=a" (eax), "=d" (edx)
+ : "c" (XCR_XFEATURE_ENABLED_MASK));
+
+ /* Check if SSE and YMM states are supported. */
+ if (!has_osxsave
+ || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
+ {
+ has_avx = 0;
+ has_avx2 = 0;
+ has_fma = 0;
+ has_fma4 = 0;
+ has_f16c = 0;
+ has_xop = 0;
+ }
+
if (!arch)
{
- if (vendor == SIG_AMD)
+ if (vendor == SIG_AMD
+ || vendor == SIG_CENTAUR
+ || vendor == SIG_CYRIX
+ || vendor == SIG_NSC)
cache = detect_caches_amd (ext_level);
else if (vendor == SIG_INTEL)
{
if (name == SIG_GEODE)
processor = PROCESSOR_GEODE;
+ else if (has_bmi)
+ processor = PROCESSOR_BDVER2;
+ else if (has_xop)
+ processor = PROCESSOR_BDVER1;
+ else if (has_sse4a && has_ssse3)
+ processor = PROCESSOR_BTVER1;
else if (has_sse4a)
processor = PROCESSOR_AMDFAM10;
else if (has_sse2 || has_longmode)
processor = PROCESSOR_K8;
- else if (has_3dnowp)
+ else if (has_3dnowp && family == 6)
processor = PROCESSOR_ATHLON;
else if (has_mmx)
processor = PROCESSOR_K6;
else
processor = PROCESSOR_PENTIUM;
}
+ else if (vendor == SIG_CENTAUR)
+ {
+ if (arch)
+ {
+ switch (family)
+ {
+ case 6:
+ if (model > 9)
+ /* Use the default detection procedure. */
+ processor = PROCESSOR_GENERIC32;
+ else if (model == 9)
+ cpu = "c3-2";
+ else if (model >= 6)
+ cpu = "c3";
+ else
+ processor = PROCESSOR_GENERIC32;
+ break;
+ case 5:
+ if (has_3dnow)
+ cpu = "winchip2";
+ else if (has_mmx)
+ cpu = "winchip2-c6";
+ else
+ processor = PROCESSOR_GENERIC32;
+ break;
+ default:
+ /* We have no idea. */
+ processor = PROCESSOR_GENERIC32;
+ }
+ }
+ }
else
{
switch (family)
/* Atom. */
cpu = "atom";
break;
+ case 0x0f:
+ /* Merom. */
+ case 0x17:
+ case 0x1d:
+ /* Penryn. */
+ cpu = "core2";
+ break;
case 0x1a:
case 0x1e:
case 0x1f:
case 0x2e:
- /* FIXME: Optimize for Nehalem. */
- cpu = "core2";
- break;
+ /* Nehalem. */
case 0x25:
+ case 0x2c:
case 0x2f:
- /* FIXME: Optimize for Westmere. */
- cpu = "core2";
+ /* Westmere. */
+ cpu = "corei7";
break;
- case 0x17:
- case 0x1d:
- /* Penryn. FIXME: -mtune=core2 is slower than -mtune=generic */
- cpu = "core2";
+ case 0x2a:
+ case 0x2d:
+ /* Sandy Bridge. */
+ cpu = "corei7-avx";
break;
- case 0x0f:
- /* Merom. FIXME: -mtune=core2 is slower than -mtune=generic */
- cpu = "core2";
+ case 0x3a:
+ case 0x3e:
+ /* Ivy Bridge. */
+ cpu = "core-avx-i";
break;
default:
if (arch)
{
- if (has_ssse3)
- /* If it is an unknown CPU with SSSE3, assume Core 2. */
- cpu = "core2";
+ /* This is unknown family 0x6 CPU. */
+ if (has_avx)
+ /* Assume Sandy Bridge. */
+ cpu = "corei7-avx";
+ else if (has_sse4_2)
+ /* Assume Core i7. */
+ cpu = "corei7";
+ else if (has_ssse3)
+ {
+ if (has_movbe)
+ /* Assume Atom. */
+ cpu = "atom";
+ else
+ /* Assume Core 2. */
+ cpu = "core2";
+ }
else if (has_sse3)
/* It is Core Duo. */
cpu = "pentium-m";
case PROCESSOR_AMDFAM10:
cpu = "amdfam10";
break;
+ case PROCESSOR_BDVER1:
+ cpu = "bdver1";
+ break;
+ case PROCESSOR_BDVER2:
+ cpu = "bdver2";
+ break;
+ case PROCESSOR_BTVER1:
+ cpu = "btver1";
+ break;
default:
/* Use something reasonable. */
if (arch)
{
- if (has_cmpxchg16b)
- options = concat (options, " -mcx16", NULL);
- if (has_lahf_lm)
- options = concat (options, " -msahf", NULL);
- if (has_movbe)
- options = concat (options, " -mmovbe", NULL);
- if (has_aes)
- options = concat (options, " -maes", NULL);
- if (has_pclmul)
- options = concat (options, " -mpclmul", NULL);
- if (has_popcnt)
- options = concat (options, " -mpopcnt", NULL);
- if (has_abm)
- options = concat (options, " -mabm", NULL);
- if (has_lwp)
- options = concat (options, " -mlwp", NULL);
-
- if (has_avx)
- options = concat (options, " -mavx", NULL);
- else if (has_sse4_2)
- options = concat (options, " -msse4.2", NULL);
- else if (has_sse4_1)
- options = concat (options, " -msse4.1", NULL);
+ const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
+ const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
+ const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
+ const char *ase = has_aes ? " -maes" : " -mno-aes";
+ const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
+ const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
+ const char *abm = has_abm ? " -mabm" : " -mno-abm";
+ const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
+ const char *fma = has_fma ? " -mfma" : " -mno-fma";
+ const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
+ const char *xop = has_xop ? " -mxop" : " -mno-xop";
+ const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
+ const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
+ const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
+ const char *avx = has_avx ? " -mavx" : " -mno-avx";
+ const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
+ const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
+ const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
+ const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
+ const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
+ const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
+ const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
+
+ options = concat (options, cx16, sahf, movbe, ase, pclmul,
+ popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
+ tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rdrnd,
+ f16c, fsgsbase, NULL);
}
done:
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