Merge remote-tracking branch 'gnu/gcc-4_7-branch' into rework

[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / cpuid.h

diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 3c3f47b..49de691 100644 (file)
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -24,6 +24,7 @@
 /* %ecx */
 #define bit_SSE3       (1 << 0)
 #define bit_PCLMUL     (1 << 1)
+#define bit_LZCNT      (1 << 5)
 #define bit_SSSE3      (1 << 9)
 #define bit_FMA                (1 << 12)
 #define bit_CMPXCHG16B (1 << 13)
@@ -65,40 +66,57 @@
 /* Extended Features (%eax == 7) */
 #define bit_FSGSBASE   (1 << 0)
 #define bit_BMI                (1 << 3)
+#define bit_AVX2       (1 << 5)
+#define bit_BMI2       (1 << 8)
 
 #if defined(__i386__) && defined(__PIC__)
 /* %ebx may be the PIC register.  */
 #if __GNUC__ >= 3
 #define __cpuid(level, a, b, c, d)                     \
-  __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                  \
+  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"                 \
           "cpuid\n\t"                                  \
-          "xchg{l}\t{%%}ebx, %1\n\t"                   \
-          : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
+          "xchg{l}\t{%%}ebx, %k1\n\t"                  \
+          : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
           : "0" (level))
 
 #define __cpuid_count(level, count, a, b, c, d)                \
-  __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                  \
+  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"                 \
           "cpuid\n\t"                                  \
-          "xchg{l}\t{%%}ebx, %1\n\t"                   \
-          : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
+          "xchg{l}\t{%%}ebx, %k1\n\t"                  \
+          : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
           : "0" (level), "2" (count))
 #else
 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
    nor alternatives in i386 code.  */
 #define __cpuid(level, a, b, c, d)                     \
-  __asm__ ("xchgl\t%%ebx, %1\n\t"                      \
+  __asm__ ("xchgl\t%%ebx, %k1\n\t"                     \
           "cpuid\n\t"                                  \
-          "xchgl\t%%ebx, %1\n\t"                       \
-          : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
+          "xchgl\t%%ebx, %k1\n\t"                      \
+          : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
           : "0" (level))
 
 #define __cpuid_count(level, count, a, b, c, d)                \
-  __asm__ ("xchgl\t%%ebx, %1\n\t"                      \
+  __asm__ ("xchgl\t%%ebx, %k1\n\t"                     \
           "cpuid\n\t"                                  \
-          "xchgl\t%%ebx, %1\n\t"                       \
-          : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
+          "xchgl\t%%ebx, %k1\n\t"                      \
+          : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
           : "0" (level), "2" (count))
 #endif
+#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
+/* %rbx may be the PIC register.  */
+#define __cpuid(level, a, b, c, d)                     \
+  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"                 \
+          "cpuid\n\t"                                  \
+          "xchg{q}\t{%%}rbx, %q1\n\t"                  \
+          : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
+          : "0" (level))
+
+#define __cpuid_count(level, count, a, b, c, d)                \
+  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"                 \
+          "cpuid\n\t"                                  \
+          "xchg{q}\t{%%}rbx, %q1\n\t"                  \
+          : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
+          : "0" (level), "2" (count))
 #else
 #define __cpuid(level, a, b, c, d)                     \
   __asm__ ("cpuid\n\t"                                 \