;; movqi
+(define_insn "pushqi1_h8300"
+ [(parallel [(set (reg:HI 7)
+ (plus:HI (reg:HI 7) (const_int -2)))
+ (set (mem:QI (plus:HI (reg:HI 7) (const_int -1)))
+ (match_operand:QI 0 "register_operand" "r"))])]
+ "TARGET_H8300"
+ "mov.w %T0,@-r7"
+ [(set_attr "length" "2")
+ (set_attr "cc" "clobber")])
+
+(define_insn "pushqi1_h8300hs"
+ [(parallel [(set (reg:SI 7)
+ (plus:SI (reg:SI 7) (const_int -4)))
+ (set (mem:QI (plus:SI (reg:SI 7) (const_int -3)))
+ (match_operand:QI 0 "register_operand" "r"))])]
+ "TARGET_H8300H || TARGET_H8300S"
+ "mov.l %S0,@-er7"
+ [(set_attr "length" "4")
+ (set_attr "cc" "clobber")])
+
+(define_expand "pushqi1"
+ [(use (match_operand:QI 0 "register_operand" "r"))]
+ ""
+ "
+{
+ if (TARGET_H8300)
+ emit_insn (gen_pushqi1_h8300 (operands[0]));
+ else
+ emit_insn (gen_pushqi1_h8300hs (operands[0]));
+ DONE;
+}")
+
(define_insn ""
- [(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,T,r,r,m")
- (match_operand:QI 1 "general_operand_src" " I,r>,r,r,n,m,r"))]
+ [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
+ (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
"TARGET_H8300
- && (register_operand (operands[0],QImode)
+ && (register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
"@
sub.b %X0,%X0
mov.b %R1,%X0
mov.b %X1,%R0
- mov.w %T1,@-r7
mov.b %R1,%X0
mov.b %R1,%X0
mov.b %X1,%R0"
- [(set_attr "length" "2,2,2,2,2,4,4")
- (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
+ [(set_attr "length" "2,2,2,2,4,4")
+ (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_insn ""
- [(set (match_operand:QI 0 "general_operand_dst_push" "=r,r ,<,r,T,r,m")
- (match_operand:QI 1 "general_operand_src" " I,r>,r,n,r,m,r"))]
+ [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
+ (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
"(TARGET_H8300H || TARGET_H8300S)
- && (register_operand (operands[0],QImode)
+ && (register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
"@
sub.b %X0,%X0
mov.b %R1,%X0
mov.b %X1,%R0
mov.b %R1,%X0
- mov.l %S1,@-er7
mov.b %R1,%X0
mov.b %X1,%R0"
- [(set_attr "length" "2,2,2,2,4,8,8")
- (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
+ [(set_attr "length" "2,2,2,2,8,8")
+ (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
(define_expand "movqi"
- [(set (match_operand:QI 0 "general_operand_dst_push" "")
+ [(set (match_operand:QI 0 "general_operand_dst" "")
(match_operand:QI 1 "general_operand_src" ""))]
""
"
;; movhi
+(define_expand "pushhi1_h8300"
+ [(set (mem:QI (pre_dec:HI (reg:HI 7)))
+ (match_operand:QI 0 "register_operand" "r"))]
+ "TARGET_H8300"
+ "")
+
+(define_insn "pushhi1_h8300hs"
+ [(parallel [(set (reg:SI 7)
+ (plus:SI (reg:SI 7) (const_int -4)))
+ (set (mem:HI (plus:SI (reg:SI 7) (const_int -2)))
+ (match_operand:HI 0 "register_operand" "r"))])]
+ "TARGET_H8300H || TARGET_H8300S"
+ "mov.l %S0,@-er7"
+ [(set_attr "length" "4")
+ (set_attr "cc" "clobber")])
+
+(define_expand "pushhi1"
+ [(use (match_operand:QI 0 "register_operand" "r"))]
+ ""
+ "
+{
+ if (TARGET_H8300)
+ emit_insn (gen_pushhi1_h8300 (operands[0]));
+ else
+ emit_insn (gen_pushhi1_h8300hs (operands[0]));
+ DONE;
+}")
+
(define_insn ""
[(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
"TARGET_H8300
- && (register_operand (operands[0],HImode)
+ && (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))
&& !(GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_insn ""
- [(set (match_operand:HI 0 "general_operand_dst_push" "=r,r,<,T,r,r,m")
- (match_operand:HI 1 "general_operand_src" "I,r>,r,r,i,m,r"))]
+ [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
+ (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
"(TARGET_H8300H || TARGET_H8300S)
- && (register_operand (operands[0],HImode)
+ && (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
"@
sub.w %T0,%T0
mov.w %T1,%T0
mov.w %T1,%T0
- mov.l %S1,@-er7
mov.w %T1,%T0
mov.w %T1,%T0
mov.w %T1,%T0"
- [(set_attr "length" "2,2,2,4,4,8,8")
- (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv,set_znv")])
+ [(set_attr "length" "2,2,2,4,8,8")
+ (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_expand "movhi"
- [(set (match_operand:HI 0 "general_operand_dst_push" "")
+ [(set (match_operand:HI 0 "general_operand_dst" "")
(match_operand:HI 1 "general_operand_src" ""))]
""
"
/* Make sure we don't trample the register we index with. */
if (GET_CODE (operands[1]) == MEM)
{
- rtx inside = XEXP (operands[1],0);
+ rtx inside = XEXP (operands[1], 0);
if (REG_P (inside))
{
rn = REGNO (inside);
}
else if (GET_CODE (inside) == PLUS)
{
- rtx lhs = XEXP (inside,0);
- rtx rhs = XEXP (inside,1);
+ rtx lhs = XEXP (inside, 0);
+ rtx rhs = XEXP (inside, 1);
if (REG_P (lhs)) rn = REGNO (lhs);
if (REG_P (rhs)) rn = REGNO (rhs);
}
/* Make sure we don't trample the register we index with. */
if (GET_CODE (operands[1]) == MEM)
{
- rtx inside = XEXP (operands[1],0);
+ rtx inside = XEXP (operands[1], 0);
if (REG_P (inside))
{
rn = REGNO (inside);
}
else if (GET_CODE (inside) == PLUS)
{
- rtx lhs = XEXP (inside,0);
- rtx rhs = XEXP (inside,1);
+ rtx lhs = XEXP (inside, 0);
+ rtx rhs = XEXP (inside, 1);
if (REG_P (lhs)) rn = REGNO (lhs);
if (REG_P (rhs)) rn = REGNO (rhs);
}
/* Look for constants that can be obtained by subs, inc, and
dec to 0. */
- switch (val)
+ switch (val & 0xffffffff)
{
case 0xffffffff:
return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
;; ----------------------------------------------------------------------
(define_insn ""
- [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "rU")
+ [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
(const_int 1)
- (match_operand:QI 1 "const_int_operand" "n")))]
+ (match_operand:QI 1 "const_int_operand" "n,n")))]
""
"btst %Z1,%R0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,8")
+ (set_attr "cc" "set_zn,set_zn")])
(define_insn ""
- [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
+ [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
(const_int 1)
- (match_operand:QI 1 "const_int_operand" "n")))]
+ (match_operand:QI 1 "const_int_operand" "n,n")))]
""
"btst %Z1,%Y0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,8")
+ (set_attr "cc" "set_zn,set_zn")])
(define_insn ""
- [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
+ [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
(const_int 1)
- (match_operand:QI 1 "const_int_operand" "n")))]
+ (match_operand:QI 1 "const_int_operand" "n,n")))]
""
"btst %Z1,%Y0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,8")
+ (set_attr "cc" "set_zn,set_zn")])
(define_insn ""
[(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=a")
- (plus (mult:SI
+ (plus:SI (mult:SI
(sign_extend:SI (mem:HI
(post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
(sign_extend:SI (mem:HI
(set_attr "cc" "none_0hit")])
;; ----------------------------------------------------------------------
-;; DIVIDE INSTRUCTIONS
+;; DIVIDE/MOD INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "udivqi3"
+(define_insn "udivmodqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
(truncate:QI
(udiv:HI
(match_operand:HI 1 "general_operand" "0")
- (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
- ""
- "divxu %X2,%T0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
-
-;; ??? Will divxu always work here?
-
-(define_insn "divqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
+ (set (match_operand:QI 3 "register_operand" "=r")
(truncate:QI
- (div:HI
- (match_operand:HI 1 "general_operand" "0")
- (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
- ""
- "divxu %X2,%T0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
-
-(define_insn "udivhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (truncate:HI
- (udiv:SI
- (match_operand:SI 1 "general_operand" "0")
- (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
- "TARGET_H8300H || TARGET_H8300S"
- "divxu.w %T2,%S0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
-
-(define_insn "divhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (truncate:HI
- (div:SI
- (match_operand:SI 1 "general_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+ (umod:HI
+ (match_dup 1)
+ (zero_extend:HI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxs.w %T2,%S0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxu.b\\t%X2,%T0\";
+ else
+ return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
+}"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
-;; ----------------------------------------------------------------------
-;; MOD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "umodqi3"
+(define_insn "divmodqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
(truncate:QI
- (umod:HI
+ (div:HI
(match_operand:HI 1 "general_operand" "0")
- (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
- ""
- "divxu %X2,%T0\;mov %t0,%s0"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
-
-(define_insn "modqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
+ (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
+ (set (match_operand:QI 3 "register_operand" "=r")
(truncate:QI
(mod:HI
- (match_operand:HI 1 "general_operand" "0")
- (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
+ (match_dup 1)
+ (sign_extend:HI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxs.b %X2,%T0\;mov %t0,%s0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxs.b\\t%X2,%T0\";
+ else
+ return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
+}"
[(set_attr "length" "6")
(set_attr "cc" "clobber")])
-(define_insn "umodhi3"
+(define_insn "udivmodhi4"
[(set (match_operand:HI 0 "register_operand" "=r")
(truncate:HI
- (umod:SI
+ (udiv:SI
(match_operand:SI 1 "general_operand" "0")
- (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+ (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
+ (set (match_operand:HI 3 "register_operand" "=r")
+ (truncate:HI
+ (umod:SI
+ (match_dup 1)
+ (zero_extend:SI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxu.w %T2,%S0\;mov %e0,%f0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxu.w\\t%T2,%S0\";
+ else
+ return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
+}"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
-(define_insn "modhi3"
+(define_insn "divmodhi4"
[(set (match_operand:HI 0 "register_operand" "=r")
(truncate:HI
- (mod:SI
+ (div:SI
(match_operand:SI 1 "general_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+ (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
+ (set (match_operand:HI 3 "register_operand" "=r")
+ (truncate:HI
+ (mod:SI
+ (match_dup 1)
+ (sign_extend:SI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxs.w %T2,%S0\;mov %e0,%f0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxs.w\\t%T2,%S0\";
+ else
+ return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
+}"
[(set_attr "length" "6")
(set_attr "cc" "clobber")])
\f
"@
and %X2,%X0
bclr %W2,%R0"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
[(set_attr "length" "2,4")
(set_attr "cc" "set_znv,clobber")])
+(define_insn "*andorhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
+ (match_operand:HI 3 "p_operand" "P"))
+ (match_operand:HI 1 "register_operand" "0")))]
+ ""
+ "*
+{
+ if (INTVAL (operands[3]) > 128)
+ {
+ operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
+ return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
+ }
+ return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
+}"
+ [(set_attr "length" "4")
+ (set_attr "cc" "clobber")])
+
(define_expand "andsi3"
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "register_operand" "")
"@
or %X2,%X0
bset %V2,%R0"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
(define_expand "iorqi3"
- [(set (match_operand:QI 0 "bit_operand" "=r,U")
- (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
+ [(set (match_operand:QI 0 "bit_operand" "")
+ (ior:QI (match_operand:QI 1 "bit_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"
{
}")
(define_expand "iorhi3"
- [(set (match_operand:HI 0 "general_operand" "=r,r")
- (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "J,rn")))]
+ [(set (match_operand:HI 0 "general_operand" "")
+ (ior:HI (match_operand:HI 1 "general_operand" "")
+ (match_operand:HI 2 "general_operand" "")))]
""
"")
"@
xor %X2,%X0
bnot %V2,%R0"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
(define_expand "xorqi3"
- [(set (match_operand:QI 0 "bit_operand" "=r,U")
- (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
+ [(set (match_operand:QI 0 "bit_operand" "")
+ (xor:QI (match_operand:QI 1 "bit_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"
{
{
if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
&& SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
- return \"jsr\\t\@%0:8\";
+ return \"jsr\\t@%0:8\";
else
return \"jsr\\t%0\";
}"
{
if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
&& SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
- return \"jsr\\t\@%1:8\";
+ return \"jsr\\t@%1:8\";
else
return \"jsr\\t%1\";
}"
;; EXTEND INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "zero_extendqihi2"
+(define_expand "zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
- ""
+ "TARGET_H8300"
"@
mov.b #0,%t0
mov.b %R1,%s0\;mov.b #0,%t0"
[(set_attr "length" "2,10")
(set_attr "cc" "clobber,clobber")])
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "@
+ extu.w %T0
+ mov.b %R1,%s0\;extu.w %T0"
+ [(set_attr "length" "2,10")
+ (set_attr "cc" "set_znv,set_znv")])
+
;; The compiler can synthesize a 300H variant of this which is
;; just as efficient as one that we'd create
(define_insn "zero_extendqisi2"
(ashift:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
(define_expand "ashrqi3"
[(set (match_operand:QI 0 "register_operand" "")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
(define_expand "lshrqi3"
[(set (match_operand:QI 0 "register_operand" "")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r,r")
(ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
(define_expand "lshrhi3"
[(set (match_operand:HI 0 "register_operand" "")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
(define_expand "ashrhi3"
[(set (match_operand:HI 0 "register_operand" "")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r,r")
(match_operand:SI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(rotate:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
+ "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
(define_insn "*rotlqi3_1"
[(set (match_operand:QI 0 "register_operand" "=r")
(rotate:HI (match_operand:HI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
+ "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
(define_insn "*rotlhi3_1"
[(set (match_operand:HI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
"TARGET_H8300H || TARGET_H8300S"
- "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
+ "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
(define_insn "*rotlsi3_1"
[(set (match_operand:SI 0 "register_operand" "=r")
;;
;; Inverted loads with a 32bit destination.
;;
-;; Yes, all seven cases are needed.
+;; Yes, all five cases are needed.
;;
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
- (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
- (match_operand:SI 2 "p_operand" "P")))]
- ""
- "* return output_simode_bld (1, 1, operands);"
- [(set_attr "cc" "clobber")
- (set (attr "length")
- (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
- (const_int 0))
- (const_int 10)
- (const_int 8)))])
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (and:SI (not:SI
(zero_extend:SI
(lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n"))))
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
- (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
- (match_operand:SI 2 "p_operand" "P")))]
- ""
- "* return output_simode_bld (1, 1, operands);"
- [(set_attr "cc" "clobber")
- (set (attr "length")
- (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
- (const_int 0))
- (const_int 10)
- (const_int 8)))])
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (and:SI (not:SI
(zero_extend:SI
(lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n"))))
[(set_attr "cc" "clobber")
(set_attr "length" "6")
(set_attr "adjust_length" "no")])
+\f
+;; -----------------------------------------------------------------
+;; COMBINE PATTERNS
+;; -----------------------------------------------------------------
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "or\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[1])
+ && (REGNO (operands[0]) != REGNO (operands[1]))"
+ "or.w\\t%T1,%f0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI
+ (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "or\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (xor:HI
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "xor\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[1])
+ && (REGNO (operands[0]) != REGNO (operands[1]))"
+ "xor.w\\t%T1,%f0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI
+ (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "xor\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+ (ashift:HI (match_operand:HI 2 "register_operand" "r")
+ (const_int 8))))]
+ "REG_P (operands[0])
+ && REG_P (operands[2])
+ && REGNO (operands[0]) != REGNO (operands[2])"
+ "mov.b\\t%s2,%t0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 16))))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[2])
+ && (REGNO (operands[0]) != REGNO (operands[2]))"
+ "mov.w\\t%f2,%e0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
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