;; GCC machine description for Hitachi H8/300
-;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
-;; Free Software Foundation, Inc.
+;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
+;; 2001 Free Software Foundation, Inc.
;; Contributed by Steve Chamberlain (sac@cygnus.com),
;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
;; Long term, we want to expose the "e" half to the compiler (gives us
;; 8 more 16bit registers). At that point addhi and subhi can't use adds/subs.
-;; There's currently no way to have a insv/extzv expander for the h8/300h
-;; because word_mode is different for the h8/300 and h8/300h.
+;; There's currently no way to have a insv/extzv expander for the H8/300H
+;; because word_mode is different for the H8/300 and H8/300H.
;; Shifts/rotates by small constants should be handled by special
;; patterns so we get the length and cc status correct.
;; The size of instructions in bytes.
-(define_attr "length" ""
+(define_attr "length" ""
(cond [(eq_attr "type" "branch")
(if_then_else (and (ge (minus (pc) (match_dup 0))
(const_int -120))
;; movqi
-(define_insn "movqi_push"
- [(set (match_operand:QI 0 "push_operand" "=<")
- (match_operand:QI 1 "register_operand" "r"))]
+(define_insn "pushqi1_h8300"
+ [(parallel [(set (reg:HI 7)
+ (plus:HI (reg:HI 7) (const_int -2)))
+ (set (mem:QI (plus:HI (reg:HI 7) (const_int -1)))
+ (match_operand:QI 0 "register_operand" "r"))])]
+ "TARGET_H8300"
+ "mov.w %T0,@-r7"
+ [(set_attr "length" "2")
+ (set_attr "cc" "clobber")])
+
+(define_insn "pushqi1_h8300hs"
+ [(parallel [(set (reg:SI 7)
+ (plus:SI (reg:SI 7) (const_int -4)))
+ (set (mem:QI (plus:SI (reg:SI 7) (const_int -3)))
+ (match_operand:QI 0 "register_operand" "r"))])]
+ "TARGET_H8300H || TARGET_H8300S"
+ "mov.l %S0,@-er7"
+ [(set_attr "length" "4")
+ (set_attr "cc" "clobber")])
+
+(define_expand "pushqi1"
+ [(use (match_operand:QI 0 "register_operand" "r"))]
""
- "*
+ "
{
if (TARGET_H8300)
- return \"push.w %T1\";
+ emit_insn (gen_pushqi1_h8300 (operands[0]));
else
- return \"push.l %S1\";
-}"
- [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
- (set_attr "cc" "set_znv")])
+ emit_insn (gen_pushqi1_h8300hs (operands[0]));
+ DONE;
+}")
(define_insn ""
- [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m")
- (match_operand:QI 1 "general_operand_src" "I,r>,r,n,m,r"))]
- "register_operand (operands[0],QImode)
- || register_operand (operands[1], QImode)"
+ [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
+ (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
+ "TARGET_H8300
+ && (register_operand (operands[0], QImode)
+ || register_operand (operands[1], QImode))"
"@
sub.b %X0,%X0
mov.b %R1,%X0
mov.b %R1,%X0
mov.b %R1,%X0
mov.b %X1,%R0"
- [(set_attr_alternative "length"
- [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
- (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
- (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
+ [(set_attr "length" "2,2,2,2,4,4")
(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
+(define_insn ""
+ [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
+ (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && (register_operand (operands[0], QImode)
+ || register_operand (operands[1], QImode))"
+ "@
+ sub.b %X0,%X0
+ mov.b %R1,%X0
+ mov.b %X1,%R0
+ mov.b %R1,%X0
+ mov.b %R1,%X0
+ mov.b %X1,%R0"
+ [(set_attr "length" "2,2,2,2,8,8")
+ (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
+
(define_expand "movqi"
[(set (match_operand:QI 0 "general_operand_dst" "")
(match_operand:QI 1 "general_operand_src" ""))]
""
"
{
- /* One of the ops has to be in a register */
- if (!register_operand(operand0, QImode)
- && !register_operand(operand1, QImode))
+ /* One of the ops has to be in a register. */
+ if (!register_operand (operand0, QImode)
+ && !register_operand (operand1, QImode))
{
- operands[1] = copy_to_mode_reg(QImode, operand1);
+ operands[1] = copy_to_mode_reg (QImode, operand1);
}
}")
(define_insn "movstrictqi"
- [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,r"))
+ [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
(match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
""
"@
[(const_int 2) (const_int 2) (const_int 2)
(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
(set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
-
+
;; movhi
-;; ??? We use push.l on the h8300h to push a 16bit value?!? We have
-;; 16bit push insns!
-(define_insn "movhi_push"
- [(set (match_operand:HI 0 "push_operand" "=<")
- (match_operand:HI 1 "register_operand" "r"))]
+(define_expand "pushhi1_h8300"
+ [(set (mem:QI (pre_dec:HI (reg:HI 7)))
+ (match_operand:QI 0 "register_operand" "r"))]
+ "TARGET_H8300"
+ "")
+
+(define_insn "pushhi1_h8300hs"
+ [(parallel [(set (reg:SI 7)
+ (plus:SI (reg:SI 7) (const_int -4)))
+ (set (mem:HI (plus:SI (reg:SI 7) (const_int -2)))
+ (match_operand:HI 0 "register_operand" "r"))])]
+ "TARGET_H8300H || TARGET_H8300S"
+ "mov.l %S0,@-er7"
+ [(set_attr "length" "4")
+ (set_attr "cc" "clobber")])
+
+(define_expand "pushhi1"
+ [(use (match_operand:QI 0 "register_operand" "r"))]
""
- "*
+ "
{
if (TARGET_H8300)
- return \"push.w %T1\";
+ emit_insn (gen_pushhi1_h8300 (operands[0]));
else
- return \"push.l %S1\";
-}"
- [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
- (set_attr "cc" "set_znv")])
+ emit_insn (gen_pushhi1_h8300hs (operands[0]));
+ DONE;
+}")
(define_insn ""
[(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
- "register_operand (operands[0],HImode)
- || register_operand (operands[1], HImode)"
+ "TARGET_H8300
+ && (register_operand (operands[0], HImode)
+ || register_operand (operands[1], HImode))
+ && !(GET_CODE (operands[0]) == MEM
+ && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
+ && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
+ && GET_CODE (operands[1]) == REG
+ && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
"@
sub.w %T0,%T0
mov.w %T1,%T0
mov.w %T1,%T0
mov.w %T1,%T0
mov.w %T1,%T0"
- [(set_attr_alternative "length"
- [(const_int 2) (const_int 2) (const_int 2) (const_int 4)
- (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
- (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
+ [(set_attr "length" "2,2,2,4,4,4")
+ (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
+
+(define_insn ""
+ [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
+ (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && (register_operand (operands[0], HImode)
+ || register_operand (operands[1], HImode))"
+ "@
+ sub.w %T0,%T0
+ mov.w %T1,%T0
+ mov.w %T1,%T0
+ mov.w %T1,%T0
+ mov.w %T1,%T0
+ mov.w %T1,%T0"
+ [(set_attr "length" "2,2,2,4,8,8")
(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
(define_expand "movhi"
""
"
{
- /* One of the ops has to be in a register */
- if (!register_operand(operand1, HImode)
- && !register_operand(operand0, HImode))
+ /* One of the ops has to be in a register. */
+ if (!register_operand (operand1, HImode)
+ && !register_operand (operand0, HImode))
{
- operands[1] = copy_to_mode_reg(HImode, operand1);
+ operands[1] = copy_to_mode_reg (HImode, operand1);
}
}")
(define_insn "movstricthi"
- [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,r"))
+ [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
(match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
""
"@
case 0:
return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
case 1:
- if (REGNO(operands[0]) < REGNO(operands[1]))
+ if (REGNO (operands[0]) < REGNO (operands[1]))
return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
- else
+ else
return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
case 2:
/* Make sure we don't trample the register we index with. */
-
- if (GET_CODE(operands[1]) == MEM)
+ if (GET_CODE (operands[1]) == MEM)
{
- rtx inside = XEXP (operands[1],0);
- if (REG_P (inside))
+ rtx inside = XEXP (operands[1], 0);
+ if (REG_P (inside))
{
- rn = REGNO(inside);
+ rn = REGNO (inside);
}
- else if (GET_CODE (inside) == PLUS)
+ else if (GET_CODE (inside) == PLUS)
{
- rtx lhs = XEXP (inside,0);
- rtx rhs = XEXP (inside,1);
+ rtx lhs = XEXP (inside, 0);
+ rtx rhs = XEXP (inside, 1);
if (REG_P (lhs)) rn = REGNO (lhs);
if (REG_P (rhs)) rn = REGNO (rhs);
}
}
- if (rn == REGNO (operands[0]))
+ if (rn == REGNO (operands[0]))
{
/* Move the second word first. */
return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
}
- else
+ else
{
/* See if either half is zero. If so, use sub.w to clear
that half. */
- if (GET_CODE (operands[1]) == CONST_INT)
- {
- if ((INTVAL (operands[1]) & 0xffff) == 0)
- return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
- if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
- return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
- }
- return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
+ if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ if ((INTVAL (operands[1]) & 0xffff) == 0)
+ return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
+ if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
+ return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
+ }
+ return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
}
case 3:
- return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
+ return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
case 4:
return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
case 5:
|| register_operand (operands[1], SFmode))"
"*
{
- /* Copy of the movsi stuff */
+ /* Copy of the movsi stuff. */
int rn = -1;
switch (which_alternative)
{
case 0:
return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
case 1:
- if (REGNO(operands[0]) < REGNO(operands[1]))
+ if (REGNO (operands[0]) < REGNO (operands[1]))
return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
- else
+ else
return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
case 2:
/* Make sure we don't trample the register we index with. */
-
- if (GET_CODE (operands[1]) == MEM)
+ if (GET_CODE (operands[1]) == MEM)
{
- rtx inside = XEXP (operands[1],0);
+ rtx inside = XEXP (operands[1], 0);
if (REG_P (inside))
{
rn = REGNO (inside);
}
- else if (GET_CODE (inside) == PLUS)
+ else if (GET_CODE (inside) == PLUS)
{
- rtx lhs = XEXP (inside,0);
- rtx rhs = XEXP (inside,1);
+ rtx lhs = XEXP (inside, 0);
+ rtx rhs = XEXP (inside, 1);
if (REG_P (lhs)) rn = REGNO (lhs);
if (REG_P (rhs)) rn = REGNO (rhs);
}
}
if (rn == REGNO (operands[0]))
- {
- /* move the second word first */
- return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
- }
- else
- {
- return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
- }
-
+ /* Move the second word first. */
+ return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
+ else
+ /* Move the first word first. */
+ return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
+
case 3:
return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
case 4:
(set_attr "cc" "clobber")])
(define_insn "movsi_h8300hs"
- [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r,*a,*a,r")
- (match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>,I,r,*a"))]
+ [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
+ (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
"(TARGET_H8300S || TARGET_H8300H)
&& (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
+ || register_operand (operands[1], SImode))
+ && !(GET_CODE (operands[0]) == MEM
+ && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
+ && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
+ && GET_CODE (operands[1]) == REG
+ && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
"*
{
- if (which_alternative == 0)
- return \"sub.l %S0,%S0\";
- if (which_alternative == 6)
- return \"clrmac\";
- if (which_alternative == 7)
- return \"clrmac\;ldmac %1,macl\";
- if (which_alternative == 8)
- return \"stmac macl,%0\";
- if (GET_CODE (operands[1]) == CONST_INT)
+ switch (which_alternative)
{
- int val = INTVAL (operands[1]);
-
- /* Look for constants which can be made by adding an 8-bit
- number to zero in one of the two low bytes. */
- if (val == (val & 0xff))
- {
- operands[1] = GEN_INT ((char)val & 0xff);
- return \"sub.l %S0,%S0\;add.b %1,%w0\";
- }
-
- if (val == (val & 0xff00))
+ case 0:
+ return \"sub.l %S0,%S0\";
+ case 7:
+ return \"clrmac\";
+ case 8:
+ return \"clrmac\;ldmac %1,macl\";
+ case 9:
+ return \"stmac macl,%0\";
+ default:
+ if (GET_CODE (operands[1]) == CONST_INT)
{
- operands[1] = GEN_INT ((char)(val >> 8) & 0xff);
- return \"sub.l %S0,%S0\;add.b %1,%x0\";
- }
+ int val = INTVAL (operands[1]);
- /* Now look for small negative numbers. We can subtract them
- from zero to get the desired constant. */
- if (val == -4 || val == -2 || val == -1)
- {
- operands[1] = GEN_INT (-INTVAL (operands[1]));
- return \"sub.l %S0,%S0\;subs %1,%S0\";
+ /* Look for constants which can be made by adding an 8-bit
+ number to zero in one of the two low bytes. */
+ if (val == (val & 0xff))
+ {
+ operands[1] = GEN_INT ((char) val & 0xff);
+ return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
+ }
+
+ if (val == (val & 0xff00))
+ {
+ operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
+ return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
+ }
+
+ /* Look for constants that can be obtained by subs, inc, and
+ dec to 0. */
+ switch (val & 0xffffffff)
+ {
+ case 0xffffffff:
+ return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
+ case 0xfffffffe:
+ return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
+ case 0xfffffffc:
+ return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
+
+ case 0x0000ffff:
+ return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
+ case 0x0000fffe:
+ return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
+
+ case 0xffff0000:
+ return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
+ case 0xfffe0000:
+ return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
+
+ case 0x00010000:
+ return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
+ case 0x00020000:
+ return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
+ }
}
}
return \"mov.l %S1,%S0\";
}"
- [(set_attr "length" "2,2,10,10,4,4,2,6,4")
- (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
+ [(set_attr "length" "2,2,10,10,10,4,4,2,6,4")
+ (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
(define_insn "movsf_h8300h"
[(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
;; ----------------------------------------------------------------------
(define_insn ""
- [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "rU")
+ [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
(const_int 1)
- (match_operand:QI 1 "const_int_operand" "n")))]
+ (match_operand:QI 1 "const_int_operand" "n,n")))]
""
"btst %Z1,%R0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,8")
+ (set_attr "cc" "set_zn,set_zn")])
(define_insn ""
- [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
+ [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
(const_int 1)
- (match_operand:QI 1 "const_int_operand" "n")))]
+ (match_operand:QI 1 "const_int_operand" "n,n")))]
""
"btst %Z1,%Y0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,8")
+ (set_attr "cc" "set_zn,set_zn")])
(define_insn ""
- [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
+ [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
(const_int 1)
- (match_operand:QI 1 "const_int_operand" "n")))]
+ (match_operand:QI 1 "const_int_operand" "n,n")))]
""
"btst %Z1,%Y0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "2,8")
+ (set_attr "cc" "set_zn,set_zn")])
(define_insn ""
[(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
"btst %Z1,%R0"
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
-
+
(define_insn ""
[(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
(const_int 1)
"
{
/* Force operand1 into a register if we're compiling
- for the h8/300. */
+ for the H8/300. */
if (GET_CODE (operands[1]) != REG && TARGET_H8300)
operands[1] = force_reg (HImode, operands[1]);
}")
"@
adds %2,%A0
subs %G2,%A0
- add.b %s2,%s0\;addx %t2,%t0
+ add.b %s2,%s0\;addx %t2,%t0
add.w %T2,%T0
- mov.w %T1,%T0\;add.w %T2,%T0"
+ mov.w %T1,%T0\;add.w %T2,%T0"
[(set_attr "length" "2,2,4,2,6")
(set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
;; MULTIPLY INSTRUCTIONS
;; ----------------------------------------------------------------------
-;; Note that the h8/300 can only handle umulqihi3.
+;; Note that the H8/300 can only handle umulqihi3.
(define_insn "mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
(sign_extend:SI
(mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
- "TARGET_H8300S"
- "clrmac\;mac %2,%1"
+ "TARGET_MAC"
+ "clrmac\;mac @%2+,@%1+"
[(set_attr "length" "6")
(set_attr "cc" "none_0hit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=a")
- (plus (mult:SI
+ (plus:SI (mult:SI
(sign_extend:SI (mem:HI
(post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
(sign_extend:SI (mem:HI
(post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
(match_operand:SI 3 "register_operand" "0")))]
- "TARGET_H8300S"
- "mac %2,%1"
+ "TARGET_MAC"
+ "mac @%2+,@%1+"
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")])
;; ----------------------------------------------------------------------
-;; DIVIDE INSTRUCTIONS
+;; DIVIDE/MOD INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "udivqi3"
+(define_insn "udivmodqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
(truncate:QI
(udiv:HI
(match_operand:HI 1 "general_operand" "0")
- (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
- ""
- "divxu %X2,%T0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
-
-;; ??? Will divxu always work here?
-
-(define_insn "divqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
+ (set (match_operand:QI 3 "register_operand" "=r")
(truncate:QI
- (div:HI
- (match_operand:HI 1 "general_operand" "0")
- (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
- ""
- "divxu %X2,%T0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
-
-(define_insn "udivhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (truncate:HI
- (udiv:SI
- (match_operand:SI 1 "general_operand" "0")
- (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
- "TARGET_H8300H || TARGET_H8300S"
- "divxu.w %T2,%S0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
-
-(define_insn "divhi3"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (truncate:HI
- (div:SI
- (match_operand:SI 1 "general_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+ (umod:HI
+ (match_dup 1)
+ (zero_extend:HI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxs.w %T2,%S0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxu.b\\t%X2,%T0\";
+ else
+ return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
+}"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
-;; ----------------------------------------------------------------------
-;; MOD INSTRUCTIONS
-;; ----------------------------------------------------------------------
-
-(define_insn "umodqi3"
+(define_insn "divmodqi4"
[(set (match_operand:QI 0 "register_operand" "=r")
(truncate:QI
- (umod:HI
+ (div:HI
(match_operand:HI 1 "general_operand" "0")
- (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
- ""
- "divxu %X2,%T0\;mov %t0,%s0"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
-
-(define_insn "modqi3"
- [(set (match_operand:QI 0 "register_operand" "=r")
+ (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
+ (set (match_operand:QI 3 "register_operand" "=r")
(truncate:QI
(mod:HI
- (match_operand:HI 1 "general_operand" "0")
- (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
+ (match_dup 1)
+ (sign_extend:HI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxs.b %X2,%T0\;mov %t0,%s0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxs.b\\t%X2,%T0\";
+ else
+ return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
+}"
[(set_attr "length" "6")
(set_attr "cc" "clobber")])
-(define_insn "umodhi3"
+(define_insn "udivmodhi4"
[(set (match_operand:HI 0 "register_operand" "=r")
(truncate:HI
- (umod:SI
+ (udiv:SI
(match_operand:SI 1 "general_operand" "0")
- (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+ (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
+ (set (match_operand:HI 3 "register_operand" "=r")
+ (truncate:HI
+ (umod:SI
+ (match_dup 1)
+ (zero_extend:SI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxu.w %T2,%S0\;mov %e0,%f0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxu.w\\t%T2,%S0\";
+ else
+ return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
+}"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
-(define_insn "modhi3"
+(define_insn "divmodhi4"
[(set (match_operand:HI 0 "register_operand" "=r")
(truncate:HI
- (mod:SI
+ (div:SI
(match_operand:SI 1 "general_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
+ (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
+ (set (match_operand:HI 3 "register_operand" "=r")
+ (truncate:HI
+ (mod:SI
+ (match_dup 1)
+ (sign_extend:SI (match_dup 2)))))]
"TARGET_H8300H || TARGET_H8300S"
- "divxs.w %T2,%S0\;mov %e0,%f0"
+ "*
+{
+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
+ return \"divxs.w\\t%T2,%S0\";
+ else
+ return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
+}"
[(set_attr "length" "6")
(set_attr "cc" "clobber")])
\f
"@
and %X2,%X0
bclr %W2,%R0"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
DONE;
}")
-(define_insn "andhi3"
+(define_expand "andhi3"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (and:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:HI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r")
(and:HI (match_operand:HI 1 "register_operand" "%0")
(match_operand:HI 2 "nonmemory_operand" "rn")))]
+ "TARGET_H8300"
+ "* return output_logical_op (HImode, AND, operands);"
+ [(set_attr "length" "4")
+ (set_attr "cc" "clobber")])
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (and:HI (match_operand:HI 1 "register_operand" "%0,0")
+ (match_operand:HI 2 "nonmemory_operand" "r,n")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "* return output_logical_op (HImode, AND, operands);"
+ [(set_attr "length" "2,4")
+ (set_attr "cc" "set_znv,clobber")])
+
+(define_insn "*andorhi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
+ (match_operand:HI 3 "p_operand" "P"))
+ (match_operand:HI 1 "register_operand" "0")))]
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (INTVAL (operands[3]) > 128)
{
- int i = INTVAL (operands[2]);
-
- if ((i & 0x00ff) != 0x00ff)
- output_asm_insn (\"and %s2,%s0\", operands);
- if ((i & 0xff00) != 0xff00)
- output_asm_insn (\"and %t2,%t0\", operands);
- return \"\";
+ operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
+ return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
}
- if (TARGET_H8300H || TARGET_H8300S)
- return \"and.w %T2,%T0\";
- return \"and %s2,%s0\;and %t2,%t0;\";
+ return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
}"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
-(define_insn "andsi3"
+(define_expand "andsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (and:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "nonmemory_operand" "rn")))]
- ""
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- int i = INTVAL (operands[2]);
- int upper_cleared, lower_cleared;
-
- /* The h8300h can't do byte-wise operations on the
- upper 16bits of 32bit registers. However, if
- those bits aren't going to change, or they're
- going to be zero'd out, then we can work on the
- low-order bits. */
- if ((TARGET_H8300H || TARGET_H8300S)
- && ((i & 0xffff0000) != 0xffff0000
- || (i & 0xffff0000) == 0x00000000))
- return \"and.l %S2,%S0\";
-
- lower_cleared = 0;
- if ((i & 0x0000ffff) == 0x00000000)
- {
- output_asm_insn (\"sub.w %f0,%f0\", operands);
- lower_cleared = 1;
- }
-
- upper_cleared = 0;
- if ((i & 0xffff0000) == 0x00000000)
- {
- output_asm_insn (\"sub.w %e0,%e0\", operands);
- upper_cleared = 1;
- }
-
- if ((i & 0x000000ff) != 0x000000ff && !lower_cleared)
- output_asm_insn (\"and %w2,%w0\", operands);
- if ((i & 0x0000ff00) != 0x0000ff00 && !lower_cleared)
- output_asm_insn (\"and %x2,%x0\", operands);
- if ((i & 0x00ff0000) != 0x00ff0000 && !upper_cleared)
- output_asm_insn (\"and %y2,%y0\", operands);
- if ((i & 0xff000000) != 0xff000000 && !upper_cleared)
- output_asm_insn (\"and %z2,%z0\", operands);
- return \"\";
- }
- if (TARGET_H8300H || TARGET_H8300S)
- return \"and.l %S2,%S0\";
- return \"and %w2,%w0\;and %x2,%x0\;and %y2,%y0\;and %z2,%z0\;\";
-}"
+ "TARGET_H8300"
+ "* return output_logical_op (SImode, AND, operands);"
[(set_attr "length" "8")
(set_attr "cc" "clobber")])
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (and:SI (match_operand:SI 1 "register_operand" "%0,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,n")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "* return output_logical_op (SImode, AND, operands);"
+ [(set_attr "length" "4,6")
+ (set_attr "cc" "set_znv,clobber")])
;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
"@
or %X2,%X0
bset %V2,%R0"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
(define_expand "iorqi3"
- [(set (match_operand:QI 0 "bit_operand" "=r,U")
- (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
+ [(set (match_operand:QI 0 "bit_operand" "")
+ (ior:QI (match_operand:QI 1 "bit_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"
{
DONE;
}")
-(define_insn "iorhi3"
+(define_expand "iorhi3"
+ [(set (match_operand:HI 0 "general_operand" "")
+ (ior:HI (match_operand:HI 1 "general_operand" "")
+ (match_operand:HI 2 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:HI 0 "general_operand" "=r,r")
(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "general_operand" "J,rn")))]
- ""
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- int i = INTVAL (operands[2]);
-
- if ((i & 0x00ff) != 0)
- output_asm_insn (\"or %s2,%s0\", operands);
- if ((i & 0xff00) != 0)
- output_asm_insn (\"or %t2,%t0\", operands);
- return \"\";
- }
- if (TARGET_H8300H || TARGET_H8300S)
- return \"or.w %T2,%T0\";
- return \"or %s2,%s0\;or %t2,%t0; %2 or2\";
-}"
+ "TARGET_H8300"
+ "* return output_logical_op (HImode, IOR, operands);"
[(set_attr "length" "2,4")
(set_attr "cc" "clobber,clobber")])
-(define_insn "iorsi3"
+(define_insn ""
+ [(set (match_operand:HI 0 "general_operand" "=r,r,r")
+ (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0")
+ (match_operand:HI 2 "general_operand" "J,r,n")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "* return output_logical_op (HImode, IOR, operands);"
+ [(set_attr "length" "2,2,4")
+ (set_attr "cc" "clobber,set_znv,clobber")])
+
+(define_expand "iorsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (ior:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
- ""
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- int i = INTVAL (operands[2]);
-
- /* The h8300h can't do byte-wise operations on the
- upper 16bits of 32bit registers. However, if
- those bits aren't going to change, then we can
- work on the low-order bits. */
- if ((TARGET_H8300H || TARGET_H8300S)
- && (i & 0xffff0000) != 0x00000000)
- return \"or.l %S2,%S0\";
-
- if ((i & 0x000000ff) != 0)
- output_asm_insn (\"or %w2,%w0\", operands);
- if ((i & 0x0000ff00) != 0)
- output_asm_insn (\"or %x2,%x0\", operands);
- if ((i & 0x00ff0000) != 0)
- output_asm_insn (\"or %y2,%y0\", operands);
- if ((i & 0xff000000) != 0)
- output_asm_insn (\"or %z2,%z0\", operands);
- return \"\";
- }
- if (TARGET_H8300H || TARGET_H8300S)
- return \"or.l %S2,%S0\";
- return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\;\";
-}"
+ "TARGET_H8300"
+ "* return output_logical_op (SImode, IOR, operands);"
[(set_attr "length" "2,8")
(set_attr "cc" "clobber,clobber")])
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "* return output_logical_op (SImode, IOR, operands);"
+ [(set_attr "length" "2,4,6")
+ (set_attr "cc" "clobber,set_znv,clobber")])
+
;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------
"@
xor %X2,%X0
bnot %V2,%R0"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
(define_expand "xorqi3"
- [(set (match_operand:QI 0 "bit_operand" "=r,U")
- (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
+ [(set (match_operand:QI 0 "bit_operand" "")
+ (xor:QI (match_operand:QI 1 "bit_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
""
"
{
DONE;
}")
-(define_insn "xorhi3"
+(define_expand "xorhi3"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (xor:HI (match_operand:HI 1 "general_operand" "")
+ (match_operand:HI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r,r")
(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
(match_operand:HI 2 "nonmemory_operand" "J,rn")))]
- ""
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- int i = INTVAL (operands[2]);
-
- if ((i & 0x00ff) != 0)
- output_asm_insn (\"xor %s2,%s0\", operands);
- if ((i & 0xff00) != 0)
- output_asm_insn (\"xor %t2,%t0\", operands);
- return \"\";
- }
- if (TARGET_H8300H || TARGET_H8300S)
- return \"xor.w %T2,%T0\";
- return \"xor %s2,%s0\;xor %t2,%t0\";
-}"
+ "TARGET_H8300"
+ "* return output_logical_op (HImode, XOR, operands);"
[(set_attr "length" "2,4")
(set_attr "cc" "clobber,clobber")])
-(define_insn "xorsi3"
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+ (xor:HI (match_operand:HI 1 "general_operand" "%0,0,0")
+ (match_operand:HI 2 "nonmemory_operand" "J,r,n")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "* return output_logical_op (HImode, XOR, operands);"
+ [(set_attr "length" "2,2,4")
+ (set_attr "cc" "clobber,set_znv,clobber")])
+
+(define_expand "xorsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (xor:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
- ""
- "*
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- int i = INTVAL (operands[2]);
-
- /* The h8300h can't do byte-wise operations on the
- upper 16bits of 32bit registers. However, if
- those bits aren't going to change, then we can
- work on the low-order bits. */
- if ((TARGET_H8300H || TARGET_H8300S)
- && (i & 0xffff0000) != 0x00000000)
- return \"xor.l %S2,%S0\";
-
- if ((i & 0x000000ff) != 0)
- output_asm_insn (\"xor %w2,%w0\", operands);
- if ((i & 0x0000ff00) != 0)
- output_asm_insn (\"xor %x2,%x0\", operands);
- if ((i & 0x00ff0000) != 0)
- output_asm_insn (\"xor %y2,%y0\", operands);
- if ((i & 0xff000000) != 0)
- output_asm_insn (\"xor %z2,%z0\", operands);
- return \"\";
- }
- if (TARGET_H8300H || TARGET_H8300S)
- return \"xor.l %S2,%S0\";
- return \"xor %w2,%w0\;xor %x2,%x0\;xor %y2,%y0\;xor %z2,%z0\;\";
-}"
+ "TARGET_H8300"
+ "* return output_logical_op (SImode, XOR, operands);"
[(set_attr "length" "2,8")
(set_attr "cc" "clobber,clobber")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0")
+ (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "* return output_logical_op (SImode, XOR, operands);"
+ [(set_attr "length" "2,4,6")
+ (set_attr "cc" "clobber,set_znv,clobber")])
\f
;; ----------------------------------------------------------------------
;; NEGATION INSTRUCTIONS
(const_int 0))
(const_int 8)
(const_int 2)))])
-
\f
;; ----------------------------------------------------------------------
;; JUMP INSTRUCTIONS
return 0;
}
- if (get_attr_length (insn) == 2)
+ if (get_attr_length (insn) == 2)
return \"b%j1 %l0\";
- else if (get_attr_length (insn) == 4)
+ else if (get_attr_length (insn) == 4)
return \"b%j1 %l0:16\";
else
return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
-}"
+}"
[(set_attr "type" "branch")
(set_attr "cc" "none")])
return 0;
}
- if (get_attr_length (insn) == 2)
+ if (get_attr_length (insn) == 2)
return \"b%k1 %l0\";
- else if (get_attr_length (insn) == 4)
+ else if (get_attr_length (insn) == 4)
return \"b%k1 %l0:16\";
else
return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
{
if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
&& SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
- return \"jsr\\t\@%0:8\";
+ return \"jsr\\t@%0:8\";
else
return \"jsr\\t%0\";
}"
{
if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
&& SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
- return \"jsr\\t\@%1:8\";
+ return \"jsr\\t@%1:8\";
else
return \"jsr\\t%1\";
}"
;; EXTEND INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "zero_extendqihi2"
+(define_expand "zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
+ ""
+ "")
+
+(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
- ""
+ "TARGET_H8300"
"@
mov.b #0,%t0
mov.b %R1,%s0\;mov.b #0,%t0"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "2,10")
(set_attr "cc" "clobber,clobber")])
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "@
+ extu.w %T0
+ mov.b %R1,%s0\;extu.w %T0"
+ [(set_attr "length" "2,10")
+ (set_attr "cc" "set_znv,set_znv")])
+
;; The compiler can synthesize a 300H variant of this which is
;; just as efficient as one that we'd create
(define_insn "zero_extendqisi2"
(zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
"TARGET_H8300"
"@
- mov.b #0,%x0\;sub.w %e0,%e0
- mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
+ mov.b #0,%x0\;sub.w %e0,%e0
+ mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
[(set_attr "length" "4,6")
(set_attr "cc" "clobber,clobber")])
(define_expand "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "general_operand" "")))]
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
""
- "
-{
- if (TARGET_H8300
- && GET_CODE (operands[1]) != CONST_INT
- && !optimize)
- {
- emit_insn (gen_zero_extendhisi2_h8300 (operands[0], operands[1]));
- DONE;
- }
-}")
-
-;; This is used when not optimizing. It avoids severe code explosion
-;; due to poor register allocation.
-(define_expand "zero_extendhisi2_h8300"
- [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
- (set (reg:SI 0) (zero_extend:SI (reg:HI 1)))
- (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
- "TARGET_H8300"
"")
;; %e prints the high part of a CONST_INT, not the low part. Arggh.
"TARGET_H8300"
"@
sub.w %e0,%e0
- mov.w %f1,%f0\;sub.w %e0,%e0
- mov.w %e1,%f0\;sub.w %e0,%e0"
+ mov.w %f1,%f0\;sub.w %e0,%e0
+ mov.w %e1,%f0\;sub.w %e0,%e0"
[(set_attr "length" "2,4,4")
(set_attr "cc" "clobber,clobber,clobber")])
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
"TARGET_H8300H || TARGET_H8300S"
- "@
- extu.l %S0
- mov.w %T1,%T0\;extu.l %S0"
- [(set_attr "length" "2,4")
- (set_attr "cc" "set_znv,set_znv")])
+ "extu.l %S0"
+ [(set_attr "length" "2")
+ (set_attr "cc" "set_znv")])
(define_expand "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
- (sign_extend:HI (match_operand:QI 1 "general_operand" "")))]
+ (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
""
"")
(set_attr "cc" "clobber,clobber")])
(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
"TARGET_H8300H || TARGET_H8300S"
- "@
- exts.w %T0
- mov.b %R1,%s0\;exts.w %T0"
- [(set_attr "length" "2,4")
- (set_attr "cc" "set_znv,set_znv")])
+ "exts.w %T0"
+ [(set_attr "length" "2")
+ (set_attr "cc" "set_znv")])
;; The compiler can synthesize a 300H variant of this which is
;; just as efficient as one that we'd create
"TARGET_H8300"
"@
bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
- mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
+ mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
[(set_attr "length" "8,10")
(set_attr "cc" "clobber,clobber")])
(define_expand "extendhisi2"
[(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
+ (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
""
- "
-{
- if (TARGET_H8300
- && GET_CODE (operands[1]) != CONST_INT
- && !optimize)
- {
- emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1]));
- DONE;
- }
-}")
-
-;; This is used when not optimizing. It avoids severe code explosion
-;; due to poor register allocation.
-(define_expand "extendhisi2_h8300"
- [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
- (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
- (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
- "TARGET_H8300"
"")
(define_insn ""
(set_attr "cc" "clobber,clobber")])
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
"TARGET_H8300H || TARGET_H8300S"
- "@
- exts.l %S0
- mov.w %T1,%T0\;exts.l %S0"
- [(set_attr "length" "2,4")
- (set_attr "cc" "set_znv,set_znv")])
+ "exts.l %S0"
+ [(set_attr "length" "2")
+ (set_attr "cc" "set_znv")])
\f
;; ----------------------------------------------------------------------
;; SHIFTS
;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
;; give the optimizer more cracks at the code. However, we wish to do things
;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
-;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
+;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
;; to detect cases it can optimize.
;;
(ashift:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
(define_expand "ashrqi3"
[(set (match_operand:QI 0 "register_operand" "")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
(define_expand "lshrqi3"
[(set (match_operand:QI 0 "register_operand" "")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
(define_insn ""
[(set (match_operand:QI 0 "register_operand" "=r,r")
- (match_operator:QI 3 "nshift_operator"
+ (match_operator:QI 3 "nshift_operator"
[ (match_operand:QI 1 "register_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
(clobber (match_scratch:QI 4 "=X,&r"))]
(ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
(define_expand "lshrhi3"
[(set (match_operand:HI 0 "register_operand" "")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
(define_expand "ashrhi3"
[(set (match_operand:HI 0 "register_operand" "")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=r,r")
- (match_operator:HI 3 "nshift_operator"
+ (match_operator:HI 3 "nshift_operator"
[ (match_operand:HI 1 "register_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
(clobber (match_scratch:QI 4 "=X,&r"))]
(match_operand:SI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "general_operand" "")
(match_operand:QI 2 "nonmemory_operand" "")))]
""
- "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
+ "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (match_operator:SI 3 "nshift_operator"
+ (match_operator:SI 3 "nshift_operator"
[ (match_operand:SI 1 "register_operand" "0,0")
(match_operand:QI 2 "nonmemory_operand" "K,rn")]))
(clobber (match_scratch:QI 4 "=X,&r"))]
[(set_attr "length" "20")
(set_attr "cc" "clobber")])
\f
+;; ----------------------------------------------------------------------
+;; ROTATIONS
+;; ----------------------------------------------------------------------
+
+(define_expand "rotlqi3"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (rotate:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ ""
+ "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
+
+(define_insn "*rotlqi3_1"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (rotate:QI (match_operand:QI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "")))]
+ ""
+ "* return emit_a_rotate (ROTATE, operands);"
+ [(set_attr "length" "20")
+ (set_attr "cc" "clobber")])
+
+(define_expand "rotlhi3"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (rotate:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ ""
+ "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
+
+(define_insn "*rotlhi3_1"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (rotate:HI (match_operand:HI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "")))]
+ ""
+ "* return emit_a_rotate (ROTATE, operands);"
+ [(set_attr "length" "20")
+ (set_attr "cc" "clobber")])
+
+(define_expand "rotlsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (rotate:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:QI 2 "nonmemory_operand" "")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
+
+(define_insn "*rotlsi3_1"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "register_operand" "0")
+ (match_operand:QI 2 "immediate_operand" "")))]
+ "TARGET_H8300H || TARGET_H8300S"
+ "* return emit_a_rotate (ROTATE, operands);"
+ [(set_attr "length" "20")
+ (set_attr "cc" "clobber")])
+\f
;; -----------------------------------------------------------------
;; BIT FIELDS
;; -----------------------------------------------------------------
;; You'll never believe all these patterns perform one basic action --
;; load a bit from the source, optionally invert the bit, then store it
-;; in the destination (which is known to be zero)..
+;; in the destination (which is known to be zero).
;;
;; Combine obviously need some work to better identify this situation and
;; canonicalize the form better.
-;;
+;;
;; Normal loads with a 16bit destination.
-;;
+;;
;; Yes, both cases are needed.
;;
(define_insn ""
(subreg:HI (zero_extract:SI
(match_operand:HI 1 "register_operand" "r")
(const_int 1)
- (match_operand:HI 2 "immediate_operand" "n")) 1))]
+ (match_operand:HI 2 "immediate_operand" "n")) 2))]
""
"sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
[(set_attr "cc" "clobber")
(set_attr "length" "6")])
-;;
+;;
;; Inverted loads with a 16bit destination.
-;;
+;;
;; Yes, all four cases are needed.
;;
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=&r")
- (and:HI (not:HI
+ (and:HI (not:HI
(lshiftrt:HI
(match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n")))
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=&r")
- (and:HI (not:HI
- (subreg:HI
+ (and:HI (not:HI
+ (subreg:HI
(lshiftrt:SI
(match_operand:SI 1 "register_operand" "Ur")
- (match_operand:SI 2 "const_int_operand" "n")) 1))
+ (match_operand:SI 2 "const_int_operand" "n")) 2))
(const_int 1)))]
"INTVAL (operands[2]) < 16"
"sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=&r")
- (and:HI (not:HI
- (subreg:HI
+ (and:HI (not:HI
+ (subreg:HI
(lshiftrt:SI
(match_operand:SI 1 "bit_operand" "Ur")
(match_operand:SI 2 "const_int_operand" "n")) 0))
[(set_attr "cc" "clobber")
(set_attr "length" "8")])
-;;
+;;
;; Normal loads with a 32bit destination.
-;;
+;;
;; Yes, all three cases are needed.
;;
(define_insn ""
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
- (and:SI (zero_extend:SI
+ (and:SI (zero_extend:SI
(lshiftrt:QI
(match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n")))
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
- (and:SI (zero_extend:SI
+ (and:SI (zero_extend:SI
(lshiftrt:HI
(match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n")))
(const_int 10)
(const_int 8)))])
-;;
+;;
;; Inverted loads with a 32bit destination.
-;;
-;; Yes, all seven cases are needed.
;;
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (and:SI (not:SI
- (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
- (match_operand:SI 2 "p_operand" "P")))]
- ""
- "* return output_simode_bld (1, 1, operands);"
- [(set_attr "cc" "clobber")
- (set (attr "length")
- (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
- (const_int 0))
- (const_int 10)
- (const_int 8)))])
+;; Yes, all five cases are needed.
+;;
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
- (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
- (match_operand:SI 2 "p_operand" "P")))]
- ""
- "* return output_simode_bld (1, 1, operands);"
- [(set_attr "cc" "clobber")
- (set (attr "length")
- (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
- (const_int 0))
- (const_int 10)
- (const_int 8)))])
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (and:SI (not:SI
(zero_extend:SI
(lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n"))))
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
- (subreg:SI
+ (subreg:SI
(lshiftrt:HI
(match_operand:HI 1 "bit_operand" "Ur")
(match_operand:HI 2 "const_int_operand" "n")) 0))
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(and:SI (not:SI
- (subreg:SI
+ (subreg:SI
(lshiftrt:QI
(match_operand:QI 1 "bit_operand" "Ur")
(match_operand:QI 2 "const_int_operand" "n")) 0))
(set_attr "length" "4")])
(define_expand "extzv"
- [(set (match_operand:HI 0 "register_operand" "")
+ [(set (match_operand:HI 0 "register_operand" "")
(zero_extract:HI (match_operand:HI 1 "bit_operand" "")
(match_operand:HI 2 "general_operand" "")
(match_operand:HI 3 "general_operand" "")))]
[(set_attr "cc" "clobber")
(set_attr "length" "6")
(set_attr "adjust_length" "no")])
-
\f
-;; ----------------------------------------------
-;; Peepholes go at the end.
-;; ----------------------------------------------
+;; -----------------------------------------------------------------
+;; COMBINE PATTERNS
+;; -----------------------------------------------------------------
-;; Notice a move which could be post incremented.
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "or\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
-(define_peephole
- [(set (match_operand:QI 0 "register_operand" "")
- (mem:QI (match_operand:HI 1 "register_operand" "")))
- (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
- "REGNO(operands[1]) != REGNO(operands[0])"
- "mov.b @%T1+,%X0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_znv")])
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[1])
+ && (REGNO (operands[0]) != REGNO (operands[1]))"
+ "or.w\\t%T1,%f0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
-(define_peephole
- [(set (match_operand:HI 0 "register_operand" "")
- (mem:HI (match_operand:HI 1 "register_operand" "")))
- (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))]
- "REGNO(operands[1]) != REGNO(operands[0])"
- "mov.w @%T1+,%T0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_znv")])
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI
+ (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "or\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
-;; Notice a move which could be predecremented.
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (xor:HI
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "xor\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
-(define_peephole
- [(set (match_operand:HI 1 "register_operand" "")
- (plus:HI (match_dup 1) (const_int -1)))
- (set (mem:QI (match_dup 1))
- (match_operand:QI 0 "register_operand" ""))]
- "REGNO(operands[1]) != REGNO(operands[0])"
- "mov.b %X0,@-%T1"
- [(set_attr "length" "2")
- (set_attr "cc" "set_znv")])
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[1])
+ && (REGNO (operands[0]) != REGNO (operands[1]))"
+ "xor.w\\t%T1,%f0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
-(define_peephole
- [(set (match_operand:HI 1 "register_operand" "")
- (plus:HI (match_dup 1) (const_int -2)))
- (set (mem:HI (match_dup 1))
- (match_operand:HI 0 "register_operand" ""))]
- "REGNO(operands[1]) != REGNO(operands[0])"
- "mov.w %T0,@-%T1"
- [(set_attr "length" "2")
- (set_attr "cc" "set_znv")])
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI
+ (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "xor\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI
+ (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+ (ashift:HI (match_operand:HI 2 "register_operand" "r")
+ (const_int 8))))]
+ "REG_P (operands[0])
+ && REG_P (operands[2])
+ && REGNO (operands[0]) != REGNO (operands[2])"
+ "mov.b\\t%s2,%t0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 16))))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[2])
+ && (REGNO (operands[0]) != REGNO (operands[2]))"
+ "mov.w\\t%f2,%e0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
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