-/* Subroutines for insn-output.c for Hitachi H8/300.
+/* Subroutines for insn-output.c for Renesas H8/300.
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002, 2003 Free Software Foundation, Inc.
+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+ Free Software Foundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com),
Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
+the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "recog.h"
#include "expr.h"
#include "function.h"
+#include "optabs.h"
#include "toplev.h"
#include "c-pragma.h"
#include "tm_p.h"
#include "target.h"
#include "target-def.h"
+/* Classifies a h8300_src_operand or h8300_dst_operand.
+
+ H8OP_IMMEDIATE
+ A constant operand of some sort.
+
+ H8OP_REGISTER
+ An ordinary register.
+
+ H8OP_MEM_ABSOLUTE
+ A memory reference with a constant address.
+
+ H8OP_MEM_BASE
+ A memory reference with a register as its address.
+
+ H8OP_MEM_COMPLEX
+ Some other kind of memory reference. */
+enum h8300_operand_class
+{
+ H8OP_IMMEDIATE,
+ H8OP_REGISTER,
+ H8OP_MEM_ABSOLUTE,
+ H8OP_MEM_BASE,
+ H8OP_MEM_COMPLEX,
+ NUM_H8OPS
+};
+
+/* For a general two-operand instruction, element [X][Y] gives
+ the length of the opcode fields when the first operand has class
+ (X + 1) and the second has class Y. */
+typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
+
/* Forward declarations. */
static const char *byte_reg (rtx, int);
static int h8300_interrupt_function_p (tree);
+static int h8300_saveall_function_p (tree);
static int h8300_monitor_function_p (tree);
static int h8300_os_task_function_p (tree);
-static void dosize (int, unsigned int);
-static int round_frame_size (int);
+static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
+static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
static unsigned int compute_saved_regs (void);
static void push (int);
static void pop (int);
static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
#ifndef OBJECT_FORMAT_ELF
-static void h8300_asm_named_section (const char *, unsigned int);
+static void h8300_asm_named_section (const char *, unsigned int, tree);
#endif
static int h8300_and_costs (rtx);
static int h8300_shift_costs (rtx);
+static void h8300_push_pop (int, int, bool, bool);
+static int h8300_stack_offset_p (rtx, int);
+static int h8300_ldm_stm_regno (rtx, int, int, int);
+static void h8300_reorg (void);
+static unsigned int h8300_constant_length (rtx);
+static unsigned int h8300_displacement_length (rtx, int);
+static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
+static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
+static unsigned int h8300_unary_length (rtx);
+static unsigned int h8300_short_immediate_length (rtx);
+static unsigned int h8300_bitfield_length (rtx, rtx);
+static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
+static bool h8300_short_move_mem_p (rtx, enum rtx_code);
+static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
+static bool h8300_hard_regno_scratch_ok (unsigned int);
/* CPU_TYPE, says what cpu we're compiling for. */
int cpu_type;
const char *h8_push_op, *h8_pop_op, *h8_mov_op;
-/* Machine-specific symbol_ref flags. */
-#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
-#define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
-#define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
+/* Value of MOVE_RATIO. */
+int h8300_move_ratio;
\f
/* See below where shifts are handled for explanation of this enum. */
if (!TARGET_H8300S && TARGET_MAC)
{
error ("-ms2600 is used without -ms");
- target_flags |= MASK_H8300S;
+ target_flags |= MASK_H8300S_1;
}
if (TARGET_H8300 && TARGET_NORMAL_MODE)
/* H8S */
shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
}
+
+ /* Work out a value for MOVE_RATIO. */
+ if (!TARGET_H8300SX)
+ {
+ /* Memory-memory moves are quite expensive without the
+ h8sx instructions. */
+ h8300_move_ratio = 3;
+ }
+ else if (flag_omit_frame_pointer)
+ {
+ /* movmd sequences are fairly cheap when er6 isn't fixed. They can
+ sometimes be as short as two individual memory-to-memory moves,
+ but since they use all the call-saved registers, it seems better
+ to allow up to three moves here. */
+ h8300_move_ratio = 4;
+ }
+ else if (optimize_size)
+ {
+ /* In this case we don't use movmd sequences since they tend
+ to be longer than calls to memcpy(). Memory-to-memory
+ moves are cheaper than for !TARGET_H8300SX, so it makes
+ sense to have a slightly higher threshold. */
+ h8300_move_ratio = 4;
+ }
+ else
+ {
+ /* We use movmd sequences for some moves since it can be quicker
+ than calling memcpy(). The sequences will need to save and
+ restore er6 though, so bump up the cost. */
+ h8300_move_ratio = 6;
+ }
}
+/* Implement REG_CLASS_FROM_LETTER.
+
+ Some patterns need to use er6 as a scratch register. This is
+ difficult to arrange since er6 is the frame pointer and usually
+ can't be spilled.
+
+ Such patterns should define two alternatives, one which allows only
+ er6 and one which allows any general register. The former alternative
+ should have a 'd' constraint while the latter should be disparaged and
+ use 'D'.
+
+ Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
+ However, there are cases where they should be NO_REGS:
+
+ - 'd' should be NO_REGS when reloading a function that uses the
+ frame pointer. In this case, DESTINATION_REGS won't contain any
+ spillable registers, so the first alternative can't be used.
+
+ - -fno-omit-frame-pointer means that the frame pointer will
+ always be in use. It's therefore better to map 'd' to NO_REGS
+ before reload so that register allocator will pick the second
+ alternative.
+
+ - we would like 'D' to be be NO_REGS when the frame pointer isn't
+ live, but we the frame pointer may turn out to be needed after
+ we start reload, and then we may have already decided we don't
+ have a choice, so we can't do that. Forcing the register
+ allocator to use er6 if possible might produce better code for
+ small functions: it's more efficient to save and restore er6 in
+ the prologue & epilogue than to do it in a define_split.
+ Hopefully disparaging 'D' will have a similar effect, without
+ forcing a reload failure if the frame pointer is found to be
+ needed too late. */
+
+enum reg_class
+h8300_reg_class_from_letter (int c)
+{
+ switch (c)
+ {
+ case 'a':
+ return MAC_REGS;
+
+ case 'c':
+ return COUNTER_REGS;
+
+ case 'd':
+ if (!flag_omit_frame_pointer && !reload_completed)
+ return NO_REGS;
+ if (frame_pointer_needed && reload_in_progress)
+ return NO_REGS;
+ return DESTINATION_REGS;
+
+ case 'D':
+ /* The meaning of a constraint shouldn't change dynamically, so
+ we can't make this NO_REGS. */
+ return GENERAL_REGS;
+
+ case 'f':
+ return SOURCE_REGS;
+
+ default:
+ return NO_REGS;
+ }
+}
+
+/* Return the byte register name for a register rtx X. B should be 0
+ if you want a lower byte register. B should be 1 if you want an
+ upper byte register. */
+
static const char *
byte_reg (rtx x, int b)
{
"r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
};
+ gcc_assert (REG_P (x));
+
return names_small[REGNO (x) * 2 + b];
}
/* REGNO must be saved/restored across calls if this macro is true. */
#define WORD_REG_USED(regno) \
- (regno < 7 \
+ (regno < SP_REG \
/* No need to save registers if this function will not return. */ \
&& ! TREE_THIS_VOLATILE (current_function_decl) \
- && (pragma_saveall \
+ && (h8300_saveall_function_p (current_function_decl) \
/* Save any call saved register that was used. */ \
- || (regs_ever_live[regno] && !call_used_regs[regno]) \
+ || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
/* Save the frame pointer if it was used. */ \
- || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
+ || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
/* Save any register used in an interrupt handler. */ \
|| (h8300_current_function_interrupt_function_p () \
- && regs_ever_live[regno]) \
+ && df_regs_ever_live_p (regno)) \
/* Save call clobbered registers in non-leaf interrupt \
handlers. */ \
|| (h8300_current_function_interrupt_function_p () \
&& call_used_regs[regno] \
&& !current_function_is_leaf)))
+/* We use this to wrap all emitted insns in the prologue. */
+static rtx
+F (rtx x, bool set_it)
+{
+ if (set_it)
+ RTX_FRAME_RELATED_P (x) = 1;
+ return x;
+}
+
+/* Mark all the subexpressions of the PARALLEL rtx PAR as
+ frame-related. Return PAR.
+
+ dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
+ PARALLEL rtx other than the first if they do not have the
+ FRAME_RELATED flag set on them. */
+static rtx
+Fpa (rtx par)
+{
+ int len = XVECLEN (par, 0);
+ int i;
+
+ for (i = 0; i < len; i++)
+ F (XVECEXP (par, 0, i), true);
+
+ return par;
+}
+
/* Output assembly language to FILE for the operation OP with operand size
SIZE to adjust the stack pointer. */
static void
-dosize (sign, size)
- int sign;
- unsigned int size;
+h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
{
+ /* If the frame size is 0, we don't have anything to do. */
+ if (size == 0)
+ return;
+
/* H8/300 cannot add/subtract a large constant with a single
instruction. If a temporary register is available, load the
constant to it and then do the addition. */
if (TARGET_H8300
&& size > 4
&& !h8300_current_function_interrupt_function_p ()
- && !(current_function_needs_context && sign < 0))
+ && !(cfun->static_chain_decl != NULL && sign < 0))
{
- rtx new_sp;
rtx r3 = gen_rtx_REG (Pmode, 3);
- emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
- new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
- emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
+ F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
+ F (emit_insn (gen_addhi3 (stack_pointer_rtx,
+ stack_pointer_rtx, r3)), in_prologue);
}
else
{
/* The stack adjustment made here is further optimized by the
splitter. In case of H8/300, the splitter always splits the
- addition emitted here to make the adjustment
- interrupt-safe. */
- rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
- emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
+ addition emitted here to make the adjustment interrupt-safe.
+ FIXME: We don't always tag those, because we don't know what
+ the splitter will do. */
+ if (Pmode == HImode)
+ {
+ rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
+ stack_pointer_rtx, GEN_INT (sign * size)));
+ if (size < 4)
+ F (x, in_prologue);
+ }
+ else
+ F (emit_insn (gen_addsi3 (stack_pointer_rtx,
+ stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
}
}
/* Round up frame size SIZE. */
-static int
-round_frame_size (int size)
+static HOST_WIDE_INT
+round_frame_size (HOST_WIDE_INT size)
{
return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
& -STACK_BOUNDARY / BITS_PER_UNIT);
int regno;
/* Construct a bit vector of registers to be pushed/popped. */
- for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
+ for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
{
if (WORD_REG_USED (regno))
saved_regs |= 1 << regno;
/* Don't push/pop the frame pointer as it is treated separately. */
if (frame_pointer_needed)
- saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
+ saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
return saved_regs;
}
if (TARGET_H8300)
x = gen_push_h8300 (reg);
+ else if (!TARGET_NORMAL_MODE)
+ x = gen_push_h8300hs_advanced (reg);
else
- x = gen_push_h8300hs (reg);
- x = emit_insn (x);
+ x = gen_push_h8300hs_normal (reg);
+ x = F (emit_insn (x), true);
REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
}
if (TARGET_H8300)
x = gen_pop_h8300 (reg);
+ else if (!TARGET_NORMAL_MODE)
+ x = gen_pop_h8300hs_advanced (reg);
else
- x = gen_pop_h8300hs (reg);
+ x = gen_pop_h8300hs_normal (reg);
x = emit_insn (x);
REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
}
+/* Emit an instruction to push or pop NREGS consecutive registers
+ starting at register REGNO. POP_P selects a pop rather than a
+ push and RETURN_P is true if the instruction should return.
+
+ It must be possible to do the requested operation in a single
+ instruction. If NREGS == 1 && !RETURN_P, use a normal push
+ or pop insn. Otherwise emit a parallel of the form:
+
+ (parallel
+ [(return) ;; if RETURN_P
+ (save or restore REGNO)
+ (save or restore REGNO + 1)
+ ...
+ (save or restore REGNO + NREGS - 1)
+ (set sp (plus sp (const_int adjust)))] */
+
+static void
+h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
+{
+ int i, j;
+ rtvec vec;
+ rtx sp, offset, x;
+
+ /* See whether we can use a simple push or pop. */
+ if (!return_p && nregs == 1)
+ {
+ if (pop_p)
+ pop (regno);
+ else
+ push (regno);
+ return;
+ }
+
+ /* We need one element for the return insn, if present, one for each
+ register, and one for stack adjustment. */
+ vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
+ sp = stack_pointer_rtx;
+ i = 0;
+
+ /* Add the return instruction. */
+ if (return_p)
+ {
+ RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
+ i++;
+ }
+
+ /* Add the register moves. */
+ for (j = 0; j < nregs; j++)
+ {
+ rtx lhs, rhs;
+
+ if (pop_p)
+ {
+ /* Register REGNO + NREGS - 1 is popped first. Before the
+ stack adjustment, its slot is at address @sp. */
+ lhs = gen_rtx_REG (SImode, regno + j);
+ rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
+ }
+ else
+ {
+ /* Register REGNO is pushed first and will be stored at @(-4,sp). */
+ lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
+ rhs = gen_rtx_REG (SImode, regno + j);
+ }
+ RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
+ }
+
+ /* Add the stack adjustment. */
+ offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
+ RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
+ gen_rtx_PLUS (Pmode, sp, offset));
+
+ x = gen_rtx_PARALLEL (VOIDmode, vec);
+ if (!pop_p)
+ x = Fpa (x);
+
+ if (return_p)
+ emit_jump_insn (x);
+ else
+ emit_insn (x);
+}
+
+/* Return true if X has the value sp + OFFSET. */
+
+static int
+h8300_stack_offset_p (rtx x, int offset)
+{
+ if (offset == 0)
+ return x == stack_pointer_rtx;
+
+ return (GET_CODE (x) == PLUS
+ && XEXP (x, 0) == stack_pointer_rtx
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && INTVAL (XEXP (x, 1)) == offset);
+}
+
+/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
+ something that may be an ldm or stm instruction. If it fits
+ the required template, return the register it loads or stores,
+ otherwise return -1.
+
+ LOAD_P is true if X should be a load, false if it should be a store.
+ NREGS is the number of registers that the whole instruction is expected
+ to load or store. INDEX is the index of the register that X should
+ load or store, relative to the lowest-numbered register. */
+
+static int
+h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
+{
+ int regindex, memindex, offset;
+
+ if (load_p)
+ regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
+ else
+ memindex = 0, regindex = 1, offset = (index + 1) * -4;
+
+ if (GET_CODE (x) == SET
+ && GET_CODE (XEXP (x, regindex)) == REG
+ && GET_CODE (XEXP (x, memindex)) == MEM
+ && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
+ return REGNO (XEXP (x, regindex));
+
+ return -1;
+}
+
+/* Return true if the elements of VEC starting at FIRST describe an
+ ldm or stm instruction (LOAD_P says which). */
+
+int
+h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
+{
+ rtx last;
+ int nregs, i, regno, adjust;
+
+ /* There must be a stack adjustment, a register move, and at least one
+ other operation (a return or another register move). */
+ if (GET_NUM_ELEM (vec) < 3)
+ return false;
+
+ /* Get the range of registers to be pushed or popped. */
+ nregs = GET_NUM_ELEM (vec) - first - 1;
+ regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
+
+ /* Check that the call to h8300_ldm_stm_regno succeeded and
+ that we're only dealing with GPRs. */
+ if (regno < 0 || regno + nregs > 8)
+ return false;
+
+ /* 2-register h8s instructions must start with an even-numbered register.
+ 3- and 4-register instructions must start with er0 or er4. */
+ if (!TARGET_H8300SX)
+ {
+ if ((regno & 1) != 0)
+ return false;
+ if (nregs > 2 && (regno & 3) != 0)
+ return false;
+ }
+
+ /* Check the other loads or stores. */
+ for (i = 1; i < nregs; i++)
+ if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
+ != regno + i)
+ return false;
+
+ /* Check the stack adjustment. */
+ last = RTVEC_ELT (vec, first + nregs);
+ adjust = (load_p ? nregs : -nregs) * 4;
+ return (GET_CODE (last) == SET
+ && SET_DEST (last) == stack_pointer_rtx
+ && h8300_stack_offset_p (SET_SRC (last), adjust));
+}
+
/* This is what the stack looks like after the prolog of
a function with a frame has been set up:
if (frame_pointer_needed)
{
/* Push fp. */
- push (FRAME_POINTER_REGNUM);
- emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
+ push (HARD_FRAME_POINTER_REGNUM);
+ F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
}
- /* Leave room for locals. */
- dosize (-1, round_frame_size (get_frame_size ()));
-
/* Push the rest of the registers in ascending order. */
saved_regs = compute_saved_regs ();
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
if (TARGET_H8300S)
{
/* See how many registers we can push at the same time. */
- if ((regno == 0 || regno == 4)
+ if ((!TARGET_H8300SX || (regno & 3) == 0)
&& ((saved_regs >> regno) & 0x0f) == 0x0f)
n_regs = 4;
- else if ((regno == 0 || regno == 4)
+ else if ((!TARGET_H8300SX || (regno & 3) == 0)
&& ((saved_regs >> regno) & 0x07) == 0x07)
n_regs = 3;
- else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
+ else if ((!TARGET_H8300SX || (regno & 1) == 0)
&& ((saved_regs >> regno) & 0x03) == 0x03)
n_regs = 2;
}
- switch (n_regs)
- {
- case 1:
- push (regno);
- break;
- case 2:
- emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
- gen_rtx_REG (SImode, regno + 1)));
- break;
- case 3:
- emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
- gen_rtx_REG (SImode, regno + 1),
- gen_rtx_REG (SImode, regno + 2)));
- break;
- case 4:
- emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
- gen_rtx_REG (SImode, regno + 1),
- gen_rtx_REG (SImode, regno + 2),
- gen_rtx_REG (SImode, regno + 3)));
- break;
- default:
- abort ();
- }
+ h8300_push_pop (regno, n_regs, false, false);
}
}
+
+ /* Leave room for locals. */
+ h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
}
+/* Return nonzero if we can use "rts" for the function currently being
+ compiled. */
+
int
h8300_can_use_return_insn_p (void)
{
int regno;
int saved_regs;
int n_regs;
+ HOST_WIDE_INT frame_size;
+ bool returned_p;
if (h8300_os_task_function_p (current_function_decl))
/* OS_Task epilogues are nearly naked -- they just have an
rts instruction. */
return;
+ frame_size = round_frame_size (get_frame_size ());
+ returned_p = false;
+
+ /* Deallocate locals. */
+ h8300_emit_stack_adjustment (1, frame_size, false);
+
/* Pop the saved registers in descending order. */
saved_regs = compute_saved_regs ();
for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
if (TARGET_H8300S)
{
/* See how many registers we can pop at the same time. */
- if ((regno == 7 || regno == 3)
- && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
+ if ((TARGET_H8300SX || (regno & 3) == 3)
+ && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
n_regs = 4;
- else if ((regno == 6 || regno == 2)
- && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
+ else if ((TARGET_H8300SX || (regno & 3) == 2)
+ && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
n_regs = 3;
- else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
- && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
+ else if ((TARGET_H8300SX || (regno & 1) == 1)
+ && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
n_regs = 2;
}
- switch (n_regs)
- {
- case 1:
- pop (regno);
- break;
- case 2:
- emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
- gen_rtx_REG (SImode, regno)));
- break;
- case 3:
- emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
- gen_rtx_REG (SImode, regno - 1),
- gen_rtx_REG (SImode, regno)));
- break;
- case 4:
- emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
- gen_rtx_REG (SImode, regno - 2),
- gen_rtx_REG (SImode, regno - 1),
- gen_rtx_REG (SImode, regno)));
- break;
- default:
- abort ();
- }
+ /* See if this pop would be the last insn before the return.
+ If so, use rte/l or rts/l instead of pop or ldm.l. */
+ if (TARGET_H8300SX
+ && !frame_pointer_needed
+ && frame_size == 0
+ && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
+ returned_p = true;
+
+ h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
}
}
- /* Deallocate locals. */
- dosize (1, round_frame_size (get_frame_size ()));
-
/* Pop frame pointer if we had one. */
if (frame_pointer_needed)
- pop (FRAME_POINTER_REGNUM);
-}
-
-/* Output assembly language code for the function epilogue. */
+ {
+ if (TARGET_H8300SX)
+ returned_p = true;
+ h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
+ }
-static void
-h8300_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
- HOST_WIDE_INT size ATTRIBUTE_UNUSED)
-{
- pragma_saveall = 0;
+ if (!returned_p)
+ emit_jump_insn (gen_rtx_RETURN (VOIDmode));
}
/* Return nonzero if the current function is an interrupt
if (TARGET_H8300H)
fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
+ else if (TARGET_H8300SX)
+ fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
else if (TARGET_H8300S)
fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
}
fputs ("\t.end\n", asm_out_file);
}
\f
-/* Return true if OP is a valid source operand for an integer move
- instruction. */
-
-int
-general_operand_src (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) == mode
- && GET_CODE (op) == MEM
- && GET_CODE (XEXP (op, 0)) == POST_INC)
- return 1;
- return general_operand (op, mode);
-}
-
-/* Return true if OP is a valid destination operand for an integer move
- instruction. */
-
-int
-general_operand_dst (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) == mode
- && GET_CODE (op) == MEM
- && GET_CODE (XEXP (op, 0)) == PRE_DEC)
- return 1;
- return general_operand (op, mode);
-}
-
-/* Return true if OP is a constant that contains only one 1 in its
- binary representation. */
-
-int
-single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (operand) == CONST_INT)
- {
- /* We really need to do this masking because 0x80 in QImode is
- represented as -128 for example. */
- if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
- return 1;
- }
-
- return 0;
-}
-
-/* Return true if OP is a constant that contains only one 0 in its
- binary representation. */
-
-int
-single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (operand) == CONST_INT)
- {
- /* We really need to do this masking because 0x80 in QImode is
- represented as -128 for example. */
- if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
- return 1;
- }
-
- return 0;
-}
-
-/* Return true if OP is a valid call operand. */
-
-int
-call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (op) == MEM)
- {
- rtx inside = XEXP (op, 0);
- if (register_operand (inside, Pmode))
- return 1;
- if (CONSTANT_ADDRESS_P (inside))
- return 1;
- }
- return 0;
-}
-
-/* Return 1 if an addition/subtraction of a constant integer can be
- transformed into two consecutive adds/subs that are faster than the
- straightforward way. Otherwise, return 0. */
-
-int
-two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
-{
- if (GET_CODE (op) == CONST_INT)
- {
- HOST_WIDE_INT value = INTVAL (op);
-
- /* Force VALUE to be positive so that we do not have to consider
- the negative case. */
- if (value < 0)
- value = -value;
- if (TARGET_H8300H || TARGET_H8300S)
- {
- /* A constant addition/subtraction takes 2 states in QImode,
- 4 states in HImode, and 6 states in SImode. Thus, the
- only case we can win is when SImode is used, in which
- case, two adds/subs are used, taking 4 states. */
- if (mode == SImode
- && (value == 2 + 1
- || value == 4 + 1
- || value == 4 + 2
- || value == 4 + 4))
- return 1;
- }
- else
- {
- /* We do not profit directly by splitting addition or
- subtraction of 3 and 4. However, since these are
- implemented as a sequence of adds or subs, they do not
- clobber (cc0) unlike a sequence of add.b and add.x. */
- if (mode == HImode
- && (value == 2 + 1
- || value == 2 + 2))
- return 1;
- }
- }
-
- return 0;
-}
-
/* Split an add of a small constant into two adds/subs insns.
If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* Try different amounts in descending order. */
return;
}
-/* Return true if OP is a valid call operand, and OP represents
- an operand for a small call (4 bytes instead of 6 bytes). */
-
-int
-small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (op) == MEM)
- {
- rtx inside = XEXP (op, 0);
-
- /* Register indirect is a small call. */
- if (register_operand (inside, Pmode))
- return 1;
-
- /* A call through the function vector is a small call too. */
- if (GET_CODE (inside) == SYMBOL_REF
- && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
- return 1;
- }
- /* Otherwise it's a large call. */
- return 0;
-}
-
-/* Return true if OP is a valid jump operand. */
-
-int
-jump_address_operand (rtx op, enum machine_mode mode)
-{
- if (GET_CODE (op) == REG)
- return mode == Pmode;
-
- if (GET_CODE (op) == MEM)
- {
- rtx inside = XEXP (op, 0);
- if (register_operand (inside, Pmode))
- return 1;
- if (CONSTANT_ADDRESS_P (inside))
- return 1;
- }
- return 0;
-}
-
-/* Recognize valid operands for bit-field instructions. */
-
-extern int rtx_equal_function_value_matters;
-
-int
-bit_operand (rtx op, enum machine_mode mode)
-{
- /* We can accept any general operand, except that MEM operands must
- be limited to those that use addresses valid for the 'U' constraint. */
- if (!general_operand (op, mode))
- return 0;
-
- /* Accept any mem during RTL generation. Otherwise, the code that does
- insv and extzv will think that we can not handle memory. However,
- to avoid reload problems, we only accept 'U' MEM operands after RTL
- generation. This means that any named pattern which uses this predicate
- must force its operands to match 'U' before emitting RTL. */
-
- if (GET_CODE (op) == REG)
- return 1;
- if (GET_CODE (op) == SUBREG)
- return 1;
- return (GET_CODE (op) == MEM
- && EXTRA_CONSTRAINT (op, 'U'));
-}
-
-int
-bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == MEM
- && EXTRA_CONSTRAINT (op, 'U'));
-}
-
/* Handle machine specific pragmas for compatibility with existing
compilers for the H8/300.
return result;
}
\f
+/* Compute the cost of an and insn. */
+
static int
h8300_and_costs (rtx x)
{
return 100;
operands[0] = NULL;
- operands[1] = NULL;
+ operands[1] = XEXP (x, 0);
operands[2] = XEXP (x, 1);
operands[3] = x;
return compute_logical_op_length (GET_MODE (x), operands) / 2;
}
+/* Compute the cost of a shift insn. */
+
static int
h8300_shift_costs (rtx x)
{
return compute_a_shift_length (NULL, operands) / 2;
}
+/* Worker function for TARGET_RTX_COSTS. */
+
static bool
-h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
+h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
{
+ if (TARGET_H8300SX && outer_code == MEM)
+ {
+ /* Estimate the number of execution states needed to calculate
+ the address. */
+ if (register_operand (x, VOIDmode)
+ || GET_CODE (x) == POST_INC
+ || GET_CODE (x) == POST_DEC
+ || CONSTANT_P (x))
+ *total = 0;
+ else
+ *total = COSTS_N_INSNS (1);
+ return true;
+ }
+
switch (code)
{
case CONST_INT:
{
HOST_WIDE_INT n = INTVAL (x);
+ if (TARGET_H8300SX)
+ {
+ /* Constant operands need the same number of processor
+ states as register operands. Although we could try to
+ use a size-based cost for !speed, the lack of
+ of a mode makes the results very unpredictable. */
+ *total = 0;
+ return true;
+ }
if (-4 <= n || n <= 4)
{
switch ((int) n)
case CONST:
case LABEL_REF:
case SYMBOL_REF:
+ if (TARGET_H8300SX)
+ {
+ /* See comment for CONST_INT. */
+ *total = 0;
+ return true;
+ }
*total = 3;
return true;
*total = 20;
return true;
+ case COMPARE:
+ if (XEXP (x, 1) == const0_rtx)
+ *total = 0;
+ return false;
+
case AND:
+ if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
+ || !h8300_src_operand (XEXP (x, 1), VOIDmode))
+ return false;
*total = COSTS_N_INSNS (h8300_and_costs (x));
return true;
generate some really horrible code for division of a power of two. */
case MOD:
case DIV:
- *total = 60;
+ case UMOD:
+ case UDIV:
+ if (TARGET_H8300SX)
+ switch (GET_MODE (x))
+ {
+ case QImode:
+ case HImode:
+ *total = COSTS_N_INSNS (!speed ? 4 : 10);
+ return false;
+
+ case SImode:
+ *total = COSTS_N_INSNS (!speed ? 4 : 18);
+ return false;
+
+ default:
+ break;
+ }
+ *total = COSTS_N_INSNS (12);
return true;
case MULT:
- *total = 20;
+ if (TARGET_H8300SX)
+ switch (GET_MODE (x))
+ {
+ case QImode:
+ case HImode:
+ *total = COSTS_N_INSNS (2);
+ return false;
+
+ case SImode:
+ *total = COSTS_N_INSNS (5);
+ return false;
+
+ default:
+ break;
+ }
+ *total = COSTS_N_INSNS (4);
return true;
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
+ if (h8sx_binary_shift_operator (x, VOIDmode))
+ {
+ *total = COSTS_N_INSNS (2);
+ return false;
+ }
+ else if (h8sx_unary_shift_operator (x, VOIDmode))
+ {
+ *total = COSTS_N_INSNS (1);
+ return false;
+ }
*total = COSTS_N_INSNS (h8300_shift_costs (x));
return true;
return true;
default:
- *total = 4;
- return true;
+ *total = COSTS_N_INSNS (1);
+ return false;
}
}
\f
If this operand isn't a register, fall back to 'R' handling.
'Z' print int & 7.
'c' print the opcode corresponding to rtl
- 'e' first word of 32 bit value - if reg, then least reg. if mem
+ 'e' first word of 32-bit value - if reg, then least reg. if mem
then least. if const then most sig word
- 'f' second word of 32 bit value - if reg, then biggest reg. if mem
+ 'f' second word of 32-bit value - if reg, then biggest reg. if mem
then +2. if const then least sig word
'j' print operand as condition code.
'k' print operand as reverse condition code.
- 's' print as low byte of 16 bit value
- 't' print as high byte of 16 bit value
- 'w' print as low byte of 32 bit value
- 'x' print as 2nd byte of 32 bit value
- 'y' print as 3rd byte of 32 bit value
- 'z' print as msb of 32 bit value
+ 'm' convert an integer operand to a size suffix (.b, .w or .l)
+ 'o' print an integer without a leading '#'
+ 's' print as low byte of 16-bit value
+ 't' print as high byte of 16-bit value
+ 'w' print as low byte of 32-bit value
+ 'x' print as 2nd byte of 32-bit value
+ 'y' print as 3rd byte of 32-bit value
+ 'z' print as msb of 32-bit value
*/
/* Return assembly language string which identifies a comparison type. */
case LTU:
return "lo";
default:
- abort ();
+ gcc_unreachable ();
}
}
fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
case 'F':
fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
case 'G':
- if (GET_CODE (x) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (x) == CONST_INT);
fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
break;
case 'S':
goto def;
break;
case 'V':
- bitint = exact_log2 (INTVAL (x) & 0xff);
- if (bitint == -1)
- abort ();
+ bitint = (INTVAL (x) & 0xffff);
+ if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
+ bitint = exact_log2 (bitint & 0xff);
+ else
+ bitint = exact_log2 ((bitint >> 8) & 0xff);
+ gcc_assert (bitint >= 0);
fprintf (file, "#%d", bitint);
break;
case 'W':
- bitint = exact_log2 ((~INTVAL (x)) & 0xff);
- if (bitint == -1)
- abort ();
+ bitint = ((~INTVAL (x)) & 0xffff);
+ if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
+ bitint = exact_log2 (bitint & 0xff);
+ else
+ bitint = (exact_log2 ((bitint >> 8) & 0xff));
+ gcc_assert (bitint >= 0);
fprintf (file, "#%d", bitint);
break;
case 'R':
goto def;
break;
case 'Y':
- if (bitint == -1)
- abort ();
+ gcc_assert (bitint >= 0);
if (GET_CODE (x) == REG)
fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
else
break;
}
default:
- abort ();
+ gcc_unreachable ();
break;
}
break;
break;
}
default:
- abort ();
+ gcc_unreachable ();
}
break;
case 'j':
case 'k':
fputs (cond_string (reverse_condition (GET_CODE (x))), file);
break;
+ case 'm':
+ gcc_assert (GET_CODE (x) == CONST_INT);
+ switch (INTVAL (x))
+ {
+ case 1:
+ fputs (".b", file);
+ break;
+
+ case 2:
+ fputs (".w", file);
+ break;
+
+ case 4:
+ fputs (".l", file);
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+ break;
+ case 'o':
+ print_operand_address (file, x);
+ break;
case 's':
if (GET_CODE (x) == CONST_INT)
fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
fprintf (file, "%s", names_extended[REGNO (x)]);
break;
default:
- abort ();
+ gcc_unreachable ();
}
break;
fprintf (file, "@");
output_address (addr);
- /* We fall back from smaller addressing to larger
- addressing in various ways depending on CODE. */
- switch (code)
- {
- case 'R':
- /* Used for mov.b and bit operations. */
- if (h8300_eightbit_constant_address_p (addr))
- {
- fprintf (file, ":8");
- break;
- }
-
- /* Fall through. We should not get here if we are
- processing bit operations on H8/300 or H8/300H
- because 'U' constraint does not allow bit
- operations on the tiny area on these machines. */
-
- case 'T':
- case 'S':
- /* Used for mov.w and mov.l. */
- if (h8300_tiny_constant_address_p (addr))
- fprintf (file, ":16");
- break;
- default:
- break;
- }
+ /* Add a length suffix to constant addresses. Although this
+ is often unnecessary, it helps to avoid ambiguity in the
+ syntax of mova. If we wrote an insn like:
+
+ mova/w.l @(1,@foo.b),er0
+
+ then .b would be considered part of the symbol name.
+ Adding a length after foo will avoid this. */
+ if (CONSTANT_P (addr))
+ switch (code)
+ {
+ case 'R':
+ /* Used for mov.b and bit operations. */
+ if (h8300_eightbit_constant_address_p (addr))
+ {
+ fprintf (file, ":8");
+ break;
+ }
+
+ /* Fall through. We should not get here if we are
+ processing bit operations on H8/300 or H8/300H
+ because 'U' constraint does not allow bit
+ operations on the tiny area on these machines. */
+
+ case 'X':
+ case 'T':
+ case 'S':
+ if (h8300_constant_length (addr) == 2)
+ fprintf (file, ":16");
+ else
+ fprintf (file, ":32");
+ break;
+ default:
+ break;
+ }
}
break;
void
print_operand_address (FILE *file, rtx addr)
{
+ rtx index;
+ int size;
+
switch (GET_CODE (addr))
{
case REG:
fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
break;
+ case PRE_INC:
+ fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
+ break;
+
+ case POST_DEC:
+ fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
+ break;
+
case PLUS:
fprintf (file, "(");
- if (GET_CODE (XEXP (addr, 0)) == REG)
+
+ index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
+ if (GET_CODE (index) == REG)
{
/* reg,foo */
print_operand_address (file, XEXP (addr, 1));
fprintf (file, ",");
- print_operand_address (file, XEXP (addr, 0));
+ switch (size)
+ {
+ case 0:
+ print_operand_address (file, index);
+ break;
+
+ case 1:
+ print_operand (file, index, 'X');
+ fputs (".b", file);
+ break;
+
+ case 2:
+ print_operand (file, index, 'T');
+ fputs (".w", file);
+ break;
+
+ case 4:
+ print_operand (file, index, 'S');
+ fputs (".l", file);
+ break;
+ }
+ /* print_operand_address (file, XEXP (addr, 0)); */
}
else
{
case CONST_INT:
{
- /* Since the H8/300 only has 16 bit pointers, negative values are also
+ /* Since the H8/300 only has 16-bit pointers, negative values are also
those >= 32768. This happens for example with pointer minus a
constant. We don't want to turn (char *p - 2) into
(char *p + 65534) because loop unrolling can build upon this
/* Prepare for an SI sized move. */
int
-do_movsi (rtx operands[])
+h8300_expand_movsi (rtx operands[])
{
rtx src = operands[1];
rtx dst = operands[0];
return 0;
}
+/* Given FROM and TO register numbers, say whether this elimination is allowed.
+ Frame pointer elimination is automatically handled.
+
+ For the h8300, if frame pointer elimination is being done, we would like to
+ convert ap and rp into sp, not fp.
+
+ All other eliminations are valid. */
+
+static bool
+h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
+{
+ return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
+}
+
/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
Define the offset between two registers, one to be eliminated, and
the other its replacement, at the start of a routine. */
int
h8300_initial_elimination_offset (int from, int to)
{
- int offset = 0;
/* The number of bytes that the return address takes on the stack. */
int pc_size = POINTER_SIZE / BITS_PER_UNIT;
- if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
- offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
- else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
- offset = frame_pointer_needed * UNITS_PER_WORD;
- else
- {
- int regno;
+ /* The number of bytes that the saved frame pointer takes on the stack. */
+ int fp_size = frame_pointer_needed * UNITS_PER_WORD;
- for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
- if (WORD_REG_USED (regno))
- offset += UNITS_PER_WORD;
+ /* The number of bytes that the saved registers, excluding the frame
+ pointer, take on the stack. */
+ int saved_regs_size = 0;
- /* See the comments for get_frame_size. We need to round it up to
- STACK_BOUNDARY. */
+ /* The number of bytes that the locals takes on the stack. */
+ int frame_size = round_frame_size (get_frame_size ());
- offset += round_frame_size (get_frame_size ());
+ int regno;
- if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
- /* Skip saved PC. */
- offset += pc_size;
- }
+ for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
+ if (WORD_REG_USED (regno))
+ saved_regs_size += UNITS_PER_WORD;
+
+ /* Adjust saved_regs_size because the above loop took the frame
+ pointer int account. */
+ saved_regs_size -= fp_size;
- return offset;
+ switch (to)
+ {
+ case HARD_FRAME_POINTER_REGNUM:
+ switch (from)
+ {
+ case ARG_POINTER_REGNUM:
+ return pc_size + fp_size;
+ case RETURN_ADDRESS_POINTER_REGNUM:
+ return fp_size;
+ case FRAME_POINTER_REGNUM:
+ return -saved_regs_size;
+ default:
+ gcc_unreachable ();
+ }
+ break;
+ case STACK_POINTER_REGNUM:
+ switch (from)
+ {
+ case ARG_POINTER_REGNUM:
+ return pc_size + saved_regs_size + frame_size;
+ case RETURN_ADDRESS_POINTER_REGNUM:
+ return saved_regs_size + frame_size;
+ case FRAME_POINTER_REGNUM:
+ return frame_size;
+ default:
+ gcc_unreachable ();
+ }
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ gcc_unreachable ();
}
+/* Worker function for RETURN_ADDR_RTX. */
+
rtx
h8300_return_addr_rtx (int count, rtx frame)
{
else
cc_status.value2 = SET_DEST (set);
}
- break;
+ break;
+
+ case CC_COMPARE:
+ /* The insn is a compare instruction. */
+ CC_STATUS_INIT;
+ cc_status.value1 = SET_SRC (body);
+ break;
+
+ case CC_CLOBBER:
+ /* Insn doesn't leave CC in a usable state. */
+ CC_STATUS_INIT;
+ break;
+ }
+}
+\f
+/* Given that X occurs in an address of the form (plus X constant),
+ return the part of X that is expected to be a register. There are
+ four kinds of addressing mode to recognize:
+
+ @(dd,Rn)
+ @(dd,RnL.b)
+ @(dd,Rn.w)
+ @(dd,ERn.l)
+
+ If SIZE is nonnull, and the address is one of the last three forms,
+ set *SIZE to the index multiplication factor. Set it to 0 for
+ plain @(dd,Rn) addresses.
+
+ MODE is the mode of the value being accessed. It can be VOIDmode
+ if the address is known to be valid, but its mode is unknown. */
+
+rtx
+h8300_get_index (rtx x, enum machine_mode mode, int *size)
+{
+ int dummy, factor;
+
+ if (size == 0)
+ size = &dummy;
+
+ factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
+ if (TARGET_H8300SX
+ && factor <= 4
+ && (mode == VOIDmode
+ || GET_MODE_CLASS (mode) == MODE_INT
+ || GET_MODE_CLASS (mode) == MODE_FLOAT))
+ {
+ if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
+ {
+ /* When accessing byte-sized values, the index can be
+ a zero-extended QImode or HImode register. */
+ *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
+ return XEXP (x, 0);
+ }
+ else
+ {
+ /* We're looking for addresses of the form:
+
+ (mult X I)
+ or (mult (zero_extend X) I)
+
+ where I is the size of the operand being accessed.
+ The canonical form of the second expression is:
+
+ (and (mult (subreg X) I) J)
+
+ where J == GET_MODE_MASK (GET_MODE (X)) * I. */
+ rtx index;
+
+ if (GET_CODE (x) == AND
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && (factor == 0
+ || INTVAL (XEXP (x, 1)) == 0xff * factor
+ || INTVAL (XEXP (x, 1)) == 0xffff * factor))
+ {
+ index = XEXP (x, 0);
+ *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
+ }
+ else
+ {
+ index = x;
+ *size = 4;
+ }
+
+ if (GET_CODE (index) == MULT
+ && GET_CODE (XEXP (index, 1)) == CONST_INT
+ && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
+ return XEXP (index, 0);
+ }
+ }
+ *size = 0;
+ return x;
+}
+\f
+static const h8300_length_table addb_length_table =
+{
+ /* #xx Rs @aa @Rs @xx */
+ { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
+ { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
+ { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
+ { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
+};
+
+static const h8300_length_table addw_length_table =
+{
+ /* #xx Rs @aa @Rs @xx */
+ { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
+ { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
+ { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
+ { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
+};
+
+static const h8300_length_table addl_length_table =
+{
+ /* #xx Rs @aa @Rs @xx */
+ { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
+ { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
+ { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
+ { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
+};
+
+#define logicb_length_table addb_length_table
+#define logicw_length_table addw_length_table
+
+static const h8300_length_table logicl_length_table =
+{
+ /* #xx Rs @aa @Rs @xx */
+ { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
+ { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
+ { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
+ { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
+};
+
+static const h8300_length_table movb_length_table =
+{
+ /* #xx Rs @aa @Rs @xx */
+ { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
+ { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
+ { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
+ { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
+};
+
+#define movw_length_table movb_length_table
+
+static const h8300_length_table movl_length_table =
+{
+ /* #xx Rs @aa @Rs @xx */
+ { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
+ { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
+ { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
+ { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
+};
+
+/* Return the size of the given address or displacement constant. */
+
+static unsigned int
+h8300_constant_length (rtx constant)
+{
+ /* Check for (@d:16,Reg). */
+ if (GET_CODE (constant) == CONST_INT
+ && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
+ return 2;
+
+ /* Check for (@d:16,Reg) in cases where the displacement is
+ an absolute address. */
+ if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
+ return 2;
+
+ return 4;
+}
+
+/* Return the size of a displacement field in address ADDR, which should
+ have the form (plus X constant). SIZE is the number of bytes being
+ accessed. */
+
+static unsigned int
+h8300_displacement_length (rtx addr, int size)
+{
+ rtx offset;
+
+ offset = XEXP (addr, 1);
+
+ /* Check for @(d:2,Reg). */
+ if (register_operand (XEXP (addr, 0), VOIDmode)
+ && GET_CODE (offset) == CONST_INT
+ && (INTVAL (offset) == size
+ || INTVAL (offset) == size * 2
+ || INTVAL (offset) == size * 3))
+ return 0;
+
+ return h8300_constant_length (offset);
+}
+
+/* Store the class of operand OP in *OPCLASS and return the length of any
+ extra operand fields. SIZE is the number of bytes in OP. OPCLASS
+ can be null if only the length is needed. */
+
+static unsigned int
+h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
+{
+ enum h8300_operand_class dummy;
+
+ if (opclass == 0)
+ opclass = &dummy;
+
+ if (CONSTANT_P (op))
+ {
+ *opclass = H8OP_IMMEDIATE;
+
+ /* Byte-sized immediates are stored in the opcode fields. */
+ if (size == 1)
+ return 0;
+
+ /* If this is a 32-bit instruction, see whether the constant
+ will fit into a 16-bit immediate field. */
+ if (TARGET_H8300SX
+ && size == 4
+ && GET_CODE (op) == CONST_INT
+ && IN_RANGE (INTVAL (op), 0, 0xffff))
+ return 2;
+
+ return size;
+ }
+ else if (GET_CODE (op) == MEM)
+ {
+ op = XEXP (op, 0);
+ if (CONSTANT_P (op))
+ {
+ *opclass = H8OP_MEM_ABSOLUTE;
+ return h8300_constant_length (op);
+ }
+ else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
+ {
+ *opclass = H8OP_MEM_COMPLEX;
+ return h8300_displacement_length (op, size);
+ }
+ else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
+ {
+ *opclass = H8OP_MEM_COMPLEX;
+ return 0;
+ }
+ else if (register_operand (op, VOIDmode))
+ {
+ *opclass = H8OP_MEM_BASE;
+ return 0;
+ }
+ }
+ gcc_assert (register_operand (op, VOIDmode));
+ *opclass = H8OP_REGISTER;
+ return 0;
+}
- case CC_COMPARE:
- /* The insn is a compare instruction. */
- CC_STATUS_INIT;
- cc_status.value1 = SET_SRC (body);
- break;
+/* Return the length of the instruction described by TABLE given that
+ its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
+ and OP2 must be an h8300_src_operand. */
- case CC_CLOBBER:
- /* Insn doesn't leave CC in a usable state. */
- CC_STATUS_INIT;
- break;
+static unsigned int
+h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
+{
+ enum h8300_operand_class op1_class, op2_class;
+ unsigned int size, immediate_length;
+
+ size = GET_MODE_SIZE (GET_MODE (op1));
+ immediate_length = (h8300_classify_operand (op1, size, &op1_class)
+ + h8300_classify_operand (op2, size, &op2_class));
+ return immediate_length + (*table)[op1_class - 1][op2_class];
+}
+
+/* Return the length of a unary instruction such as neg or not given that
+ its operand is OP. */
+
+unsigned int
+h8300_unary_length (rtx op)
+{
+ enum h8300_operand_class opclass;
+ unsigned int size, operand_length;
+
+ size = GET_MODE_SIZE (GET_MODE (op));
+ operand_length = h8300_classify_operand (op, size, &opclass);
+ switch (opclass)
+ {
+ case H8OP_REGISTER:
+ return 2;
+
+ case H8OP_MEM_BASE:
+ return (size == 4 ? 6 : 4);
+
+ case H8OP_MEM_ABSOLUTE:
+ return operand_length + (size == 4 ? 6 : 4);
+
+ case H8OP_MEM_COMPLEX:
+ return operand_length + 6;
+
+ default:
+ gcc_unreachable ();
}
}
-/* Return nonzero if X is a stack pointer. */
+/* Likewise short immediate instructions such as add.w #xx:3,OP. */
-int
-stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+static unsigned int
+h8300_short_immediate_length (rtx op)
{
- return x == stack_pointer_rtx;
+ enum h8300_operand_class opclass;
+ unsigned int size, operand_length;
+
+ size = GET_MODE_SIZE (GET_MODE (op));
+ operand_length = h8300_classify_operand (op, size, &opclass);
+
+ switch (opclass)
+ {
+ case H8OP_REGISTER:
+ return 2;
+
+ case H8OP_MEM_BASE:
+ case H8OP_MEM_ABSOLUTE:
+ case H8OP_MEM_COMPLEX:
+ return 4 + operand_length;
+
+ default:
+ gcc_unreachable ();
+ }
}
-/* Return nonzero if X is a constant whose absolute value is greater
- than 2. */
+/* Likewise bitfield load and store instructions. */
-int
-const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+static unsigned int
+h8300_bitfield_length (rtx op, rtx op2)
{
- return (GET_CODE (x) == CONST_INT
- && abs (INTVAL (x)) > 2);
+ enum h8300_operand_class opclass;
+ unsigned int size, operand_length;
+
+ if (GET_CODE (op) == REG)
+ op = op2;
+ gcc_assert (GET_CODE (op) != REG);
+
+ size = GET_MODE_SIZE (GET_MODE (op));
+ operand_length = h8300_classify_operand (op, size, &opclass);
+
+ switch (opclass)
+ {
+ case H8OP_MEM_BASE:
+ case H8OP_MEM_ABSOLUTE:
+ case H8OP_MEM_COMPLEX:
+ return 4 + operand_length;
+
+ default:
+ gcc_unreachable ();
+ }
}
-/* Return nonzero if X is a constant whose absolute value is no
- smaller than 8. */
+/* Calculate the length of general binary instruction INSN using TABLE. */
-int
-const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+static unsigned int
+h8300_binary_length (rtx insn, const h8300_length_table *table)
{
- return (GET_CODE (x) == CONST_INT
- && abs (INTVAL (x)) >= 8);
+ rtx set;
+
+ set = single_set (insn);
+ gcc_assert (set);
+
+ if (BINARY_P (SET_SRC (set)))
+ return h8300_length_from_table (XEXP (SET_SRC (set), 0),
+ XEXP (SET_SRC (set), 1), table);
+ else
+ {
+ gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
+ return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
+ XEXP (XEXP (SET_SRC (set), 1), 1),
+ table);
+ }
}
-/* Return nonzero if X is a constant expressible in QImode. */
+/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
+ memory reference and either (1) it has the form @(d:16,Rn) or
+ (2) its address has the code given by INC_CODE. */
-int
-const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+static bool
+h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
{
- return (GET_CODE (x) == CONST_INT
- && (INTVAL (x) & 0xff) == INTVAL (x));
+ rtx addr;
+ unsigned int size;
+
+ if (GET_CODE (op) != MEM)
+ return false;
+
+ addr = XEXP (op, 0);
+ size = GET_MODE_SIZE (GET_MODE (op));
+ if (size != 1 && size != 2)
+ return false;
+
+ return (GET_CODE (addr) == inc_code
+ || (GET_CODE (addr) == PLUS
+ && GET_CODE (XEXP (addr, 0)) == REG
+ && h8300_displacement_length (addr, size) == 2));
}
-/* Return nonzero if X is a constant expressible in HImode. */
+/* Calculate the length of move instruction INSN using the given length
+ table. Although the tables are correct for most cases, there is some
+ irregularity in the length of mov.b and mov.w. The following forms:
-int
-const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+ mov @ERs+, Rd
+ mov @(d:16,ERs), Rd
+ mov Rs, @-ERd
+ mov Rs, @(d:16,ERd)
+
+ are two bytes shorter than most other "mov Rs, @complex" or
+ "mov @complex,Rd" combinations. */
+
+static unsigned int
+h8300_move_length (rtx *operands, const h8300_length_table *table)
{
- return (GET_CODE (x) == CONST_INT
- && (INTVAL (x) & 0xffff) == INTVAL (x));
+ unsigned int size;
+
+ size = h8300_length_from_table (operands[0], operands[1], table);
+ if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
+ size -= 2;
+ if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
+ size -= 2;
+ return size;
}
-/* Return nonzero if X is a constant suitable for inc/dec. */
+/* Return the length of a mova instruction with the given operands.
+ DEST is the register destination, SRC is the source address and
+ OFFSET is the 16-bit or 32-bit displacement. */
-int
-incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+static unsigned int
+h8300_mova_length (rtx dest, rtx src, rtx offset)
{
- return (GET_CODE (x) == CONST_INT
- && (CONST_OK_FOR_M (INTVAL (x))
- || CONST_OK_FOR_O (INTVAL (x))));
+ unsigned int size;
+
+ size = (2
+ + h8300_constant_length (offset)
+ + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
+ if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
+ size += 2;
+ return size;
}
-/* Return nonzero if X is either EQ or NE. */
+/* Compute the length of INSN based on its length_table attribute.
+ OPERANDS is the array of its operands. */
-int
-eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+unsigned int
+h8300_insn_length_from_table (rtx insn, rtx * operands)
{
- enum rtx_code code = GET_CODE (x);
+ switch (get_attr_length_table (insn))
+ {
+ case LENGTH_TABLE_NONE:
+ gcc_unreachable ();
+
+ case LENGTH_TABLE_ADDB:
+ return h8300_binary_length (insn, &addb_length_table);
+
+ case LENGTH_TABLE_ADDW:
+ return h8300_binary_length (insn, &addw_length_table);
+
+ case LENGTH_TABLE_ADDL:
+ return h8300_binary_length (insn, &addl_length_table);
+
+ case LENGTH_TABLE_LOGICB:
+ return h8300_binary_length (insn, &logicb_length_table);
+
+ case LENGTH_TABLE_MOVB:
+ return h8300_move_length (operands, &movb_length_table);
+
+ case LENGTH_TABLE_MOVW:
+ return h8300_move_length (operands, &movw_length_table);
+
+ case LENGTH_TABLE_MOVL:
+ return h8300_move_length (operands, &movl_length_table);
+
+ case LENGTH_TABLE_MOVA:
+ return h8300_mova_length (operands[0], operands[1], operands[2]);
- return (code == EQ || code == NE);
+ case LENGTH_TABLE_MOVA_ZERO:
+ return h8300_mova_length (operands[0], operands[1], const0_rtx);
+
+ case LENGTH_TABLE_UNARY:
+ return h8300_unary_length (operands[0]);
+
+ case LENGTH_TABLE_MOV_IMM4:
+ return 2 + h8300_classify_operand (operands[0], 0, 0);
+
+ case LENGTH_TABLE_SHORT_IMMEDIATE:
+ return h8300_short_immediate_length (operands[0]);
+
+ case LENGTH_TABLE_BITFIELD:
+ return h8300_bitfield_length (operands[0], operands[1]);
+
+ case LENGTH_TABLE_BITBRANCH:
+ return h8300_bitfield_length (operands[1], operands[2]) - 2;
+
+ default:
+ gcc_unreachable ();
+ }
}
-/* Return nonzero if X is GT, LE, GTU, or LEU. */
+/* Return true if LHS and RHS are memory references that can be mapped
+ to the same h8sx assembly operand. LHS appears as the destination of
+ an instruction and RHS appears as a source.
-int
-gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+ Three cases are allowed:
+
+ - RHS is @+Rn or @-Rn, LHS is @Rn
+ - RHS is @Rn, LHS is @Rn+ or @Rn-
+ - RHS and LHS have the same address and neither has side effects. */
+
+bool
+h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
{
- enum rtx_code code = GET_CODE (x);
+ if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
+ {
+ rhs = XEXP (rhs, 0);
+ lhs = XEXP (lhs, 0);
+
+ if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
+ return rtx_equal_p (XEXP (rhs, 0), lhs);
- return (code == GT || code == LE || code == GTU || code == LEU);
+ if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
+ return rtx_equal_p (rhs, XEXP (lhs, 0));
+
+ if (rtx_equal_p (rhs, lhs))
+ return true;
+ }
+ return false;
}
-/* Return nonzero if X is either GTU or LEU. */
+/* Return true if OPERANDS[1] can be mapped to the same assembly
+ operand as OPERANDS[0]. */
-int
-gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+bool
+h8300_operands_match_p (rtx *operands)
{
- enum rtx_code code = GET_CODE (x);
+ if (register_operand (operands[0], VOIDmode)
+ && register_operand (operands[1], VOIDmode))
+ return true;
- return (code == GTU || code == LEU);
+ if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
+ return true;
+
+ return false;
}
+\f
+/* Try using movmd to move LENGTH bytes from memory region SRC to memory
+ region DEST. The two regions do not overlap and have the common
+ alignment given by ALIGNMENT. Return true on success.
-/* Return nonzero if X is either IOR or XOR. */
+ Using movmd for variable-length moves seems to involve some
+ complex trade-offs. For instance:
-int
-iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+ - Preparing for a movmd instruction is similar to preparing
+ for a memcpy. The main difference is that the arguments
+ are moved into er4, er5 and er6 rather than er0, er1 and er2.
+
+ - Since movmd clobbers the frame pointer, we need to save
+ and restore it somehow when frame_pointer_needed. This can
+ sometimes make movmd sequences longer than calls to memcpy().
+
+ - The counter register is 16 bits, so the instruction is only
+ suitable for variable-length moves when sizeof (size_t) == 2.
+ That's only true in normal mode.
+
+ - We will often lack static alignment information. Falling back
+ on movmd.b would likely be slower than calling memcpy(), at least
+ for big moves.
+
+ This function therefore only uses movmd when the length is a
+ known constant, and only then if -fomit-frame-pointer is in
+ effect or if we're not optimizing for size.
+
+ At the moment the function uses movmd for all in-range constants,
+ but it might be better to fall back on memcpy() for large moves
+ if ALIGNMENT == 1. */
+
+bool
+h8sx_emit_movmd (rtx dest, rtx src, rtx length,
+ HOST_WIDE_INT alignment)
{
- enum rtx_code code = GET_CODE (x);
+ if (!flag_omit_frame_pointer && optimize_size)
+ return false;
+
+ if (GET_CODE (length) == CONST_INT)
+ {
+ rtx dest_reg, src_reg, first_dest, first_src;
+ HOST_WIDE_INT n;
+ int factor;
+
+ /* Use movmd.l if the alignment allows it, otherwise fall back
+ on movmd.b. */
+ factor = (alignment >= 2 ? 4 : 1);
+
+ /* Make sure the length is within range. We can handle counter
+ values up to 65536, although HImode truncation will make
+ the count appear negative in rtl dumps. */
+ n = INTVAL (length);
+ if (n <= 0 || n / factor > 65536)
+ return false;
+
+ /* Create temporary registers for the source and destination
+ pointers. Initialize them to the start of each region. */
+ dest_reg = copy_addr_to_reg (XEXP (dest, 0));
+ src_reg = copy_addr_to_reg (XEXP (src, 0));
+
+ /* Create references to the movmd source and destination blocks. */
+ first_dest = replace_equiv_address (dest, dest_reg);
+ first_src = replace_equiv_address (src, src_reg);
+
+ set_mem_size (first_dest, GEN_INT (n & -factor));
+ set_mem_size (first_src, GEN_INT (n & -factor));
- return (code == IOR || code == XOR);
+ length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
+ emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
+
+ if ((n & -factor) != n)
+ {
+ /* Move SRC and DEST past the region we just copied.
+ This is done to update the memory attributes. */
+ dest = adjust_address (dest, BLKmode, n & -factor);
+ src = adjust_address (src, BLKmode, n & -factor);
+
+ /* Replace the addresses with the source and destination
+ registers, which movmd has left with the right values. */
+ dest = replace_equiv_address (dest, dest_reg);
+ src = replace_equiv_address (src, src_reg);
+
+ /* Mop up the left-over bytes. */
+ if (n & 2)
+ emit_move_insn (adjust_address (dest, HImode, 0),
+ adjust_address (src, HImode, 0));
+ if (n & 1)
+ emit_move_insn (adjust_address (dest, QImode, n & 2),
+ adjust_address (src, QImode, n & 2));
+ }
+ return true;
+ }
+ return false;
}
-/* Recognize valid operators for bit instructions. */
+/* Move ADDR into er6 after pushing its old value onto the stack. */
-int
-bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+void
+h8300_swap_into_er6 (rtx addr)
{
- enum rtx_code code = GET_CODE (x);
+ push (HARD_FRAME_POINTER_REGNUM);
+ emit_move_insn (hard_frame_pointer_rtx, addr);
+ if (REGNO (addr) == SP_REG)
+ emit_move_insn (hard_frame_pointer_rtx,
+ plus_constant (hard_frame_pointer_rtx,
+ GET_MODE_SIZE (word_mode)));
+}
- return (code == XOR
- || code == AND
- || code == IOR);
+/* Move the current value of er6 into ADDR and pop its old value
+ from the stack. */
+
+void
+h8300_swap_out_of_er6 (rtx addr)
+{
+ if (REGNO (addr) != SP_REG)
+ emit_move_insn (addr, hard_frame_pointer_rtx);
+ pop (HARD_FRAME_POINTER_REGNUM);
}
\f
/* Return the length of mov instruction. */
if (REG_P (src))
return 4;
+ if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
+ return 4;
+
return 8;
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* Adjust the length based on the addressing mode used.
return base_length - 2;
else
/* In SImode and SFmode, we use two mov.w instructions, so
- double the adustment. */
+ double the adjustment. */
return base_length - 4;
}
if (val == (val & 0x00ff) || val == (val & 0xff00))
return 4;
-
+
switch (val & 0xffffffff)
{
case 0xffffffff:
if (REG_P (src))
return 2;
- if (src == const0_rtx)
+ if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
return 2;
+
return 6;
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* Adjust the length based on the addressing mode used.
}
}
\f
+/* Output an addition insn. */
+
const char *
output_plussi (rtx *operands)
{
enum machine_mode mode = GET_MODE (operands[0]);
- if (mode != SImode)
- abort ();
+ gcc_assert (mode == SImode);
if (TARGET_H8300)
{
}
else
{
- if (GET_CODE (operands[2]) == REG)
- return "add.l\t%S2,%S0";
-
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (GET_CODE (operands[2]) == CONST_INT
+ && register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
+ if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
+ return "add.l\t%S2,%S0";
+ if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
+ return "sub.l\t%G2,%S0";
+
/* See if we can finish with 2 bytes. */
switch ((unsigned int) intval & 0xffffffff)
}
}
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ return "sub.l\t%S2,%S0";
+ }
return "add.l\t%S2,%S0";
}
}
+/* ??? It would be much easier to add the h8sx stuff if a single function
+ classified the addition as either inc/dec, adds/subs, add.w or add.l. */
+/* Compute the length of an addition insn. */
+
unsigned int
compute_plussi_length (rtx *operands)
{
enum machine_mode mode = GET_MODE (operands[0]);
- if (mode != SImode)
- abort ();
+ gcc_assert (mode == SImode);
if (TARGET_H8300)
{
}
else
{
- if (GET_CODE (operands[2]) == REG)
- return 2;
-
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (GET_CODE (operands[2]) == CONST_INT
+ && register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
+ if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
+ return 2;
+ if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
+ return 2;
+
/* See if we can finish with 2 bytes. */
switch ((unsigned int) intval & 0xffffffff)
return 4;
}
+ if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+ return h8300_length_from_table (operands[0],
+ GEN_INT (-INTVAL (operands[2])),
+ &addl_length_table);
+ else
+ return h8300_length_from_table (operands[0], operands[2],
+ &addl_length_table);
return 6;
}
}
+/* Compute which flag bits are valid after an addition insn. */
+
int
compute_plussi_cc (rtx *operands)
{
enum machine_mode mode = GET_MODE (operands[0]);
- if (mode != SImode)
- abort ();
+ gcc_assert (mode == SImode);
if (TARGET_H8300)
{
}
else
{
- if (GET_CODE (operands[2]) == REG)
- return CC_SET_ZN;
-
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (GET_CODE (operands[2]) == CONST_INT
+ && register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
+ if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
+ return CC_SET_ZN;
+ if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
+ return CC_SET_ZN;
+
/* See if we can finish with 2 bytes. */
switch ((unsigned int) intval & 0xffffffff)
}
}
\f
+/* Output a logical insn. */
+
const char *
output_logical_op (enum machine_mode mode, rtx *operands)
{
/* Pretend that every byte is affected if both operands are registers. */
const unsigned HOST_WIDE_INT intval =
(unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+ /* Always use the full instruction if the
+ first operand is in memory. It is better
+ to use define_splits to generate the shorter
+ sequence where valid. */
+ && register_operand (operands[1], VOIDmode)
? INTVAL (operands[2]) : 0x55555555);
/* The determinant of the algorithm. If we perform an AND, 0
affects a bit. Otherwise, 1 affects a bit. */
opname = "xor";
break;
default:
- abort ();
+ gcc_unreachable ();
}
switch (mode)
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
return "";
}
+/* Compute the length of a logical insn. */
+
unsigned int
compute_logical_op_length (enum machine_mode mode, rtx *operands)
{
/* Pretend that every byte is affected if both operands are registers. */
const unsigned HOST_WIDE_INT intval =
(unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+ /* Always use the full instruction if the
+ first operand is in memory. It is better
+ to use define_splits to generate the shorter
+ sequence where valid. */
+ && register_operand (operands[1], VOIDmode)
? INTVAL (operands[2]) : 0x55555555);
/* The determinant of the algorithm. If we perform an AND, 0
affects a bit. Otherwise, 1 affects a bit. */
&& b0 != 0
&& b1 != 0)
{
- if (REG_P (operands[2]))
- length += 2;
- else
- length += 4;
+ length = h8300_length_from_table (operands[1], operands[2],
+ &logicw_length_table);
}
else
{
&& !(code == IOR && w1 == 0xffff
&& (w0 & 0x8000) != 0 && lower_half_easy_p))
{
- if (REG_P (operands[2]))
- length += 4;
- else
- length += 6;
+ length = h8300_length_from_table (operands[1], operands[2],
+ &logicl_length_table);
}
else
{
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
return length;
}
+/* Compute which flag bits are valid after a logical insn. */
+
int
compute_logical_op_cc (enum machine_mode mode, rtx *operands)
{
/* Pretend that every byte is affected if both operands are registers. */
const unsigned HOST_WIDE_INT intval =
(unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+ /* Always use the full instruction if the
+ first operand is in memory. It is better
+ to use define_splits to generate the shorter
+ sequence where valid. */
+ && register_operand (operands[1], VOIDmode)
? INTVAL (operands[2]) : 0x55555555);
/* The determinant of the algorithm. If we perform an AND, 0
affects a bit. Otherwise, 1 affects a bit. */
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
return cc;
}
\f
+/* Expand a conditional branch. */
+
+void
+h8300_expand_branch (rtx operands[])
+{
+ enum rtx_code code = GET_CODE (operands[0]);
+ rtx op0 = operands[1];
+ rtx op1 = operands[2];
+ rtx label = operands[3];
+ rtx tmp;
+
+ tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
+ emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
+
+ tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
+ tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
+ gen_rtx_LABEL_REF (VOIDmode, label),
+ pc_rtx);
+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
+}
+
+
+/* Expand a conditional store. */
+
+void
+h8300_expand_store (rtx operands[])
+{
+ rtx dest = operands[0];
+ enum rtx_code code = GET_CODE (operands[1]);
+ rtx op0 = operands[2];
+ rtx op1 = operands[3];
+ rtx tmp;
+
+ tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
+ emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
+
+ tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
+}
+\f
/* Shifts.
We devote a fair bit of code to getting efficient shifts since we
For the details of the shift algorithms for various shift counts,
refer to shift_alg_[qhs]i. */
-int
-nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+/* Classify a shift with the given mode and code. OP is the shift amount. */
+
+enum h8sx_shift_type
+h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
{
- switch (GET_CODE (x))
+ if (!TARGET_H8300SX)
+ return H8SX_SHIFT_NONE;
+
+ switch (code)
{
- case ASHIFTRT:
+ case ASHIFT:
case LSHIFTRT:
+ /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
+ if (GET_CODE (op) != CONST_INT)
+ return H8SX_SHIFT_BINARY;
+
+ /* Reject out-of-range shift amounts. */
+ if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
+ return H8SX_SHIFT_NONE;
+
+ /* Power-of-2 shifts are effectively unary operations. */
+ if (exact_log2 (INTVAL (op)) >= 0)
+ return H8SX_SHIFT_UNARY;
+
+ return H8SX_SHIFT_BINARY;
+
+ case ASHIFTRT:
+ if (op == const1_rtx || op == const2_rtx)
+ return H8SX_SHIFT_UNARY;
+ return H8SX_SHIFT_NONE;
+
+ case ROTATE:
+ if (GET_CODE (op) == CONST_INT
+ && (INTVAL (op) == 1
+ || INTVAL (op) == 2
+ || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
+ || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
+ return H8SX_SHIFT_UNARY;
+ return H8SX_SHIFT_NONE;
+
+ default:
+ return H8SX_SHIFT_NONE;
+ }
+}
+
+/* Return the asm template for a single h8sx shift instruction.
+ OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
+ is the source and OPERANDS[3] is the shift. SUFFIX is the
+ size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
+ prefix for the destination operand. */
+
+const char *
+output_h8sx_shift (rtx *operands, int suffix, int optype)
+{
+ static char buffer[16];
+ const char *stem;
+
+ switch (GET_CODE (operands[3]))
+ {
case ASHIFT:
- return 1;
+ stem = "shll";
+ break;
+
+ case ASHIFTRT:
+ stem = "shar";
+ break;
+
+ case LSHIFTRT:
+ stem = "shlr";
+ break;
+
+ case ROTATE:
+ stem = "rotl";
+ if (INTVAL (operands[2]) > 2)
+ {
+ /* This is really a right rotate. */
+ operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
+ - INTVAL (operands[2]));
+ stem = "rotr";
+ }
+ break;
default:
- return 0;
+ gcc_unreachable ();
}
+ if (operands[2] == const1_rtx)
+ sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
+ else
+ sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
+ return buffer;
}
/* Emit code to do shifts. */
-void
+bool
expand_a_shift (enum machine_mode mode, int code, rtx operands[])
{
- emit_move_insn (operands[0], operands[1]);
+ switch (h8sx_classify_shift (mode, code, operands[2]))
+ {
+ case H8SX_SHIFT_BINARY:
+ operands[1] = force_reg (mode, operands[1]);
+ return false;
+
+ case H8SX_SHIFT_UNARY:
+ return false;
+
+ case H8SX_SHIFT_NONE:
+ break;
+ }
+
+ emit_move_insn (copy_rtx (operands[0]), operands[1]);
/* Need a loop to get all the bits we want - we generate the
code at emit time, but need to allocate a scratch reg now. */
emit_insn (gen_rtx_PARALLEL
(VOIDmode,
gen_rtvec (2,
- gen_rtx_SET (VOIDmode, operands[0],
- gen_rtx (code, mode, operands[0],
- operands[2])),
+ gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
+ gen_rtx_fmt_ee (code, mode,
+ copy_rtx (operands[0]), operands[2])),
gen_rtx_CLOBBER (VOIDmode,
gen_rtx_SCRATCH (QImode)))));
+ return true;
}
/* Symbols of the various modes which can be used as indices. */
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
case QIshift:
/* For ASHIFTRT by 7 bits, the sign bit is simply replicated
through the entire value. */
- if (shift_type == SHIFT_ASHIFTRT && count == 7)
- {
- info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
- goto end;
- }
- abort ();
+ gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
+ info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
+ goto end;
case HIshift:
if (count == 7)
info->cc_special = CC_SET_ZNV;
}
else /* TARGET_H8300S */
- abort ();
+ gcc_unreachable ();
goto end;
}
}
goto end;
}
}
- abort ();
+ gcc_unreachable ();
case SIshift:
if (TARGET_H8300 && 8 <= count && count <= 9)
switch (shift_type)
{
case SHIFT_ASHIFT:
- abort ();
+ gcc_unreachable ();
case SHIFT_LSHIFTRT:
info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
goto end;
info->cc_special = CC_SET_ZNV;
goto end;
case SHIFT_ASHIFTRT:
- abort ();
+ gcc_unreachable ();
}
}
else if ((TARGET_H8300 && 16 <= count && count <= 20)
info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
goto end;
case SHIFT_ASHIFTRT:
- abort ();
+ gcc_unreachable ();
}
}
else if (!TARGET_H8300 && count == 29)
}
goto end;
case SHIFT_ASHIFTRT:
- abort ();
+ gcc_unreachable ();
}
}
else if (!TARGET_H8300 && count == 30)
info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
goto end;
case SHIFT_ASHIFTRT:
- abort ();
+ gcc_unreachable ();
}
}
else if (count == 31)
}
}
}
- abort ();
+ gcc_unreachable ();
default:
- abort ();
+ gcc_unreachable ();
}
end:
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* On H8/300H, count == 8 uses a scratch register. */
|| (TARGET_H8300H && mode == SImode && count == 8));
}
-/* Emit the assembler code for doing shifts. */
+/* Output the assembler code for doing shifts. */
const char *
output_a_shift (rtx *operands)
enum shift_type shift_type;
enum shift_mode shift_mode;
struct shift_info info;
+ int n;
loopend_lab++;
shift_mode = SIshift;
break;
default:
- abort ();
+ gcc_unreachable ();
}
switch (code)
shift_type = SHIFT_ASHIFT;
break;
default:
- abort ();
+ gcc_unreachable ();
}
- if (GET_CODE (operands[2]) != CONST_INT)
- {
- /* This case must be taken care of by one of the two splitters
- that convert a variable shift into a loop. */
- abort ();
- }
- else
+ /* This case must be taken care of by one of the two splitters
+ that convert a variable shift into a loop. */
+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+
+ n = INTVAL (operands[2]);
+
+ /* If the count is negative, make it 0. */
+ if (n < 0)
+ n = 0;
+ /* If the count is too big, truncate it.
+ ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
+ do the intuitive thing. */
+ else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
+ n = GET_MODE_BITSIZE (mode);
+
+ get_shift_alg (shift_type, shift_mode, n, &info);
+
+ switch (info.alg)
{
- int n = INTVAL (operands[2]);
-
- /* If the count is negative, make it 0. */
- if (n < 0)
- n = 0;
- /* If the count is too big, truncate it.
- ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
- do the intuitive thing. */
- else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
- n = GET_MODE_BITSIZE (mode);
-
- get_shift_alg (shift_type, shift_mode, n, &info);
-
- switch (info.alg)
- {
- case SHIFT_SPECIAL:
- output_asm_insn (info.special, operands);
- /* Fall through. */
-
- case SHIFT_INLINE:
- n = info.remainder;
-
- /* Emit two bit shifts first. */
- if (info.shift2 != NULL)
- {
- for (; n > 1; n -= 2)
- output_asm_insn (info.shift2, operands);
- }
-
- /* Now emit one bit shifts for any residual. */
- for (; n > 0; n--)
- output_asm_insn (info.shift1, operands);
- return "";
+ case SHIFT_SPECIAL:
+ output_asm_insn (info.special, operands);
+ /* Fall through. */
- case SHIFT_ROT_AND:
- {
- int m = GET_MODE_BITSIZE (mode) - n;
- const int mask = (shift_type == SHIFT_ASHIFT
- ? ((1 << m) - 1) << n
- : (1 << m) - 1);
- char insn_buf[200];
+ case SHIFT_INLINE:
+ n = info.remainder;
- /* Not all possibilities of rotate are supported. They shouldn't
- be generated, but let's watch for 'em. */
- if (info.shift1 == 0)
- abort ();
+ /* Emit two bit shifts first. */
+ if (info.shift2 != NULL)
+ {
+ for (; n > 1; n -= 2)
+ output_asm_insn (info.shift2, operands);
+ }
- /* Emit two bit rotates first. */
- if (info.shift2 != NULL)
- {
- for (; m > 1; m -= 2)
- output_asm_insn (info.shift2, operands);
- }
+ /* Now emit one bit shifts for any residual. */
+ for (; n > 0; n--)
+ output_asm_insn (info.shift1, operands);
+ return "";
+
+ case SHIFT_ROT_AND:
+ {
+ int m = GET_MODE_BITSIZE (mode) - n;
+ const int mask = (shift_type == SHIFT_ASHIFT
+ ? ((1 << m) - 1) << n
+ : (1 << m) - 1);
+ char insn_buf[200];
+
+ /* Not all possibilities of rotate are supported. They shouldn't
+ be generated, but let's watch for 'em. */
+ gcc_assert (info.shift1);
+
+ /* Emit two bit rotates first. */
+ if (info.shift2 != NULL)
+ {
+ for (; m > 1; m -= 2)
+ output_asm_insn (info.shift2, operands);
+ }
+
+ /* Now single bit rotates for any residual. */
+ for (; m > 0; m--)
+ output_asm_insn (info.shift1, operands);
+
+ /* Now mask off the high bits. */
+ switch (mode)
+ {
+ case QImode:
+ sprintf (insn_buf, "and\t#%d,%%X0", mask);
+ break;
- /* Now single bit rotates for any residual. */
- for (; m > 0; m--)
- output_asm_insn (info.shift1, operands);
+ case HImode:
+ gcc_assert (TARGET_H8300H || TARGET_H8300S);
+ sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
+ break;
- /* Now mask off the high bits. */
- if (mode == QImode)
- sprintf (insn_buf, "and\t#%d,%%X0", mask);
- else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
- sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
- else
- abort ();
-
- output_asm_insn (insn_buf, operands);
- return "";
+ default:
+ gcc_unreachable ();
}
- case SHIFT_LOOP:
- /* A loop to shift by a "large" constant value.
- If we have shift-by-2 insns, use them. */
- if (info.shift2 != NULL)
- {
- fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
- names_big[REGNO (operands[4])]);
- fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
- output_asm_insn (info.shift2, operands);
- output_asm_insn ("add #0xff,%X4", operands);
- fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
- if (n % 2)
- output_asm_insn (info.shift1, operands);
- }
- else
- {
- fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
- names_big[REGNO (operands[4])]);
- fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
- output_asm_insn (info.shift1, operands);
- output_asm_insn ("add #0xff,%X4", operands);
- fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
- }
- return "";
+ output_asm_insn (insn_buf, operands);
+ return "";
+ }
- default:
- abort ();
+ case SHIFT_LOOP:
+ /* A loop to shift by a "large" constant value.
+ If we have shift-by-2 insns, use them. */
+ if (info.shift2 != NULL)
+ {
+ fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
+ names_big[REGNO (operands[4])]);
+ fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
+ output_asm_insn (info.shift2, operands);
+ output_asm_insn ("add #0xff,%X4", operands);
+ fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
+ if (n % 2)
+ output_asm_insn (info.shift1, operands);
+ }
+ else
+ {
+ fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
+ names_big[REGNO (operands[4])]);
+ fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
+ output_asm_insn (info.shift1, operands);
+ output_asm_insn ("add #0xff,%X4", operands);
+ fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
}
+ return "";
+
+ default:
+ gcc_unreachable ();
}
}
+/* Count the number of assembly instructions in a string TEMPL. */
+
static unsigned int
-h8300_asm_insn_count (const char *template)
+h8300_asm_insn_count (const char *templ)
{
unsigned int count = 1;
- for (; *template; template++)
- if (*template == '\n')
+ for (; *templ; templ++)
+ if (*templ == '\n')
count++;
return count;
}
+/* Compute the length of a shift insn. */
+
unsigned int
compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
{
shift_mode = SIshift;
break;
default:
- abort ();
+ gcc_unreachable ();
}
switch (code)
shift_type = SHIFT_ASHIFT;
break;
default:
- abort ();
+ gcc_unreachable ();
}
if (GET_CODE (operands[2]) != CONST_INT)
/* Not all possibilities of rotate are supported. They shouldn't
be generated, but let's watch for 'em. */
- if (info.shift1 == 0)
- abort ();
+ gcc_assert (info.shift1);
if (info.shift2 != NULL)
{
wlength += 2;
break;
case SImode:
- if (TARGET_H8300)
- abort ();
+ gcc_assert (!TARGET_H8300);
wlength += 3;
break;
default:
- abort ();
+ gcc_unreachable ();
}
return 2 * wlength;
}
return 2 * wlength;
default:
- abort ();
+ gcc_unreachable ();
}
}
}
+/* Compute which flag bits are valid after a shift insn. */
+
int
compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
{
enum shift_type shift_type;
enum shift_mode shift_mode;
struct shift_info info;
-
+ int n;
+
switch (mode)
{
case QImode:
shift_mode = SIshift;
break;
default:
- abort ();
+ gcc_unreachable ();
}
switch (code)
shift_type = SHIFT_ASHIFT;
break;
default:
- abort ();
+ gcc_unreachable ();
}
- if (GET_CODE (operands[2]) != CONST_INT)
- {
- /* This case must be taken care of by one of the two splitters
- that convert a variable shift into a loop. */
- abort ();
- }
- else
+ /* This case must be taken care of by one of the two splitters
+ that convert a variable shift into a loop. */
+ gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+
+ n = INTVAL (operands[2]);
+
+ /* If the count is negative, make it 0. */
+ if (n < 0)
+ n = 0;
+ /* If the count is too big, truncate it.
+ ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
+ do the intuitive thing. */
+ else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
+ n = GET_MODE_BITSIZE (mode);
+
+ get_shift_alg (shift_type, shift_mode, n, &info);
+
+ switch (info.alg)
{
- int n = INTVAL (operands[2]);
-
- /* If the count is negative, make it 0. */
- if (n < 0)
- n = 0;
- /* If the count is too big, truncate it.
- ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
- do the intuitive thing. */
- else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
- n = GET_MODE_BITSIZE (mode);
+ case SHIFT_SPECIAL:
+ if (info.remainder == 0)
+ return info.cc_special;
- get_shift_alg (shift_type, shift_mode, n, &info);
+ /* Fall through. */
- switch (info.alg)
+ case SHIFT_INLINE:
+ return info.cc_inline;
+
+ case SHIFT_ROT_AND:
+ /* This case always ends with an and instruction. */
+ return CC_SET_ZNV;
+
+ case SHIFT_LOOP:
+ /* A loop to shift by a "large" constant value.
+ If we have shift-by-2 insns, use them. */
+ if (info.shift2 != NULL)
{
- case SHIFT_SPECIAL:
- if (info.remainder == 0)
- return info.cc_special;
-
- /* Fall through. */
-
- case SHIFT_INLINE:
- return info.cc_inline;
-
- case SHIFT_ROT_AND:
- /* This case always ends with an and instruction. */
- return CC_SET_ZNV;
-
- case SHIFT_LOOP:
- /* A loop to shift by a "large" constant value.
- If we have shift-by-2 insns, use them. */
- if (info.shift2 != NULL)
- {
- if (n % 2)
- return info.cc_inline;
- }
- return CC_CLOBBER;
-
- default:
- abort ();
+ if (n % 2)
+ return info.cc_inline;
}
+ return CC_CLOBBER;
+
+ default:
+ gcc_unreachable ();
}
}
\f
output_a_rotate () at the insn emit time. */
int
-expand_a_rotate (enum rtx_code code, rtx operands[])
+expand_a_rotate (rtx operands[])
{
rtx dst = operands[0];
rtx src = operands[1];
rtx rotate_amount = operands[2];
enum machine_mode mode = GET_MODE (dst);
- rtx tmp;
+
+ if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
+ return false;
/* We rotate in place. */
emit_move_insn (dst, src);
/* If the rotate amount is less than or equal to 0,
we go out of the loop. */
- emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
+ emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
QImode, 0, end_label);
/* Initialize the loop counter. */
emit_label (start_label);
/* Rotate by one bit. */
- tmp = gen_rtx (code, mode, dst, GEN_INT (1));
- emit_insn (gen_rtx_SET (mode, dst, tmp));
+ switch (mode)
+ {
+ case QImode:
+ emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
+ break;
+ case HImode:
+ emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
+ break;
+ case SImode:
+ emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
+ break;
+ default:
+ gcc_unreachable ();
+ }
/* Decrement the counter by 1. */
- tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
- emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
+ emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
/* If the loop counter is nonzero, we go back to the beginning
of the loop. */
- emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
+ emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
start_label);
emit_label (end_label);
else
{
/* Rotate by AMOUNT bits. */
- tmp = gen_rtx (code, mode, dst, rotate_amount);
- emit_insn (gen_rtx_SET (mode, dst, tmp));
+ switch (mode)
+ {
+ case QImode:
+ emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
+ break;
+ case HImode:
+ emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
+ break;
+ case SImode:
+ emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
+ break;
+ default:
+ gcc_unreachable ();
+ }
}
return 1;
}
-/* Output rotate insns. */
+/* Output a rotate insn. */
const char *
output_a_rotate (enum rtx_code code, rtx *operands)
int amount;
enum machine_mode mode = GET_MODE (dst);
- if (GET_CODE (rotate_amount) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
switch (mode)
{
rotate_mode = SIshift;
break;
default:
- abort ();
+ gcc_unreachable ();
}
switch (code)
rotate_type = SHIFT_LSHIFTRT;
break;
default:
- abort ();
+ gcc_unreachable ();
}
amount = INTVAL (rotate_amount);
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* Adjust AMOUNT and flip the direction. */
(rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
}
- /* Emit rotate insns. */
+ /* Output rotate insns. */
for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
{
if (bits == 2)
return "";
}
+/* Compute the length of a rotate insn. */
+
unsigned int
compute_a_rotate_length (rtx *operands)
{
int amount;
unsigned int length = 0;
- if (GET_CODE (amount_rtx) != CONST_INT)
- abort ();
+ gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
amount = INTVAL (amount_rtx);
operating insn. */
int
-fix_bit_operand (rtx *operands, int what, enum rtx_code type)
+fix_bit_operand (rtx *operands, enum rtx_code code)
{
/* The bit_operand predicate accepts any memory during RTL generation, but
only 'U' memory afterwards, so if this is a MEM operand, we must force
it to be valid for 'U' by reloading the address. */
- if ((what == 0 && single_zero_operand (operands[2], QImode))
- || (what == 1 && single_one_operand (operands[2], QImode)))
+ if (code == AND
+ ? single_zero_operand (operands[2], QImode)
+ : single_one_operand (operands[2], QImode))
{
/* OK to have a memory dest. */
if (GET_CODE (operands[0]) == MEM
- && !EXTRA_CONSTRAINT (operands[0], 'U'))
+ && !OK_FOR_U (operands[0]))
{
rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
copy_to_mode_reg (Pmode,
}
if (GET_CODE (operands[1]) == MEM
- && !EXTRA_CONSTRAINT (operands[1], 'U'))
+ && !OK_FOR_U (operands[1]))
{
rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
copy_to_mode_reg (Pmode,
operands[1] = force_reg (QImode, operands[1]);
{
rtx res = gen_reg_rtx (QImode);
- emit_insn (gen_rtx_SET (VOIDmode, res,
- gen_rtx (type, QImode, operands[1], operands[2])));
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
+ switch (code)
+ {
+ case AND:
+ emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
+ break;
+ case IOR:
+ emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
+ break;
+ case XOR:
+ emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ emit_insn (gen_movqi (operands[0], res));
}
return 1;
}
return a != NULL_TREE;
}
+/* Return nonzero if FUNC is a saveall function as specified by the
+ "saveall" attribute. */
+
+static int
+h8300_saveall_function_p (tree func)
+{
+ tree a;
+
+ if (TREE_CODE (func) != FUNCTION_DECL)
+ return 0;
+
+ a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
+ return a != NULL_TREE;
+}
+
/* Return nonzero if FUNC is an OS_Task function as specified
by the "OS_Task" attribute. */
return a != NULL_TREE;
}
-/* Generate an 'interrupt_handler' attribute for decls. */
+/* Generate an 'interrupt_handler' attribute for decls. We convert
+ all the pragmas to corresponding attributes. */
static void
h8300_insert_attributes (tree node, tree *attributes)
{
- if (!pragma_interrupt
- || TREE_CODE (node) != FUNCTION_DECL)
- return;
+ if (TREE_CODE (node) == FUNCTION_DECL)
+ {
+ if (pragma_interrupt)
+ {
+ pragma_interrupt = 0;
+
+ /* Add an 'interrupt_handler' attribute. */
+ *attributes = tree_cons (get_identifier ("interrupt_handler"),
+ NULL, *attributes);
+ }
- pragma_interrupt = 0;
+ if (pragma_saveall)
+ {
+ pragma_saveall = 0;
- /* Add an 'interrupt_handler' attribute. */
- *attributes = tree_cons (get_identifier ("interrupt_handler"),
- NULL, *attributes);
+ /* Add an 'saveall' attribute. */
+ *attributes = tree_cons (get_identifier ("saveall"),
+ NULL, *attributes);
+ }
+ }
}
/* Supported attributes:
interrupt_handler: output a prologue and epilogue suitable for an
interrupt handler.
+ saveall: output a prologue and epilogue that saves and restores
+ all registers except the stack pointer.
+
function_vector: This function should be called through the
function vector.
tiny_data: This variable lives in the tiny data area and can be
referenced with 16-bit absolute memory references. */
-const struct attribute_spec h8300_attribute_table[] =
+static const struct attribute_spec h8300_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
{ "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
+ { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
{ "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
{ "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
{ "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
- warning ("`%s' attribute only applies to functions",
- IDENTIFIER_POINTER (name));
+ warning (OPT_Wattributes, "%qE attribute only applies to functions",
+ name);
*no_add_attrs = true;
}
}
else
{
- warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
+ warning (OPT_Wattributes, "%qE attribute ignored",
+ name);
*no_add_attrs = true;
}
}
else
{
- warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
+ warning (OPT_Wattributes, "%qE attribute ignored",
+ name);
*no_add_attrs = true;
}
SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
}
+/* Output a single-bit extraction. */
+
const char *
output_simode_bld (int bild, rtx operands[])
{
return "";
}
+/* Delayed-branch scheduling is more effective if we have some idea
+ how long each instruction will be. Use a shorten_branches pass
+ to get an initial estimate. */
+
+static void
+h8300_reorg (void)
+{
+ if (flag_delayed_branch)
+ shorten_branches (get_insns ());
+}
+
#ifndef OBJECT_FORMAT_ELF
static void
-h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
+h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
+ tree decl)
{
/* ??? Perhaps we should be using default_coff_asm_named_section. */
fprintf (asm_out_file, "\t.section %s\n", name);
int
h8300_eightbit_constant_address_p (rtx x)
{
- /* The ranges of the 8-bit area. */
+ /* The ranges of the 8-bit area. */
const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
unsigned HOST_WIDE_INT addr;
- /* We accept symbols declared with tiny_data. */
- if (GET_CODE (x) == SYMBOL_REF)
- return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
+ switch (GET_CODE (x))
+ {
+ case SYMBOL_REF:
+ /* In the normal mode, any symbol fits in the 16-bit absolute
+ address range. We also accept symbols declared with
+ tiny_data. */
+ return (TARGET_NORMAL_MODE
+ || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
- if (GET_CODE (x) != CONST_INT)
- return 0;
+ case CONST_INT:
+ addr = INTVAL (x);
+ return (TARGET_NORMAL_MODE
+ || (TARGET_H8300H
+ && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
+ || (TARGET_H8300S
+ && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
- addr = INTVAL (x);
+ case CONST:
+ return TARGET_NORMAL_MODE;
+
+ default:
+ return 0;
+ }
- return (0
- || TARGET_NORMAL_MODE
- || (TARGET_H8300H
- && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
- || (TARGET_H8300S
- && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
}
+/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
+ locations that can be accessed as a 16-bit word. */
+
int
byte_accesses_mergeable_p (rtx addr1, rtx addr2)
{
return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
&& any_condjump_p (i2) && onlyjump_p (i2));
}
+
+/* Return nonzero if we have the same comparison insn as I1 two insns
+ after I1. I1 is assumed to be a comparison insn. */
+
+int
+same_cmp_following_p (rtx i1)
+{
+ rtx i2, i3;
+
+ /* Make sure we have a sequence of three insns. */
+ i2 = next_nonnote_insn (i1);
+ if (i2 == NULL_RTX)
+ return 0;
+ i3 = next_nonnote_insn (i2);
+ if (i3 == NULL_RTX)
+ return 0;
+
+ return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
+ && any_condjump_p (i2) && onlyjump_p (i2));
+}
+
+/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
+ (or pops) N registers. OPERANDS are assumed to be an array of
+ registers. */
+
+int
+h8300_regs_ok_for_stm (int n, rtx operands[])
+{
+ switch (n)
+ {
+ case 2:
+ return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
+ || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
+ || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
+ case 3:
+ return ((REGNO (operands[0]) == 0
+ && REGNO (operands[1]) == 1
+ && REGNO (operands[2]) == 2)
+ || (REGNO (operands[0]) == 4
+ && REGNO (operands[1]) == 5
+ && REGNO (operands[2]) == 6));
+
+ case 4:
+ return (REGNO (operands[0]) == 0
+ && REGNO (operands[1]) == 1
+ && REGNO (operands[2]) == 2
+ && REGNO (operands[3]) == 3);
+ default:
+ gcc_unreachable ();
+ }
+}
+
+/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
+
+int
+h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
+ unsigned int new_reg)
+{
+ /* Interrupt functions can only use registers that have already been
+ saved by the prologue, even if they would normally be
+ call-clobbered. */
+
+ if (h8300_current_function_interrupt_function_p ()
+ && !df_regs_ever_live_p (new_reg))
+ return 0;
+
+ return 1;
+}
+
+/* Returns true if register REGNO is safe to be allocated as a scratch
+ register in the current function. */
+
+static bool
+h8300_hard_regno_scratch_ok (unsigned int regno)
+{
+ if (h8300_current_function_interrupt_function_p ()
+ && ! WORD_REG_USED (regno))
+ return false;
+
+ return true;
+}
+
+
+/* Return nonzero if X is a legitimate constant. */
+
+int
+h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+/* Return nonzero if X is a REG or SUBREG suitable as a base register. */
+
+static int
+h8300_rtx_ok_for_base_p (rtx x, int strict)
+{
+ /* Strip off SUBREG if any. */
+ if (GET_CODE (x) == SUBREG)
+ x = SUBREG_REG (x);
+
+ return (REG_P (x)
+ && (strict
+ ? REG_OK_FOR_BASE_STRICT_P (x)
+ : REG_OK_FOR_BASE_NONSTRICT_P (x)));
+}
+
+/* Return nozero if X is a legitimate address. On the H8/300, a
+ legitimate address has the form REG, REG+CONSTANT_ADDRESS or
+ CONSTANT_ADDRESS. */
+
+static bool
+h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
+{
+ /* The register indirect addresses like @er0 is always valid. */
+ if (h8300_rtx_ok_for_base_p (x, strict))
+ return 1;
+
+ if (CONSTANT_ADDRESS_P (x))
+ return 1;
+
+ if (TARGET_H8300SX
+ && ( GET_CODE (x) == PRE_INC
+ || GET_CODE (x) == PRE_DEC
+ || GET_CODE (x) == POST_INC
+ || GET_CODE (x) == POST_DEC)
+ && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
+ return 1;
+
+ if (GET_CODE (x) == PLUS
+ && CONSTANT_ADDRESS_P (XEXP (x, 1))
+ && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
+ mode, 0), strict))
+ return 1;
+
+ return 0;
+}
+
+/* Worker function for HARD_REGNO_NREGS.
+
+ We pretend the MAC register is 32bits -- we don't have any data
+ types on the H8 series to handle more than 32bits. */
+
+int
+h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
+{
+ return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+}
+
+/* Worker function for HARD_REGNO_MODE_OK. */
+
+int
+h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
+{
+ if (TARGET_H8300)
+ /* If an even reg, then anything goes. Otherwise the mode must be
+ QI or HI. */
+ return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
+ else
+ /* MAC register can only be of SImode. Otherwise, anything
+ goes. */
+ return regno == MAC_REG ? mode == SImode : 1;
+}
+\f
+/* Perform target dependent optabs initialization. */
+static void
+h8300_init_libfuncs (void)
+{
+ set_optab_libfunc (smul_optab, HImode, "__mulhi3");
+ set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
+ set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
+ set_optab_libfunc (smod_optab, HImode, "__modhi3");
+ set_optab_libfunc (umod_optab, HImode, "__umodhi3");
+}
+\f
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
+
+static bool
+h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
+{
+ return (TYPE_MODE (type) == BLKmode
+ || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
+}
+\f
+/* We emit the entire trampoline here. Depending on the pointer size,
+ we use a different trampoline.
+
+ Pmode == HImode
+ vvvv context
+ 1 0000 7903xxxx mov.w #0x1234,r3
+ 2 0004 5A00xxxx jmp @0x1234
+ ^^^^ function
+
+ Pmode == SImode
+ vvvvvvvv context
+ 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
+ 3 0006 5Axxxxxx jmp @0x123456
+ ^^^^^^ function
+*/
+
+static void
+h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
+{
+ rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
+ rtx mem;
+
+ if (Pmode == HImode)
+ {
+ mem = adjust_address (m_tramp, HImode, 0);
+ emit_move_insn (mem, GEN_INT (0x7903));
+ mem = adjust_address (m_tramp, Pmode, 2);
+ emit_move_insn (mem, cxt);
+ mem = adjust_address (m_tramp, HImode, 4);
+ emit_move_insn (mem, GEN_INT (0x5a00));
+ mem = adjust_address (m_tramp, Pmode, 6);
+ emit_move_insn (mem, fnaddr);
+ }
+ else
+ {
+ rtx tem;
+
+ mem = adjust_address (m_tramp, HImode, 0);
+ emit_move_insn (mem, GEN_INT (0x7a03));
+ mem = adjust_address (m_tramp, Pmode, 2);
+ emit_move_insn (mem, cxt);
+
+ tem = copy_to_reg (fnaddr);
+ emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
+ emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
+ mem = adjust_address (m_tramp, SImode, 6);
+ emit_move_insn (mem, tem);
+ }
+}
\f
/* Initialize the GCC target structure. */
#undef TARGET_ATTRIBUTE_TABLE
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
-#undef TARGET_ASM_FUNCTION_EPILOGUE
-#define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
-
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START h8300_file_start
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS h8300_rtx_costs
+#undef TARGET_INIT_LIBFUNCS
+#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
+
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
+
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
+
+#undef TARGET_HARD_REGNO_SCRATCH_OK
+#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
+
+#undef TARGET_LEGITIMATE_ADDRESS_P
+#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
+
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
+
+#undef TARGET_CAN_ELIMINATE
+#define TARGET_CAN_ELIMINATE h8300_can_eliminate
+
+#undef TARGET_TRAMPOLINE_INIT
+#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
+
struct gcc_target targetm = TARGET_INITIALIZER;
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