;; FR30 machine description.
-;; Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
+;; Copyright (C) 1998, 1999, 2000, 2002, 2004, 2005, 2007, 2010
+;; Free Software Foundation, Inc.
;; Contributed by Cygnus Solutions.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
;; Define an attribute to be used by the delay slot code.
-;; An instruction by default is considered to be 'delyabable'
+;; An instruction by default is considered to be 'delayable'
;; that is, it can be placed into a delay slot, but it is not
;; itself a delayed branch type instruction. An instruction
-;; whoes type is 'delayed' is one which has a delay slot, and
-;; an instruction whoes delay_type is 'other' is one which does
+;; whose type is 'delayed' is one which has a delay slot, and
+;; an instruction whose delay_type is 'other' is one which does
;; not have a delay slot, nor can it be placed into a delay slot.
(define_attr "delay_type" "delayable,delayed,other" (const_string "delayable"))
(nil)]
)
+(include "predicates.md")
+(include "constraints.md")
+
;;}}}
;;{{{ Moves
;; Push a register onto the stack
(define_insn "movsi_push"
- [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
+ [(set (mem:SI (pre_dec:SI (reg:SI 15)))
(match_operand:SI 0 "register_operand" "a"))]
""
"st %0, @-r15"
;; Pop a register off the stack
(define_insn "movsi_pop"
- [(set:SI (match_operand:SI 0 "register_operand" "=a")
+ [(set (match_operand:SI 0 "register_operand" "=a")
(mem:SI (post_inc:SI (reg:SI 15))))]
""
"ld @r15+, %0"
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
- "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128"
- [(set:SI (match_dup 0) (match_dup 1))
- (set:SI (match_dup 0) (sign_extend:SI (match_dup 2)))]
+ "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128
+ && (GET_CODE (operands[0]) != SUBREG
+ || SCALAR_INT_MODE_P (GET_MODE (XEXP (operands[0], 0))))"
+ [(set (match_dup 0) (match_dup 1))
+ (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
"{
operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
operands[2] = gen_lowpart (QImode, operands[0]);
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
"(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)"
- [(set:SI (match_dup 0) (match_dup 2))
- (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
+ [(set (match_dup 0) (match_dup 2))
+ (parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 24)))
(clobber (reg:CC 16))])]
"{
HOST_WIDE_INT val = INTVAL (operands[1]);
)
;; If we are loading a large positive constant, one which has bits
-;; in the top byte set, but whoes set bits all lie within an 8 bit
+;; in the top byte set, but whose set bits all lie within an 8 bit
;; range, then we can save time and space by loading the byte value
;; and shifting it into place.
(define_split
(match_operand:SI 1 "const_int_operand" ""))]
"(INTVAL (operands[1]) > 0x00ffffff)
&& ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)"
- [(set:SI (match_dup 0) (match_dup 2))
- (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
+ [(set (match_dup 0) (match_dup 2))
+ (parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))
(clobber (reg:CC 16))])]
"{
HOST_WIDE_INT val = INTVAL (operands[1]);
;; values are addresses which will fit in 20 bits.
(define_insn "movsi_internal"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,m,r")
- (match_operand:SI 1 "general_operand" "L,M,n,i,rde,r,rm"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,red,V,r,m")
+ (match_operand:SI 1 "general_operand" "L,M,n,i,rde,r,rm,r"))]
""
"*
{
case 4: return \"mov \\t%1, %0\";
case 5: return \"st \\t%1, %0\";
case 6: return \"ld \\t%1, %0\";
- default: abort ();
- }
+ case 7: return \"st \\t%1, %0\";
+ default: gcc_unreachable ();
+ }
}"
[(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 4)
(eq_attr "alternative" "2") (const_int 6)
;; Note - the FR30 does not have an 8 byte load/store instruction
;; but we have to support this pattern because some other patterns
-;; (eg muldisi2) can produce a DImode result.
+;; (e.g. muldisi2) can produce a DImode result.
;; (This code is stolen from the M32R port.)
(define_expand "movdi"
- [(set (match_operand:DI 0 "general_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (match_operand:DI 1 "general_operand" ""))]
""
"
/* Everything except mem = const or mem = mem can be done easily. */
-
+
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (DImode, operands[1]);
- ")
+ "
+)
;; We use an insn and a split so that we can generate
;; RTL rather than text from fr30_move_double().
(define_insn "*movdi_insn"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,m,r")
- (match_operand:DI 1 "di_operand" "r,m,r,nF"))]
+ (match_operand:DI 1 "di_operand" "r,m,r,nF"))]
"register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
"#"
[(set_attr "length" "4,8,12,12")]
(define_split
[(set (match_operand:DI 0 "nonimmediate_di_operand" "")
- (match_operand:DI 1 "di_operand" ""))]
+ (match_operand:DI 1 "di_operand" ""))]
"reload_completed"
[(match_dup 2)]
- "operands[2] = fr30_move_double (operands);")
+ "operands[2] = fr30_move_double (operands);"
+)
;;}}}
;;{{{ Load & Store Multiple Registers
;; is during function prologues and epilogues.
(define_peephole
- [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 0 "high_register_operand" "h"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 1 "high_register_operand" "h"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 2 "high_register_operand" "h"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 3 "high_register_operand" "h"))]
+ [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 0 "high_register_operand" "h"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 1 "high_register_operand" "h"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 2 "high_register_operand" "h"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 3 "high_register_operand" "h"))]
"fr30_check_multiple_regs (operands, 4, 1)"
"stm1 (%0, %1, %2, %3)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 0 "high_register_operand" "h"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 1 "high_register_operand" "h"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 2 "high_register_operand" "h"))]
+ [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 0 "high_register_operand" "h"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 1 "high_register_operand" "h"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 2 "high_register_operand" "h"))]
"fr30_check_multiple_regs (operands, 3, 1)"
"stm1 (%0, %1, %2)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 0 "high_register_operand" "h"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 1 "high_register_operand" "h"))]
+ [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 0 "high_register_operand" "h"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 1 "high_register_operand" "h"))]
"fr30_check_multiple_regs (operands, 2, 1)"
"stm1 (%0, %1)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (match_operand:SI 0 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))
- (set:SI (match_operand:SI 1 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))
- (set:SI (match_operand:SI 2 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))
- (set:SI (match_operand:SI 3 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))]
+ [(set (match_operand:SI 0 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))
+ (set (match_operand:SI 1 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))
+ (set (match_operand:SI 2 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))
+ (set (match_operand:SI 3 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))]
"fr30_check_multiple_regs (operands, 4, 0)"
"ldm1 (%0, %1, %2, %3)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (match_operand:SI 0 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))
- (set:SI (match_operand:SI 1 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))
- (set:SI (match_operand:SI 2 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))]
+ [(set (match_operand:SI 0 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))
+ (set (match_operand:SI 1 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))
+ (set (match_operand:SI 2 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))]
"fr30_check_multiple_regs (operands, 3, 0)"
"ldm1 (%0, %1, %2)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (match_operand:SI 0 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))
- (set:SI (match_operand:SI 1 "high_register_operand" "h")
- (mem:SI (post_inc:SI (reg:SI 15))))]
+ [(set (match_operand:SI 0 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))
+ (set (match_operand:SI 1 "high_register_operand" "h")
+ (mem:SI (post_inc:SI (reg:SI 15))))]
"fr30_check_multiple_regs (operands, 2, 0)"
"ldm1 (%0, %1)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 0 "low_register_operand" "l"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 1 "low_register_operand" "l"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 2 "low_register_operand" "l"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 3 "low_register_operand" "l"))]
+ [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 0 "low_register_operand" "l"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 1 "low_register_operand" "l"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 2 "low_register_operand" "l"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 3 "low_register_operand" "l"))]
"fr30_check_multiple_regs (operands, 4, 1)"
"stm0 (%0, %1, %2, %3)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 0 "low_register_operand" "l"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 1 "low_register_operand" "l"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 2 "low_register_operand" "l"))]
+ [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 0 "low_register_operand" "l"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 1 "low_register_operand" "l"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 2 "low_register_operand" "l"))]
"fr30_check_multiple_regs (operands, 3, 1)"
"stm0 (%0, %1, %2)"
[(set_attr "delay_type" "other")]
)
(define_peephole
- [(set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 0 "low_register_operand" "l"))
- (set:SI (mem:SI (pre_dec:SI (reg:SI 15)))
- (match_operand:SI 1 "low_register_operand" "l"))]
+ [(set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 0 "low_register_operand" "l"))
+ (set (mem:SI (pre_dec:SI (reg:SI 15)))
+ (match_operand:SI 1 "low_register_operand" "l"))]
"fr30_check_multiple_regs (operands, 2, 1)"
"stm0 (%0, %1)"
[(set_attr "delay_type" "other")]
case 2: return \"mov \\t%1, %0\";
case 3: return \"st \\t%1, %0\";
case 4: return \"ld \\t%1, %0\";
- default: abort ();
+ default: gcc_unreachable ();
}
}"
[(set (attr "length") (cond [(eq_attr "alternative" "0") (const_int 6)
const char * tmp_reg;
static char buffer[100];
- ldi_instr = fr30_const_double_is_zero (operands[1])
- ? ldi_instr = \"ldi:8\" : \"ldi:32\";
+ ldi_instr = fr30_const_double_is_zero (operands[1]) ? \"ldi:8\" : \"ldi:32\";
tmp_reg = reg_names [COMPILER_SCRATCH_REGISTER];
)
;; We need some trickery to be able to handle the addition of
-;; large (ie outside +/- 16) constants. We need to be able to
+;; large (i.e. outside +/- 16) constants. We need to be able to
;; handle this because reload assumes that it can generate add
;; instructions with arbitrary sized constants.
(define_expand "addsi3"
emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
else if (GET_CODE (operands[2]) != CONST_INT)
emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
- else if ( (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
- && (REGNO (operands[1]) != ARG_POINTER_REGNUM)
- && (INTVAL (operands[2]) >= -16)
- && (INTVAL (operands[2]) <= 15))
+ else if (INTVAL (operands[2]) >= -16
+ && INTVAL (operands[2]) <= 15
+ && (!REG_P (operands[1])
+ || !REGNO_PTR_FRAME_P (REGNO (operands[1]))
+ || REGNO (operands[1]) == STACK_POINTER_REGNUM))
emit_insn (gen_addsi_small_int (operands[0], operands[1], operands[2]));
else
emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
[(set (match_operand:SI 0 "register_operand" "=r,r")
(plus:SI (match_operand:SI 1 "register_operand" "0,0")
(match_operand:SI 2 "add_immediate_operand" "I,J")))]
- " (REGNO (operands[1]) != FRAME_POINTER_REGNUM)
- && (REGNO (operands[1]) != ARG_POINTER_REGNUM)"
+ "!REG_P (operands[1])
+ || !REGNO_PTR_FRAME_P (REGNO (operands[1]))
+ || REGNO (operands[1]) == STACK_POINTER_REGNUM"
"@
addn %2, %0
addn2 %2, %0"
""
"{
/* Cope with the possibility that ops 0 and 1 are the same register. */
- if (REGNO (operands[0]) == REGNO (operands[1]))
+ if (rtx_equal_p (operands[0], operands[1]))
{
if (reload_in_progress || reload_completed)
{
;;}}}
;;{{{ Multiplication
-;; Signed multiplication producing 64 bit results from 32 bit inputs
+;; Signed multiplication producing 64-bit results from 32-bit inputs
(define_insn "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
[(set_attr "length" "6")]
)
-;; Unsigned multiplication producing 64 bit results from 32 bit inputs
+;; Unsigned multiplication producing 64-bit results from 32-bit inputs
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
[(set_attr "length" "6")]
)
-;; Signed multiplication producing 32 bit result from 16 bit inputs
+;; Signed multiplication producing 32-bit result from 16-bit inputs
(define_insn "mulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
[(set_attr "length" "4")]
)
-;; Unsigned multiplication producing 32 bit result from 16 bit inputs
+;; Unsigned multiplication producing 32-bit result from 16-bit inputs
(define_insn "umulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r"))
[(set_attr "length" "4")]
)
-;; Signed multiplication producing 32 bit result from 32 bit inputs
+;; Signed multiplication producing 32-bit result from 32-bit inputs
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" "%r")
)
;;}}}
-;;{{{ Negation
-
-(define_expand "negsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (neg:SI (match_operand:SI 1 "register_operand" "")))]
- ""
- "{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- {
- if (reload_in_progress || reload_completed)
- {
- rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
-
- emit_insn (gen_movsi (reg, GEN_INT (0)));
- emit_insn (gen_subsi3 (reg, reg, operands[0]));
- emit_insn (gen_movsi (operands[0], reg));
- }
- else
- {
- rtx reg = gen_reg_rtx (SImode);
-
- emit_insn (gen_movsi (reg, GEN_INT (0)));
- emit_insn (gen_subsi3 (reg, reg, operands[0]));
- emit_insn (gen_movsi (operands[0], reg));
- }
- }
- else
- {
- emit_insn (gen_movsi_internal (operands[0], GEN_INT (0)));
- emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
- }
- DONE;
- }"
-)
-
-;;}}}
-
;;}}} \f
;;{{{ Shifts
;;}}} \f
;;{{{ Logical Operations
-;; Logical AND, 32 bit integers
+;; Logical AND, 32-bit integers
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (match_operand:SI 1 "register_operand" "%r")
"and %1, %0"
)
-;; Inclusive OR, 32 bit integers
+;; Inclusive OR, 32-bit integers
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (match_operand:SI 1 "register_operand" "%r")
"or %1, %0"
)
-;; Exclusive OR, 32 bit integers
+;; Exclusive OR, 32-bit integers
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(xor:SI (match_operand:SI 1 "register_operand" "%r")
"eor %1, %0"
)
-;; One's complement, 32 bit integers
+;; One's complement, 32-bit integers
(define_expand "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "")
(not:SI (match_operand:SI 1 "register_operand" "")))]
""
"{
- if (REGNO (operands[0]) == REGNO (operands[1]))
+ if (rtx_equal_p (operands[0], operands[1]))
{
if (reload_in_progress || reload_completed)
{
rtx reg = gen_rtx_REG (SImode, 0/*COMPILER_SCRATCH_REGISTER*/);
- emit_insn (gen_movsi (reg, GEN_INT (-1)));
+ emit_insn (gen_movsi (reg, constm1_rtx));
emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
}
else
{
rtx reg = gen_reg_rtx (SImode);
- emit_insn (gen_movsi (reg, GEN_INT (-1)));
+ emit_insn (gen_movsi (reg, constm1_rtx));
emit_insn (gen_xorsi3 (operands[0], operands[0], reg));
}
}
else
{
- emit_insn (gen_movsi_internal (operands[0], GEN_INT (-1)));
+ emit_insn (gen_movsi_internal (operands[0], constm1_rtx));
emit_insn (gen_xorsi3 (operands[0], operands[1], operands[0]));
}
DONE;
;;}}} \f
;;{{{ Comparisons
-;; Note, we store the operands in the comparison insns, and use them later
-;; when generating the branch or scc operation.
-
-;; First the routines called by the machine independent part of the compiler
-(define_expand "cmpsi"
- [(set (reg:CC 16)
- (compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "nonmemory_operand" "")))]
- ""
- "{
- fr30_compare_op0 = operands[0];
- fr30_compare_op1 = operands[1];
- DONE;
- }"
-)
-
-;; Now, the actual comparisons, generated by the branch and/or scc operations
+;; The actual comparisons, generated by the cbranch and/or cstore expanders
(define_insn "*cmpsi_internal"
[(set (reg:CC 16)
;; Define_expands called by the machine independent part of the compiler
;; to allocate a new comparison register
-(define_expand "beq"
+(define_expand "cbranchsi4"
[(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
+ (compare:CC (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))
(set (pc)
- (if_then_else (eq:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(reg:CC 16) (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
(pc)))]
""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "bne"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (ne:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
)
-(define_expand "blt"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (lt:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "ble"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (le:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "bgt"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (gt:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "bge"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (ge:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "bltu"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (ltu:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "bleu"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (leu:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "bgtu"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (gtu:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
-
-(define_expand "bgeu"
- [(set (reg:CC 16)
- (compare:CC (match_dup 1)
- (match_dup 2)))
- (set (pc)
- (if_then_else (geu:CC (reg:CC 16)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{
- operands[1] = fr30_compare_op0;
- operands[2] = fr30_compare_op1;
- }"
-)
;; Actual branches. We must allow for the (label_ref) and the (pc) to be
;; swapped. If they are swapped, it reverses the sense of the branch.
;; far away the destination is.
;; The calculation for the instruction length is derived as follows:
-;; The branch instruction has a 9 bit signed displacement so we have
+;; The branch instruction has a 9-bit signed displacement so we have
;; this inequality for the displacement:
;;
;; -256 <= pc < 256
;; or
;; -256 + 256 <= pc + 256 < 256 + 256
-;; ie
+;; i.e.
;; 0 <= pc + 256 < 512
;;
;; if we consider the displacement as an unsigned value, then negative
(define_insn "*branch_true"
[(set (pc)
- (if_then_else (match_operator:CC 0 "comparison_operator"
+ (if_then_else (match_operator 0 "comparison_operator"
[(reg:CC 16)
(const_int 0)])
(label_ref (match_operand 1 "" ""))
;; branch occurs if the test is false, so the %B operator is used.
(define_insn "*branch_false"
[(set (pc)
- (if_then_else (match_operator:CC 0 "comparison_operator"
+ (if_then_else (match_operator 0 "comparison_operator"
[(reg:CC 16)
(const_int 0)])
(pc)
)
(define_insn "leave_func"
- [(set (reg:SI 15) (reg:SI 14))
- (set (reg:SI 14) (mem:SI (post_inc:SI (reg:SI 15))))]
+ [(set (reg:SI 15) (plus:SI (reg:SI 14) (const_int 4)))
+ (set (reg:SI 14) (mem:SI (minus:SI (reg:SI 15) (const_int 4))))]
"reload_completed"
"leave"
)
-(define_insn "enter_func"
- [(set:SI (mem:SI (minus:SI (reg:SI 15)
- (const_int 4)))
- (reg:SI 14))
- (set:SI (reg:SI 14)
- (minus:SI (reg:SI 15)
- (const_int 4)))
- (set:SI (reg:SI 15)
- (minus:SI (reg:SI 15)
- (match_operand 0 "immediate_operand" "i")))]
+(define_expand "enter_func"
+ [(parallel
+ [(set (mem:SI (minus:SI (match_dup 1)
+ (const_int 4)))
+ (match_dup 2))
+ (set (match_dup 2)
+ (minus:SI (match_dup 1)
+ (const_int 4)))
+ (set (match_dup 1)
+ (minus:SI (match_dup 1)
+ (match_operand:SI 0 "immediate_operand")))]
+ )]
+ ""
+{
+ operands[1] = stack_pointer_rtx;
+ operands[2] = hard_frame_pointer_rtx;
+})
+
+(define_insn "*enter_func"
+ [(set (mem:SI (minus:SI (reg:SI 15)
+ (const_int 4)))
+ (reg:SI 14))
+ (set (reg:SI 14)
+ (minus:SI (reg:SI 15)
+ (const_int 4)))
+ (set (reg:SI 15)
+ (minus:SI (reg:SI 15)
+ (match_operand 0 "immediate_operand" "i")))]
"reload_completed"
"enter #%0"
[(set_attr "delay_type" "other")]
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