;; Machine description for the TMS320C[34]x for GCC
;; Copyright (C) 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
+;; 1999, 2000, 2002, 2004, 2005, 2007 Free Software Foundation, Inc.
;; Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
;; and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl)
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;
; TODO :
; for QImode and Pmode, whether Pmode was QImode or PQImode.
; For addresses we wouldn't have to have a clobber of the CC
; associated with each insn and we could use MPYI in address
-; calculations without having to synthesize a proper 32 bit multiply.
+; calculations without having to synthesize a proper 32-bit multiply.
; Additional C30/C40 instructions not coded:
; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond
; L unsigned 16-bit
; M unsigned 8-bit (C4x only)
; N ones complement of unsigned 16-bit
-; O 16 bit high constant
+; O 16-bit high constant
; Q ARx + 9-bit signed disp
; R ARx + 5-bit unsigned disp (C4x only)
; S ARx + 0, 1, IRx disp
; not for 'c'.
; The 'f' constraint is only for float register operands---when
-; a register satisying the 'f' constraint is used as a dst operand,
+; a register satisfying the 'f' constraint is used as a dst operand,
; the CC gets clobbered (except for LDFcond).
; The ! in front of the 'b' constraint says to GCC to disparage the
; didn't allow it to move the CC around.
; Note that fundamental operations, such as moves, must not clobber the
-; CC. Thus movqi choses a move instruction that doesn't clobber the CC.
+; CC. Thus movqi chooses a move instruction that doesn't clobber the CC.
; If GCC wants to combine a move with a compare, it is smart enough to
; chose the move instruction that sets the CC.
; op3 fetch executed
; This means that we can allow any instruction in the last delay slot
; and only instructions which modify registers in the first two.
-; lda can not be executed in the first delay slot
-; and ldpk can not be executed in the first two delay slots.
+; lda cannot be executed in the first delay slot
+; and ldpk cannot be executed in the first two delay slots.
(define_attr "onlyreg" "false,true"
(cond [(eq_attr "type" "unary,unarycc")
])
;
-; C4x FUNCTIONAL UNITS
-;
-; Define functional units for instruction scheduling to minimize
-; pipeline conflicts.
+; C4x PIPELINE MODEL
;
; With the C3x, an external memory write (with no wait states) takes
; two cycles and an external memory read (with no wait states) takes
; one cycle. However, an external read following an external write
; takes two cycles. With internal memory, reads and writes take
; half a cycle.
-;
; When a C4x address register is loaded it will not be available for
; an extra machine cycle. Calculating with a C4x address register
-; makes it unavailable for 2 machine cycles. To notify GCC of these
-; pipeline delays, each of the auxiliary and index registers are declared
-; as separate functional units.
+; makes it unavailable for 2 machine cycles.
;
-; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
-; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
-;
-; MULTIPLICITY 1 (C4x has no independent identical function units)
-; SIMULTANEITY 0 (C4x is pipelined)
-; READY_DELAY 1 (Results usually ready after every cyle)
-; ISSUE_DELAY 1 (Can issue insns every cycle)
-
; Just some dummy definitions. The real work is done in c4x_adjust_cost.
; These are needed so the min/max READY_DELAY is known.
-(define_function_unit "dummy" 1 0 (const_int 0) 1 1)
-(define_function_unit "dummy" 1 0 (const_int 0) 2 1)
-(define_function_unit "dummy" 1 0 (const_int 0) 3 1)
+(define_insn_reservation "any_insn" 1 (const_int 1) "nothing")
+(define_insn_reservation "slowest_insn" 3 (const_int 0) "nothing")
; The attribute setar0 is set to 1 for insns where ar0 is a dst operand.
; Note that the attributes unarycc and binarycc do not apply
(const_int 1) (const_int 0))]
(const_int 0)))
+(include "predicates.md")
;
; C4x INSN PATTERNS:
operands[2]));
DONE;
}
- c4x_emit_libcall3 (smul_optab->handlers[(int) QImode].libfunc,
+ c4x_emit_libcall3 (optab_libfunc (smul_optab, QImode),
MULT, QImode, operands);
DONE;
}
emit_insn (gen_rtx_SET (QImode, operands[0],
gen_rtx_IF_THEN_ELSE (QImode,
gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx),
- operands[2], operands[3])));
+ operands[2], operands[3])));
DONE;}")
(define_insn "*ldf_conditional"
emit_insn (gen_rtx_SET (QFmode, operands[0],
gen_rtx_IF_THEN_ELSE (QFmode,
gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx),
- operands[2], operands[3])));
+ operands[2], operands[3])));
DONE;}")
(define_insn "*ldhf_conditional"
emit_insn (gen_rtx_SET (HFmode, operands[0],
gen_rtx_IF_THEN_ELSE (HFmode,
gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx),
- operands[2], operands[3])));
+ operands[2], operands[3])));
DONE;}")
(define_expand "seq"
"0"
"")
-(define_expand "movstrqi_small"
+(define_expand "movmemqi_small"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
(mem:BLK (match_operand:BLK 1 "src_operand" "")))
(use (match_operand:QI 2 "immediate_operand" ""))
; operand 3 is the shared alignment
; operand 4 is a scratch register
-(define_insn "movstrqi_large"
+(define_insn "movmemqi_large"
[(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "a"))
(mem:BLK (match_operand:QI 1 "addr_reg_operand" "a")))
(use (match_operand:QI 2 "immediate_operand" "i"))
[(set_attr "type" "multi")])
; Operand 2 is the count, operand 3 is the alignment.
-(define_expand "movstrqi"
+(define_expand "movmemqi"
[(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
(mem:BLK (match_operand:BLK 1 "src_operand" "")))
(use (match_operand:QI 2 "immediate_operand" ""))
tmp = gen_reg_rtx (QImode);
/* Disabled because of reload problems. */
if (0 && INTVAL (operands[2]) < 8)
- emit_insn (gen_movstrqi_small (operands[0], operands[1], operands[2],
+ emit_insn (gen_movmemqi_small (operands[0], operands[1], operands[2],
operands[3], tmp));
else
{
- emit_insn (gen_movstrqi_large (operands[0], operands[1], operands[2],
+ emit_insn (gen_movmemqi_large (operands[0], operands[1], operands[2],
operands[3], tmp));
}
DONE;
}")
-(define_insn "*cmpstrqi"
+(define_insn "*cmpstrnqi"
[(set (match_operand:QI 0 "ext_reg_operand" "=d")
(compare:QI (mem:BLK (match_operand:QI 1 "addr_reg_operand" "+a"))
(mem:BLK (match_operand:QI 2 "addr_reg_operand" "+a"))))
return \"\";
}")
-(define_expand "cmpstrqi"
+(define_expand "cmpstrnqi"
[(parallel [(set (match_operand:QI 0 "reg_operand" "")
(compare:QI (match_operand:BLK 1 "general_operand" "")
(match_operand:BLK 2 "general_operand" "")))
"push\\t%0"
[(set_attr "type" "push")])
-; we can not use this because the popf will destroy the low 8 bits
+; we cannot use this because the popf will destroy the low 8 bits
;(define_insn "pophf"
; [(set (match_operand:HF 0 "reg_operand" "=h")
; (mem:HF (post_dec:QI (reg:QI 20))))
(match_operand:HI 2 "src_operand" "")))
(clobber (reg:CC 21))])]
""
- "c4x_emit_libcall3 (smul_optab->handlers[(int) HImode].libfunc,
+ "c4x_emit_libcall3 (optab_libfunc (smul_optab, HImode),
MULT, HImode, operands);
DONE;")
OSDN Git Service
