/* Definitions of target machine for GNU compiler. TMS320C[34]x
- Copyright (C) 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+ Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+ 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
- This file is part of GNU CC.
+ This file is part of GCC.
- GNU CC is free software; you can redistribute it and/or modify
+ GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
- GNU CC is distributed in the hope that it will be useful,
+ GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with GNU CC; see the file COPYING. If not, write to
- the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
-
-#include "hwint.h"
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
/* RUN-TIME TARGET SPECIFICATION. */
#define C4x 1
-/* Name of the c4x assembler. */
-
-#define ASM_PROG "c4x-as"
-
-/* Name of the c4x linker. */
-
-#define LD_PROG "c4x-ld"
+#define TARGET_CPU_CPP_BUILTINS() \
+ do \
+ { \
+ extern int flag_inline_trees; \
+ if (!TARGET_SMALL) \
+ builtin_define ("_BIGMODEL"); \
+ if (!TARGET_MEMPARM) \
+ builtin_define ("_REGPARM"); \
+ if (flag_inline_functions) \
+ builtin_define ("_INLINE"); \
+ if (TARGET_C3X) \
+ { \
+ builtin_define ("_TMS320C3x"); \
+ builtin_define ("_C3x"); \
+ if (TARGET_C30) \
+ { \
+ builtin_define ("_TMS320C30"); \
+ builtin_define ("_C30"); \
+ } \
+ else if (TARGET_C31) \
+ { \
+ builtin_define ("_TMS320C31"); \
+ builtin_define ("_C31"); \
+ } \
+ else if (TARGET_C32) \
+ { \
+ builtin_define ("_TMS320C32"); \
+ builtin_define ("_C32"); \
+ } \
+ else if (TARGET_C33) \
+ { \
+ builtin_define ("_TMS320C33"); \
+ builtin_define ("_C33"); \
+ } \
+ } \
+ else \
+ { \
+ builtin_define ("_TMS320C4x"); \
+ builtin_define ("_C4x"); \
+ if (TARGET_C40) \
+ { \
+ builtin_define ("_TMS320C40"); \
+ builtin_define ("_C40"); \
+ } \
+ else if (TARGET_C44) \
+ { \
+ builtin_define ("_TMS320C44"); \
+ builtin_define ("_C44"); \
+ } \
+ } \
+ } \
+ while (0)
/* Define assembler options. */
#define ASM_SPEC "\
%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
-%{!m30:%{!m40:-m40}}}}}}}} \
-%{mcpu=30:-m30} \
-%{mcpu=31:-m31} \
-%{mcpu=32:-m32} \
-%{mcpu=33:-m33} \
-%{mcpu=40:-m40} \
-%{mcpu=44:-m44} \
-%{m30:-m30} \
-%{m31:-m31} \
-%{m32:-m32} \
-%{m33:-m33} \
-%{m40:-m40} \
-%{m44:-m44} \
-%{mmemparm:-p} %{mregparm:-r} \
-%{!mmemparm:%{!mregparm:-r}} \
-%{mbig:-b} %{msmall:-s} \
-%{!msmall:%{!mbig:-b}}"
+%{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \
+%{mcpu=30} \
+%{mcpu=31} \
+%{mcpu=32} \
+%{mcpu=33} \
+%{mcpu=40} \
+%{mcpu=44} \
+%{m30} \
+%{m31} \
+%{m32} \
+%{m33} \
+%{m40} \
+%{m44} \
+%{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \
+%{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}"
/* Define linker options. */
%{mcpu=32:--architecture c3x} \
%{mcpu=33:--architecture c3x}"
-/* Define C preprocessor options. */
-
-#define CPP_SPEC "\
-%{!m30:%{!m31:%{!m32:%{!m33:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:\
-%{!mcpu=40:%{!mcpu=44:%{\
-!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40}}}}}}}}}}}} \
-%{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
-%{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
-%{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
-%{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
-%{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
-%{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
-%{mcpu=33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
-%{m33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
-%{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
-%{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
-%{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
-%{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
-%{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
-%{!mmemparm:%{!mregparm:-D_REGPARM }} \
-%{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
-%{!msmall:%{!mbig:-D_BIGMODEL }} \
-%{finline-functions:-D_INLINE }"
-
/* Specify the end file to link with. */
#define ENDFILE_SPEC ""
-/* Target compilation option flags. */
-
-#define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
-#define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
-#define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
-#define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
-#define C3X_FLAG 0x0000010 /* Emit C3x code. */
-#define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
-#define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
-#define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
-#define DEVEL_FLAG 0x0000100 /* Enable features under development. */
-#define RPTB_FLAG 0x0000200 /* Enable repeat block. */
-#define BK_FLAG 0x0000400 /* Use BK as general register. */
-#define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
-#define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
-#define HOIST_FLAG 0x0002000 /* Force constants into registers. */
-#define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
-#define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
-#define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
-#define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
-#define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
-#define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
-
-#define C30_FLAG 0x0100000 /* Emit C30 code. */
-#define C31_FLAG 0x0200000 /* Emit C31 code. */
-#define C32_FLAG 0x0400000 /* Emit C32 code. */
-#define C33_FLAG 0x0400000 /* Emit C33 code. */
-#define C40_FLAG 0x1000000 /* Emit C40 code. */
-#define C44_FLAG 0x2000000 /* Emit C44 code. */
-
-/* Run-time compilation parameters selecting different hardware subsets.
-
- Macro to define tables used to set the flags.
- This is a list in braces of triplets in braces,
- each pair being { "NAME", VALUE, "DESCRIPTION" }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
-{ { "small", SMALL_MEMORY_FLAG, \
- N_("Small memory model") }, \
- { "big", -SMALL_MEMORY_FLAG, \
- N_("Big memory model") }, \
- { "mpyi", MPYI_FLAG, \
- N_("Use MPYI instruction for C3x") }, \
- { "no-mpyi", -MPYI_FLAG, \
- N_("Do not use MPYI instruction for C3x") }, \
- { "fast-fix", FAST_FIX_FLAG, \
- N_("Use fast but approximate float to integer conversion") }, \
- { "no-fast-fix", -FAST_FIX_FLAG, \
- N_("Use slow but accurate float to integer conversion") }, \
- { "rpts", RPTS_FLAG, \
- N_("Enable use of RTPS instruction") }, \
- { "no-rpts", -RPTS_FLAG, \
- N_("Disable use of RTPS instruction") }, \
- { "rptb", RPTB_FLAG, \
- N_("Enable use of RTPB instruction") }, \
- { "no-rptb", -RPTB_FLAG, \
- N_("Disable use of RTPB instruction") }, \
- { "30", C30_FLAG, \
- N_("Generate code for C30 CPU")}, \
- { "31", C31_FLAG, \
- N_("Generate code for C31 CPU")}, \
- { "32", C32_FLAG, \
- N_("Generate code for C32 CPU")}, \
- { "33", C33_FLAG, \
- N_("Generate code for C33 CPU")}, \
- { "40", C40_FLAG, \
- N_("Generate code for C40 CPU")}, \
- { "44", C44_FLAG, \
- N_("Generate code for C44 CPU")}, \
- { "ti", TI_FLAG, \
- N_("Emit code compatible with TI tools")}, \
- { "no-ti", -TI_FLAG, \
- N_("Emit code to use GAS extensions")}, \
- { "paranoid", PARANOID_FLAG, \
- N_("Save DP across ISR in small memory model") }, \
- { "no-paranoid", -PARANOID_FLAG, \
- N_("Don't save DP across ISR in small memory model") }, \
- { "isr-dp-reload", PARANOID_FLAG, \
- N_("Save DP across ISR in small memory model") }, \
- { "no-isr-dp-reload", -PARANOID_FLAG, \
- N_("Don't save DP across ISR in small memory model") }, \
- { "memparm", MEMPARM_FLAG, \
- N_("Pass arguments on the stack") }, \
- { "regparm", -MEMPARM_FLAG, \
- N_("Pass arguments in registers") }, \
- { "devel", DEVEL_FLAG, \
- N_("Enable new features under development") }, \
- { "no-devel", -DEVEL_FLAG, \
- N_("Disable new features under development") }, \
- { "bk", BK_FLAG, \
- N_("Use the BK register as a general purpose register") }, \
- { "no-bk", -BK_FLAG, \
- N_("Do not allocate BK register") }, \
- { "db", DB_FLAG, \
- N_("Enable use of DB instruction") }, \
- { "no-db", -DB_FLAG, \
- N_("Disable use of DB instruction") }, \
- { "debug", DEBUG_FLAG, \
- N_("Enable debugging") }, \
- { "no-debug", -DEBUG_FLAG, \
- N_("Disable debugging") }, \
- { "hoist", HOIST_FLAG, \
- N_("Force constants into registers to improve hoisting") }, \
- { "no-hoist", -HOIST_FLAG, \
- N_("Don't force constants into registers") }, \
- { "force", FORCE_FLAG, \
- N_("Force RTL generation to emit valid 3 operand insns") }, \
- { "no-force", -FORCE_FLAG, \
- N_("Allow RTL generation to emit invalid 3 operand insns") }, \
- { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
- N_("Allow unsigned interation counts for RPTB/DB") }, \
- { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
- N_("Disallow unsigned iteration counts for RPTB/DB") }, \
- { "preserve-float", PRESERVE_FLOAT_FLAG, \
- N_("Preserve all 40 bits of FP reg across call") }, \
- { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
- N_("Only preserve 32 bits of FP reg across call") }, \
- { "parallel-insns", PARALLEL_INSN_FLAG, \
- N_("Enable parallel instructions") }, \
- { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
- N_("Disable parallel instructions") }, \
- { "parallel-mpy", PARALLEL_MPY_FLAG, \
- N_("Enable MPY||ADD and MPY||SUB instructions") }, \
- { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
- N_("Disable MPY||ADD and MPY||SUB instructions") }, \
- { "aliases", ALIASES_FLAG, \
- N_("Assume that pointers may be aliased") }, \
- { "no-aliases", -ALIASES_FLAG, \
- N_("Assume that pointers not aliased") }, \
- { "", TARGET_DEFAULT, ""} }
-
-/* Default target switches. */
-
-/* Play safe, not the fastest code. */
-#define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
- | PARALLEL_MPY_FLAG | RPTB_FLAG
-
/* Caveats:
Max iteration count for RPTB/RPTS is 2^31 + 1.
Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
RPTS blocks interrupts. */
-extern int target_flags;
+extern int c4x_cpu_version; /* Cpu version C30/31/32/33/40/44. */
#define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
#define TARGET_SMALL_REG_CLASS 0
-#define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
-#define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
-#define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
-#define TARGET_RPTS (target_flags & RPTS_FLAG)
-#define TARGET_TI (target_flags & TI_FLAG)
-#define TARGET_PARANOID (target_flags & PARANOID_FLAG)
-#define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
-#define TARGET_DEVEL (target_flags & DEVEL_FLAG)
-#define TARGET_RPTB (target_flags & RPTB_FLAG \
- && optimize >= 2)
-#define TARGET_BK (target_flags & BK_FLAG)
-#define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
-#define TARGET_DEBUG (target_flags & DEBUG_FLAG)
-#define TARGET_HOIST (target_flags & HOIST_FLAG)
-#define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
-#define TARGET_FORCE (target_flags & FORCE_FLAG)
-#define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
-#define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
- && optimize >= 2)
-#define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
- && (target_flags & PARALLEL_MPY_FLAG))
-#define TARGET_ALIASES (target_flags & ALIASES_FLAG)
-
-#define TARGET_C3X (target_flags & C3X_FLAG)
-#define TARGET_C30 (target_flags & C30_FLAG)
-#define TARGET_C31 (target_flags & C31_FLAG)
-#define TARGET_C32 (target_flags & C32_FLAG)
-#define TARGET_C33 (target_flags & C33_FLAG)
-#define TARGET_C40 (target_flags & C40_FLAG)
-#define TARGET_C44 (target_flags & C44_FLAG)
-
-/* Define some options to control code generation. */
+#define TARGET_C3X (c4x_cpu_version >= 30 \
+ && c4x_cpu_version <= 39)
+
+#define TARGET_C30 (c4x_cpu_version == 30)
+#define TARGET_C31 (c4x_cpu_version == 31)
+#define TARGET_C32 (c4x_cpu_version == 32)
+#define TARGET_C33 (c4x_cpu_version == 33)
+#define TARGET_C40 (c4x_cpu_version == 40)
+#define TARGET_C44 (c4x_cpu_version == 44)
+
+/* Nonzero to use load_immed_addr pattern rather than forcing memory
+ addresses into memory. */
#define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
+
/* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
during RTL generation. */
#define TARGET_EXPOSE_LDP 0
+
/* Nonzero to force loading of direct memory references into a register. */
#define TARGET_LOAD_DIRECT_MEMS 0
#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
-#define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
-
-/* -mcpu=XX with XX = target DSP version number. */
-
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
- command options that have values. Its definition is an
- initializer with a subgrouping for each command option.
-
- Each subgrouping contains a string constant, that defines the
- fixed part of the option name, and the address of a variable.
- The variable, type `char *', is set to the variable part of the
- given option if the fixed part matches. The actual option name
- is made by appending `-m' to the specified name.
-
- Here is an example which defines `-mshort-data-NUMBER'. If the
- given option is `-mshort-data-512', the variable `m88k_short_data'
- will be set to the string `"512"'.
-
- extern char *m88k_short_data;
- #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
-
-extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
-
-#define TARGET_OPTIONS \
-{ {"rpts=", &c4x_rpts_cycles_string, \
- N_("Specify maximum number of iterations for RPTS") }, \
- {"cpu=", &c4x_cpu_version_string, \
- N_("Select CPU to generate code for") } }
-
/* Sometimes certain combinations of command options do not make sense
on a particular target machine. You can define a macro
`OVERRIDE_OPTIONS' to take account of this. This macro, if
sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
#define BITS_PER_UNIT 32
-#define BITS_PER_WORD 32
#define UNITS_PER_WORD 1
-#define POINTER_SIZE 32
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define FUNCTION_BOUNDARY 32
#define MAX_FIXED_MODE_SIZE 64 /* HImode. */
/* If a structure has a floating point field then force structure
- to have BLKMODE. */
-#define MEMBER_TYPE_FORCES_BLK(FIELD) \
- (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE)
+ to have BLKMODE, unless it is the only field. */
+#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
+ (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
/* Number of bits in the high and low parts of a two stage
load of an immediate constant. */
#define BITS_PER_HIGH 16
#define BITS_PER_LO_SUM 16
-/* Use the internal floating point stuff in the compiler and not the
- host floating point stuff. */
-
-#define REAL_ARITHMETIC
-
/* Define register numbers. */
/* Extended-precision registers. */
is defined since the MPY|ADD insns require the classes R0R1_REGS and
R2R3_REGS which are used by the function return registers (R0,R1) and
the register arguments (R2,R3), respectively. I'm reluctant to define
- this macro since it stomps on many potential optimisations. Ideally
+ this macro since it stomps on many potential optimizations. Ideally
it should have a register class argument so that not all the register
- classes gets penalised for the sake of a naughty few... For long
+ classes gets penalized for the sake of a naughty few... For long
double arithmetic we need two additional registers that we can use as
spill registers. */
/* #define STACK_GROWS_DOWNWARD. */
/* Like the dsp16xx, i370, i960, and we32k ports. */
-/* Define this if the nominal address of the stack frame
+/* Define this to nonzero if the nominal address of the stack frame
is at the high-address end of the local variables;
that is, each additional local variable allocated
goes at a more negative offset in the frame. */
-/* #define FRAME_GROWS_DOWNWARD. */
+#define FRAME_GROWS_DOWNWARD 0
/* Registers That Address the Stack Frame. */
int regno; \
int offset = 0; \
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
- if (regs_ever_live[regno] && ! call_used_regs[regno]) \
+ if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) \
offset += TARGET_PRESERVE_FLOAT \
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
(DEPTH) = -(offset + get_frame_size ()); \
int regno; \
int offset = 0; \
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
- if (regs_ever_live[regno] && ! call_used_regs[regno]) \
+ if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) \
offset += TARGET_PRESERVE_FLOAT \
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
(OFFSET) = -(offset + get_frame_size ()); \
/* Passing Function Arguments on the Stack. */
-#if 0
+#define PUSH_ARGS 1
#define PUSH_ROUNDING(BYTES) (BYTES)
-#endif
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
/* The following structure is used by calls.c, function.c, c4x.c. */
}
CUMULATIVE_ARGS;
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
(c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
#define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
-/* Never pass data by reference. */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-
/* 1 if N is a possible register number for function argument passing. */
#define FUNCTION_ARG_REGNO_P(REGNO) \
/* How Scalar Function Values Are Returned. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
+ gen_rtx_REG (TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
#define LIBCALL_VALUE(MODE) \
- gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */
+ gen_rtx_REG (MODE, R0_REGNO) /* Return in R0. */
#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
/* How Large Values Are Returned. */
#define DEFAULT_PCC_STRUCT_RETURN 0
-#define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */
-
-/* Varargs handling. */
-
-#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
- c4x_va_start (stdarg, valist, nextarg)
-
-#define EXPAND_BUILTIN_VA_ARG(valist, type) \
- c4x_va_arg (valist, type)
/* Generating Code for Profiling. */
fprintf (FILE, "\tpop\tar2\n"); \
}
-/* Implicit Calls to Library Routines. */
-
-#define MULQI3_LIBCALL "__mulqi3"
-#define DIVQI3_LIBCALL "__divqi3"
-#define UDIVQI3_LIBCALL "__udivqi3"
-#define MODQI3_LIBCALL "__modqi3"
-#define UMODQI3_LIBCALL "__umodqi3"
-
-#define DIVQF3_LIBCALL "__divqf3"
-
-#define MULHF3_LIBCALL "__mulhf3"
-#define DIVHF3_LIBCALL "__divhf3"
-
-#define MULHI3_LIBCALL "__mulhi3"
-#define SMULHI3_LIBCALL "__smulhi3_high"
-#define UMULHI3_LIBCALL "__umulhi3_high"
-#define DIVHI3_LIBCALL "__divhi3"
-#define UDIVHI3_LIBCALL "__udivhi3"
-#define MODHI3_LIBCALL "__modhi3"
-#define UMODHI3_LIBCALL "__umodhi3"
-
-#define FLOATHIQF2_LIBCALL "__floathiqf2"
-#define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
-#define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
-#define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
-
-#define FLOATHIHF2_LIBCALL "__floathihf2"
-#define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
-#define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
-#define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
-
-#define FFS_LIBCALL "__ffs"
-
-#define INIT_TARGET_OPTABS \
- do { \
- smul_optab->handlers[(int) QImode].libfunc \
- = init_one_libfunc (MULQI3_LIBCALL); \
- sdiv_optab->handlers[(int) QImode].libfunc \
- = init_one_libfunc (DIVQI3_LIBCALL); \
- udiv_optab->handlers[(int) QImode].libfunc \
- = init_one_libfunc (UDIVQI3_LIBCALL); \
- smod_optab->handlers[(int) QImode].libfunc \
- = init_one_libfunc (MODQI3_LIBCALL); \
- umod_optab->handlers[(int) QImode].libfunc \
- = init_one_libfunc (UMODQI3_LIBCALL); \
- sdiv_optab->handlers[(int) QFmode].libfunc \
- = init_one_libfunc (DIVQF3_LIBCALL); \
- smul_optab->handlers[(int) HFmode].libfunc \
- = init_one_libfunc (MULHF3_LIBCALL); \
- sdiv_optab->handlers[(int) HFmode].libfunc \
- = init_one_libfunc (DIVHF3_LIBCALL); \
- smul_optab->handlers[(int) HImode].libfunc \
- = init_one_libfunc (MULHI3_LIBCALL); \
- sdiv_optab->handlers[(int) HImode].libfunc \
- = init_one_libfunc (DIVHI3_LIBCALL); \
- udiv_optab->handlers[(int) HImode].libfunc \
- = init_one_libfunc (UDIVHI3_LIBCALL); \
- smod_optab->handlers[(int) HImode].libfunc \
- = init_one_libfunc (MODHI3_LIBCALL); \
- umod_optab->handlers[(int) HImode].libfunc \
- = init_one_libfunc (UMODHI3_LIBCALL); \
- ffs_optab->handlers[(int) QImode].libfunc \
- = init_one_libfunc (FFS_LIBCALL); \
- smulhi3_libfunc \
- = init_one_libfunc(SMULHI3_LIBCALL); \
- umulhi3_libfunc \
- = init_one_libfunc(UMULHI3_LIBCALL); \
- fix_truncqfhi2_libfunc \
- = init_one_libfunc(FIX_TRUNCQFHI2_LIBCALL); \
- fixuns_truncqfhi2_libfunc \
- = init_one_libfunc(FIXUNS_TRUNCQFHI2_LIBCALL); \
- fix_trunchfhi2_libfunc \
- = init_one_libfunc(FIX_TRUNCHFHI2_LIBCALL); \
- fixuns_trunchfhi2_libfunc \
- = init_one_libfunc(FIXUNS_TRUNCHFHI2_LIBCALL); \
- floathiqf2_libfunc \
- = init_one_libfunc(FLOATHIQF2_LIBCALL); \
- floatunshiqf2_libfunc \
- = init_one_libfunc(FLOATUNSHIQF2_LIBCALL); \
- floathihf2_libfunc \
- = init_one_libfunc(FLOATHIHF2_LIBCALL); \
- floatunshihf2_libfunc \
- = init_one_libfunc(FLOATUNSHIHF2_LIBCALL); \
- } while (0)
-
-#define TARGET_MEM_FUNCTIONS
-
-/* Add any extra modes needed to represent the condition code.
-
- On the C4x, we have a "no-overflow" mode which is used when an ADD,
- SUB, NEG, or MPY insn is used to set the condition code. This is
- to prevent the combiner from optimising away a following CMP of the
- result with zero when a signed conditional branch or load insn
- follows.
-
- The problem is a subtle one and deals with the manner in which the
- negative condition (N) flag is used on the C4x. This flag does not
- reflect the status of the actual result but of the ideal result had
- no overflow occurred (when considering signed operands).
-
- For example, 0x7fffffff + 1 => 0x80000000 Z=0 V=1 N=0 C=0. Here
- the flags reflect the untruncated result, not the actual result.
- While the actual result is less than zero, the N flag is not set
- since the ideal result of the addition without truncation would
- have been positive.
-
- Note that the while the N flag is handled differently to most other
- architectures, the use of it is self consistent and is not the
- cause of the problem.
-
- Logical operations set the N flag to the MSB of the result so if
- the result is negative, N is 1. However, integer and floating
- point operations set the N flag to be the MSB of the result
- exclusive ored with the overflow (V) flag. Thus if an overflow
- occurs and the result does not have the MSB set (i.e., the result
- looks like a positive number), the N flag is set. Conversely, if
- an overflow occurs and the MSB of the result is set, N is set to 0.
- Thus the N flag represents the sign of the result if it could have
- been stored without overflow but does not represent the apparent
- sign of the result. Note that most architectures set the N flag to
- be the MSB of the result.
-
- The C4x approach to setting the N flag simplifies signed
- conditional branches and loads which only have to test the state of
- the N flag, whereas most architectures have to look at both the N
- and V flags. The disadvantage is that there is no flag giving the
- status of the sign bit of the operation. However, there are no
- conditional load or branch instructions that make use of this
- feature (e.g., BMI---branch minus) instruction. Note that BN and
- BLT are identical in the C4x.
-
- To handle the problem where the N flag is set differently whenever
- there is an overflow we use a different CC mode, CC_NOOVmode which
- says that the CC reflects the comparison of the result against zero
- if no overflow occurred.
-
- For example,
-
- [(set (reg:CC_NOOV 21)
- (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "")
- (match_operand:QI 2 "src_operand" ""))
- (const_int 0)))
- (set (match_operand:QI 0 "ext_reg_operand" "")
- (minus:QI (match_dup 1)
- (match_dup 2)))]
-
- Note that there is no problem for insns that don't return a result
- like CMP, since the CC reflects the effect of operation.
-
- An example of a potential problem is when GCC
- converts (LTU (MINUS (0x80000000) (0x7fffffff) (0x80000000)))
- to (LEU (MINUS (0x80000000) (0x7fffffff) (0x7fffffff)))
- to (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000)))
-
- Now (MINUS (0x80000000) (0x7fffffff)) returns 0x00000001 but the
- C4x sets the N flag since the result without overflow would have
- been 0xffffffff when treating the operands as signed integers.
- Thus (GE (MINUS (0x80000000) (0x7fffffff) (0x00000000))) sets the N
- flag but (GE (0x00000001)) does not set the N flag.
-
- The upshot is that we can not use signed branch and conditional
- load instructions after an add, subtract, neg, abs or multiply.
- We must emit a compare insn to check the result against 0. */
-
-#define EXTRA_CC_MODES CC(CC_NOOVmode, "CC_NOOV")
-
/* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
or MULT.
CCmode should be used when no special processing is needed. */
#ifndef REG_OK_STRICT
-/* Nonzero if X is a hard or pseudo reg that can be used as an base. */
+/* Nonzero if X is a hard or pseudo reg that can be used as a base. */
#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
- if (c4x_check_legit_addr (MODE, X, 0)) \
+ if (c4x_legitimate_address_p (MODE, X, 0)) \
goto ADDR; \
}
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
- if (c4x_check_legit_addr (MODE, X, 1)) \
+ if (c4x_legitimate_address_p (MODE, X, 1)) \
goto ADDR; \
}
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
{ \
rtx new; \
+ \
new = c4x_legitimize_address (X, MODE); \
if (new != NULL_RTX) \
{ \
if (! TARGET_SMALL) \
{ \
int i; \
- X = gen_rtx_LO_SUM (GET_MODE (X), \
+ (X) = gen_rtx_LO_SUM (GET_MODE (X), \
gen_rtx_HIGH (GET_MODE (X), X), X); \
i = push_reload (XEXP (X, 0), NULL_RTX, \
&XEXP (X, 0), NULL, \
rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
rld[i].nocombine = 1; \
} \
+ else \
+ { \
+ /* make_memloc in reload will substitute invalid memory \
+ references. We need to fix them up. */ \
+ (X) = gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, DP_REGNO), (X)); \
+ } \
goto WIN; \
} \
else if (MODE != HImode \
}
/* No mode-dependent addresses on the C4x are autoincrements. */
-
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
- if (GET_CODE (ADDR) == PRE_DEC \
- || GET_CODE (ADDR) == POST_DEC \
- || GET_CODE (ADDR) == PRE_INC \
- || GET_CODE (ADDR) == POST_INC \
- || GET_CODE (ADDR) == POST_MODIFY \
+ if (GET_CODE (ADDR) == POST_MODIFY \
|| GET_CODE (ADDR) == PRE_MODIFY) \
goto LABEL
#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
-/* Define this macro if references to a symbol must be treated
- differently depending on something about the variable or
- function named by the symbol (such as what section it is in).
-
- The macro definition, if any, is executed immediately after the
- rtl for DECL or other node is created.
- The value of the rtl will be a `mem' whose address is a
- `symbol_ref'.
-
- The usual thing for this macro to do is to a flag in the
- `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
- name string in the `symbol_ref' (if one bit is not enough
- information).
-
- On the C4x we use this to indicate if a symbol is in text or
- data space. */
-
-#define ENCODE_SECTION_INFO(DECL) c4x_encode_section_info (DECL);
-
-/* Descripting Relative Cost of Operations. */
-
-/* Provide the costs of a rtl expression. This is in the body of a
- switch on CODE.
-
- Note that we return, rather than break so that rtx_cost doesn't
- include CONST_COSTS otherwise expand_mult will think that it is
- cheaper to synthesise a multiply rather than to use a multiply
- instruction. I think this is because the algorithm synth_mult
- doesn't take into account the loading of the operands, whereas the
- calculation of mult_cost does.
-*/
-
-
-#define RTX_COSTS(RTX, CODE, OUTER_CODE) \
- case PLUS: \
- case MINUS: \
- case AND: \
- case IOR: \
- case XOR: \
- case ASHIFT: \
- case ASHIFTRT: \
- case LSHIFTRT: \
- return COSTS_N_INSNS (1); \
- case MULT: \
- return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
- || TARGET_MPYI ? 1 : 14); \
- case DIV: \
- case UDIV: \
- case MOD: \
- case UMOD: \
- return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
- ? 15 : 50);
-
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch.
-
- An insn is assumed to cost 4 units.
- COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
-
- Some small integers are effectively free for the C40. We should
- also consider if we are using the small memory model. With
- the big memory model we require an extra insn for a constant
- loaded from memory.
-
- This is used by expand_binop to decide whether to force a constant
- into a register. If the cost is greater than 2 and the constant
- is used within a short loop, it gets forced into a register.
- Ideally, there should be some weighting as to how mnay times it is used
- within the loop. */
-
-#define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
-
-#define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
- || (C) == IOR || (C) == XOR)
-
-#define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST_INT: \
- if (c4x_J_constant (RTX)) \
- return 0; \
- if (! TARGET_C3X \
- && OUTER_CODE == AND \
- && GET_CODE (RTX) == CONST_INT \
- && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \
- return 0; \
- if (! TARGET_C3X \
- && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \
- && GET_CODE (RTX) == CONST_INT \
- && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \
- return 0; \
- if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
- return 3; \
- if (LOGICAL_CODE_P (OUTER_CODE) \
- ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
- return 2; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 4; \
- case CONST_DOUBLE: \
- if (c4x_H_constant (RTX)) \
- return 2; \
- if (GET_MODE (RTX) == QFmode) \
- return 4; \
- else \
- return 8;
-
-/* Compute the cost of an address. This is meant to approximate the size
- and/or execution delay of an insn using that address. If the cost is
- approximated by the RTL complexity, including CONST_COSTS above, as
- is usually the case for CISC machines, this macro should not be defined.
- For aggressively RISCy machines, only one insn format is allowed, so
- this macro should be a constant. The value of this macro only matters
- for valid addresses. We handle the most common address without
- a call to c4x_address_cost. */
-
-#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
+/* Describing Relative Cost of Operations. */
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
if (REG_P (OP1) && ! REG_P (OP0)) \
#define DATA_SECTION_ASM_OP "\t.data"
-#define USE_CONST_SECTION 1
-
-#define CONST_SECTION_ASM_OP "\t.sect\t\".const\""
+#define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
/* Do not use .init section so __main will be called on startup. This will
call __do_global_ctors and prepare for __do_global_dtors on exit. */
#define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
-#undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_init, in_fini
-
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS \
- CONST_SECTION_FUNCTION \
- INIT_SECTION_FUNCTION \
- FINI_SECTION_FUNCTION
-
-#define INIT_SECTION_FUNCTION \
-extern void init_section PARAMS ((void)); \
-void \
-init_section () \
-{ \
- if (in_section != in_init) \
- { \
- fprintf (asm_out_file, ";\t.init\n"); \
- in_section = in_init; \
- } \
-}
-
-#define FINI_SECTION_FUNCTION \
-void \
-fini_section () \
-{ \
- if (in_section != in_fini) \
- { \
- fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
- in_section = in_fini; \
- } \
-}
-
-#define READONLY_DATA_SECTION() const_section ()
-
-#define CONST_SECTION_FUNCTION \
-void \
-const_section () \
-{ \
- if (! USE_CONST_SECTION) \
- text_section(); \
- else if (in_section != in_const) \
- { \
- fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \
- in_section = in_const; \
- } \
-}
-
-#define ASM_STABS_OP "\t.stabs\t"
-
/* Switch into a generic section. */
#define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
-/* A C statement or statements to switch to the appropriate
- section for output of DECL. DECL is either a `VAR_DECL' node
- or a constant of some sort. RELOC indicates whether forming
- the initial value of DECL requires link-time relocations. */
-
-#define SELECT_SECTION(DECL, RELOC, ALIGN) \
-{ \
- if (TREE_CODE (DECL) == STRING_CST) \
- { \
- if (! flag_writable_strings) \
- const_section (); \
- else \
- data_section (); \
- } \
- else if (TREE_CODE (DECL) == VAR_DECL) \
- { \
- if ((0 && RELOC) /* Should be (flag_pic && RELOC). */ \
- || ! TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \
- || ! DECL_INITIAL (DECL) \
- || (DECL_INITIAL (DECL) != error_mark_node \
- && ! TREE_CONSTANT (DECL_INITIAL (DECL)))) \
- data_section (); \
- else \
- const_section (); \
- } \
- else \
- const_section (); \
-}
-
-/* The TI assembler wants to have hex numbers this way. */
-
-#undef HOST_WIDE_INT_PRINT_HEX
-#ifndef HOST_WIDE_INT_PRINT_HEX
-# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
-# define HOST_WIDE_INT_PRINT_HEX "0%xh"
-# else
-# if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
-# define HOST_WIDE_INT_PRINT_HEX "0%lxh"
-# else
-# define HOST_WIDE_INT_PRINT_HEX "0%llxh"
-# endif
-# endif
-#endif /* ! HOST_WIDE_INT_PRINT_HEX */
-
-/* A C statement or statements to switch to the appropriate
- section for output of RTX in mode MODE. RTX is some kind
- of constant in RTL. The argument MODE is redundant except
- in the case of a `const_int' rtx. Currently, these always
- go into the const section. */
-
-#define SELECT_RTX_SECTION(MODE, RTX, ALIGN) const_section()
-
/* Overall Framework of an Assembler File. */
-/* We need to have a data section we can identify so that we can set
- the DP register back to a data pointer in the small memory model.
- This is only required for ISRs if we are paranoid that someone
- may have quietly changed this register on the sly. */
-
-#define ASM_FILE_START(FILE) \
-{ \
- int dspversion = 0; \
- if (TARGET_C30) dspversion = 30; \
- if (TARGET_C31) dspversion = 31; \
- if (TARGET_C32) dspversion = 32; \
- if (TARGET_C40) dspversion = 40; \
- if (TARGET_C44) dspversion = 44; \
- fprintf (FILE, "\t.version\t%d\n", dspversion); \
- fprintf (FILE, "\t.file\t"); \
- if (TARGET_TI) \
- { \
- const char *p; \
- const char *after_dir = main_input_filename; \
- for (p = main_input_filename; *p; p++) \
- if (*p == '/') \
- after_dir = p + 1; \
- output_quoted_string (FILE, after_dir); \
- } \
- else \
- output_quoted_string (FILE, main_input_filename); \
- fputs ("\n\t.data\ndata_sec:\n", FILE); \
-}
#define ASM_COMMENT_START ";"
#define NO_DOT_IN_LABEL /* Only required for TI format. */
-#define ASM_OUTPUT_LABEL(FILE, NAME) \
-do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0);
-
-#define ASM_GLOBALIZE_LABEL(FILE, NAME) \
- do { \
- fprintf (FILE, "\t.global\t"); \
- assemble_name (FILE, NAME); \
- fputs ("\n", FILE); \
- c4x_global_label (NAME); \
- } while (0);
+/* Globalizing directive for a label. */
+#define GLOBAL_ASM_OP "\t.global\t"
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
c4x_external_ref (NAME)
-/* A C statement to output on FILE an assembler pseudo-op to
- declare a library function named external.
- (Only needed to keep asm30 happy for ___divqf3 etc.) */
-
-#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
-c4x_external_ref (XSTR (FUN, 0))
-
-#define ASM_FILE_END(FILE) \
-c4x_file_end (FILE)
-
/* The prefix to add to user-visible assembler symbols. */
#define USER_LABEL_PREFIX "_"
-/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
-
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
-asm_fprintf (FILE, "%s%d:\n", PREFIX, NUM)
-
/* This is how to store into the string LABEL
the symbol_ref name of an internal numbered label where
PREFIX is the class of label and NUM is the number within the class.
This is suitable for output with `assemble_name'. */
#define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
- sprintf (BUFFER, "*%s%d", PREFIX, NUM)
-
-/* Store in OUTPUT a string (made with alloca) containing
- an assembler-name for a local static variable named NAME.
- LABELNO is an integer which is different for each call. */
-
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s$%d", (NAME), (LABELNO)))
+ sprintf (BUFFER, "*%s%lu", PREFIX, (unsigned long)(NUM))
/* A C statement to output to the stdio stream STREAM assembler code which
defines (equates) the symbol NAME to have the value VALUE. */
#define DOUBLE_TYPE_SIZE 32
#define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
-/* Allow #sccs in preprocessor. */
-
-#define SCCS_DIRECTIVE
-
/* Output #ident as a .ident. */
#define ASM_OUTPUT_IDENT(FILE, NAME) \
fprintf (FILE, "\t.ident \"%s\"\n", NAME);
-#define CPP_PREDEFINES ""
-
/* Output of Uninitialized Variables. */
/* This says how to output an assembler line to define a local
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
( fputs ("\t.bss\t", FILE), \
assemble_name (FILE, (NAME)), \
- fprintf (FILE, ",%u\n", (ROUNDED)))
+ fprintf (FILE, ",%u\n", (int)(ROUNDED)))
/* This says how to output an assembler line to define a global
uninitialized variable. */
assemble_name (FILE, (NAME)), \
fputs ("\n\t.bss\t", FILE), \
assemble_name (FILE, (NAME)), \
- fprintf (FILE, ",%u\n", (ROUNDED)))
+ fprintf (FILE, ",%u\n", (int)(ROUNDED)))
#undef ASM_OUTPUT_BSS
#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
assemble_name (FILE, (NAME)), \
fputs ("\n\t.bss\t", FILE), \
assemble_name (FILE, (NAME)), \
- fprintf (FILE, ",%u\n", (SIZE)))
+ fprintf (FILE, ",%u\n", (int)(SIZE)))
/* Macros Controlling Initialization Routines. */
#define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
/* C4x specific pragmas. */
-#define REGISTER_TARGET_PRAGMAS(PFILE) do { \
- cpp_register_pragma (PFILE, 0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
- cpp_register_pragma (PFILE, 0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
- cpp_register_pragma (PFILE, 0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
- cpp_register_pragma (PFILE, 0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
- cpp_register_pragma (PFILE, 0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
- cpp_register_pragma (PFILE, 0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
- cpp_register_pragma (PFILE, 0, "FUNC_NEVER_RETURNS", \
- c4x_pr_FUNC_NEVER_RETURNS); \
- cpp_register_pragma (PFILE, 0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
- cpp_register_pragma (PFILE, 0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
- cpp_register_pragma (PFILE, 0, "INTERRUPT", c4x_pr_INTERRUPT); \
+#define REGISTER_TARGET_PRAGMAS() do { \
+ c_register_pragma (0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
+ c_register_pragma (0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
+ c_register_pragma (0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
+ c_register_pragma (0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
+ c_register_pragma (0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
+ c_register_pragma (0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
+ c_register_pragma (0, "FUNC_NEVER_RETURNS", c4x_pr_FUNC_NEVER_RETURNS); \
+ c_register_pragma (0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
+ c_register_pragma (0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
+ c_register_pragma (0, "INTERRUPT", c4x_pr_INTERRUPT); \
} while (0)
/* Assembler Commands for Alignment. */
to avoid conflict with TI's use of .def). */
#define SDB_DELIM "\n"
-#define SDB_DEBUGGING_INFO
+#define SDB_DEBUGGING_INFO 1
/* Don't use octal since this can confuse gas for the c4x. */
#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
{ \
if (TARGET_C3X) \
{ \
- asm_fprintf (FILE, "\tldiu\t0,ar1\n"); \
- asm_fprintf (FILE, "\tlsh\t16,ar1\n"); \
- asm_fprintf (FILE, "\tor\t0,ar1\n"); \
- asm_fprintf (FILE, "\tldiu\t0,ar0\n"); \
- asm_fprintf (FILE, "\tbud\tar1\n"); \
- asm_fprintf (FILE, "\tlsh\t16,ar0\n"); \
- asm_fprintf (FILE, "\tor\t0,ar0\n"); \
- asm_fprintf (FILE, "\tor\t1000h,st\n"); \
+ fprintf (FILE, "\tldiu\t0,ar1\n"); \
+ fprintf (FILE, "\tlsh\t16,ar1\n"); \
+ fprintf (FILE, "\tor\t0,ar1\n"); \
+ fprintf (FILE, "\tldiu\t0,ar0\n"); \
+ fprintf (FILE, "\tbud\tar1\n"); \
+ fprintf (FILE, "\tlsh\t16,ar0\n"); \
+ fprintf (FILE, "\tor\t0,ar0\n"); \
+ fprintf (FILE, "\tor\t1000h,st\n"); \
} \
else \
{ \
- asm_fprintf (FILE, "\tlaj\t$+4\n"); \
- asm_fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
- asm_fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
- asm_fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
- asm_fprintf (FILE, "\tbud\tar1\n"); \
- asm_fprintf (FILE, "\tnop\n"); \
- asm_fprintf (FILE, "\tnop\n"); \
- asm_fprintf (FILE, "\tor\t1000h,st\n"); \
- asm_fprintf (FILE, "\t.word\t0\n"); \
- asm_fprintf (FILE, "\t.word\t0\n"); \
+ fprintf (FILE, "\tlaj\t$+4\n"); \
+ fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
+ fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
+ fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
+ fprintf (FILE, "\tbud\tar1\n"); \
+ fprintf (FILE, "\tnop\n"); \
+ fprintf (FILE, "\tnop\n"); \
+ fprintf (FILE, "\tor\t1000h,st\n"); \
+ fprintf (FILE, "\t.word\t0\n"); \
+ fprintf (FILE, "\t.word\t0\n"); \
} \
}
tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
size_int (16), 0, 1); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
- gen_rtx (CONST_INT, VOIDmode, 0x5069), \
- size_int (16), 0, 1); \
+ GEN_INT (0x5069), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
- emit_move_insn (gen_rtx (MEM, QImode, \
- plus_constant (tramp, 0)), tmp1); \
- tmp1 = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, \
- 0xffff), 0); \
+ emit_move_insn (gen_rtx_MEM (QImode, \
+ plus_constant (TRAMP, 0)), tmp1); \
+ tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
- gen_rtx (CONST_INT, VOIDmode, 0x1069), \
- size_int (16), 0, 1); \
+ GEN_INT (0x1069), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
- emit_move_insn (gen_rtx (MEM, QImode, \
- plus_constant (tramp, 2)), tmp1); \
+ emit_move_insn (gen_rtx_MEM (QImode, \
+ plus_constant (TRAMP, 2)), tmp1); \
tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
size_int (16), 0, 1); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
- gen_rtx (CONST_INT, VOIDmode, 0x5068), \
- size_int (16), 0, 1); \
+ GEN_INT (0x5068), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
- emit_move_insn (gen_rtx (MEM, QImode, \
- plus_constant (tramp, 3)), tmp1); \
- tmp1 = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, \
- 0xffff), 0); \
+ emit_move_insn (gen_rtx_MEM (QImode, \
+ plus_constant (TRAMP, 3)), tmp1); \
+ tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
- gen_rtx (CONST_INT, VOIDmode, 0x1068), \
- size_int (16), 0, 1); \
+ GEN_INT (0x1068), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
- emit_move_insn (gen_rtx (MEM, QImode, \
- plus_constant (tramp, 6)), tmp1); \
+ emit_move_insn (gen_rtx_MEM (QImode, \
+ plus_constant (TRAMP, 6)), tmp1); \
} \
else \
{ \
- emit_move_insn (gen_rtx (MEM, QImode, \
+ emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 8)), FNADDR); \
- emit_move_insn (gen_rtx (MEM, QImode, \
+ emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 9)), CXT); \
} \
}
#define BSS_SECTION_ASM_OP "\t.bss"
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
- asm_fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
+ fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
/* This is how to output an insn to pop a register from the stack.
It need not be very fast code. */
#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
- asm_fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
+ fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
is done just by pretending it is already truncated. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
-/* We need to use direct addressing for large constants and addresses
- that cannot fit within an instruction. We must check for these
- after after the final jump optimisation pass, since this may
- introduce a local_move insn for a SYMBOL_REF. This pass
- must come before delayed branch slot filling since it can generate
- additional instructions. */
-
-#define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
-
#define DBR_OUTPUT_SEQEND(FILE) \
if (final_sequence != NULL_RTX) \
{ \
#define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
-/* Define the codes that are matched by predicates in c4x.c. */
-
-#define PREDICATE_CODES \
- {"fp_zero_operand", {CONST_DOUBLE}}, \
- {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
- {"stik_const_operand", {CONST_INT}}, \
- {"not_const_operand", {CONST_INT}}, \
- {"reg_operand", {REG, SUBREG}}, \
- {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
- {"r0r1_reg_operand", {REG, SUBREG}}, \
- {"r2r3_reg_operand", {REG, SUBREG}}, \
- {"ext_low_reg_operand", {REG, SUBREG}}, \
- {"ext_reg_operand", {REG, SUBREG}}, \
- {"std_reg_operand", {REG, SUBREG}}, \
- {"std_or_reg_operand", {REG, SUBREG}}, \
- {"addr_reg_operand", {REG, SUBREG}}, \
- {"index_reg_operand", {REG, SUBREG}}, \
- {"dp_reg_operand", {REG}}, \
- {"sp_reg_operand", {REG}}, \
- {"st_reg_operand", {REG}}, \
- {"rc_reg_operand", {REG}}, \
- {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
- {"dst_operand", {SUBREG, REG, MEM}}, \
- {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
- {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
- {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
- {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
- {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
- {"par_ind_operand", {MEM}}, \
- {"parallel_operand", {SUBREG, REG, MEM}}, \
- {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
- {"mem_operand", {MEM}},
-
-
/* Define the intrinsic functions for the c3x/c4x. */
enum c4x_builtins
C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
};
+
+
+/* Hack to overcome use of libgcc2.c using auto-host.h to determine
+ HAVE_GAS_HIDDEN. */
+#undef HAVE_GAS_HIDDEN
OSDN Git Service
