* config/bfin/constraints.md: New file.

[pf3gnuchains/gcc-fork.git] / gcc / config / bfin / predicates.md

diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index 1415ea0..23ca2e4 100644 (file)
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -1,12 +1,12 @@
 ;; Predicate definitions for the Blackfin.
-;; Copyright (C) 2005, 2006  Free Software Foundation, Inc.
+;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
 ;; Contributed by Analog Devices.
 ;;
 ;; This file is part of GCC.
 ;;
 ;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
 ;; any later version.
 ;;
 ;; GCC is distributed in the hope that it will be useful,
@@ -15,9 +15,8 @@
 ;; GNU General Public License for more details.
 ;;
 ;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-;; Boston, MA 02110-1301, USA.
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
 
 ;; Return nonzero iff OP is one of the integer constants 1 or 2.
 (define_predicate "pos_scale_operand"
@@ -35,7 +34,7 @@
 ;; if the constant would be cheap to load.
 (define_predicate "highbits_operand"
   (and (match_code "const_int")
-       (match_test "log2constp (-INTVAL (op)) && !CONST_7BIT_IMM_P (INTVAL (op))")))
+       (match_test "log2constp (-INTVAL (op)) && !satisfies_constraint_Ks7 (op)")))
 
 ;; Return nonzero if OP is suitable as a right-hand side operand for an
 ;; andsi3 operation.
@@ -76,6 +75,11 @@
   return 1;
 })
 
+;; Return nonzero if OP is a D register.
+(define_predicate "d_register_operand"
+  (and (match_code "reg")
+       (match_test "D_REGNO_P (REGNO (op))")))
+
 ;; Return nonzero if OP is a LC register.
 (define_predicate "lc_register_operand"
   (and (match_code "reg")
@@ -91,11 +95,11 @@
   (and (match_code "reg")
        (match_test "REGNO (op) == REG_LB0 || REGNO (op) == REG_LB1")))
 
-;; Return nonzero if OP is a register or a 7 bit signed constant.
+;; Return nonzero if OP is a register or a 7-bit signed constant.
 (define_predicate "reg_or_7bit_operand"
   (ior (match_operand 0 "register_operand")
        (and (match_code "const_int")
-           (match_test "CONST_7BIT_IMM_P (INTVAL (op))"))))
+           (match_test "satisfies_constraint_Ks7 (op)"))))
 
 ;; Return nonzero if OP is a register other than DREG and PREG.
 (define_predicate "nondp_register_operand"
@@ -114,6 +118,13 @@
   (ior (match_operand 0 "nondp_register_operand")
        (match_operand 0 "memory_operand")))
 
+;; Return nonzero if OP is a register or, when negated, a 7-bit signed
+;; constant.
+(define_predicate "reg_or_neg7bit_operand"
+  (ior (match_operand 0 "register_operand")
+       (and (match_code "const_int")
+           (match_test "satisfies_constraint_KN7 (op)"))))
+
 ;; Used for secondary reloads, this function returns 1 if OP is of the
 ;; form (plus (fp) (const_int)).
 (define_predicate "fp_plus_const_operand"
@@ -164,3 +175,31 @@
 ;; Test for an operator valid in a conditional branch
 (define_predicate "bfin_cbranch_operator"
   (match_code "eq,ne"))
+
+;; The following two are used to compute the addrtype attribute.  They return
+;; true if passed a memory address usable for a 16-bit load or store using a
+;; P or I register, respectively.  If neither matches, we know we have a
+;; 32-bit instruction.
+(define_predicate "mem_p_address_operand"
+  (match_code "mem")
+{
+  if (effective_address_32bit_p (op, mode))
+    return 0;
+  op = XEXP (op, 0);
+  if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
+    op = XEXP (op, 0);
+  gcc_assert (REG_P (op));
+  return PREG_P (op);
+})
+
+(define_predicate "mem_i_address_operand"
+  (match_code "mem")
+{
+  if (effective_address_32bit_p (op, mode))
+    return 0;
+  op = XEXP (op, 0);
+  if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
+    op = XEXP (op, 0);
+  gcc_assert (REG_P (op));
+  return IREG_P (op);
+})