/* Definitions for the Blackfin port.
- Copyright (C) 2005 Free Software Foundation, Inc.
+ Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
Contributed by Analog Devices.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 2, or (at your
+ by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
License for more details.
You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING. If not, write to
- the Free Software Foundation, 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
#ifndef _BFIN_CONFIG
#define _BFIN_CONFIG
extern int target_flags;
+#ifndef DEFAULT_CPU_TYPE
+#define DEFAULT_CPU_TYPE BFIN_CPU_BF532
+#endif
+
/* Predefinition in the preprocessor for this target machine */
#ifndef TARGET_CPU_CPP_BUILTINS
-#define TARGET_CPU_CPP_BUILTINS() \
- do \
- { \
- builtin_define ("bfin"); \
- builtin_define ("BFIN"); \
+#define TARGET_CPU_CPP_BUILTINS() \
+ do \
+ { \
+ builtin_define_std ("bfin"); \
+ builtin_define_std ("BFIN"); \
builtin_define ("__ADSPBLACKFIN__"); \
+ builtin_define ("__ADSPLPBLACKFIN__"); \
+ \
+ switch (bfin_cpu_type) \
+ { \
+ case BFIN_CPU_BF522: \
+ builtin_define ("__ADSPBF522__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF523: \
+ builtin_define ("__ADSPBF523__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF524: \
+ builtin_define ("__ADSPBF524__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF525: \
+ builtin_define ("__ADSPBF525__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF526: \
+ builtin_define ("__ADSPBF526__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF527: \
+ builtin_define ("__ADSPBF527__"); \
+ builtin_define ("__ADSPBF52x__"); \
+ break; \
+ case BFIN_CPU_BF531: \
+ builtin_define ("__ADSPBF531__"); \
+ break; \
+ case BFIN_CPU_BF532: \
+ builtin_define ("__ADSPBF532__"); \
+ break; \
+ case BFIN_CPU_BF533: \
+ builtin_define ("__ADSPBF533__"); \
+ break; \
+ case BFIN_CPU_BF534: \
+ builtin_define ("__ADSPBF534__"); \
+ break; \
+ case BFIN_CPU_BF536: \
+ builtin_define ("__ADSPBF536__"); \
+ break; \
+ case BFIN_CPU_BF537: \
+ builtin_define ("__ADSPBF537__"); \
+ break; \
+ case BFIN_CPU_BF538: \
+ builtin_define ("__ADSPBF538__"); \
+ break; \
+ case BFIN_CPU_BF539: \
+ builtin_define ("__ADSPBF539__"); \
+ break; \
+ case BFIN_CPU_BF542: \
+ builtin_define ("__ADSPBF542__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF544: \
+ builtin_define ("__ADSPBF544__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF548: \
+ builtin_define ("__ADSPBF548__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF547: \
+ builtin_define ("__ADSPBF547__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF549: \
+ builtin_define ("__ADSPBF549__"); \
+ builtin_define ("__ADSPBF54x__"); \
+ break; \
+ case BFIN_CPU_BF561: \
+ builtin_define ("__ADSPBF561__"); \
+ break; \
+ } \
+ \
+ if (bfin_si_revision != -1) \
+ { \
+ /* space of 0xnnnn and a NUL */ \
+ char *buf = alloca (7); \
+ \
+ sprintf (buf, "0x%04x", bfin_si_revision); \
+ builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
+ } \
+ \
+ if (bfin_workarounds) \
+ builtin_define ("__WORKAROUNDS_ENABLED"); \
+ if (ENABLE_WA_SPECULATIVE_LOADS) \
+ builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
+ if (ENABLE_WA_SPECULATIVE_SYNCS) \
+ builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
+ \
if (TARGET_FDPIC) \
- builtin_define ("__BFIN_FDPIC__"); \
- if (TARGET_ID_SHARED_LIBRARY) \
+ { \
+ builtin_define ("__BFIN_FDPIC__"); \
+ builtin_define ("__FDPIC__"); \
+ } \
+ if (TARGET_ID_SHARED_LIBRARY \
+ && !TARGET_SEP_DATA) \
builtin_define ("__ID_SHARED_LIB__"); \
- } \
+ if (flag_no_builtin) \
+ builtin_define ("__NO_BUILTIN"); \
+ } \
while (0)
#endif
#define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
+ %{!mcpu=*:-mcpu=bf532} \
+ %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
%{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
%{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
"
# define SUBTARGET_DRIVER_SELF_SPECS
#endif
-#define LINK_GCC_C_SEQUENCE_SPEC \
- "%{mfdpic:%{!static: %L} %{static: %G %L %G}} \
- %{!mfdpic:%G %L %G}"
+#define LINK_GCC_C_SEQUENCE_SPEC "\
+ %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
+"
/* A C string constant that tells the GCC driver program options to pass to
the assembler. It can also specify how to translate options you give to GNU
/* Generate DSP instructions, like DSP halfword loads */
#define TARGET_DSP (1)
-#define TARGET_DEFAULT (MASK_SPECLD_ANOMALY | MASK_CSYNC_ANOMALY)
+#define TARGET_DEFAULT 0
/* Maximum number of library ids we permit */
#define MAX_LIBRARY_ID 255
/* Define this if the above stack space is to be considered part of the
* space allocated by the caller. */
-#define OUTGOING_REG_PARM_STACK_SPACE
+#define OUTGOING_REG_PARM_STACK_SPACE 1
/* Define this if the maximum size of all the outgoing args is to be
accumulated and pushed during the prologue. The amount can be
- found in the variable current_function_outgoing_args_size. */
+ found in the variable crtl->outgoing_args_size. */
#define ACCUMULATE_OUTGOING_ARGS 1
/* Value should be nonzero if functions must have frame pointers.
/*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
+/* If defined, a C expression to compute the alignment for a local
+ variable. TYPE is the data type, and ALIGN is the alignment that
+ the object would ordinarily have. The value of this macro is used
+ instead of that alignment to align the object.
+
+ If this macro is not defined, then ALIGN is used.
+
+ One use of this macro is to increase alignment of medium-size
+ data to make it all fit in fewer cache lines. */
+
+#define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
+
/* Make strings word-aligned so strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
CCREGS,
EVEN_DREGS,
ODD_DREGS,
+ D0REGS,
+ D1REGS,
+ D2REGS,
+ D3REGS,
+ D4REGS,
+ D5REGS,
+ D6REGS,
+ D7REGS,
DREGS,
+ P0REGS,
FDPIC_REGS,
FDPIC_FPTR_REGS,
PREGS_CLOBBERED,
"CCREGS", \
"EVEN_DREGS", \
"ODD_DREGS", \
+ "D0REGS", \
+ "D1REGS", \
+ "D2REGS", \
+ "D3REGS", \
+ "D4REGS", \
+ "D5REGS", \
+ "D6REGS", \
+ "D7REGS", \
"DREGS", \
+ "P0REGS", \
"FDPIC_REGS", \
"FDPIC_FPTR_REGS", \
"PREGS_CLOBBERED", \
{ 0x00000000, 0x4 }, /* CCREGS */ \
{ 0x00000055, 0 }, /* EVEN_DREGS */ \
{ 0x000000aa, 0 }, /* ODD_DREGS */ \
+ { 0x00000001, 0 }, /* D0REGS */ \
+ { 0x00000002, 0 }, /* D1REGS */ \
+ { 0x00000004, 0 }, /* D2REGS */ \
+ { 0x00000008, 0 }, /* D3REGS */ \
+ { 0x00000010, 0 }, /* D4REGS */ \
+ { 0x00000020, 0 }, /* D5REGS */ \
+ { 0x00000040, 0 }, /* D6REGS */ \
+ { 0x00000080, 0 }, /* D7REGS */ \
{ 0x000000ff, 0 }, /* DREGS */ \
+ { 0x00000100, 0x000 }, /* P0REGS */ \
{ 0x00000800, 0x000 }, /* FDPIC_REGS */ \
{ 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
{ 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
#define REGNO_OK_FOR_INDEX_P(X) 0
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(LETTER) \
- ((LETTER) == 'a' ? PREGS : \
- (LETTER) == 'Z' ? FDPIC_REGS : \
- (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
- (LETTER) == 'd' ? DREGS : \
- (LETTER) == 'z' ? PREGS_CLOBBERED : \
- (LETTER) == 'D' ? EVEN_DREGS : \
- (LETTER) == 'W' ? ODD_DREGS : \
- (LETTER) == 'e' ? AREGS : \
- (LETTER) == 'A' ? EVEN_AREGS : \
- (LETTER) == 'B' ? ODD_AREGS : \
- (LETTER) == 'b' ? IREGS : \
- (LETTER) == 'v' ? BREGS : \
- (LETTER) == 'f' ? MREGS : \
- (LETTER) == 'c' ? CIRCREGS : \
- (LETTER) == 'C' ? CCREGS : \
- (LETTER) == 't' ? LT_REGS : \
- (LETTER) == 'k' ? LC_REGS : \
- (LETTER) == 'u' ? LB_REGS : \
- (LETTER) == 'x' ? MOST_REGS : \
- (LETTER) == 'y' ? PROLOGUE_REGS : \
- (LETTER) == 'w' ? NON_A_CC_REGS : \
- NO_REGS)
-
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) < REG_P0 ? DREGS \
+((REGNO) == REG_R0 ? D0REGS \
+ : (REGNO) == REG_R1 ? D1REGS \
+ : (REGNO) == REG_R2 ? D2REGS \
+ : (REGNO) == REG_R3 ? D3REGS \
+ : (REGNO) == REG_R4 ? D4REGS \
+ : (REGNO) == REG_R5 ? D5REGS \
+ : (REGNO) == REG_R6 ? D6REGS \
+ : (REGNO) == REG_R7 ? D7REGS \
+ : (REGNO) == REG_P0 ? P0REGS \
: (REGNO) < REG_I0 ? PREGS \
: (REGNO) == REG_ARGP ? PREGS \
: (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
#define CLASS_LIKELY_SPILLED_P(CLASS) \
((CLASS) == PREGS_CLOBBERED \
|| (CLASS) == PROLOGUE_REGS \
+ || (CLASS) == P0REGS \
+ || (CLASS) == D0REGS \
+ || (CLASS) == D1REGS \
+ || (CLASS) == D2REGS \
|| (CLASS) == CCREGS)
/* Do not allow to store a value in REG_CC for any mode */
If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
MODE2)' must be zero. */
-#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+ ((MODE1) == (MODE2) \
+ || ((GET_MODE_CLASS (MODE1) == MODE_INT \
+ || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
+ && (GET_MODE_CLASS (MODE2) == MODE_INT \
+ || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
+ && (MODE1) != BImode && (MODE2) != BImode \
+ && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
+ && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
/* `PREFERRED_RELOAD_CLASS (X, CLASS)'
A C expression that places additional restrictions on the register
class to use when it is necessary to copy value X into a register
in class CLASS. The value is a register class; perhaps CLASS, or
perhaps another, smaller class. */
-#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
+#define PREFERRED_RELOAD_CLASS(X, CLASS) \
+ (GET_CODE (X) == POST_INC \
+ || GET_CODE (X) == POST_DEC \
+ || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
/* Function Calling Conventions. */
#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
#define EH_RETURN_HANDLER_RTX \
- gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
+ gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
/* Addressing Modes */
See force_const_mem().
If -mno-pool, all constants are legitimate.
*/
-#define LEGITIMATE_CONSTANT_P(x) 1
+#define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
/* A number, the maximum number of registers that can appear in a
valid memory address. Note that it is up to you to specify a
You may assume that ADDR is a valid address for the machine.
*/
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
-do { \
- if (GET_CODE (ADDR) == POST_INC \
- || GET_CODE (ADDR) == POST_DEC \
- || GET_CODE (ADDR) == PRE_DEC) \
- goto LABEL; \
-} while (0)
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
#define NOTICE_UPDATE_CC(EXPR, INSN) 0
in one reasonably fast instruction. */
#define MOVE_MAX UNITS_PER_WORD
+/* If a memory-to-memory move would take MOVE_RATIO or more simple
+ move-instruction pairs, we will do a movmem or libcall instead. */
+
+#define MOVE_RATIO 5
/* STORAGE LAYOUT: target machine storage layout
Define this macro as a C expression which is nonzero if accessing
#define WORD_REGISTER_OPERATIONS
*/
-#define CONST_18UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 262140)
-#define CONST_16BIT_IMM_P(VALUE) ((VALUE) >= -32768 && (VALUE) <= 32767)
-#define CONST_16UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 65535)
-#define CONST_7BIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 63)
-#define CONST_7NBIT_IMM_P(VALUE) ((VALUE) >= -64 && (VALUE) <= 0)
-#define CONST_5UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 31)
-#define CONST_4BIT_IMM_P(VALUE) ((VALUE) >= -8 && (VALUE) <= 7)
-#define CONST_4UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 15)
-#define CONST_3BIT_IMM_P(VALUE) ((VALUE) >= -4 && (VALUE) <= 3)
-#define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
-
-#define CONSTRAINT_LEN(C, STR) \
- ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2 \
- : (C) == 'K' ? 3 \
- : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
-
-#define CONST_OK_FOR_P(VALUE, STR) \
- ((STR)[1] == '0' ? (VALUE) == 0 \
- : (STR)[1] == '1' ? (VALUE) == 1 \
- : (STR)[1] == '2' ? (VALUE) == 2 \
- : (STR)[1] == '3' ? (VALUE) == 3 \
- : (STR)[1] == '4' ? (VALUE) == 4 \
- : 0)
-
-#define CONST_OK_FOR_K(VALUE, STR) \
- ((STR)[1] == 'u' \
- ? ((STR)[2] == '3' ? CONST_3UBIT_IMM_P (VALUE) \
- : (STR)[2] == '4' ? CONST_4UBIT_IMM_P (VALUE) \
- : (STR)[2] == '5' ? CONST_5UBIT_IMM_P (VALUE) \
- : (STR)[2] == 'h' ? CONST_16UBIT_IMM_P (VALUE) \
- : 0) \
- : (STR)[1] == 's' \
- ? ((STR)[2] == '3' ? CONST_3BIT_IMM_P (VALUE) \
- : (STR)[2] == '4' ? CONST_4BIT_IMM_P (VALUE) \
- : (STR)[2] == '7' ? CONST_7BIT_IMM_P (VALUE) \
- : (STR)[2] == 'h' ? CONST_16BIT_IMM_P (VALUE) \
- : 0) \
- : (STR)[1] == 'n' \
- ? ((STR)[2] == '7' ? CONST_7NBIT_IMM_P (VALUE) \
- : 0) \
- : 0)
-
-#define CONST_OK_FOR_M(VALUE, STR) \
- ((STR)[1] == '1' ? (VALUE) == 255 \
- : (STR)[1] == '2' ? (VALUE) == 65535 \
- : 0)
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- bfin constant operands are as follows
-
- J 2**N 5bit imm scaled
- Ks7 -64 .. 63 signed 7bit imm
- Ku5 0..31 unsigned 5bit imm
- Ks4 -8 .. 7 signed 4bit imm
- Ks3 -4 .. 3 signed 3bit imm
- Ku3 0 .. 7 unsigned 3bit imm
- Pn 0, 1, 2 constants 0, 1 or 2, corresponding to n
-*/
-#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
- ((C) == 'J' ? (log2constp (VALUE)) \
- : (C) == 'K' ? CONST_OK_FOR_K (VALUE, STR) \
- : (C) == 'L' ? log2constp (~(VALUE)) \
- : (C) == 'M' ? CONST_OK_FOR_M (VALUE, STR) \
- : (C) == 'P' ? CONST_OK_FOR_P (VALUE, STR) \
- : 0)
-
- /*Constant Output Formats */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'H' ? 1 : 0)
-
-#define EXTRA_CONSTRAINT(VALUE, D) \
- ((D) == 'Q' ? GET_CODE (VALUE) == SYMBOL_REF : 0)
+/* Evaluates to true if A and B are mac flags that can be used
+ together in a single multiply insn. That is the case if they are
+ both the same flag not involving M, or if one is a combination of
+ the other with M. */
+#define MACFLAGS_MATCH_P(A, B) \
+ ((A) == (B) \
+ || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
+ || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
+ || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
+ || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
/* Switch into a generic section. */
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
LAST_DIR_NM
} DIR_ENUM_T;
+#define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
+ ((C) == ';' \
+ || ((C) == '|' && (STR)[1] == '|'))
+
#define TEXT_SECTION_ASM_OP ".text;"
#define DATA_SECTION_ASM_OP ".data;"
#define ASM_COMMENT_START "//"
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- do {\
- fprintf (FILE, "\tP1.l =LP$%d; P1.h =LP$%d; call mcount;\n", \
- LABELNO, LABELNO);\
+#define FUNCTION_PROFILER(FILE, LABELNO) \
+ do { \
+ fprintf (FILE, "\tCALL __mcount;\n"); \
} while(0)
+#undef NO_PROFILE_COUNTERS
+#define NO_PROFILE_COUNTERS 1
+
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
#define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
#define SIZE_ASM_OP "\t.size\t"
+extern int splitting_for_sched;
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
+
#endif /* _BFIN_CONFIG */
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