/* Definitions of target machine for GNU compiler, for ARM.
Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002, 2003 Free Software Foundation, Inc.
+ 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
More major hacks by Richard Earnshaw (rearnsha@arm.com)
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
- if (TARGET_ARM) \
- builtin_define ("__arm__"); \
- else \
+ /* Define __arm__ even when in thumb mode, for \
+ consistency with armcc. */ \
+ builtin_define ("__arm__"); \
+ if (TARGET_THUMB) \
builtin_define ("__thumb__"); \
\
if (TARGET_BIG_END) \
if (TARGET_SOFT_FLOAT) \
builtin_define ("__SOFTFP__"); \
\
- /* FIXME: TARGET_HARD_FLOAT currently implies \
- FPA. */ \
- if (TARGET_VFP && !TARGET_HARD_FLOAT) \
+ if (TARGET_VFP) \
builtin_define ("__VFP_FP__"); \
\
/* Add a define for interworking. \
#define TARGET_CPU_arm9tdmi 0x0080
#define TARGET_CPU_xscale 0x0100
#define TARGET_CPU_ep9312 0x0200
+#define TARGET_CPU_iwmmxt 0x0400
+#define TARGET_CPU_arm926ejs 0x0800
+#define TARGET_CPU_arm1026ejs 0x1000
+#define TARGET_CPU_arm1136js 0x2000
+#define TARGET_CPU_arm1136jfs 0x4000
/* Configure didn't specify. */
#define TARGET_CPU_generic 0x8000
+/* The various ARM cores. */
+enum processor_type
+{
+#define ARM_CORE(NAME, FLAGS, COSTS) \
+ NAME,
+#include "arm-cores.def"
+#undef ARM_CORE
+ /* Used to indicate that no processor has been specified. */
+ arm_none
+};
+
+/* The processor for which instructions should be scheduled. */
+extern enum processor_type arm_tune;
+
typedef enum arm_cond_code
{
ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
extern GTY(()) rtx arm_target_insn;
/* Run-time compilation parameters selecting different hardware subsets. */
extern int target_flags;
-/* The floating point instruction architecture, can be 2 or 3 */
-extern const char * target_fp_name;
+/* The floating point mode. */
+extern const char *target_fpu_name;
+/* For backwards compatibility. */
+extern const char *target_fpe_name;
+/* Whether to use floating point hardware. */
+extern const char *target_float_abi_name;
/* Define the information needed to generate branch insns. This is
stored from the compare operation. */
extern GTY(()) rtx arm_compare_op0;
/* The label of the current constant pool. */
extern rtx pool_vector_label;
/* Set to 1 when a return insn is output, this means that the epilogue
- is not needed. */
+ is not needed. */
extern int return_used_this_function;
/* Used to produce AOF syntax assembler. */
extern GTY(()) rtx aof_pic_label;
\f
-/* Just in case configure has failed to define anything. */
+/* Just in case configure has failed to define anything. */
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT TARGET_CPU_generic
#endif
#ifdef TARGET_DEFAULT
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
-#endif /* TARGET_CPU_DEFAULT */
+#endif
+#else
+#if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
+#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__"
#else
-Unrecognized value in TARGET_CPU_DEFAULT.
+#if (TARGET_CPU_DEFAULT == TARGET_CPU_arm926ejs || \
+ TARGET_CPU_DEFAULT == TARGET_CPU_arm1026ejs)
+#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TEJ__"
+#else
+#if (TARGET_CPU_DEFAULT == TARGET_CPU_arm1136js || \
+ TARGET_CPU_DEFAULT == TARGET_CPU_arm1136jfs)
+#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_6J__"
+#else
+#error Unrecognized value in TARGET_CPU_DEFAULT.
+#endif
+#endif
+#endif
#endif
#endif
#endif
%{march=arm9:-D__ARM_ARCH_4T__} \
%{march=arm920:-D__ARM_ARCH_4__} \
%{march=arm920t:-D__ARM_ARCH_4T__} \
+%{march=arm926ejs:-D__ARM_ARCH_5TEJ__} \
%{march=arm9tdmi:-D__ARM_ARCH_4T__} \
+%{march=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
+%{march=arm1136js:-D__ARM_ARCH_6J__} \
+%{march=arm1136jfs:-D__ARM_ARCH_6J__} \
%{march=strongarm:-D__ARM_ARCH_4__} \
%{march=strongarm110:-D__ARM_ARCH_4__} \
%{march=strongarm1100:-D__ARM_ARCH_4__} \
%{march=armv5t:-D__ARM_ARCH_5T__} \
%{march=armv5e:-D__ARM_ARCH_5E__} \
%{march=armv5te:-D__ARM_ARCH_5TE__} \
+%{march=armv6:-D__ARM_ARCH6__} \
+%{march=armv6j:-D__ARM_ARCH6J__} \
%{!march=*: \
%{mcpu=arm2:-D__ARM_ARCH_2__} \
%{mcpu=arm250:-D__ARM_ARCH_2__} \
%{mcpu=arm9:-D__ARM_ARCH_4T__} \
%{mcpu=arm920:-D__ARM_ARCH_4__} \
%{mcpu=arm920t:-D__ARM_ARCH_4T__} \
+ %{mcpu=arm926ejs:-D__ARM_ARCH_5TEJ__} \
%{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
+ %{mcpu=arm1026ejs:-D__ARM_ARCH_5TEJ__} \
+ %{mcpu=arm1136js:-D__ARM_ARCH_6J__} \
+ %{mcpu=arm1136jfs:-D__ARM_ARCH_6J__} \
%{mcpu=strongarm:-D__ARM_ARCH_4__} \
%{mcpu=strongarm110:-D__ARM_ARCH_4__} \
%{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
%{mcpu=xscale:-D__XSCALE__} \
%{mcpu=ep9312:-D__ARM_ARCH_4T__} \
%{mcpu=ep9312:-D__MAVERICK__} \
+ %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \
+ %{mcpu=iwmmxt:-D__XSCALE__} \
+ %{mcpu=iwmmxt:-D__IWMMXT__} \
%{!mcpu*:%(cpp_cpu_arch_default)}} \
"
function tries to return. */
#define ARM_FLAG_ABORT_NORETURN (1 << 13)
-/* Nonzero if function prologues should not load the PIC register. */
+/* Nonzero if function prologues should not load the PIC register. */
#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
/* Nonzero if all call instructions should be indirect. */
destination is non-Thumb aware. */
#define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
-/* Nonzero means target uses VFP FP. */
-#define ARM_FLAG_VFP (1 << 21)
-
/* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */
-#define ARM_FLAG_ATPCS (1 << 22)
+#define ARM_FLAG_ATPCS (1 << 21)
/* Fix invalid Cirrus instruction combinations by inserting NOPs. */
-#define CIRRUS_FIX_INVALID_INSNS (1 << 23)
+#define CIRRUS_FIX_INVALID_INSNS (1 << 22)
#define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
#define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS)
#define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
-#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
-#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
-#define TARGET_CIRRUS (arm_is_cirrus)
-#define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS)
-#define TARGET_VFP (target_flags & ARM_FLAG_VFP)
+#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
+#define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD)
+#define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD)
+#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
+#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
+#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
+#define TARGET_IWMMXT (arm_arch_iwmmxt)
+#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
#define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
{"", TARGET_DEFAULT, "" } \
}
-#define TARGET_OPTIONS \
-{ \
- {"cpu=", & arm_select[0].string, \
- N_("Specify the name of the target CPU"), 0}, \
- {"arch=", & arm_select[1].string, \
- N_("Specify the name of the target architecture"), 0}, \
- {"tune=", & arm_select[2].string, "", 0}, \
- {"fpe=", & target_fp_name, "" , 0}, \
- {"fp=", & target_fp_name, \
- N_("Specify the version of the floating point emulator"), 0},\
- {"structure-size-boundary=", & structure_size_string, \
- N_("Specify the minimum bit alignment of structures"), 0}, \
- {"pic-register=", & arm_pic_register_string, \
- N_("Specify the register to be used for PIC addressing"), 0} \
+#define TARGET_OPTIONS \
+{ \
+ {"cpu=", & arm_select[0].string, \
+ N_("Specify the name of the target CPU"), 0}, \
+ {"arch=", & arm_select[1].string, \
+ N_("Specify the name of the target architecture"), 0}, \
+ {"tune=", & arm_select[2].string, "", 0}, \
+ {"fpe=", & target_fpe_name, "", 0}, \
+ {"fp=", & target_fpe_name, "", 0}, \
+ {"fpu=", & target_fpu_name, \
+ N_("Specify the name of the target floating point hardware/format"), 0}, \
+ {"float-abi=", & target_float_abi_name, \
+ N_("Specify if floating point hardware should be used"), 0}, \
+ {"structure-size-boundary=", & structure_size_string, \
+ N_("Specify the minimum bit alignment of structures"), 0}, \
+ {"pic-register=", & arm_pic_register_string, \
+ N_("Specify the register to be used for PIC addressing"), 0} \
}
/* Support for a compile-time default CPU, et cetera. The rules are:
by --with-arch.
--with-tune is ignored if -mtune or -mcpu are specified (but not affected
by -march).
- --with-float is ignored if -mhard-float or -msoft-float are
- specified. */
+ --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
+ specified.
+ --with-fpu is ignored if -mfpu is specified. */
#define OPTION_DEFAULT_SPECS \
{"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
{"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
{"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
- {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
+ {"float", \
+ "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
+ {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"},
struct arm_cpu_select
{
prog_mode32
};
-/* Recast the program mode class to be the prog_mode attribute */
+/* Recast the program mode class to be the prog_mode attribute. */
#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
extern enum prog_mode_type arm_prgmode;
-/* What sort of floating point unit do we have? Hardware or software.
- If software, is it issue 2 or issue 3? */
+/* Which floating point model to use. */
+enum arm_fp_model
+{
+ ARM_FP_MODEL_UNKNOWN,
+ /* FPA model (Hardware or software). */
+ ARM_FP_MODEL_FPA,
+ /* Cirrus Maverick floating point model. */
+ ARM_FP_MODEL_MAVERICK,
+ /* VFP floating point model. */
+ ARM_FP_MODEL_VFP
+};
+
+extern enum arm_fp_model arm_fp_model;
+
+/* Which floating point hardware is available. Also update
+ fp_model_for_fpu in arm.c when adding entries to this list. */
enum fputype
{
- /* Software floating point, FPA style double fmt. */
- FPUTYPE_SOFT_FPA,
+ /* No FP hardware. */
+ FPUTYPE_NONE,
/* Full FPA support. */
FPUTYPE_FPA,
/* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
/* Emulated FPA hardware, Issue 3 emulator. */
FPUTYPE_FPA_EMU3,
/* Cirrus Maverick floating point co-processor. */
- FPUTYPE_MAVERICK
+ FPUTYPE_MAVERICK,
+ /* VFP. */
+ FPUTYPE_VFP
};
/* Recast the floating point class to be the floating point attribute. */
/* What type of floating point instructions are available */
extern enum fputype arm_fpu_arch;
+enum float_abi_type
+{
+ ARM_FLOAT_ABI_SOFT,
+ ARM_FLOAT_ABI_SOFTFP,
+ ARM_FLOAT_ABI_HARD
+};
+
+extern enum float_abi_type arm_float_abi;
+
/* Default floating point architecture. Override in sub-target if
- necessary. */
+ necessary.
+ FIXME: Is this still necessary/desirable? Do we want VFP chips to
+ default to VFP unless overridden by a subtarget? If so it would be best
+ to remove these definitions. It also assumes there is only one cpu model
+ with a Maverick fpu. */
#ifndef FPUTYPE_DEFAULT
#define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2
#endif
#define FPUTYPE_DEFAULT FPUTYPE_MAVERICK
#endif
-/* Nonzero if the processor has a fast multiply insn, and one that does
- a 64-bit multiply of two 32-bit values. */
-extern int arm_fast_multiply;
+/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
+extern int arm_arch3m;
-/* Nonzero if this chip supports the ARM Architecture 4 extensions */
+/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
extern int arm_arch4;
-/* Nonzero if this chip supports the ARM Architecture 5 extensions */
+/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
extern int arm_arch5;
-/* Nonzero if this chip supports the ARM Architecture 5E extensions */
+/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
extern int arm_arch5e;
+/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
+extern int arm_arch6;
+
/* Nonzero if this chip can benefit from load scheduling. */
extern int arm_ld_sched;
/* Nonzero if this chip is a Cirrus variant. */
extern int arm_is_cirrus;
+/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
+extern int arm_arch_iwmmxt;
+
/* Nonzero if this chip is an XScale. */
extern int arm_arch_xscale;
(MODE) = SImode; \
}
-/* Define this macro if the promotion described by `PROMOTE_MODE'
- should also be done for outgoing function arguments. */
-/* This is required to ensure that push insns always push a word. */
-#define PROMOTE_FUNCTION_ARGS
-
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN 0
#define PARM_BOUNDARY 32
+#define IWMMXT_ALIGNMENT 64
+
#define STACK_BOUNDARY 32
#define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32)
#define EMPTY_FIELD_BOUNDARY 32
-#define BIGGEST_ALIGNMENT 32
+#define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32)
+
+#define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \
+ (TARGET_REALLY_IWMMXT \
+ && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode)))
+
+/* XXX Blah -- this macro is used directly by libobjc. Since it
+ supports no vector modes, cut out the complexity and fall back
+ on BIGGEST_FIELD_ALIGNMENT. */
+#ifdef IN_TARGET_LIBS
+#define BIGGEST_FIELD_ALIGNMENT 64
+#else
+/* An expression for the alignment of a structure field FIELD if the
+ alignment computed in the usual way is COMPUTED. GCC uses this
+ value instead of the value in `BIGGEST_ALIGNMENT' or
+ `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
+#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
+ (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \
+ ? IWMMXT_ALIGNMENT \
+ : (COMPUTED))
+#endif
+
+/* If defined, a C expression to compute the alignment for a static variable.
+ TYPE is the data type, and ALIGN is the alignment that the object
+ would ordinarily have. The value of this macro is used instead of that
+ alignment to align the object.
+
+ If this macro is not defined, then ALIGN is used. */
+#define DATA_ALIGNMENT(TYPE, ALIGN) \
+ (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
+
+/* If defined, a C expression to compute the alignment for a
+ variables in the local store. TYPE is the data type, and
+ BASIC-ALIGN is the alignment that the object would ordinarily
+ have. The value of this macro is used instead of that alignment
+ to align the object.
+
+ If this macro is not defined, then BASIC-ALIGN is used. */
+#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
+ (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN)
/* Make strings word-aligned so strcpy from constants will be faster. */
-#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_arch_xscale ? 1 : 2)
+#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- ((TREE_CODE (EXP) == STRING_CST \
+ ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \
+ (TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
mvf1-mvf3 Cirrus floating point scratch
mvf4-mvf15 S Cirrus floating point variable. */
+/* s0-s15 VFP scratch (aka d0-d7).
+ s16-s31 S VFP variable (aka d8-d15).
+ vfpcc Not a real register. Represents the VFP condition
+ code flags. */
+
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
| return link value | [fp, #-4]
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
-#define FIXED_REGISTERS \
-{ \
- 0,0,0,0,0,0,0,0, \
- 0,0,0,0,0,1,0,1, \
- 0,0,0,0,0,0,0,0, \
+#define FIXED_REGISTERS \
+{ \
+ 0,0,0,0,0,0,0,0, \
+ 0,0,0,0,0,1,0,1, \
+ 0,0,0,0,0,0,0,0, \
1,1,1, \
1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1 \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1 \
}
/* 1 for registers not available across function calls.
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like.
The CC is not preserved over function calls on the ARM 6, so it is
- easier to assume this for all. SFP is preserved, since FP is. */
+ easier to assume this for all. SFP is preserved, since FP is. */
#define CALL_USED_REGISTERS \
{ \
1,1,1,1,0,0,0,0, \
1,1,1,1,0,0,0,0, \
1,1,1, \
1,1,1,1,1,1,1,1, \
- 1,1,1,1,1,1,1,1 \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1,1,1,1,1,1,1,1, \
+ 1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
{ \
int regno; \
\
- if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
+ if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
{ \
- for (regno = FIRST_ARM_FP_REGNUM; \
- regno <= LAST_ARM_FP_REGNUM; ++regno) \
+ for (regno = FIRST_FPA_REGNUM; \
+ regno <= LAST_FPA_REGNUM; ++regno) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
\
- if (TARGET_CIRRUS) \
+ if (TARGET_THUMB && optimize_size) \
{ \
- for (regno = FIRST_ARM_FP_REGNUM; \
- regno <= LAST_ARM_FP_REGNUM; ++ regno) \
+ /* When optimizing for size, it's better not to use \
+ the HI regs, because of the overhead of stacking \
+ them. */ \
+ for (regno = FIRST_HI_REGNUM; \
+ regno <= LAST_HI_REGNUM; ++regno) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
- for (regno = FIRST_CIRRUS_FP_REGNUM; \
- regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
+ } \
+ \
+ /* The link register can be clobbered by any branch insn, \
+ but we have no way to track that at present, so mark \
+ it as unavailable. */ \
+ if (TARGET_THUMB) \
+ fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
+ \
+ if (TARGET_ARM && TARGET_HARD_FLOAT) \
+ { \
+ if (TARGET_MAVERICK) \
+ { \
+ for (regno = FIRST_FPA_REGNUM; \
+ regno <= LAST_FPA_REGNUM; ++ regno) \
+ fixed_regs[regno] = call_used_regs[regno] = 1; \
+ for (regno = FIRST_CIRRUS_FP_REGNUM; \
+ regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
+ { \
+ fixed_regs[regno] = 0; \
+ call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
+ } \
+ } \
+ if (TARGET_VFP) \
+ { \
+ for (regno = FIRST_VFP_REGNUM; \
+ regno <= LAST_VFP_REGNUM; ++ regno) \
+ { \
+ fixed_regs[regno] = 0; \
+ call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
+ } \
+ } \
+ } \
+ \
+ if (TARGET_REALLY_IWMMXT) \
+ { \
+ regno = FIRST_IWMMXT_GR_REGNUM; \
+ /* The 2002/10/09 revision of the XScale ABI has wCG0 \
+ and wCG1 as call-preserved registers. The 2002/11/21 \
+ revision changed this so that all wCG registers are \
+ scratch registers. */ \
+ for (regno = FIRST_IWMMXT_GR_REGNUM; \
+ regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
+ fixed_regs[regno] = call_used_regs[regno] = 0; \
+ /* The XScale ABI has wR0 - wR9 as scratch registers, \
+ the rest as call-preserved registers. */ \
+ for (regno = FIRST_IWMMXT_REGNUM; \
+ regno <= LAST_IWMMXT_REGNUM; ++ regno) \
{ \
fixed_regs[regno] = 0; \
- call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
+ call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
} \
} \
\
/* Convert fron bytes to ints. */
#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* The number of (integer) registers required to hold a quantity of type MODE. */
+/* The number of (integer) registers required to hold a quantity of type MODE.
+ Also used for VFP registers. */
#define ARM_NUM_REGS(MODE) \
ARM_NUM_INTS (GET_MODE_SIZE (MODE))
/* The number of (integer) argument register available. */
#define NUM_ARG_REGS 4
-/* Return the regiser number of the N'th (integer) argument. */
+/* Return the register number of the N'th (integer) argument. */
#define ARG_REGISTER(N) (N - 1)
-#if 0 /* FIXME: The ARM backend has special code to handle structure
- returns, and will reserve its own hidden first argument. So
- if this macro is enabled a *second* hidden argument will be
- reserved, which will break binary compatibility with old
- toolchains and also thunk handling. One day this should be
- fixed. */
-/* RTX for structure returns. NULL means use a hidden first argument. */
-#define STRUCT_VALUE 0
-#else
-/* Register in which address to store a structure value
- is passed to a function. */
-#define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
-#endif
-
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
/* The number of the last argument register. */
#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
-/* The number of the last "lo" register (thumb). */
+/* The numbers of the Thumb register ranges. */
+#define FIRST_LO_REGNUM 0
#define LAST_LO_REGNUM 7
+#define FIRST_HI_REGNUM 8
+#define LAST_HI_REGNUM 11
/* The register that holds the return address in exception handlers. */
#define EXCEPTION_LR_REGNUM 2
#define STACK_POINTER_REGNUM SP_REGNUM
/* ARM floating pointer registers. */
-#define FIRST_ARM_FP_REGNUM 16
-#define LAST_ARM_FP_REGNUM 23
+#define FIRST_FPA_REGNUM 16
+#define LAST_FPA_REGNUM 23
+
+#define FIRST_IWMMXT_GR_REGNUM 43
+#define LAST_IWMMXT_GR_REGNUM 46
+#define FIRST_IWMMXT_REGNUM 47
+#define LAST_IWMMXT_REGNUM 62
+#define IS_IWMMXT_REGNUM(REGNUM) \
+ (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
+#define IS_IWMMXT_GR_REGNUM(REGNUM) \
+ (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
/* Base register for access to local variables of the function. */
#define FRAME_POINTER_REGNUM 25
#define IS_CIRRUS_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
+#define FIRST_VFP_REGNUM 63
+#define LAST_VFP_REGNUM 94
+#define IS_VFP_REGNUM(REGNUM) \
+ (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
+
/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
/* + 16 Cirrus registers take us up to 43. */
-#define FIRST_PSEUDO_REGISTER 43
+/* Intel Wireless MMX Technology registers add 16 + 4 more. */
+/* VFP adds 32 + 1 more. */
+#define FIRST_PSEUDO_REGISTER 96
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms may be accessed
mode. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((TARGET_ARM \
- && REGNO >= FIRST_ARM_FP_REGNUM \
+ && REGNO >= FIRST_FPA_REGNUM \
&& REGNO != FRAME_POINTER_REGNUM \
&& REGNO != ARG_POINTER_REGNUM) \
+ && !IS_VFP_REGNUM (REGNO) \
? 1 : ARM_NUM_REGS (MODE))
/* Return true if REGNO is suitable for holding a quantity of type MODE. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
+#define VECTOR_MODE_SUPPORTED_P(MODE) \
+ ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode)
+
+#define VALID_IWMMXT_REG_MODE(MODE) \
+ (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode)
+
/* The order in which register should be allocated. It is good to use ip
since no saving is required (though calls clobber it) and it never contains
function parameters. It is quite good to use lr since other calls may
clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
least likely to contain a function parameter; in addition results are
returned in r0. */
+
#define REG_ALLOC_ORDER \
{ \
3, 2, 1, 0, 12, 14, 4, 5, \
16, 17, 18, 19, 20, 21, 22, 23, \
27, 28, 29, 30, 31, 32, 33, 34, \
35, 36, 37, 38, 39, 40, 41, 42, \
- 24, 25, 26 \
+ 43, 44, 45, 46, 47, 48, 49, 50, \
+ 51, 52, 53, 54, 55, 56, 57, 58, \
+ 59, 60, 61, 62, \
+ 24, 25, 26, \
+ 78, 77, 76, 75, 74, 73, 72, 71, \
+ 70, 69, 68, 67, 66, 65, 64, 63, \
+ 79, 80, 81, 82, 83, 84, 85, 86, \
+ 87, 88, 89, 90, 91, 92, 93, 94, \
+ 95 \
}
/* Interrupt functions can only use registers that have already been
NO_REGS,
FPA_REGS,
CIRRUS_REGS,
+ VFP_REGS,
+ IWMMXT_GR_REGS,
+ IWMMXT_REGS,
LO_REGS,
STACK_REG,
BASE_REGS,
HI_REGS,
CC_REG,
+ VFPCC_REG,
GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"FPA_REGS", \
"CIRRUS_REGS", \
+ "VFP_REGS", \
+ "IWMMXT_GR_REGS", \
+ "IWMMXT_REGS", \
"LO_REGS", \
"STACK_REG", \
"BASE_REGS", \
"HI_REGS", \
"CC_REG", \
+ "VFPCC_REG", \
"GENERAL_REGS", \
"ALL_REGS", \
}
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
-#define REG_CLASS_CONTENTS \
-{ \
- { 0x00000000, 0x0 }, /* NO_REGS */ \
- { 0x00FF0000, 0x0 }, /* FPA_REGS */ \
- { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \
- { 0x000000FF, 0x0 }, /* LO_REGS */ \
- { 0x00002000, 0x0 }, /* STACK_REG */ \
- { 0x000020FF, 0x0 }, /* BASE_REGS */ \
- { 0x0000FF00, 0x0 }, /* HI_REGS */ \
- { 0x01000000, 0x0 }, /* CC_REG */ \
- { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\
- { 0xFAFFFFFF, 0x000007FF } /* ALL_REGS */ \
+#define REG_CLASS_CONTENTS \
+{ \
+ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
+ { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
+ { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
+ { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
+ { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
+ { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
+ { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
+ { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
+ { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
+ { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
+ { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
+ { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
+ { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
+ { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
}
/* The same information, inverted:
or could index an array. */
#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
+/* FPA registers can't do subreg as all values are reformatted to internal
+ precision. VFP registers may only be accessed in the mode they
+ were set. */
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
+ ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
+ || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
+ : 0)
+
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
registers explicitly used in the rtl to be used as spill registers
but prevents the compiler from extending the lifetime of these
- registers. */
+ registers. */
#define SMALL_REGISTER_CLASSES TARGET_THUMB
/* Get reg_class from a letter such as appears in the machine description.
#define REG_CLASS_FROM_LETTER(C) \
( (C) == 'f' ? FPA_REGS \
: (C) == 'v' ? CIRRUS_REGS \
+ : (C) == 'w' ? VFP_REGS \
+ : (C) == 'y' ? IWMMXT_REGS \
+ : (C) == 'z' ? IWMMXT_GR_REGS \
: (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
: TARGET_ARM ? NO_REGS \
: (C) == 'h' ? HI_REGS \
(TARGET_ARM ? \
CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
-/* Constant letter 'G' for the FPA immediate constants.
+/* Constant letter 'G' for the FP immediate constants.
'H' means the same constant negated. */
#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
- ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \
+ ((C) == 'G' ? arm_const_double_rtx (X) : \
(C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
an offset from a register.
`S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
address. This means that the symbol is in the text segment and can be
- accessed without using a load. */
-
-#define EXTRA_CONSTRAINT_ARM(OP, C) \
- ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
- (C) == 'R' ? (GET_CODE (OP) == MEM \
- && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
- && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
- (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
- (C) == 'T' ? cirrus_memory_offset (OP) : \
- 0)
+ accessed without using a load.
+ 'U' Prefixes an extended memory constraint where:
+ 'Uv' is an address valid for VFP load/store insns.
+ 'Uq' is an address valid for ldrsb. */
+
+#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
+ (((C) == 'Q') ? (GET_CODE (OP) == MEM \
+ && GET_CODE (XEXP (OP, 0)) == REG) : \
+ ((C) == 'R') ? (GET_CODE (OP) == MEM \
+ && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
+ && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
+ ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
+ ((C) == 'T') ? cirrus_memory_offset (OP) : \
+ ((C) == 'U' && (STR)[1] == 'v') ? vfp_mem_operand (OP) : \
+ ((C) == 'U' && (STR)[1] == 'q') \
+ ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
+ : 0)
+
+#define CONSTRAINT_LEN(C,STR) \
+ ((C) == 'U' ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
#define EXTRA_CONSTRAINT_THUMB(X, C) \
((C) == 'Q' ? (GET_CODE (X) == MEM \
&& GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
-#define EXTRA_CONSTRAINT(X, C) \
- (TARGET_ARM ? \
- EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
+#define EXTRA_CONSTRAINT_STR(X, C, STR) \
+ (TARGET_ARM \
+ ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
+ : EXTRA_CONSTRAINT_THUMB (X, C))
+
+#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
or out of a register in CLASS in MODE. If it can be done directly,
NO_REGS is returned. */
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
- (TARGET_ARM ? \
- (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
+ /* Restrict which direct reloads are allowed for VFP regs. */ \
+ ((TARGET_VFP && TARGET_HARD_FLOAT \
+ && (CLASS) == VFP_REGS) \
+ ? vfp_secondary_reload_class (MODE, X) \
+ : TARGET_ARM \
+ ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
-/* If we need to load shorts byte-at-a-time, then we need a scratch. */
+/* If we need to load shorts byte-at-a-time, then we need a scratch. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
+ /* Restrict which direct reloads are allowed for VFP regs. */ \
+ ((TARGET_VFP && TARGET_HARD_FLOAT \
+ && (CLASS) == VFP_REGS) \
+ ? vfp_secondary_reload_class (MODE, X) : \
/* Cannot load constants into Cirrus registers. */ \
- ((TARGET_CIRRUS \
+ (TARGET_MAVERICK && TARGET_HARD_FLOAT \
&& (CLASS) == CIRRUS_REGS \
&& (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
? GENERAL_REGS : \
(TARGET_ARM ? \
+ (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
+ && CONSTANT_P (X)) \
+ ? GENERAL_REGS : \
(((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
HOST_WIDE_INT low, high; \
\
- if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
+ if (MODE == DImode || (TARGET_SOFT_FLOAT && TARGET_FPA \
+ && MODE == DFmode)) \
low = ((val & 0xf) ^ 0x8) - 0x8; \
- else if (TARGET_CIRRUS) \
+ else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
/* Need to be careful, -256 is not a valid offset. */ \
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
else if (MODE == SImode \
- || (MODE == SFmode && TARGET_SOFT_FLOAT) \
+ || (MODE == SFmode && TARGET_SOFT_FLOAT && TARGET_FPA) \
|| ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
/* Need to be careful, -4096 is not a valid offset. */ \
low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
/* Need to be careful, -256 is not a valid offset. */ \
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
- && TARGET_HARD_FLOAT) \
+ && TARGET_HARD_FLOAT && TARGET_FPA) \
/* Need to be careful, -1024 is not a valid offset. */ \
low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
else \
} \
while (0)
-/* ??? If an HImode FP+large_offset address is converted to an HImode
+/* XXX If an HImode FP+large_offset address is converted to an HImode
SP+large_offset address, then reload won't know how to fix it. It sees
only that SP isn't valid for HImode, and so reloads the SP into an index
register, but the resulting address is still invalid because the offset
(TARGET_ARM ? \
((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
(FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
+ (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
+ (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
+ (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
+ (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
+ (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
(FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
(FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
2) \
/* If we generate an insn to push BYTES bytes,
this says how many the stack pointer really advances by. */
/* The push insns do not do this rounding implicitly.
- So don't define this. */
+ So don't define this. */
/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
/* Define this if the maximum size of all the outgoing args is to be
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
#define LIBCALL_VALUE(MODE) \
- (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
- ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
- : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \
+ (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA \
+ && GET_MODE_CLASS (MODE) == MODE_FLOAT \
+ ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
+ : TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK \
+ && GET_MODE_CLASS (MODE) == MODE_FLOAT \
? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
+ : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \
+ ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
: gen_rtx_REG (MODE, ARG_REGISTER (1)))
/* Define how to find the value returned by a function.
/* On a Cirrus chip, mvf0 can return results. */
#define FUNCTION_VALUE_REGNO_P(REGNO) \
((REGNO) == ARG_REGISTER (1) \
- || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \
- || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
+ || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
+ && TARGET_HARD_FLOAT && TARGET_MAVERICK) \
+ || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \
+ || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
+ && TARGET_HARD_FLOAT && TARGET_FPA))
/* How large values are returned */
/* A C expression which can inhibit the returning of certain function values
- in registers, based on the type of value. */
+ in registers, based on the type of value. */
#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
values must be in memory. On the ARM, they need only do so if larger
- than a word, or if they contain elements offset from zero in the struct. */
+ than a word, or if they contain elements offset from zero in the struct. */
#define DEFAULT_PCC_STRUCT_RETURN 0
/* Flags for the call/call_value rtl operations set up by function_arg. */
#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
-#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
+#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
/* Some macros to test these flags. */
#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
unsigned long func_type;
/* Record if the function has a variable argument list. */
int uses_anonymous_args;
+ /* Records if sibcalls are blocked because an argument
+ register is needed to preserve stack alignment. */
+ int sibcall_blocked;
}
machine_function;
{
/* This is the number of registers of arguments scanned so far. */
int nregs;
- /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
+ /* This is the number of iWMMXt register arguments scanned so far. */
+ int iwmmxt_nregs;
+ int named_count;
+ int nargs;
+ /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
int call_cookie;
} CUMULATIVE_ARGS;
On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
other arguments are passed on the stack. If (NAMED == 0) (which happens
- only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
- passed in the stack (function_prologue will indeed make it pass in the
- stack if necessary). */
+ only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
+ defined), say it is passed in the stack (function_prologue will
+ indeed make it pass in the stack if necessary). */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
this is the number of registers used.
For args passed entirely in registers or entirely in memory, zero. */
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
- ( NUM_ARG_REGS > (CUM).nregs \
+ (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \
+ NUM_ARG_REGS > (CUM).nregs \
&& (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \
? NUM_ARG_REGS - (CUM).nregs : 0)
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0.
On the ARM, the offset starts at 0. */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
/* Update the data in CUM to advance over an argument
of mode MODE and data type TYPE.
(TYPE is null for libcalls where that information may not be available.) */
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
+ (CUM).nargs += 1; \
+ if (VECTOR_MODE_SUPPORTED_P (MODE)) \
+ if ((CUM).named_count <= (CUM).nargs) \
+ (CUM).nregs += 2; \
+ else \
+ (CUM).iwmmxt_nregs += 1; \
+ else \
(CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
+/* If defined, a C expression that gives the alignment boundary, in bits, of an
+ argument with the specified mode and type. If it is not defined,
+ `PARM_BOUNDARY' is used for all arguments. */
+#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
+ (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \
+ ? IWMMXT_ALIGNMENT : PARM_BOUNDARY)
+
/* 1 if N is a possible register number for function argument passing.
On the ARM, r0-r3 are used to pass args. */
-#define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
+#define FUNCTION_ARG_REGNO_P(REGNO) \
+ (IN_RANGE ((REGNO), 0, 3) \
+ || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
/* Implement `va_arg'. */
#define EXPAND_BUILTIN_VA_ARG(valist, type) \
arm_va_arg (valist, type)
\f
-/* Perform any actions needed for a function that is receiving a variable
- number of arguments. CUM is as above. MODE and TYPE are the mode and type
- of the current parameter. PRETEND_SIZE is a variable that should be set to
- the amount of stack that must be pushed by the prolog to pretend that our
- caller pushed it.
-
- Normally, this macro will push all remaining incoming registers on the
- stack and set PRETEND_SIZE to the length of the registers pushed.
-
- On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
- named arg and all anonymous args onto the stack.
- XXX I know the prologue shouldn't be pushing registers, but it is faster
- that way. */
-#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
-{ \
- cfun->machine->uses_anonymous_args = 1; \
- if ((CUM).nregs < NUM_ARG_REGS) \
- (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
-}
-
/* If your target environment doesn't prefix user functions with an
underscore, you may wish to re-define this to prevent any conflicts.
e.g. AOF may prefix mcount with an underscore. */
assemble_name (STREAM, ARM_MCOUNT_NAME); \
fputc ('\n', STREAM); \
ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
- sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
+ sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
assemble_aligned_integer (UNITS_PER_WORD, sym); \
}
#endif
/* Determine if the epilogue should be output as RTL.
You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
#define USE_RETURN_INSN(ISCOND) \
- (TARGET_ARM ? use_return_insn (ISCOND) : 0)
+ (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
/* Definitions for register eliminations.
ldr pc, [pc]
.word static chain value
.word function's address
- ??? FIXME: When the trampoline returns, r8 will be clobbered. */
+ XXX FIXME: When the trampoline returns, r8 will be clobbered. */
#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
{ \
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
/* Emit RTL insns to initialize the variable parts of a trampoline.
FNADDR is an RTX for the address of the function's pure code.
CXT is an RTX for the static chain value for the function. */
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
-{ \
- emit_move_insn \
- (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
- emit_move_insn \
- (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
+#ifndef INITIALIZE_TRAMPOLINE
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+{ \
+ emit_move_insn (gen_rtx_MEM (SImode, \
+ plus_constant (TRAMP, \
+ TARGET_ARM ? 8 : 16)), \
+ CXT); \
+ emit_move_insn (gen_rtx_MEM (SImode, \
+ plus_constant (TRAMP, \
+ TARGET_ARM ? 12 : 20)), \
+ FNADDR); \
}
+#endif
\f
/* Addressing modes, and classification of registers for them. */
They give nonzero only if REGNO is a hard reg of the suitable class
or a pseudo reg currently allocated to a suitable hard reg.
Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c. */
+ has been allocated, which happens in local-alloc.c. */
#define TEST_REGNO(R, TEST, VALUE) \
((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
/* Maximum number of registers that can appear in a valid memory address.
- Shifts in addresses can't be by a register. */
+ Shifts in addresses can't be by a register. */
#define MAX_REGS_PER_ADDRESS 2
/* Recognize any constant value that is a valid address. */
#define THUMB_LEGITIMATE_CONSTANT_P(X) \
( GET_CODE (X) == CONST_INT \
|| GET_CODE (X) == CONST_DOUBLE \
+ || GET_CODE (X) == CONSTANT_P_RTX \
|| CONSTANT_ADDRESS_P (X) \
|| flag_pic)
#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
{ \
- if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \
+ if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
goto WIN; \
}
#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
do { \
X = arm_legitimize_address (X, OLDX, MODE); \
- \
- if (memory_address_p (MODE, X)) \
- goto WIN; \
} while (0)
-#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
-do { \
- if (flag_pic) \
- (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
+#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
+do { \
+ X = thumb_legitimize_address (X, OLDX, MODE); \
} while (0)
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
else \
THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
+ \
+ if (memory_address_p (MODE, X)) \
+ goto WIN; \
} while (0)
/* Go to LABEL if ADDR (a legitimate address expression)
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE Pmode
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
/* signed 'char' is most compatible, but RISC OS wants it unsigned.
unsigned is probably best, but may break some code. */
#ifndef DEFAULT_SIGNED_CHAR
#define MOVE_MAX 4
#undef MOVE_RATIO
-#define MOVE_RATIO (arm_arch_xscale ? 4 : 2)
+#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
On the arm, Y in a register is used modulo 256 for the shift. Only for
- rotates is modulo 32 used. */
+ rotates is modulo 32 used. */
/* #define SHIFT_COUNT_TRUNCATED 1 */
/* All integers have the same format so truncation is easy. */
/* Calling from registers is a massive pain. */
#define NO_FUNCTION_CSE 1
-/* Chars and shorts should be passed as ints. */
-#define PROMOTE_PROTOTYPES 1
-
/* The machine modes of pointers and functions */
#define Pmode SImode
#define FUNCTION_MODE Pmode
c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
} while (0)
-/* Condition code information. */
+/* Condition code information. */
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. */
} \
while (0)
-#define STORE_FLAG_VALUE 1
-
/* The arm5 clz instruction returns 32. */
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
\f
/* Output a push or a pop instruction (only used when profiling). */
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
- if (TARGET_ARM) \
- asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
- STACK_POINTER_REGNUM, REGNO); \
- else \
- asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
+ do \
+ { \
+ if (TARGET_ARM) \
+ asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
+ STACK_POINTER_REGNUM, REGNO); \
+ else \
+ asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
+ } while (0)
#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
- if (TARGET_ARM) \
- asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
- STACK_POINTER_REGNUM, REGNO); \
- else \
- asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
+ do \
+ { \
+ if (TARGET_ARM) \
+ asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
+ STACK_POINTER_REGNUM, REGNO); \
+ else \
+ asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
+ } while (0)
/* This is how to output a label which precedes a jumptable. Since
Thumb instructions are 2 bytes, we may need explicit alignment here. */
{ \
if (TARGET_THUMB) \
ASM_OUTPUT_ALIGN (FILE, 2); \
- (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
+ (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
} \
while (0)
{ \
if (TARGET_THUMB) \
{ \
- if (is_called_in_ARM_mode (DECL)) \
+ if (is_called_in_ARM_mode (DECL) \
+ || current_function_is_thunk) \
fprintf (STREAM, "\t.code 32\n") ; \
else \
- fprintf (STREAM, "\t.thumb_func\n") ; \
+ fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
} \
if (TARGET_POKE_FUNCTION_NAME) \
arm_poke_function_name (STREAM, (char *) NAME); \
/* To support -falign-* switches we need to use .p2align so
that alignment directives in code sections will be padded
with no-op instructions, rather than zeroes. */
-#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
+#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
if ((LOG) != 0) \
{ \
if ((MAX_SKIP) == 0) \
- fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
+ fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
else \
fprintf ((FILE), "\t.p2align %d,,%d\n", \
- (LOG), (MAX_SKIP)); \
+ (int) (LOG), (int) (MAX_SKIP)); \
}
#endif
\f
/* Only perform branch elimination (by making instructions conditional) if
- we're optimising. Otherwise it's of no use anyway. */
+ we're optimizing. Otherwise it's of no use anyway. */
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
if (TARGET_ARM && optimize) \
arm_final_prescan_insn (INSN); \
HOST_WIDE_INT offset = 0; \
if (GET_CODE (base) != REG) \
{ \
- /* Ensure that BASE is a register */ \
- /* (one of them must be). */ \
+ /* Ensure that BASE is a register. */ \
+ /* (one of them must be). */ \
rtx temp = base; \
base = index; \
index = temp; \
offset = INTVAL (index); \
if (is_minus) \
offset = -offset; \
- asm_fprintf (STREAM, "[%r, #%d]", \
+ asm_fprintf (STREAM, "[%r, #%wd]", \
REGNO (base), offset); \
break; \
\
{ \
asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
- asm_fprintf (STREAM, "#%d]!", \
+ asm_fprintf (STREAM, "#%wd]!", \
INTVAL (XEXP (XEXP (X, 1), 1))); \
else \
asm_fprintf (STREAM, "%r]!", \
{ \
asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
- asm_fprintf (STREAM, "#%d", \
+ asm_fprintf (STREAM, "#%wd", \
INTVAL (XEXP (XEXP (X, 1), 1))); \
else \
asm_fprintf (STREAM, "%r", \
asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
else if (GET_CODE (X) == PLUS) \
{ \
+ if (GET_CODE (XEXP (X, 0)) != REG) \
+ abort (); \
if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
- asm_fprintf (STREAM, "[%r, #%d]", \
+ asm_fprintf (STREAM, "[%r, #%wd]", \
REGNO (XEXP (X, 0)), \
- (int) INTVAL (XEXP (X, 1))); \
+ INTVAL (XEXP (X, 1))); \
else \
asm_fprintf (STREAM, "[%r, %r]", \
REGNO (XEXP (X, 0)), \
ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
else \
THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
-
+
+#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
+ if (GET_CODE (X) != CONST_VECTOR \
+ || ! arm_emit_vector_const (FILE, X)) \
+ goto FAIL;
+
/* A C expression whose value is RTL representing the value of the return
address for the frame COUNT steps up from the current frame. */
/* Define the codes that are matched by predicates in arm.c */
#define PREDICATE_CODES \
{"s_register_operand", {SUBREG, REG}}, \
+ {"arm_general_register_operand", {SUBREG, REG}}, \
{"arm_hard_register_operand", {REG}}, \
{"f_register_operand", {SUBREG, REG}}, \
{"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
- {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
- {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
+ {"arm_addimm_operand", {CONST_INT}}, \
+ {"arm_float_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
+ {"arm_float_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
{"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
{"index_operand", {SUBREG, REG, CONST_INT}}, \
{"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
+ {"thumb_cmpneg_operand", {CONST_INT}}, \
+ {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
{"offsettable_memory_operand", {MEM}}, \
- {"bad_signed_byte_operand", {MEM}}, \
{"alignable_memory_operand", {MEM}}, \
{"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
{"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
{"cirrus_register_operand", {REG}}, \
{"cirrus_fp_register", {REG}}, \
{"cirrus_shift_const", {CONST_INT}}, \
- {"dominant_cc_register", {REG}},
+ {"dominant_cc_register", {REG}}, \
+ {"arm_float_compare_operand", {REG, CONST_DOUBLE}}, \
+ {"vfp_compare_operand", {REG, CONST_DOUBLE}},
/* Define this if you have special predicates that know special things
about modes. Genrecog will warn about certain forms of
match_operand without a mode; if the operand predicate is listed in
- SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
+ SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
#define SPECIAL_MODE_PREDICATES \
"cc_register", "dominant_cc_register",
+enum arm_builtins
+{
+ ARM_BUILTIN_GETWCX,
+ ARM_BUILTIN_SETWCX,
+
+ ARM_BUILTIN_WZERO,
+
+ ARM_BUILTIN_WAVG2BR,
+ ARM_BUILTIN_WAVG2HR,
+ ARM_BUILTIN_WAVG2B,
+ ARM_BUILTIN_WAVG2H,
+
+ ARM_BUILTIN_WACCB,
+ ARM_BUILTIN_WACCH,
+ ARM_BUILTIN_WACCW,
+
+ ARM_BUILTIN_WMACS,
+ ARM_BUILTIN_WMACSZ,
+ ARM_BUILTIN_WMACU,
+ ARM_BUILTIN_WMACUZ,
+
+ ARM_BUILTIN_WSADB,
+ ARM_BUILTIN_WSADBZ,
+ ARM_BUILTIN_WSADH,
+ ARM_BUILTIN_WSADHZ,
+
+ ARM_BUILTIN_WALIGN,
+
+ ARM_BUILTIN_TMIA,
+ ARM_BUILTIN_TMIAPH,
+ ARM_BUILTIN_TMIABB,
+ ARM_BUILTIN_TMIABT,
+ ARM_BUILTIN_TMIATB,
+ ARM_BUILTIN_TMIATT,
+
+ ARM_BUILTIN_TMOVMSKB,
+ ARM_BUILTIN_TMOVMSKH,
+ ARM_BUILTIN_TMOVMSKW,
+
+ ARM_BUILTIN_TBCSTB,
+ ARM_BUILTIN_TBCSTH,
+ ARM_BUILTIN_TBCSTW,
+
+ ARM_BUILTIN_WMADDS,
+ ARM_BUILTIN_WMADDU,
+
+ ARM_BUILTIN_WPACKHSS,
+ ARM_BUILTIN_WPACKWSS,
+ ARM_BUILTIN_WPACKDSS,
+ ARM_BUILTIN_WPACKHUS,
+ ARM_BUILTIN_WPACKWUS,
+ ARM_BUILTIN_WPACKDUS,
+
+ ARM_BUILTIN_WADDB,
+ ARM_BUILTIN_WADDH,
+ ARM_BUILTIN_WADDW,
+ ARM_BUILTIN_WADDSSB,
+ ARM_BUILTIN_WADDSSH,
+ ARM_BUILTIN_WADDSSW,
+ ARM_BUILTIN_WADDUSB,
+ ARM_BUILTIN_WADDUSH,
+ ARM_BUILTIN_WADDUSW,
+ ARM_BUILTIN_WSUBB,
+ ARM_BUILTIN_WSUBH,
+ ARM_BUILTIN_WSUBW,
+ ARM_BUILTIN_WSUBSSB,
+ ARM_BUILTIN_WSUBSSH,
+ ARM_BUILTIN_WSUBSSW,
+ ARM_BUILTIN_WSUBUSB,
+ ARM_BUILTIN_WSUBUSH,
+ ARM_BUILTIN_WSUBUSW,
+
+ ARM_BUILTIN_WAND,
+ ARM_BUILTIN_WANDN,
+ ARM_BUILTIN_WOR,
+ ARM_BUILTIN_WXOR,
+
+ ARM_BUILTIN_WCMPEQB,
+ ARM_BUILTIN_WCMPEQH,
+ ARM_BUILTIN_WCMPEQW,
+ ARM_BUILTIN_WCMPGTUB,
+ ARM_BUILTIN_WCMPGTUH,
+ ARM_BUILTIN_WCMPGTUW,
+ ARM_BUILTIN_WCMPGTSB,
+ ARM_BUILTIN_WCMPGTSH,
+ ARM_BUILTIN_WCMPGTSW,
+
+ ARM_BUILTIN_TEXTRMSB,
+ ARM_BUILTIN_TEXTRMSH,
+ ARM_BUILTIN_TEXTRMSW,
+ ARM_BUILTIN_TEXTRMUB,
+ ARM_BUILTIN_TEXTRMUH,
+ ARM_BUILTIN_TEXTRMUW,
+ ARM_BUILTIN_TINSRB,
+ ARM_BUILTIN_TINSRH,
+ ARM_BUILTIN_TINSRW,
+
+ ARM_BUILTIN_WMAXSW,
+ ARM_BUILTIN_WMAXSH,
+ ARM_BUILTIN_WMAXSB,
+ ARM_BUILTIN_WMAXUW,
+ ARM_BUILTIN_WMAXUH,
+ ARM_BUILTIN_WMAXUB,
+ ARM_BUILTIN_WMINSW,
+ ARM_BUILTIN_WMINSH,
+ ARM_BUILTIN_WMINSB,
+ ARM_BUILTIN_WMINUW,
+ ARM_BUILTIN_WMINUH,
+ ARM_BUILTIN_WMINUB,
+
+ ARM_BUILTIN_WMULUM,
+ ARM_BUILTIN_WMULSM,
+ ARM_BUILTIN_WMULUL,
+
+ ARM_BUILTIN_PSADBH,
+ ARM_BUILTIN_WSHUFH,
+
+ ARM_BUILTIN_WSLLH,
+ ARM_BUILTIN_WSLLW,
+ ARM_BUILTIN_WSLLD,
+ ARM_BUILTIN_WSRAH,
+ ARM_BUILTIN_WSRAW,
+ ARM_BUILTIN_WSRAD,
+ ARM_BUILTIN_WSRLH,
+ ARM_BUILTIN_WSRLW,
+ ARM_BUILTIN_WSRLD,
+ ARM_BUILTIN_WRORH,
+ ARM_BUILTIN_WRORW,
+ ARM_BUILTIN_WRORD,
+ ARM_BUILTIN_WSLLHI,
+ ARM_BUILTIN_WSLLWI,
+ ARM_BUILTIN_WSLLDI,
+ ARM_BUILTIN_WSRAHI,
+ ARM_BUILTIN_WSRAWI,
+ ARM_BUILTIN_WSRADI,
+ ARM_BUILTIN_WSRLHI,
+ ARM_BUILTIN_WSRLWI,
+ ARM_BUILTIN_WSRLDI,
+ ARM_BUILTIN_WRORHI,
+ ARM_BUILTIN_WRORWI,
+ ARM_BUILTIN_WRORDI,
+
+ ARM_BUILTIN_WUNPCKIHB,
+ ARM_BUILTIN_WUNPCKIHH,
+ ARM_BUILTIN_WUNPCKIHW,
+ ARM_BUILTIN_WUNPCKILB,
+ ARM_BUILTIN_WUNPCKILH,
+ ARM_BUILTIN_WUNPCKILW,
+
+ ARM_BUILTIN_WUNPCKEHSB,
+ ARM_BUILTIN_WUNPCKEHSH,
+ ARM_BUILTIN_WUNPCKEHSW,
+ ARM_BUILTIN_WUNPCKEHUB,
+ ARM_BUILTIN_WUNPCKEHUH,
+ ARM_BUILTIN_WUNPCKEHUW,
+ ARM_BUILTIN_WUNPCKELSB,
+ ARM_BUILTIN_WUNPCKELSH,
+ ARM_BUILTIN_WUNPCKELSW,
+ ARM_BUILTIN_WUNPCKELUB,
+ ARM_BUILTIN_WUNPCKELUH,
+ ARM_BUILTIN_WUNPCKELUW,
+
+ ARM_BUILTIN_MAX
+};
#endif /* ! GCC_ARM_H */
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