/* Output routines for GCC for ARM.
Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
- 2002, 2003, 2004 Free Software Foundation, Inc.
+ 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
More major hacks by Richard Earnshaw (rearnsha@arm.com).
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-
+
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "target.h"
#include "target-def.h"
#include "debug.h"
+#include "langhooks.h"
/* Forward definitions of types. */
typedef struct minipool_node Mnode;
static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
inline static int thumb_index_register_rtx_p (rtx, int);
static int thumb_far_jump_used_p (void);
+static bool thumb_force_lr_save (void);
static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
-static rtx emit_multi_reg_push (int);
static rtx emit_sfm (int, int);
#ifndef AOF_ASSEMBLER
static bool arm_assemble_integer (rtx, unsigned int, int);
static rtx is_jump_table (rtx);
static const char *output_multi_immediate (rtx *, const char *, const char *,
int, HOST_WIDE_INT);
-static void print_multi_reg (FILE *, const char *, int, int);
static const char *shift_op (rtx, HOST_WIDE_INT *);
static struct machine_function *arm_init_machine_status (void);
-static int number_of_first_bit_set (int);
static void replace_symbols_in_block (tree, rtx, rtx);
-static void thumb_exit (FILE *, int, rtx);
-static void thumb_pushpop (FILE *, int, int, int *, int);
+static void thumb_exit (FILE *, int);
static rtx is_jump_table (rtx);
static HOST_WIDE_INT get_jump_table_size (rtx);
static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
static unsigned long arm_compute_func_type (void);
static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
+#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
+static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
+#endif
static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
static int arm_comp_type_attributes (tree, tree);
static void arm_set_default_type_attributes (tree);
static int arm_adjust_cost (rtx, rtx, rtx, int);
-static int arm_use_dfa_pipeline_interface (void);
static int count_insns_for_constant (HOST_WIDE_INT, int);
static int arm_get_strip_length (int);
static bool arm_function_ok_for_sibcall (tree, tree);
static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
tree);
static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
+static bool arm_size_rtx_costs (rtx, int, int, int *);
static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
static bool arm_xscale_rtx_costs (rtx, int, int, int *);
static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static void emit_constant_insn (rtx cond, rtx pattern);
+static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
+ tree, bool);
-#ifdef OBJECT_FORMAT_ELF
-static void arm_elf_asm_named_section (const char *, unsigned int);
-#endif
#ifndef ARM_PE
static void arm_encode_section_info (tree, rtx, int);
#endif
+
+static void arm_file_end (void);
+
#ifdef AOF_ASSEMBLER
static void aof_globalize_label (FILE *, const char *);
static void aof_dump_imports (FILE *);
static rtx arm_struct_value_rtx (tree, int);
static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
tree, int *, int);
+static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
+ enum machine_mode, tree, bool);
static bool arm_promote_prototypes (tree);
static bool arm_default_short_enums (void);
static bool arm_align_anon_bitfield (void);
+static tree arm_cxx_guard_type (void);
+static bool arm_cxx_guard_mask_bit (void);
+static tree arm_get_cookie_size (tree);
+static bool arm_cookie_has_size (void);
+static bool arm_cxx_cdtor_returns_this (void);
+static bool arm_cxx_key_method_may_be_inline (void);
+static bool arm_cxx_export_class_data (void);
+static void arm_init_libfuncs (void);
+static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
\f
/* Initialize the GCC target structure. */
-#ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
+#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
#undef TARGET_MERGE_DECL_ATTRIBUTES
#define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
#endif
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE arm_attribute_table
+#undef TARGET_ASM_FILE_END
+#define TARGET_ASM_FILE_END arm_file_end
+
#ifdef AOF_ASSEMBLER
#undef TARGET_ASM_BYTE_OP
#define TARGET_ASM_BYTE_OP "\tDCB\t"
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST arm_adjust_cost
-#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
-#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
-
#undef TARGET_ENCODE_SECTION_INFO
#ifdef ARM_PE
#define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST arm_address_cost
+#undef TARGET_SHIFT_TRUNCATION_MASK
+#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
+
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN arm_expand_builtin
+#undef TARGET_INIT_LIBFUNCS
+#define TARGET_INIT_LIBFUNCS arm_init_libfuncs
+
#undef TARGET_PROMOTE_FUNCTION_ARGS
#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
#undef TARGET_PROMOTE_FUNCTION_RETURN
#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
+#undef TARGET_PASS_BY_REFERENCE
+#define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
+#undef TARGET_ARG_PARTIAL_BYTES
+#define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
#undef TARGET_STRUCT_VALUE_RTX
#define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
#undef TARGET_ALIGN_ANON_BITFIELD
#define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
+#undef TARGET_CXX_GUARD_TYPE
+#define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
+
+#undef TARGET_CXX_GUARD_MASK_BIT
+#define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
+
+#undef TARGET_CXX_GET_COOKIE_SIZE
+#define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
+
+#undef TARGET_CXX_COOKIE_HAS_SIZE
+#define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
+
+#undef TARGET_CXX_CDTOR_RETURNS_THIS
+#define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
+
+#undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
+#define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
+
+#undef TARGET_CXX_EXPORT_CLASS_DATA
+#define TARGET_CXX_EXPORT_CLASS_DATA arm_cxx_export_class_data
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
/* Obstack for minipool constant handling. */
/* Set by the -mfloat-abi=... option. */
const char * target_float_abi_name = NULL;
+/* Set by the legacy -mhard-float and -msoft-float options. */
+const char * target_float_switch = NULL;
+
/* Set by the -mabi=... option. */
const char * target_abi_name = NULL;
const char * structure_size_string = NULL;
int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
+/* Used for Thumb call_via trampolines. */
+rtx thumb_call_via_label[13];
+static int thumb_call_reg_needed;
+
/* Bit values used to identify processor capabilities. */
#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
#define FL_ARCH3M (1 << 1) /* Extended multiply */
#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
#define FL_FOR_ARCH6J FL_FOR_ARCH6
+#define FL_FOR_ARCH6K FL_FOR_ARCH6
+#define FL_FOR_ARCH6Z FL_FOR_ARCH6
+#define FL_FOR_ARCH6ZK FL_FOR_ARCH6
/* The bits in this mask specify which
instructions we are allowed to generate. */
/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
int arm_arch4 = 0;
+/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
+int arm_arch4t = 0;
+
/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
int arm_arch5 = 0;
/* Nonzero if generating Thumb instructions. */
int thumb_code = 0;
+/* Nonzero if we should define __THUMB_INTERWORK__ in the
+ preprocessor.
+ XXX This is a bit of a hack, it's intended to help work around
+ problems in GLD which doesn't understand that armv5t code is
+ interworking clean. */
+int arm_cpp_interwork = 0;
+
/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
must report the mode of the memory reference from PRINT_OPERAND to
PRINT_OPERAND_ADDRESS. */
static const struct processors all_cores[] =
{
/* ARM Cores */
-#define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
- {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
+#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
+ {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
#include "arm-cores.def"
#undef ARM_CORE
{NULL, arm_none, NULL, 0, NULL}
/* ARM Architectures */
/* We don't specify rtx_costs here as it will be figured out
from the core. */
-
+
{"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
{"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
{"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
{"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
{"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
{"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
+ {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
+ {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
+ {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
{"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
{"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
{NULL, arm_none, NULL, 0 , NULL}
struct arm_cpu_select arm_select[] =
{
- /* string name processors */
+ /* string name processors */
{ NULL, "-mcpu=", all_cores },
{ NULL, "-march=", all_architectures },
{ NULL, "-mtune=", all_cores }
bit_count (unsigned long value)
{
unsigned long count = 0;
-
+
while (value)
{
count++;
return count;
}
+/* Set up library functions unique to ARM. */
+
+static void
+arm_init_libfuncs (void)
+{
+ /* There are no special library functions unless we are using the
+ ARM BPABI. */
+ if (!TARGET_BPABI)
+ return;
+
+ /* The functions below are described in Section 4 of the "Run-Time
+ ABI for the ARM architecture", Version 1.0. */
+
+ /* Double-precision floating-point arithmetic. Table 2. */
+ set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
+ set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
+ set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
+ set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
+ set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
+
+ /* Double-precision comparisons. Table 3. */
+ set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
+ set_optab_libfunc (ne_optab, DFmode, NULL);
+ set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
+ set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
+ set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
+ set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
+ set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
+
+ /* Single-precision floating-point arithmetic. Table 4. */
+ set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
+ set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
+ set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
+ set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
+ set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
+
+ /* Single-precision comparisons. Table 5. */
+ set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
+ set_optab_libfunc (ne_optab, SFmode, NULL);
+ set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
+ set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
+ set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
+ set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
+ set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
+
+ /* Floating-point to integer conversions. Table 6. */
+ set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
+ set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
+ set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
+ set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
+ set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
+ set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
+ set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
+ set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
+
+ /* Conversions between floating types. Table 7. */
+ set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
+ set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
+
+ /* Integer to floating-point conversions. Table 8. */
+ set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
+ set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
+ set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
+ set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
+ set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
+ set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
+ set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
+ set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
+
+ /* Long long. Table 9. */
+ set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
+ set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
+ set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
+ set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
+ set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
+ set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
+ set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
+ set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
+
+ /* Integer (32/32->32) division. \S 4.3.1. */
+ set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
+ set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
+
+ /* The divmod functions are designed so that they can be used for
+ plain division, even though they return both the quotient and the
+ remainder. The quotient is returned in the usual location (i.e.,
+ r0 for SImode, {r0, r1} for DImode), just as would be expected
+ for an ordinary division routine. Because the AAPCS calling
+ conventions specify that all of { r0, r1, r2, r3 } are
+ callee-saved registers, there is no need to tell the compiler
+ explicitly that those registers are clobbered by these
+ routines. */
+ set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
+ set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
+ set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
+ set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
+}
+
/* Fix up any incompatible options that the user has specified.
This has now turned into a maze. */
void
for (i = ARRAY_SIZE (arm_select); i--;)
{
struct arm_cpu_select * ptr = arm_select + i;
-
+
if (ptr->string != NULL && ptr->string[0] != '\0')
{
const struct processors * sel;
if (insn_flags != 0 && (insn_flags ^ sel->flags))
warning ("switch -mcpu=%s conflicts with -march= switch",
ptr->string);
-
+
insn_flags = sel->flags;
}
-
+
break;
}
error ("bad value (%s) for %s switch", ptr->string, ptr->name);
}
}
-
+
/* If the user did not specify a processor, choose one for them. */
if (insn_flags == 0)
{
/* Now check to see if the user has specified some command line
switch that require certain abilities from the cpu. */
sought = 0;
-
+
if (TARGET_INTERWORK || TARGET_THUMB)
{
sought |= (FL_THUMB | FL_MODE32);
-
+
/* There are no ARM processors that support both APCS-26 and
interworking. Therefore we force FL_MODE26 to be removed
from insn_flags here (if it was set), so that the search
below will always be able to find a compatible processor. */
insn_flags &= ~FL_MODE26;
}
-
+
if (sought != 0 && ((sought & insn_flags) != sought))
{
/* Try to locate a CPU type that supports all of the abilities
{
unsigned current_bit_count = 0;
const struct processors * best_fit = NULL;
-
+
/* Ideally we would like to issue an error message here
saying that it was not possible to find a CPU compatible
with the default CPU, but which also supports the command
if (arm_tune == arm_none)
arm_tune = (enum processor_type) (sel - all_cores);
}
-
+
/* The processor for which we should tune should now have been
chosen. */
if (arm_tune == arm_none)
abort ();
-
+
tune_flags = all_cores[(int)arm_tune].flags;
- targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
+ if (optimize_size)
+ targetm.rtx_costs = arm_size_rtx_costs;
+ else
+ targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
/* Make sure that the processor choice does not conflict with any of the
other command line choices. */
warning ("target CPU does not support interworking" );
target_flags &= ~ARM_FLAG_INTERWORK;
}
-
+
if (TARGET_THUMB && !(insn_flags & FL_THUMB))
{
warning ("target CPU does not support THUMB instructions");
warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
target_flags |= ARM_FLAG_APCS_FRAME;
}
-
+
if (TARGET_POKE_FUNCTION_NAME)
target_flags |= ARM_FLAG_APCS_FRAME;
-
+
if (TARGET_APCS_REENT && flag_pic)
error ("-fpic and -mapcs-reent are incompatible");
-
+
if (TARGET_APCS_REENT)
warning ("APCS reentrant code not supported. Ignored");
-
+
/* If this target is normally configured to use APCS frames, warn if they
are turned off and debugging is turned on. */
if (TARGET_ARM
&& !TARGET_APCS_FRAME
&& (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
warning ("-g with -mno-apcs-frame may not give sensible debugging");
-
+
/* If stack checking is disabled, we can use r10 as the PIC register,
which keeps r9 available. */
if (flag_pic)
arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
-
+
if (TARGET_APCS_FLOAT)
warning ("passing floating point arguments in fp regs not yet supported");
-
+
/* Initialize boolean versions of the flags, for use in the arm.md file. */
arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
arm_arch4 = (insn_flags & FL_ARCH4) != 0;
+ arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
arm_arch5 = (insn_flags & FL_ARCH5) != 0;
arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
arm_arch6 = (insn_flags & FL_ARCH6) != 0;
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
+ /* V5 code we generate is completely interworking capable, so we turn off
+ TARGET_INTERWORK here to avoid many tests later on. */
+
+ /* XXX However, we must pass the right pre-processor defines to CPP
+ or GLD can get confused. This is a hack. */
+ if (TARGET_INTERWORK)
+ arm_cpp_interwork = 1;
+
+ if (arm_arch5)
+ target_flags &= ~ARM_FLAG_INTERWORK;
+
if (target_abi_name)
{
for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
error ("invalid floating point abi: -mfloat-abi=%s",
target_float_abi_name);
}
- else
+ else if (target_float_switch)
{
- /* Use soft-float target flag. */
- if (target_flags & ARM_FLAG_SOFT_FLOAT)
- arm_float_abi = ARM_FLOAT_ABI_SOFT;
- else
+ /* This is a bit of a hack to avoid needing target flags for these. */
+ if (target_float_switch[0] == 'h')
arm_float_abi = ARM_FLOAT_ABI_HARD;
+ else
+ arm_float_abi = ARM_FLOAT_ABI_SOFT;
}
+ else
+ arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
+
+ if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
+ sorry ("-mfloat-abi=hard and VFP");
- if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
- sorry ("-mfloat-abi=softfp");
/* If soft-float is specified then don't use FPU. */
if (TARGET_SOFT_FLOAT)
arm_fpu_arch = FPUTYPE_NONE;
-
+
/* For arm2/3 there is no need to do any scheduling if there is only
a floating point emulator, or we are doing software floating-point. */
if ((TARGET_SOFT_FLOAT
|| arm_fpu_tune == FPUTYPE_FPA_EMU3)
&& (tune_flags & FL_MODE32) == 0)
flag_schedule_insns = flag_schedule_insns_after_reload = 0;
-
+
/* Override the default structure alignment for AAPCS ABI. */
if (arm_abi == ARM_ABI_AAPCS)
arm_structure_size_boundary = 8;
/* For processors with load scheduling, it never costs more than
2 cycles to load a constant, and the load scheduler may well
reduce that to 1. */
- if (tune_flags & FL_LDSCHED)
+ if (arm_ld_sched)
arm_constant_limit = 1;
/* On XScale the longer latency of a load makes it more difficult
unsigned long type = ARM_FT_UNKNOWN;
tree a;
tree attr;
-
+
if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
abort ();
register values that will never be needed again. This optimization
was added to speed up context switching in a kernel application. */
if (optimize > 0
- && current_function_nothrow
+ && TREE_NOTHROW (current_function_decl)
&& TREE_THIS_VOLATILE (current_function_decl))
type |= ARM_FT_VOLATILE;
-
+
if (cfun->static_chain_decl != NULL)
type |= ARM_FT_NESTED;
attr = DECL_ATTRIBUTES (current_function_decl);
-
+
a = lookup_attribute ("naked", attr);
if (a != NULL_TREE)
type |= ARM_FT_NAKED;
- if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
- type |= ARM_FT_EXCEPTION_HANDLER;
+ a = lookup_attribute ("isr", attr);
+ if (a == NULL_TREE)
+ a = lookup_attribute ("interrupt", attr);
+
+ if (a == NULL_TREE)
+ type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
else
- {
- a = lookup_attribute ("isr", attr);
- if (a == NULL_TREE)
- a = lookup_attribute ("interrupt", attr);
-
- if (a == NULL_TREE)
- type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
- else
- type |= arm_isr_value (TREE_VALUE (a));
- }
-
+ type |= arm_isr_value (TREE_VALUE (a));
+
return type;
}
return cfun->machine->func_type;
}
\f
-/* Return 1 if it is possible to return using a single instruction.
+/* Return 1 if it is possible to return using a single instruction.
If SIBLING is non-null, this is a test for a return before a sibling
call. SIBLING is the call insn, so we can examine its register usage. */
if (current_function_pretend_args_size
|| cfun->machine->uses_anonymous_args
/* Or if the function calls __builtin_eh_return () */
- || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
+ || current_function_calls_eh_return
/* Or if the function calls alloca */
|| current_function_calls_alloca
/* Or if there is a stack adjustment. However, if the stack pointer
pointer won't be correctly restored if the instruction takes a
page fault. We work around this problem by popping r3 along with
the other registers, since that is never slower than executing
- another instruction.
+ another instruction.
We test for !arm_arch5 here, because code for any architecture
less than this could potentially be run on one of the buggy
taken and multiple registers have been stacked. */
if (iscond && arm_is_strong)
{
- /* Conditional return when just the LR is stored is a simple
+ /* Conditional return when just the LR is stored is a simple
conditional-load instruction, that's not expensive. */
if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
return 0;
{
unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
- /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
+ /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
be all zero, or all one. */
if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
&& ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
!= ((~(unsigned HOST_WIDE_INT) 0)
& ~(unsigned HOST_WIDE_INT) 0xffffffff)))
return FALSE;
-
+
/* Fast return for 0 and powers of 2 */
if ((i & (i - 1)) == 0)
return TRUE;
*/
if (!after_arm_reorg
&& !cond
- && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
+ && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1, 0)
> arm_constant_limit + (code != SET)))
{
}
}
- return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
+ return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1);
}
do
{
int end;
-
+
if (i <= 0)
i += 32;
if (remainder & (3 << (i - 2)))
{
if (generate)
emit_constant_insn (cond,
- gen_rtx_SET (VOIDmode, target,
+ gen_rtx_SET (VOIDmode, target,
gen_rtx_MINUS (mode, GEN_INT (val),
source)));
return 1;
if (generate)
emit_constant_insn (cond,
gen_rtx_SET (VOIDmode, target,
- (source
+ (source
? gen_rtx_fmt_ee (code, mode, source,
GEN_INT (val))
: GEN_INT (val))));
if (set_sign_bit_copies > 1)
{
if (const_ok_for_arm
- (temp1 = ARM_SIGN_EXTEND (remainder
+ (temp1 = ARM_SIGN_EXTEND (remainder
<< (set_sign_bit_copies - 1))))
{
if (generate)
{
rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
emit_constant_insn (cond,
- gen_rtx_SET (VOIDmode, new_src,
+ gen_rtx_SET (VOIDmode, new_src,
GEN_INT (temp1)));
emit_constant_insn (cond,
- gen_ashrsi3 (target, new_src,
+ gen_ashrsi3 (target, new_src,
GEN_INT (set_sign_bit_copies - 1)));
}
return 2;
gen_rtx_SET (VOIDmode, new_src,
GEN_INT (temp1)));
emit_constant_insn (cond,
- gen_ashrsi3 (target, new_src,
+ gen_ashrsi3 (target, new_src,
GEN_INT (set_sign_bit_copies - 1)));
}
return 2;
source, subtargets, generate);
source = new_src;
if (generate)
- emit_constant_insn
+ emit_constant_insn
(cond,
gen_rtx_SET
(VOIDmode, target,
rtx sub = subtargets ? gen_reg_rtx (mode) : target;
emit_constant_insn (cond,
- gen_rtx_SET (VOIDmode, sub,
+ gen_rtx_SET (VOIDmode, sub,
GEN_INT (val)));
emit_constant_insn (cond,
- gen_rtx_SET (VOIDmode, target,
+ gen_rtx_SET (VOIDmode, target,
gen_rtx_fmt_ee (code, mode,
source, sub)));
}
rtx sub = subtargets ? gen_reg_rtx (mode) : target;
rtx shift = GEN_INT (set_sign_bit_copies);
- emit_constant_insn
+ emit_constant_insn
(cond,
gen_rtx_SET (VOIDmode, sub,
- gen_rtx_NOT (mode,
+ gen_rtx_NOT (mode,
gen_rtx_ASHIFT (mode,
- source,
+ source,
shift))));
- emit_constant_insn
+ emit_constant_insn
(cond,
gen_rtx_SET (VOIDmode, target,
gen_rtx_NOT (mode,
gen_rtx_LSHIFTRT (mode,
source,
shift))));
- emit_constant_insn
+ emit_constant_insn
(cond,
gen_rtx_SET (VOIDmode, target,
gen_rtx_NOT (mode,
sub = gen_reg_rtx (mode);
emit_constant_insn (cond,
gen_rtx_SET (VOIDmode, sub,
- gen_rtx_AND (mode, source,
+ gen_rtx_AND (mode, source,
GEN_INT (temp1))));
emit_constant_insn (cond,
gen_rtx_SET (VOIDmode, target,
if (generate)
{
rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
- insns = arm_gen_constant (AND, mode, cond,
+ insns = arm_gen_constant (AND, mode, cond,
remainder | shift_mask,
new_src, source, subtargets, 1);
source = new_src;
if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
{
HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
-
+
if ((remainder | shift_mask) != 0xffffffff)
{
if (generate)
rather than having to synthesize both large constants from scratch.
Therefore, we calculate how many insns would be required to emit
- the constant starting from `best_start', and also starting from
- zero (ie with bit 31 first to be output). If `best_start' doesn't
+ the constant starting from `best_start', and also starting from
+ zero (i.e. with bit 31 first to be output). If `best_start' doesn't
yield a shorter sequence, we may as well use zero. */
if (best_start != 0
&& ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
- && (count_insns_for_constant (remainder, 0) <=
+ && (count_insns_for_constant (remainder, 0) <=
count_insns_for_constant (remainder, best_start)))
best_start = 0;
temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
emit_constant_insn (cond,
- gen_rtx_SET (VOIDmode, new_src,
+ gen_rtx_SET (VOIDmode, new_src,
temp1_rtx));
source = new_src;
}
/* Define how to find the value returned by a function. */
-rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
+rtx
+arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
{
enum machine_mode mode;
int unsignedp ATTRIBUTE_UNUSED;
rtx r ATTRIBUTE_UNUSED;
-
+
mode = TYPE_MODE (type);
/* Promote integer types. */
if (INTEGRAL_TYPE_P (type))
return LIBCALL_VALUE(mode);
}
+/* Determine the amount of memory needed to store the possible return
+ registers of an untyped call. */
+int
+arm_apply_result_size (void)
+{
+ int size = 16;
+
+ if (TARGET_ARM)
+ {
+ if (TARGET_HARD_FLOAT_ABI)
+ {
+ if (TARGET_FPA)
+ size += 12;
+ if (TARGET_MAVERICK)
+ size += 8;
+ }
+ if (TARGET_IWMMXT_ABI)
+ size += 8;
+ }
+
+ return size;
+}
/* Decide whether a type should be returned in memory (true)
or in a register (false). This is called by the macro
{
HOST_WIDE_INT size;
- if (!AGGREGATE_TYPE_P (type))
- /* All simple types are returned in registers. */
+ if (!AGGREGATE_TYPE_P (type) &&
+ !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
+ /* All simple types are returned in registers.
+ For AAPCS, complex types are treated the same as aggregates. */
return 0;
size = int_size_in_bytes (type);
larger than a word (or are variable size). */
return (size < 0 || size > UNITS_PER_WORD);
}
-
+
/* For the arm-wince targets we choose to be compatible with Microsoft's
ARM and Thumb compilers, which always return aggregates in memory. */
#ifndef ARM_WINCE
we will want to return it via memory and not in a register. */
if (size < 0 || size > UNITS_PER_WORD)
return 1;
-
+
if (TREE_CODE (type) == RECORD_TYPE)
{
tree field;
has an offset of zero. For practical purposes this means
that the structure can have at most one non bit-field element
and that this element must be the first one in the structure. */
-
+
/* Find the first field, ignoring non FIELD_DECL things which will
have been created by C++. */
for (field = TYPE_FIELDS (type);
field && TREE_CODE (field) != FIELD_DECL;
field = TREE_CHAIN (field))
continue;
-
+
if (field == NULL)
return 0; /* An empty structure. Allowed by an extension to ANSI C. */
{
if (TREE_CODE (field) != FIELD_DECL)
continue;
-
+
if (!DECL_BIT_FIELD_TYPE (field))
return 1;
}
return 0;
}
-
+
if (TREE_CODE (type) == UNION_TYPE)
{
tree field;
if (FLOAT_TYPE_P (TREE_TYPE (field)))
return 1;
-
+
if (RETURN_IN_MEMORY (TREE_TYPE (field)))
return 1;
}
-
+
return 0;
}
-#endif /* not ARM_WINCE */
-
+#endif /* not ARM_WINCE */
+
/* Return all other types in memory. */
return 1;
}
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is NULL. */
void
-arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
+arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
rtx libname ATTRIBUTE_UNUSED,
tree fndecl ATTRIBUTE_UNUSED)
{
pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
pcum->iwmmxt_nregs = 0;
pcum->can_split = true;
-
+
pcum->call_cookie = CALL_NORMAL;
if (TARGET_LONG_CALLS)
pcum->call_cookie = CALL_LONG;
-
+
/* Check for long call/short call attributes. The attributes
override any command line option. */
if (fntype)
/* Varargs vectors are treated the same as long long.
named_count avoids having to change the way arm handles 'named' */
if (TARGET_IWMMXT_ABI
- && VECTOR_MODE_SUPPORTED_P (mode)
+ && arm_vector_mode_supported_p (mode)
&& pcum->named_count > pcum->nargs + 1)
{
if (pcum->iwmmxt_nregs <= 9)
if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
return NULL_RTX;
-
- return gen_rtx_REG (mode, pcum->nregs);
-}
-
-/* Variable sized types are passed by reference. This is a GCC
- extension to the ARM ABI. */
-int
-arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
- enum machine_mode mode ATTRIBUTE_UNUSED,
- tree type, int named ATTRIBUTE_UNUSED)
-{
- return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
+ return gen_rtx_REG (mode, pcum->nregs);
}
-/* Implement va_arg. */
-
-rtx
-arm_va_arg (tree valist, tree type)
+static int
+arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
+ tree type, bool named ATTRIBUTE_UNUSED)
{
- int align;
+ int nregs = pcum->nregs;
- /* Variable sized types are passed by reference. */
- if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
- {
- rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
- return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
- }
+ if (arm_vector_mode_supported_p (mode))
+ return 0;
- align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type);
- if (align > PARM_BOUNDARY)
- {
- tree mask;
- tree t;
+ if (NUM_ARG_REGS > nregs
+ && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
+ && pcum->can_split)
+ return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
- /* Maintain 64-bit alignment of the valist pointer by
- constructing: valist = ((valist + (8 - 1)) & -8). */
- mask = build_int_2 (- (align / BITS_PER_UNIT), -1);
- t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0);
- t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
- t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask);
- t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
- TREE_SIDE_EFFECTS (t) = 1;
- expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
+ return 0;
+}
- /* This is to stop the combine pass optimizing
- away the alignment adjustment. */
- mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
- }
+/* Variable sized types are passed by reference. This is a GCC
+ extension to the ARM ABI. */
- return std_expand_builtin_va_arg (valist, type);
+static bool
+arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+ enum machine_mode mode ATTRIBUTE_UNUSED,
+ tree type, bool named ATTRIBUTE_UNUSED)
+{
+ return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
}
\f
/* Encode the current state of the #pragma [no_]long_calls. */
/* Whereas these functions are always known to reside within the 26 bit
addressing range. */
{ "short_call", 0, 0, false, true, true, NULL },
- /* Interrupt Service Routines have special prologue and epilogue requirements. */
+ /* Interrupt Service Routines have special prologue and epilogue requirements. */
{ "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
{ "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
{ "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
{ "dllimport", 0, 0, true, false, false, NULL },
{ "dllexport", 0, 0, true, false, false, NULL },
{ "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
+#elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
+ { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
+ { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
+ { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
#endif
{ NULL, 0, 0, false, false, false, NULL }
};
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
- warning ("`%s' attribute only applies to functions",
+ warning ("%qs attribute only applies to functions",
IDENTIFIER_POINTER (name));
*no_add_attrs = true;
}
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
- warning ("`%s' attribute only applies to functions",
+ warning ("%qs attribute only applies to functions",
IDENTIFIER_POINTER (name));
*no_add_attrs = true;
}
{
if (arm_isr_value (args) == ARM_FT_UNKNOWN)
{
- warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
+ warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
*no_add_attrs = true;
}
}
|| TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
&& arm_isr_value (args) != ARM_FT_UNKNOWN)
{
- *node = build_type_copy (*node);
+ *node = build_variant_type_copy (*node);
TREE_TYPE (*node) = build_type_attribute_variant
(TREE_TYPE (*node),
tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
}
else
{
- warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
+ warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
}
}
}
return NULL_TREE;
}
+#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
+/* Handle the "notshared" attribute. This attribute is another way of
+ requesting hidden visibility. ARM's compiler supports
+ "__declspec(notshared)"; we support the same thing via an
+ attribute. */
+
+static tree
+arm_handle_notshared_attribute (tree *node,
+ tree name ATTRIBUTE_UNUSED,
+ tree args ATTRIBUTE_UNUSED,
+ int flags ATTRIBUTE_UNUSED,
+ bool *no_add_attrs)
+{
+ tree decl = TYPE_NAME (*node);
+
+ if (decl)
+ {
+ DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
+ DECL_VISIBILITY_SPECIFIED (decl) = 1;
+ *no_add_attrs = false;
+ }
+ return NULL_TREE;
+}
+#endif
+
/* Return 0 if the attributes for two types are incompatible, 1 if they
are compatible, and 2 if they are nearly compatible (which causes a
warning to be generated). */
arm_comp_type_attributes (tree type1, tree type2)
{
int l1, l2, s1, s2;
-
+
/* Check for mismatch of non-default calling convention. */
if (TREE_CODE (type1) != FUNCTION_TYPE)
return 1;
if ((l1 & s2) || (l2 & s1))
return 0;
}
-
+
/* Check for mismatched ISR attribute. */
l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
if (! l1)
return 1;
/* The current function is always defined within the current compilation
- unit. if it s a weak definition however, then this may not be the real
+ unit. If it s a weak definition however, then this may not be the real
definition of the function, and so we have to say no. */
if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
&& !DECL_WEAK (current_function_decl))
a. has an __attribute__((long call))
or b. is within the scope of a #pragma long_calls
or c. the -mlong-calls command line switch has been specified
+ . and either:
+ 1. -ffunction-sections is in effect
+ or 2. the current function has __attribute__ ((section))
+ or 3. the target function has __attribute__ ((section))
However we do not generate a long call if the function:
-
+
d. has an __attribute__ ((short_call))
or e. is inside the scope of a #pragma no_long_calls
- or f. has an __attribute__ ((section))
- or g. is defined within the current compilation unit.
-
+ or f. is defined within the current compilation unit.
+
This function will be called by C fragments contained in the machine
- description file. CALL_REF and CALL_COOKIE correspond to the matched
+ description file. SYM_REF and CALL_COOKIE correspond to the matched
rtl operands. CALL_SYMBOL is used to distinguish between
two different callers of the function. It is set to 1 in the
"call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
if (call_cookie & CALL_SHORT)
return 0;
- if (TARGET_LONG_CALLS && flag_function_sections)
- return 1;
-
+ if (TARGET_LONG_CALLS)
+ {
+ if (flag_function_sections
+ || DECL_SECTION_NAME (current_function_decl))
+ /* c.3 is handled by the definition of the
+ ARM_DECLARE_FUNCTION_SIZE macro. */
+ return 1;
+ }
+
if (current_file_function_operand (sym_ref))
return 0;
-
+
return (call_cookie & CALL_LONG)
|| ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
|| TARGET_LONG_CALLS;
return false;
/* If we are interworking and the function is not declared static
- then we can't tail-call it unless we know that it exists in this
+ then we can't tail-call it unless we know that it exists in this
compilation unit (since it might be a Thumb routine). */
if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
return false;
emit_insn (gen_pic_load_addr_thumb (address, orig));
if ((GET_CODE (orig) == LABEL_REF
- || (GET_CODE (orig) == SYMBOL_REF &&
+ || (GET_CODE (orig) == SYMBOL_REF &&
SYMBOL_REF_LOCAL_P (orig)))
&& NEED_GOT_RELOC)
pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
else
{
- pic_ref = gen_rtx_MEM (Pmode,
- gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
- address));
- RTX_UNCHANGING_P (pic_ref) = 1;
+ pic_ref = gen_const_mem (Pmode,
+ gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
+ address));
}
insn = emit_move_insn (reg, pic_ref);
return orig;
}
-/* Generate code to load the PIC register. PROLOGUE is true if
- called from arm_expand_prologue (in which case we want the
- generated insns at the start of the function); false if called
- by an exception receiver that needs the PIC register reloaded
- (in which case the insns are just dumped at the current location). */
+
+/* Find a spare low register to use during the prolog of a function. */
+
+static int
+thumb_find_work_register (unsigned long pushed_regs_mask)
+{
+ int reg;
+
+ /* Check the argument registers first as these are call-used. The
+ register allocation order means that sometimes r3 might be used
+ but earlier argument registers might not, so check them all. */
+ for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
+ if (!regs_ever_live[reg])
+ return reg;
+
+ /* Before going on to check the call-saved registers we can try a couple
+ more ways of deducing that r3 is available. The first is when we are
+ pushing anonymous arguments onto the stack and we have less than 4
+ registers worth of fixed arguments(*). In this case r3 will be part of
+ the variable argument list and so we can be sure that it will be
+ pushed right at the start of the function. Hence it will be available
+ for the rest of the prologue.
+ (*): ie current_function_pretend_args_size is greater than 0. */
+ if (cfun->machine->uses_anonymous_args
+ && current_function_pretend_args_size > 0)
+ return LAST_ARG_REGNUM;
+
+ /* The other case is when we have fixed arguments but less than 4 registers
+ worth. In this case r3 might be used in the body of the function, but
+ it is not being used to convey an argument into the function. In theory
+ we could just check current_function_args_size to see how many bytes are
+ being passed in argument registers, but it seems that it is unreliable.
+ Sometimes it will have the value 0 when in fact arguments are being
+ passed. (See testcase execute/20021111-1.c for an example). So we also
+ check the args_info.nregs field as well. The problem with this field is
+ that it makes no allowances for arguments that are passed to the
+ function but which are not used. Hence we could miss an opportunity
+ when a function has an unused argument in r3. But it is better to be
+ safe than to be sorry. */
+ if (! cfun->machine->uses_anonymous_args
+ && current_function_args_size >= 0
+ && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
+ && cfun->args_info.nregs < 4)
+ return LAST_ARG_REGNUM;
+
+ /* Otherwise look for a call-saved register that is going to be pushed. */
+ for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
+ if (pushed_regs_mask & (1 << reg))
+ return reg;
+
+ /* Something went wrong - thumb_compute_save_reg_mask()
+ should have arranged for a suitable register to be pushed. */
+ abort ();
+}
+
+
+/* Generate code to load the PIC register. In thumb mode SCRATCH is a
+ low register. */
+
void
-arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
+arm_load_pic_register (unsigned int scratch)
{
#ifndef AOF_ASSEMBLER
- rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
+ rtx l1, pic_tmp, pic_tmp2, pic_rtx;
rtx global_offset_table;
if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
if (!flag_pic)
abort ();
- start_sequence ();
l1 = gen_label_rtx ();
global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
-
+
if (TARGET_ARM)
{
emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
}
else
{
- emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
+ if (REGNO (pic_offset_table_rtx) > LAST_LO_REGNUM)
+ {
+ /* We will have pushed the pic register, so should always be
+ able to find a work register. */
+ pic_tmp = gen_rtx_REG (SImode, scratch);
+ emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
+ emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
+ }
+ else
+ emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
}
- seq = get_insns ();
- end_sequence ();
- if (prologue)
- emit_insn_after (seq, get_insns ());
- else
- emit_insn (seq);
-
/* Need to emit this whether or not we obey regdecls,
since setjmp/longjmp can cause life info to screw up. */
emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
#endif /* AOF_ASSEMBLER */
}
+
/* Return nonzero if X is valid as an ARM state addressing register. */
static int
arm_address_register_rtx_p (rtx x, int strict_p)
{
bool use_ldrd;
enum rtx_code code = GET_CODE (x);
-
+
if (arm_address_register_rtx_p (x, strict_p))
return 1;
{
rtx addend = XEXP (XEXP (x, 1), 1);
- /* Don't allow ldrd post increment by register becuase it's hard
+ /* Don't allow ldrd post increment by register because it's hard
to fixup invalid register choices. */
if (use_ldrd
&& GET_CODE (x) == POST_MODIFY
if (TARGET_LDRD)
return val > -256 && val < 256;
else
- return val == 4 || val == -4 || val == -8;
+ return val > -4096 && val < 4092;
}
return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
}
/* Return nonzero if x is a legitimate Thumb-state address.
-
+
The AP may be eliminated to either the SP or the FP, so we use the
least common denominator, e.g. SImode, and offsets from 0 to 64.
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
- case ROTATERT:
+ case ROTATERT:
case PLUS:
case MINUS:
case COMPARE:
case NEG:
- case NOT:
+ case NOT:
return COSTS_N_INSNS (1);
-
- case MULT:
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
- {
- int cycles = 0;
+
+ case MULT:
+ if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ {
+ int cycles = 0;
unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
-
- while (i)
- {
- i >>= 2;
- cycles++;
- }
- return COSTS_N_INSNS (2) + cycles;
+
+ while (i)
+ {
+ i >>= 2;
+ cycles++;
+ }
+ return COSTS_N_INSNS (2) + cycles;
}
return COSTS_N_INSNS (1) + 16;
-
- case SET:
- return (COSTS_N_INSNS (1)
- + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
+
+ case SET:
+ return (COSTS_N_INSNS (1)
+ + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
+ GET_CODE (SET_DEST (x)) == MEM));
-
- case CONST_INT:
- if (outer == SET)
- {
- if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
- return 0;
- if (thumb_shiftable_const (INTVAL (x)))
- return COSTS_N_INSNS (2);
- return COSTS_N_INSNS (3);
- }
+
+ case CONST_INT:
+ if (outer == SET)
+ {
+ if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
+ return 0;
+ if (thumb_shiftable_const (INTVAL (x)))
+ return COSTS_N_INSNS (2);
+ return COSTS_N_INSNS (3);
+ }
else if ((outer == PLUS || outer == COMPARE)
- && INTVAL (x) < 256 && INTVAL (x) > -256)
+ && INTVAL (x) < 256 && INTVAL (x) > -256)
return 0;
else if (outer == AND
&& INTVAL (x) < 256 && INTVAL (x) >= -256)
return COSTS_N_INSNS (1);
- else if (outer == ASHIFT || outer == ASHIFTRT
- || outer == LSHIFTRT)
- return 0;
+ else if (outer == ASHIFT || outer == ASHIFTRT
+ || outer == LSHIFTRT)
+ return 0;
return COSTS_N_INSNS (2);
-
- case CONST:
- case CONST_DOUBLE:
- case LABEL_REF:
- case SYMBOL_REF:
+
+ case CONST:
+ case CONST_DOUBLE:
+ case LABEL_REF:
+ case SYMBOL_REF:
return COSTS_N_INSNS (3);
-
+
case UDIV:
case UMOD:
case DIV:
case AND:
case XOR:
- case IOR:
+ case IOR:
/* XXX guess. */
return 8;
- case ADDRESSOF:
case MEM:
/* XXX another guess. */
/* Memory costs quite a lot for the first word, but subsequent words
case QImode:
return (1 + (mode == DImode ? 4 : 0)
+ (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
-
+
case HImode:
return (4 + (mode == DImode ? 4 : 0)
+ (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
-
+
case SImode:
return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
-
+
default:
return 99;
}
-
+
default:
return 99;
}
case ASHIFT: case LSHIFTRT: case ASHIFTRT:
if (mode == DImode)
return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
- + ((GET_CODE (XEXP (x, 0)) == REG
+ + ((GET_CODE (XEXP (x, 0)) == REG
|| (GET_CODE (XEXP (x, 0)) == SUBREG
&& GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
? 0 : 8));
return 1;
/* Fall through */
- case PLUS:
+ case PLUS:
if (GET_MODE_CLASS (mode) == MODE_FLOAT)
return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
+ ((REG_OR_SUBREG_REG (XEXP (x, 1))
? 0 : 8));
/* Fall through */
- case AND: case XOR: case IOR:
+ case AND: case XOR: case IOR:
extra_cost = 0;
/* Normally the frame registers will be spilt into reg+const during
}
abort ();
- case CONST_INT:
- if (const_ok_for_arm (INTVAL (x)))
- return outer == SET ? 2 : -1;
- else if (outer == AND
- && const_ok_for_arm (~INTVAL (x)))
- return -1;
- else if ((outer == COMPARE
- || outer == PLUS || outer == MINUS)
- && const_ok_for_arm (-INTVAL (x)))
- return -1;
- else
+ case CONST_INT:
+ if (const_ok_for_arm (INTVAL (x)))
+ return outer == SET ? 2 : -1;
+ else if (outer == AND
+ && const_ok_for_arm (~INTVAL (x)))
+ return -1;
+ else if ((outer == COMPARE
+ || outer == PLUS || outer == MINUS)
+ && const_ok_for_arm (-INTVAL (x)))
+ return -1;
+ else
return 5;
-
- case CONST:
- case LABEL_REF:
- case SYMBOL_REF:
+
+ case CONST:
+ case LABEL_REF:
+ case SYMBOL_REF:
return 6;
-
- case CONST_DOUBLE:
+
+ case CONST_DOUBLE:
if (arm_const_double_rtx (x))
- return outer == SET ? 2 : -1;
- else if ((outer == COMPARE || outer == PLUS)
- && neg_const_double_rtx_ok_for_fpa (x))
- return -1;
+ return outer == SET ? 2 : -1;
+ else if ((outer == COMPARE || outer == PLUS)
+ && neg_const_double_rtx_ok_for_fpa (x))
+ return -1;
return 7;
-
+
default:
return 99;
}
}
-/* RTX costs for cores with a slow MUL implementation. */
-
+/* RTX costs when optimizing for size. */
static bool
-arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
+arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
{
enum machine_mode mode = GET_MODE (x);
if (TARGET_THUMB)
{
+ /* XXX TBD. For now, use the standard costs. */
*total = thumb_rtx_costs (x, code, outer_code);
return true;
}
-
+
switch (code)
{
- case MULT:
- if (GET_MODE_CLASS (mode) == MODE_FLOAT
- || mode == DImode)
- {
+ case MEM:
+ /* A memory access costs 1 insn if the mode is small, or the address is
+ a single register, otherwise it costs one insn per word. */
+ if (REG_P (XEXP (x, 0)))
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+ return true;
+
+ case DIV:
+ case MOD:
+ case UDIV:
+ case UMOD:
+ /* Needs a libcall, so it costs about this. */
+ *total = COSTS_N_INSNS (2);
+ return false;
+
+ case ROTATE:
+ if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
+ {
+ *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
+ return true;
+ }
+ /* Fall through */
+ case ROTATERT:
+ case ASHIFT:
+ case LSHIFTRT:
+ case ASHIFTRT:
+ if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ {
+ *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
+ return true;
+ }
+ else if (mode == SImode)
+ {
+ *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
+ /* Slightly disparage register shifts, but not by much. */
+ if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ *total += 1 + rtx_cost (XEXP (x, 1), code);
+ return true;
+ }
+
+ /* Needs a libcall. */
+ *total = COSTS_N_INSNS (2);
+ return false;
+
+ case MINUS:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
+ {
+ *total = COSTS_N_INSNS (1);
+ return false;
+ }
+
+ if (mode == SImode)
+ {
+ enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
+ enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
+
+ if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
+ || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
+ || subcode1 == ROTATE || subcode1 == ROTATERT
+ || subcode1 == ASHIFT || subcode1 == LSHIFTRT
+ || subcode1 == ASHIFTRT)
+ {
+ /* It's just the cost of the two operands. */
+ *total = 0;
+ return false;
+ }
+
+ *total = COSTS_N_INSNS (1);
+ return false;
+ }
+
+ *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case PLUS:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
+ {
+ *total = COSTS_N_INSNS (1);
+ return false;
+ }
+
+ /* Fall through */
+ case AND: case XOR: case IOR:
+ if (mode == SImode)
+ {
+ enum rtx_code subcode = GET_CODE (XEXP (x, 0));
+
+ if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
+ || subcode == LSHIFTRT || subcode == ASHIFTRT
+ || (code == AND && subcode == NOT))
+ {
+ /* It's just the cost of the two operands. */
+ *total = 0;
+ return false;
+ }
+ }
+
+ *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case MULT:
+ *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case NEG:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
+ *total = COSTS_N_INSNS (1);
+ /* Fall through */
+ case NOT:
+ *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+
+ return false;
+
+ case IF_THEN_ELSE:
+ *total = 0;
+ return false;
+
+ case COMPARE:
+ if (cc_register (XEXP (x, 0), VOIDmode))
+ * total = 0;
+ else
+ *total = COSTS_N_INSNS (1);
+ return false;
+
+ case ABS:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
+ return false;
+
+ case SIGN_EXTEND:
+ *total = 0;
+ if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
+ {
+ if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
+ *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
+ }
+ if (mode == DImode)
+ *total += COSTS_N_INSNS (1);
+ return false;
+
+ case ZERO_EXTEND:
+ *total = 0;
+ if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
+ {
+ switch (GET_MODE (XEXP (x, 0)))
+ {
+ case QImode:
+ *total += COSTS_N_INSNS (1);
+ break;
+
+ case HImode:
+ *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
+
+ case SImode:
+ break;
+
+ default:
+ *total += COSTS_N_INSNS (2);
+ }
+ }
+
+ if (mode == DImode)
+ *total += COSTS_N_INSNS (1);
+
+ return false;
+
+ case CONST_INT:
+ if (const_ok_for_arm (INTVAL (x)))
+ *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
+ else if (const_ok_for_arm (~INTVAL (x)))
+ *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
+ else if (const_ok_for_arm (-INTVAL (x)))
+ {
+ if (outer_code == COMPARE || outer_code == PLUS
+ || outer_code == MINUS)
+ *total = 0;
+ else
+ *total = COSTS_N_INSNS (1);
+ }
+ else
+ *total = COSTS_N_INSNS (2);
+ return true;
+
+ case CONST:
+ case LABEL_REF:
+ case SYMBOL_REF:
+ *total = COSTS_N_INSNS (2);
+ return true;
+
+ case CONST_DOUBLE:
+ *total = COSTS_N_INSNS (4);
+ return true;
+
+ default:
+ if (mode != VOIDmode)
+ *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+ else
+ *total = COSTS_N_INSNS (4); /* How knows? */
+ return false;
+ }
+}
+
+/* RTX costs for cores with a slow MUL implementation. */
+
+static bool
+arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
+{
+ enum machine_mode mode = GET_MODE (x);
+
+ if (TARGET_THUMB)
+ {
+ *total = thumb_rtx_costs (x, code, outer_code);
+ return true;
+ }
+
+ switch (code)
+ {
+ case MULT:
+ if (GET_MODE_CLASS (mode) == MODE_FLOAT
+ || mode == DImode)
+ {
*total = 30;
return true;
}
int cost, const_ok = const_ok_for_arm (i);
int j, booth_unit_size;
- /* Tune as appropriate. */
+ /* Tune as appropriate. */
cost = const_ok ? 4 : 8;
booth_unit_size = 2;
for (j = 0; i && j < 32; j += booth_unit_size)
*total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
+ (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
return true;
-
+
default:
*total = arm_rtx_costs_1 (x, code, outer_code);
return true;
*total = thumb_rtx_costs (x, code, outer_code);
return true;
}
-
+
switch (code)
{
case MULT:
*total = 8;
return true;
}
-
+
if (GET_MODE_CLASS (mode) == MODE_FLOAT
|| mode == DImode)
int cost, const_ok = const_ok_for_arm (i);
int j, booth_unit_size;
- /* Tune as appropriate. */
+ /* Tune as appropriate. */
cost = const_ok ? 4 : 8;
booth_unit_size = 8;
for (j = 0; i && j < 32; j += booth_unit_size)
*total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
+ (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
return true;
-
+
default:
*total = arm_rtx_costs_1 (x, code, outer_code);
return true;
*total = thumb_rtx_costs (x, code, outer_code);
return true;
}
-
+
switch (code)
{
case MULT:
*total = 8;
return true;
}
-
+
if (GET_MODE_CLASS (mode) == MODE_FLOAT
|| mode == DImode)
*total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
+ (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
return true;
-
+
+ case COMPARE:
+ /* A COMPARE of a MULT is slow on XScale; the muls instruction
+ will stall until the multiplication is complete. */
+ if (GET_CODE (XEXP (x, 0)) == MULT)
+ *total = 4 + rtx_cost (XEXP (x, 0), code);
+ else
+ *total = arm_rtx_costs_1 (x, code, outer_code);
+ return true;
+
default:
*total = arm_rtx_costs_1 (x, code, outer_code);
return true;
enum machine_mode mode = GET_MODE (x);
int nonreg_cost;
int cost;
-
+
if (TARGET_THUMB)
{
switch (code)
case MULT:
*total = COSTS_N_INSNS (3);
return true;
-
+
default:
*total = thumb_rtx_costs (x, code, outer_code);
return true;
}
}
-
+
switch (code)
{
case MULT:
*total = 3;
return true;
}
-
+
if (GET_MODE_CLASS (mode) == MODE_FLOAT)
{
*total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
+ (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
return true;
-
+
default:
*total = arm_rtx_costs_1 (x, code, outer_code);
return true;
}
static int
-arm_use_dfa_pipeline_interface (void)
-{
- return true;
-}
-
-static int
arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
{
rtx i_pat, d_pat;
{
rtx shifted_operand;
int opno;
-
+
/* Get the shifted operand. */
extract_insn (insn);
shifted_operand = recog_data.operand[shift_opnum];
rtx src_mem = XEXP (SET_SRC (i_pat), 0);
/* This is a load after a store, there is no conflict if the load reads
from a cached area. Assume that loads from the stack, and from the
- constant pool are cached, and that others will miss. This is a
+ constant pool are cached, and that others will miss. This is a
hack. */
-
+
if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
|| reg_mentioned_p (stack_pointer_rtx, src_mem)
|| reg_mentioned_p (frame_pointer_rtx, src_mem)
{
REAL_VALUE_TYPE r;
int i;
-
+
if (!fp_consts_inited)
init_fp_table ();
-
+
REAL_VALUE_FROM_CONST_DOUBLE (r, x);
if (REAL_VALUE_MINUS_ZERO (r))
return 0;
{
REAL_VALUE_TYPE r;
int i;
-
+
if (!fp_consts_inited)
init_fp_table ();
-
+
REAL_VALUE_FROM_CONST_DOUBLE (r, x);
r = REAL_VALUE_NEGATE (r);
if (REAL_VALUE_MINUS_ZERO (r))
\f
/* Predicates for `match_operand' and `match_operator'. */
-/* s_register_operand is the same as register_operand, but it doesn't accept
- (SUBREG (MEM)...).
-
- This function exists because at the time it was put in it led to better
- code. SUBREG(MEM) always needs a reload in the places where
- s_register_operand is used, and this seemed to lead to excessive
- reloading. */
-int
-s_register_operand (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- /* We don't consider registers whose class is NO_REGS
- to be a register operand. */
- /* XXX might have to check for lo regs only for thumb ??? */
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
-}
-
-/* A hard register operand (even before reload. */
-int
-arm_hard_register_operand (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- return (GET_CODE (op) == REG
- && REGNO (op) < FIRST_PSEUDO_REGISTER);
-}
-
-/* An arm register operand. */
-int
-arm_general_register_operand (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- return (GET_CODE (op) == REG
- && (REGNO (op) <= LAST_ARM_REGNUM
- || REGNO (op) >= FIRST_PSEUDO_REGISTER));
-}
-
-/* Only accept reg, subreg(reg), const_int. */
-int
-reg_or_int_operand (rtx op, enum machine_mode mode)
-{
- if (GET_CODE (op) == CONST_INT)
- return 1;
-
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- /* We don't consider registers whose class is NO_REGS
- to be a register operand. */
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
-}
-
-/* Return 1 if OP is an item in memory, given that we are in reload. */
-int
-arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- int regno = true_regnum (op);
-
- return (!CONSTANT_P (op)
- && (regno == -1
- || (GET_CODE (op) == REG
- && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
-}
-
-/* Return TRUE for valid operands for the rhs of an ARM instruction. */
-int
-arm_rhs_operand (rtx op, enum machine_mode mode)
-{
- return (s_register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
-}
-
-/* Return TRUE for valid operands for the
- rhs of an ARM instruction, or a load. */
-int
-arm_rhsm_operand (rtx op, enum machine_mode mode)
-{
- return (s_register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
- || memory_operand (op, mode));
-}
-
-/* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
- constant that is valid when negated. */
-int
-arm_add_operand (rtx op, enum machine_mode mode)
-{
- if (TARGET_THUMB)
- return thumb_cmp_operand (op, mode);
-
- return (s_register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT
- && (const_ok_for_arm (INTVAL (op))
- || const_ok_for_arm (-INTVAL (op)))));
-}
-
-/* Return TRUE for valid ARM constants (or when valid if negated). */
-int
-arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == CONST_INT
- && (const_ok_for_arm (INTVAL (op))
- || const_ok_for_arm (-INTVAL (op))));
-}
-
-int
-arm_not_operand (rtx op, enum machine_mode mode)
-{
- return (s_register_operand (op, mode)
- || (GET_CODE (op) == CONST_INT
- && (const_ok_for_arm (INTVAL (op))
- || const_ok_for_arm (~INTVAL (op)))));
-}
-
-/* Return TRUE if the operand is a memory reference which contains an
- offsettable address. */
-int
-offsettable_memory_operand (rtx op, enum machine_mode mode)
-{
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- return (mode == GET_MODE (op)
- && GET_CODE (op) == MEM
- && offsettable_address_p (reload_completed | reload_in_progress,
- mode, XEXP (op, 0)));
-}
-
-/* Return TRUE if the operand is a memory reference which is, or can be
- made word aligned by adjusting the offset. */
-int
-alignable_memory_operand (rtx op, enum machine_mode mode)
-{
- rtx reg;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
- return 0;
-
- op = XEXP (op, 0);
-
- return ((GET_CODE (reg = op) == REG
- || (GET_CODE (op) == SUBREG
- && GET_CODE (reg = SUBREG_REG (op)) == REG)
- || (GET_CODE (op) == PLUS
- && GET_CODE (XEXP (op, 1)) == CONST_INT
- && (GET_CODE (reg = XEXP (op, 0)) == REG
- || (GET_CODE (XEXP (op, 0)) == SUBREG
- && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
- && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
-}
-
-/* Similar to s_register_operand, but does not allow hard integer
- registers. */
-int
-f_register_operand (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return 0;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- /* We don't consider registers whose class is NO_REGS
- to be a register operand. */
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
-}
-
-/* Return TRUE for valid operands for the rhs of an floating point insns.
- Allows regs or certain consts on FPA, just regs for everything else. */
-int
-arm_float_rhs_operand (rtx op, enum machine_mode mode)
-{
- if (s_register_operand (op, mode))
- return TRUE;
-
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return FALSE;
-
- if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
- return arm_const_double_rtx (op);
-
- return FALSE;
-}
-
-int
-arm_float_add_operand (rtx op, enum machine_mode mode)
-{
- if (s_register_operand (op, mode))
- return TRUE;
-
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return FALSE;
-
- if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
- return (arm_const_double_rtx (op)
- || neg_const_double_rtx_ok_for_fpa (op));
-
- return FALSE;
-}
-
-
-/* Return TRUE if OP is suitable for the rhs of a floating point comparison.
- Depends which fpu we are targeting. */
-
-int
-arm_float_compare_operand (rtx op, enum machine_mode mode)
-{
- if (TARGET_VFP)
- return vfp_compare_operand (op, mode);
- else
- return arm_float_rhs_operand (op, mode);
-}
-
-
/* Return nonzero if OP is a valid Cirrus memory address pattern. */
int
cirrus_memory_offset (rtx op)
return 0;
}
-int
-arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
-{
- if (!memory_operand (op, mode))
- return 0;
-
- return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
-}
-
-/* Return nonzero if OP is a Cirrus or general register. */
-int
-cirrus_register_operand (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return FALSE;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- return (GET_CODE (op) == REG
- && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
- || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
-}
-
-/* Return nonzero if OP is a cirrus FP register. */
-int
-cirrus_fp_register (rtx op, enum machine_mode mode)
-{
- if (GET_MODE (op) != mode && mode != VOIDmode)
- return FALSE;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
-}
-
-/* Return nonzero if OP is a 6bit constant (0..63). */
-int
-cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == CONST_INT
- && INTVAL (op) >= 0
- && INTVAL (op) < 64);
-}
-
-
/* Return TRUE if OP is a valid VFP memory address pattern.
WB if true if writeback address modes are allowed. */
return FALSE;
}
-
-/* Return TRUE if OP is a REG or constant zero. */
+/* Return true if X is a register that will be eliminated later on. */
int
-vfp_compare_operand (rtx op, enum machine_mode mode)
+arm_eliminable_register (rtx x)
{
- if (s_register_operand (op, mode))
- return TRUE;
-
- return (GET_CODE (op) == CONST_DOUBLE
- && arm_const_double_rtx (op));
+ return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
+ || REGNO (x) == ARG_POINTER_REGNUM
+ || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
+ && REGNO (x) <= LAST_VIRTUAL_REGISTER));
}
-
/* Return GENERAL_REGS if a scratch register required to reload x to/from
VFP registers. Otherwise return NO_REGS. */
int nops;
/* Any branch must be followed by 2 non Cirrus instructions. */
- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
- {
- nops = 0;
- t = next_nonnote_insn (first);
-
- if (arm_cirrus_insn_p (t))
- ++ nops;
-
- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
- ++ nops;
-
- while (nops --)
- emit_insn_after (gen_nop (), first);
-
- return;
- }
-
- /* (float (blah)) is in parallel with a clobber. */
- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
- body = XVECEXP (body, 0, 0);
-
- if (GET_CODE (body) == SET)
- {
- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
-
- /* cfldrd, cfldr64, cfstrd, cfstr64 must
- be followed by a non Cirrus insn. */
- if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
- {
- if (arm_cirrus_insn_p (next_nonnote_insn (first)))
- emit_insn_after (gen_nop (), first);
-
- return;
- }
- else if (arm_memory_load_p (first))
- {
- unsigned int arm_regno;
-
- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
- ldr/cfmv64hr combination where the Rd field is the same
- in both instructions must be split with a non Cirrus
- insn. Example:
-
- ldr r0, blah
- nop
- cfmvsr mvf0, r0. */
-
- /* Get Arm register number for ldr insn. */
- if (GET_CODE (lhs) == REG)
- arm_regno = REGNO (lhs);
- else if (GET_CODE (rhs) == REG)
- arm_regno = REGNO (rhs);
- else
- abort ();
-
- /* Next insn. */
- first = next_nonnote_insn (first);
-
- if (! arm_cirrus_insn_p (first))
- return;
-
- body = PATTERN (first);
-
- /* (float (blah)) is in parallel with a clobber. */
- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
- body = XVECEXP (body, 0, 0);
-
- if (GET_CODE (body) == FLOAT)
- body = XEXP (body, 0);
-
- if (get_attr_cirrus (first) == CIRRUS_MOVE
- && GET_CODE (XEXP (body, 1)) == REG
- && arm_regno == REGNO (XEXP (body, 1)))
- emit_insn_after (gen_nop (), first);
-
- return;
- }
- }
-
- /* get_attr aborts on USE and CLOBBER. */
- if (!first
- || GET_CODE (first) != INSN
- || GET_CODE (PATTERN (first)) == USE
- || GET_CODE (PATTERN (first)) == CLOBBER)
- return;
-
- attr = get_attr_cirrus (first);
-
- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
- must be followed by a non-coprocessor instruction. */
- if (attr == CIRRUS_COMPARE)
- {
- nops = 0;
-
- t = next_nonnote_insn (first);
-
- if (arm_cirrus_insn_p (t))
- ++ nops;
-
- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
- ++ nops;
-
- while (nops --)
- emit_insn_after (gen_nop (), first);
-
- return;
- }
-}
-
-/* Return nonzero if OP is a constant power of two. */
-int
-power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (op) == CONST_INT)
- {
- HOST_WIDE_INT value = INTVAL (op);
-
- return value != 0 && (value & (value - 1)) == 0;
- }
-
- return FALSE;
-}
-
-/* Return TRUE for a valid operand of a DImode operation.
- Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
- Note that this disallows MEM(REG+REG), but allows
- MEM(PRE/POST_INC/DEC(REG)). */
-int
-di_operand (rtx op, enum machine_mode mode)
-{
- if (s_register_operand (op, mode))
- return TRUE;
-
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
- return FALSE;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- switch (GET_CODE (op))
- {
- case CONST_DOUBLE:
- case CONST_INT:
- return TRUE;
-
- case MEM:
- return memory_address_p (DImode, XEXP (op, 0));
-
- default:
- return FALSE;
- }
-}
-
-/* Like di_operand, but don't accept constants. */
-int
-nonimmediate_di_operand (rtx op, enum machine_mode mode)
-{
- if (s_register_operand (op, mode))
- return TRUE;
-
- if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
- return FALSE;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- if (GET_CODE (op) == MEM)
- return memory_address_p (DImode, XEXP (op, 0));
-
- return FALSE;
-}
-
-/* Return TRUE for a valid operand of a DFmode operation when soft-float.
- Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
- Note that this disallows MEM(REG+REG), but allows
- MEM(PRE/POST_INC/DEC(REG)). */
-int
-soft_df_operand (rtx op, enum machine_mode mode)
-{
- if (s_register_operand (op, mode))
- return TRUE;
-
- if (mode != VOIDmode && GET_MODE (op) != mode)
- return FALSE;
-
- if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
- return FALSE;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- switch (GET_CODE (op))
- {
- case CONST_DOUBLE:
- return TRUE;
-
- case MEM:
- return memory_address_p (DFmode, XEXP (op, 0));
-
- default:
- return FALSE;
- }
-}
-
-/* Like soft_df_operand, but don't accept constants. */
-int
-nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
-{
- if (s_register_operand (op, mode))
- return TRUE;
-
- if (mode != VOIDmode && GET_MODE (op) != mode)
- return FALSE;
-
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- if (GET_CODE (op) == MEM)
- return memory_address_p (DFmode, XEXP (op, 0));
- return FALSE;
-}
+ if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
+ {
+ nops = 0;
+ t = next_nonnote_insn (first);
-/* Return TRUE for valid index operands. */
-int
-index_operand (rtx op, enum machine_mode mode)
-{
- return (s_register_operand (op, mode)
- || (immediate_operand (op, mode)
- && (GET_CODE (op) != CONST_INT
- || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
-}
+ if (arm_cirrus_insn_p (t))
+ ++ nops;
-/* Return TRUE for valid shifts by a constant. This also accepts any
- power of two on the (somewhat overly relaxed) assumption that the
- shift operator in this case was a mult. */
-int
-const_shift_operand (rtx op, enum machine_mode mode)
-{
- return (power_of_two_operand (op, mode)
- || (immediate_operand (op, mode)
- && (GET_CODE (op) != CONST_INT
- || (INTVAL (op) < 32 && INTVAL (op) > 0))));
-}
+ if (arm_cirrus_insn_p (next_nonnote_insn (t)))
+ ++ nops;
-/* Return TRUE for arithmetic operators which can be combined with a multiply
- (shift). */
-int
-shiftable_operator (rtx x, enum machine_mode mode)
-{
- enum rtx_code code;
+ while (nops --)
+ emit_insn_after (gen_nop (), first);
- if (GET_MODE (x) != mode)
- return FALSE;
+ return;
+ }
- code = GET_CODE (x);
+ /* (float (blah)) is in parallel with a clobber. */
+ if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
+ body = XVECEXP (body, 0, 0);
- return (code == PLUS || code == MINUS
- || code == IOR || code == XOR || code == AND);
-}
+ if (GET_CODE (body) == SET)
+ {
+ rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
-/* Return TRUE for binary logical operators. */
-int
-logical_binary_operator (rtx x, enum machine_mode mode)
-{
- enum rtx_code code;
+ /* cfldrd, cfldr64, cfstrd, cfstr64 must
+ be followed by a non Cirrus insn. */
+ if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
+ {
+ if (arm_cirrus_insn_p (next_nonnote_insn (first)))
+ emit_insn_after (gen_nop (), first);
- if (GET_MODE (x) != mode)
- return FALSE;
+ return;
+ }
+ else if (arm_memory_load_p (first))
+ {
+ unsigned int arm_regno;
- code = GET_CODE (x);
+ /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
+ ldr/cfmv64hr combination where the Rd field is the same
+ in both instructions must be split with a non Cirrus
+ insn. Example:
- return (code == IOR || code == XOR || code == AND);
-}
+ ldr r0, blah
+ nop
+ cfmvsr mvf0, r0. */
-/* Return TRUE for shift operators. */
-int
-shift_operator (rtx x,enum machine_mode mode)
-{
- enum rtx_code code;
+ /* Get Arm register number for ldr insn. */
+ if (GET_CODE (lhs) == REG)
+ arm_regno = REGNO (lhs);
+ else if (GET_CODE (rhs) == REG)
+ arm_regno = REGNO (rhs);
+ else
+ abort ();
- if (GET_MODE (x) != mode)
- return FALSE;
+ /* Next insn. */
+ first = next_nonnote_insn (first);
- code = GET_CODE (x);
+ if (! arm_cirrus_insn_p (first))
+ return;
- if (code == MULT)
- return power_of_two_operand (XEXP (x, 1), mode);
+ body = PATTERN (first);
- return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
- || code == ROTATERT);
-}
+ /* (float (blah)) is in parallel with a clobber. */
+ if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
+ body = XVECEXP (body, 0, 0);
-/* Return TRUE if x is EQ or NE. */
-int
-equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return GET_CODE (x) == EQ || GET_CODE (x) == NE;
-}
+ if (GET_CODE (body) == FLOAT)
+ body = XEXP (body, 0);
-/* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
-int
-arm_comparison_operator (rtx x, enum machine_mode mode)
-{
- return (comparison_operator (x, mode)
- && GET_CODE (x) != LTGT
- && GET_CODE (x) != UNEQ);
-}
+ if (get_attr_cirrus (first) == CIRRUS_MOVE
+ && GET_CODE (XEXP (body, 1)) == REG
+ && arm_regno == REGNO (XEXP (body, 1)))
+ emit_insn_after (gen_nop (), first);
-/* Return TRUE for SMIN SMAX UMIN UMAX operators. */
-int
-minmax_operator (rtx x, enum machine_mode mode)
-{
- enum rtx_code code = GET_CODE (x);
+ return;
+ }
+ }
- if (GET_MODE (x) != mode)
- return FALSE;
+ /* get_attr aborts on USE and CLOBBER. */
+ if (!first
+ || GET_CODE (first) != INSN
+ || GET_CODE (PATTERN (first)) == USE
+ || GET_CODE (PATTERN (first)) == CLOBBER)
+ return;
- return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
-}
+ attr = get_attr_cirrus (first);
-/* Return TRUE if this is the condition code register, if we aren't given
- a mode, accept any class CCmode register. */
-int
-cc_register (rtx x, enum machine_mode mode)
-{
- if (mode == VOIDmode)
+ /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
+ must be followed by a non-coprocessor instruction. */
+ if (attr == CIRRUS_COMPARE)
{
- mode = GET_MODE (x);
-
- if (GET_MODE_CLASS (mode) != MODE_CC)
- return FALSE;
- }
+ nops = 0;
- if ( GET_MODE (x) == mode
- && GET_CODE (x) == REG
- && REGNO (x) == CC_REGNUM)
- return TRUE;
+ t = next_nonnote_insn (first);
- return FALSE;
-}
+ if (arm_cirrus_insn_p (t))
+ ++ nops;
-/* Return TRUE if this is the condition code register, if we aren't given
- a mode, accept any class CCmode register which indicates a dominance
- expression. */
-int
-dominant_cc_register (rtx x, enum machine_mode mode)
-{
- if (mode == VOIDmode)
- {
- mode = GET_MODE (x);
-
- if (GET_MODE_CLASS (mode) != MODE_CC)
- return FALSE;
- }
+ if (arm_cirrus_insn_p (next_nonnote_insn (t)))
+ ++ nops;
- if (mode != CC_DNEmode && mode != CC_DEQmode
- && mode != CC_DLEmode && mode != CC_DLTmode
- && mode != CC_DGEmode && mode != CC_DGTmode
- && mode != CC_DLEUmode && mode != CC_DLTUmode
- && mode != CC_DGEUmode && mode != CC_DGTUmode)
- return FALSE;
+ while (nops --)
+ emit_insn_after (gen_nop (), first);
- return cc_register (x, mode);
+ return;
+ }
}
/* Return TRUE if X references a SYMBOL_REF. */
return 1;
fmt = GET_RTX_FORMAT (GET_CODE (x));
-
+
for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
{
if (fmt[i] == 'E')
|| (GET_CODE (XEXP (b, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
{
- int val0 = 0, val1 = 0;
- int reg0, reg1;
-
+ HOST_WIDE_INT val0 = 0, val1 = 0;
+ rtx reg0, reg1;
+ int val_diff;
+
if (GET_CODE (XEXP (a, 0)) == PLUS)
{
- reg0 = REGNO (XEXP (XEXP (a, 0), 0));
+ reg0 = XEXP (XEXP (a, 0), 0);
val0 = INTVAL (XEXP (XEXP (a, 0), 1));
}
else
- reg0 = REGNO (XEXP (a, 0));
+ reg0 = XEXP (a, 0);
if (GET_CODE (XEXP (b, 0)) == PLUS)
{
- reg1 = REGNO (XEXP (XEXP (b, 0), 0));
+ reg1 = XEXP (XEXP (b, 0), 0);
val1 = INTVAL (XEXP (XEXP (b, 0), 1));
}
else
- reg1 = REGNO (XEXP (b, 0));
+ reg1 = XEXP (b, 0);
/* Don't accept any offset that will require multiple
instructions to handle, since this would cause the
arith_adjacentmem pattern to output an overlong sequence. */
if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
return 0;
-
- return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
- }
- return 0;
-}
-
-/* Return 1 if OP is a load multiple operation. It is known to be
- parallel and the first section will be tested. */
-int
-load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- HOST_WIDE_INT count = XVECLEN (op, 0);
- int dest_regno;
- rtx src_addr;
- HOST_WIDE_INT i = 1, base = 0;
- rtx elt;
-
- if (count <= 1
- || GET_CODE (XVECEXP (op, 0, 0)) != SET)
- return 0;
-
- /* Check to see if this might be a write-back. */
- if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
- {
- i++;
- base = 1;
-
- /* Now check it more carefully. */
- if (GET_CODE (SET_DEST (elt)) != REG
- || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
- || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
- || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
- return 0;
- }
-
- /* Perform a quick check so we don't blow up below. */
- if (count <= i
- || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
- || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
- return 0;
-
- dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
- src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
-
- for (; i < count; i++)
- {
- elt = XVECEXP (op, 0, i);
-
- if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
- || GET_MODE (SET_DEST (elt)) != SImode
- || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
- || GET_CODE (SET_SRC (elt)) != MEM
- || GET_MODE (SET_SRC (elt)) != SImode
- || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
- || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
- || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
- || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
- return 0;
- }
-
- return 1;
-}
-
-/* Return 1 if OP is a store multiple operation. It is known to be
- parallel and the first section will be tested. */
-int
-store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- HOST_WIDE_INT count = XVECLEN (op, 0);
- int src_regno;
- rtx dest_addr;
- HOST_WIDE_INT i = 1, base = 0;
- rtx elt;
-
- if (count <= 1
- || GET_CODE (XVECEXP (op, 0, 0)) != SET)
- return 0;
-
- /* Check to see if this might be a write-back. */
- if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
- {
- i++;
- base = 1;
-
- /* Now check it more carefully. */
- if (GET_CODE (SET_DEST (elt)) != REG
- || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
- || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
- || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
- return 0;
- }
-
- /* Perform a quick check so we don't blow up below. */
- if (count <= i
- || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
- return 0;
-
- src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
- dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
- for (; i < count; i++)
- {
- elt = XVECEXP (op, 0, i);
+ /* Don't allow an eliminable register: register elimination can make
+ the offset too large. */
+ if (arm_eliminable_register (reg0))
+ return 0;
- if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
- || GET_MODE (SET_SRC (elt)) != SImode
- || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
- || GET_CODE (SET_DEST (elt)) != MEM
- || GET_MODE (SET_DEST (elt)) != SImode
- || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
- || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
- || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
- || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
- return 0;
+ val_diff = val1 - val0;
+ return ((REGNO (reg0) == REGNO (reg1))
+ && (val_diff == 4 || val_diff == -4));
}
- return 1;
+ return 0;
}
int
abort ();
/* Loop over the operands and check that the memory references are
- suitable (ie immediate offsets from the same base register). At
+ suitable (i.e. immediate offsets from the same base register). At
the same time, extract the target register, and the memory
offsets. */
for (i = 0; i < nops; i++)
: REGNO (SUBREG_REG (operands[i])));
order[0] = 0;
}
- else
+ else
{
if (base_reg != (int) REGNO (reg))
/* Not addressed from the same base register. */
scratch register (one of the result regs) and then doing a load
multiple actually becomes slower (and no smaller in code size).
That is the transformation
-
+
ldr rd1, [rbase + offset]
ldr rd2, [rbase + offset + 4]
-
+
to
-
+
add rd1, rbase, offset
ldmia rd1, {rd1, rd2}
-
+
produces worse code -- '3 cycles + any stalls on rd2' instead of
'2 cycles + any stalls on rd2'. On ARMs with only one cache
access per cycle, the first sequence could never complete in less
/* Can't do it without setting up the offset, only do this if it takes
no more than one insn. */
- return (const_ok_for_arm (unsorted_offsets[order[0]])
+ return (const_ok_for_arm (unsorted_offsets[order[0]])
|| const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
}
abort ();
}
- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
+ sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
for (i = 1; i < nops; i++)
abort ();
/* Loop over the operands and check that the memory references are
- suitable (ie immediate offsets from the same base register). At
+ suitable (i.e. immediate offsets from the same base register). At
the same time, extract the target register, and the memory
offsets. */
for (i = 0; i < nops; i++)
: REGNO (SUBREG_REG (operands[i])));
order[0] = 0;
}
- else
+ else
{
if (base_reg != (int) REGNO (reg))
/* Not addressed from the same base register. */
abort ();
}
- sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
+ sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
for (i = 1; i < nops; i++)
return "";
}
-int
-multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (op) != PARALLEL
- || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
- || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
- || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
- return 0;
-
- return 1;
-}
\f
/* Routines for use in generating RTL. */
rtx
arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
- int write_back, int unchanging_p, int in_struct_p,
- int scalar_p)
+ int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
{
+ HOST_WIDE_INT offset = *offsetp;
int i = 0, j;
rtx result;
int sign = up ? 1 : -1;
- rtx mem;
+ rtx mem, addr;
/* XScale has load-store double instructions, but they have stricter
- alignment requirements than load-store multiple, so we can not
+ alignment requirements than load-store multiple, so we cannot
use them.
For XScale ldm requires 2 + NREGS cycles to complete and blocks
if (arm_tune_xscale && count <= 2 && ! optimize_size)
{
rtx seq;
-
+
start_sequence ();
-
+
for (i = 0; i < count; i++)
{
- mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
- RTX_UNCHANGING_P (mem) = unchanging_p;
- MEM_IN_STRUCT_P (mem) = in_struct_p;
- MEM_SCALAR_P (mem) = scalar_p;
+ addr = plus_constant (from, i * 4 * sign);
+ mem = adjust_automodify_address (basemem, SImode, addr, offset);
emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
+ offset += 4 * sign;
}
if (write_back)
- emit_move_insn (from, plus_constant (from, count * 4 * sign));
+ {
+ emit_move_insn (from, plus_constant (from, count * 4 * sign));
+ *offsetp = offset;
+ }
seq = get_insns ();
end_sequence ();
-
+
return seq;
}
for (j = 0; i < count; i++, j++)
{
- mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
- RTX_UNCHANGING_P (mem) = unchanging_p;
- MEM_IN_STRUCT_P (mem) = in_struct_p;
- MEM_SCALAR_P (mem) = scalar_p;
+ addr = plus_constant (from, j * 4 * sign);
+ mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
XVECEXP (result, 0, i)
= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
+ offset += 4 * sign;
}
+ if (write_back)
+ *offsetp = offset;
+
return result;
}
rtx
arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
- int write_back, int unchanging_p, int in_struct_p,
- int scalar_p)
+ int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
{
+ HOST_WIDE_INT offset = *offsetp;
int i = 0, j;
rtx result;
int sign = up ? 1 : -1;
- rtx mem;
+ rtx mem, addr;
/* See arm_gen_load_multiple for discussion of
the pros/cons of ldm/stm usage for XScale. */
if (arm_tune_xscale && count <= 2 && ! optimize_size)
{
rtx seq;
-
+
start_sequence ();
-
+
for (i = 0; i < count; i++)
{
- mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
- RTX_UNCHANGING_P (mem) = unchanging_p;
- MEM_IN_STRUCT_P (mem) = in_struct_p;
- MEM_SCALAR_P (mem) = scalar_p;
+ addr = plus_constant (to, i * 4 * sign);
+ mem = adjust_automodify_address (basemem, SImode, addr, offset);
emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
+ offset += 4 * sign;
}
if (write_back)
- emit_move_insn (to, plus_constant (to, count * 4 * sign));
+ {
+ emit_move_insn (to, plus_constant (to, count * 4 * sign));
+ *offsetp = offset;
+ }
seq = get_insns ();
end_sequence ();
-
+
return seq;
}
for (j = 0; i < count; i++, j++)
{
- mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
- RTX_UNCHANGING_P (mem) = unchanging_p;
- MEM_IN_STRUCT_P (mem) = in_struct_p;
- MEM_SCALAR_P (mem) = scalar_p;
-
+ addr = plus_constant (to, j * 4 * sign);
+ mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
XVECEXP (result, 0, i)
= gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
+ offset += 4 * sign;
}
+ if (write_back)
+ *offsetp = offset;
+
return result;
}
int
-arm_gen_movstrqi (rtx *operands)
+arm_gen_movmemqi (rtx *operands)
{
HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
+ HOST_WIDE_INT srcoffset, dstoffset;
int i;
- rtx src, dst;
- rtx st_src, st_dst, fin_src, fin_dst;
+ rtx src, dst, srcbase, dstbase;
rtx part_bytes_reg = NULL;
rtx mem;
- int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
- int dst_scalar_p, src_scalar_p;
if (GET_CODE (operands[2]) != CONST_INT
|| GET_CODE (operands[3]) != CONST_INT
|| INTVAL (operands[3]) & 3)
return 0;
- st_dst = XEXP (operands[0], 0);
- st_src = XEXP (operands[1], 0);
-
- dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
- dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
- dst_scalar_p = MEM_SCALAR_P (operands[0]);
- src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
- src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
- src_scalar_p = MEM_SCALAR_P (operands[1]);
+ dstbase = operands[0];
+ srcbase = operands[1];
- fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
- fin_src = src = copy_to_mode_reg (SImode, st_src);
+ dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
+ src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
out_words_to_go = INTVAL (operands[2]) / 4;
last_bytes = INTVAL (operands[2]) & 3;
+ dstoffset = srcoffset = 0;
if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
{
if (in_words_to_go > 4)
emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
- src_unchanging_p,
- src_in_struct_p,
- src_scalar_p));
+ srcbase, &srcoffset));
else
- emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
- FALSE, src_unchanging_p,
- src_in_struct_p, src_scalar_p));
+ emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
+ FALSE, srcbase, &srcoffset));
if (out_words_to_go)
{
if (out_words_to_go > 4)
emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
- dst_unchanging_p,
- dst_in_struct_p,
- dst_scalar_p));
+ dstbase, &dstoffset));
else if (out_words_to_go != 1)
emit_insn (arm_gen_store_multiple (0, out_words_to_go,
- dst, TRUE,
+ dst, TRUE,
(last_bytes == 0
? FALSE : TRUE),
- dst_unchanging_p,
- dst_in_struct_p,
- dst_scalar_p));
+ dstbase, &dstoffset));
else
{
- mem = gen_rtx_MEM (SImode, dst);
- RTX_UNCHANGING_P (mem) = dst_unchanging_p;
- MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
- MEM_SCALAR_P (mem) = dst_scalar_p;
+ mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
emit_move_insn (mem, gen_rtx_REG (SImode, 0));
if (last_bytes != 0)
- emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
+ {
+ emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
+ dstoffset += 4;
+ }
}
}
if (out_words_to_go)
{
rtx sreg;
-
- mem = gen_rtx_MEM (SImode, src);
- RTX_UNCHANGING_P (mem) = src_unchanging_p;
- MEM_IN_STRUCT_P (mem) = src_in_struct_p;
- MEM_SCALAR_P (mem) = src_scalar_p;
- emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
- emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
-
- mem = gen_rtx_MEM (SImode, dst);
- RTX_UNCHANGING_P (mem) = dst_unchanging_p;
- MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
- MEM_SCALAR_P (mem) = dst_scalar_p;
+
+ mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
+ sreg = copy_to_reg (mem);
+
+ mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
emit_move_insn (mem, sreg);
- emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
in_words_to_go--;
-
+
if (in_words_to_go) /* Sanity check */
abort ();
}
if (in_words_to_go < 0)
abort ();
- mem = gen_rtx_MEM (SImode, src);
- RTX_UNCHANGING_P (mem) = src_unchanging_p;
- MEM_IN_STRUCT_P (mem) = src_in_struct_p;
- MEM_SCALAR_P (mem) = src_scalar_p;
+ mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
part_bytes_reg = copy_to_mode_reg (SImode, mem);
}
emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
GEN_INT (8 * (4 - last_bytes))));
part_bytes_reg = tmp;
-
+
while (last_bytes)
{
- mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
- RTX_UNCHANGING_P (mem) = dst_unchanging_p;
- MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
- MEM_SCALAR_P (mem) = dst_scalar_p;
+ mem = adjust_automodify_address (dstbase, QImode,
+ plus_constant (dst, last_bytes - 1),
+ dstoffset + last_bytes - 1);
emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
if (--last_bytes)
part_bytes_reg = tmp;
}
}
-
+
}
else
{
if (last_bytes > 1)
{
- mem = gen_rtx_MEM (HImode, dst);
- RTX_UNCHANGING_P (mem) = dst_unchanging_p;
- MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
- MEM_SCALAR_P (mem) = dst_scalar_p;
+ mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
last_bytes -= 2;
if (last_bytes)
{
rtx tmp = gen_reg_rtx (SImode);
-
emit_insn (gen_addsi3 (dst, dst, const2_rtx));
emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
part_bytes_reg = tmp;
+ dstoffset += 2;
}
}
-
+
if (last_bytes)
{
- mem = gen_rtx_MEM (QImode, dst);
- RTX_UNCHANGING_P (mem) = dst_unchanging_p;
- MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
- MEM_SCALAR_P (mem) = dst_scalar_p;
+ mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
}
}
/* Select a dominance comparison mode if possible for a test of the general
form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
- COND_OR == DOM_CC_X_AND_Y => (X && Y)
+ COND_OR == DOM_CC_X_AND_Y => (X && Y)
COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
- COND_OR == DOM_CC_X_OR_Y => (X || Y)
+ COND_OR == DOM_CC_X_OR_Y => (X || Y)
In all cases OP will be either EQ or NE, but we don't need to know which
- here. If we are unable to support a dominance comparison we return
+ here. If we are unable to support a dominance comparison we return
CC mode. This will then fail to match for the RTL expressions that
generate this call. */
enum machine_mode
/* If the comparisons are not equal, and one doesn't dominate the other,
then we can't do this. */
- if (cond1 != cond2
+ if (cond1 != cond2
&& !comparison_dominates_p (cond1, cond2)
&& (swapped = 1, !comparison_dominates_p (cond2, cond1)))
return CCmode;
if (cond2 == NE)
return CC_DNEmode;
break;
-
+
case LTU:
if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
return CC_DLTUmode;
abort ();
}
}
-
+
/* A compare with a shifted operand. Because of canonicalization, the
comparison will have to be swapped when we emit the assembler. */
if (GET_MODE (y) == SImode && GET_CODE (y) == REG
|| GET_CODE (x) == ROTATERT))
return CC_SWPmode;
- /* This is a special case that is used by combine to allow a
+ /* This is a special case that is used by combine to allow a
comparison of a shifted byte load to be split into a zero-extend
followed by a comparison of the shifted integer (only valid for
equalities and unsigned inequalities). */
|| XEXP (x, 2) == const1_rtx)
&& COMPARISON_P (XEXP (x, 0))
&& COMPARISON_P (XEXP (x, 1)))
- return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
+ return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
INTVAL (XEXP (x, 2)));
/* Alternate canonicalizations of the above. These are somewhat cleaner. */
plus_constant (base,
offset))));
emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
- gen_rtx_MEM (QImode,
+ gen_rtx_MEM (QImode,
plus_constant (base,
offset + 1))));
if (!BYTES_BIG_ENDIAN)
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
- gen_rtx_IOR (SImode,
+ gen_rtx_IOR (SImode,
gen_rtx_ASHIFT
(SImode,
gen_rtx_SUBREG (SImode, operands[0], 0),
scratch)));
else
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
- gen_rtx_IOR (SImode,
+ gen_rtx_IOR (SImode,
gen_rtx_ASHIFT (SImode, scratch,
GEN_INT (8)),
gen_rtx_SUBREG (SImode, operands[0],
if (BYTES_BIG_ENDIAN)
{
- emit_insn (gen_movqi (gen_rtx_MEM (QImode,
+ emit_insn (gen_movqi (gen_rtx_MEM (QImode,
plus_constant (base, offset + 1)),
gen_lowpart (QImode, outval)));
emit_insn (gen_lshrsi3 (scratch,
is_jump_table (rtx insn)
{
rtx table;
-
+
if (GET_CODE (insn) == JUMP_INSN
&& JUMP_LABEL (insn) != NULL
&& ((table = next_real_insn (JUMP_LABEL (insn)))
mp->next = max_mp;
mp->prev = max_mp->prev;
max_mp->prev = mp;
-
+
if (mp->prev != NULL)
mp->prev->next = mp;
else
Mnode * max_mp = NULL;
HOST_WIDE_INT max_address = fix->address + fix->forwards;
Mnode * mp;
-
+
/* If this fix's address is greater than the address of the first
entry, then we can't put the fix in this pool. We subtract the
size of the current fix to ensure that if the table is fully
}
return min_mp;
-}
+}
/* Add a constant to the minipool for a backward reference. Returns the
- node added or NULL if the constant will not fit in this pool.
+ node added or NULL if the constant will not fit in this pool.
Note that the code for insertion for a backwards reference can be
somewhat confusing because the calculated offsets for each fix do
&& rtx_equal_p (fix->value, mp->value)
/* Check that there is enough slack to move this entry to the
end of the table (this is conservative). */
- && (mp->max_address
- > (minipool_barrier->address
+ && (mp->max_address
+ > (minipool_barrier->address
+ minipool_vector_tail->offset
+ minipool_vector_tail->fix_size)))
{
mp->next = min_mp->next;
mp->prev = min_mp;
min_mp->next = mp;
-
+
if (mp->next != NULL)
mp->next->prev = mp;
else
for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
{
mp->offset = offset;
-
+
if (mp->refcount > 0)
offset += mp->fix_size;
}
{
if (dump_file)
{
- fprintf (dump_file,
+ fprintf (dump_file,
";; Offset %u, min %ld, max %ld ",
(unsigned) mp->offset, (unsigned long) mp->min_address,
(unsigned long) mp->max_address);
case CODE_LABEL:
/* It will always be better to place the table before the label, rather
than after it. */
- return 50;
+ return 50;
case INSN:
case CALL_INSN:
}
new_cost = arm_barrier_cost (from);
-
+
if (count < max_count && new_cost <= selected_cost)
{
selected = from;
fprintf (dump_file,
";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
GET_MODE_NAME (mode),
- INSN_UID (insn), (unsigned long) address,
+ INSN_UID (insn), (unsigned long) address,
-1 * (long)fix->backwards, (long)fix->forwards);
arm_print_value (dump_file, fix->value);
fprintf (dump_file, "\n");
/* Add it to the chain of fixes. */
fix->next = NULL;
-
+
if (minipool_fix_head != NULL)
minipool_fix_tail->next = fix;
else
minipool_fix_tail = fix;
}
+/* Return the cost of synthesizing the const_double VAL inline.
+ Returns the number of insns needed, or 99 if we don't know how to
+ do it. */
+int
+arm_const_double_inline_cost (rtx val)
+{
+ long parts[2];
+
+ if (GET_MODE (val) == DFmode)
+ {
+ REAL_VALUE_TYPE r;
+ if (!TARGET_SOFT_FLOAT)
+ return 99;
+ REAL_VALUE_FROM_CONST_DOUBLE (r, val);
+ REAL_VALUE_TO_TARGET_DOUBLE (r, parts);
+ }
+ else if (GET_MODE (val) != VOIDmode)
+ return 99;
+ else
+ {
+ parts[0] = CONST_DOUBLE_LOW (val);
+ parts[1] = CONST_DOUBLE_HIGH (val);
+ }
+
+ return (arm_gen_constant (SET, SImode, NULL_RTX, parts[0],
+ NULL_RTX, NULL_RTX, 0, 0)
+ + arm_gen_constant (SET, SImode, NULL_RTX, parts[1],
+ NULL_RTX, NULL_RTX, 0, 0));
+}
+
+/* Determine if a CONST_DOUBLE should be pushed to the minipool */
+static bool
+const_double_needs_minipool (rtx val)
+{
+ /* thumb only knows to load a CONST_DOUBLE from memory at the moment */
+ if (TARGET_THUMB)
+ return true;
+
+ /* Don't push anything to the minipool if a CONST_DOUBLE can be built with
+ a few ALU insns directly. On balance, the optimum is likely to be around
+ 3 insns, except when there are no load delay slots where it should be 4.
+ When optimizing for size, a limit of 3 allows saving at least one word
+ except for cases where a single minipool entry could be shared more than
+ 2 times which is rather unlikely to outweight the overall savings. */
+ return (arm_const_double_inline_cost (val)
+ > ((optimize_size || arm_ld_sched) ? 3 : 4));
+}
+
/* Scan INSN and note any of its operands that need fixing.
If DO_PUSHES is false we do not actually push any of the fixups
needed. The function returns TRUE is any fixups were needed/pushed.
{
rtx op = recog_data.operand[opno];
- if (CONSTANT_P (op))
+ if (CONSTANT_P (op)
+ && (GET_CODE (op) != CONST_DOUBLE
+ || const_double_needs_minipool (op)))
{
if (do_pushes)
push_minipool_fix (insn, address, recog_data.operand_loc[opno],
/* Casting the address of something to a mode narrower
than a word can cause avoid_constant_pool_reference()
to return the pool reference itself. That's no good to
- us here. Lets just hope that we can use the
+ us here. Lets just hope that we can use the
constant pool value directly. */
if (op == cop)
cop = get_pool_constant (XEXP (op, 0));
}
fix = minipool_fix_head;
-
+
/* Now scan the fixups and perform the required changes. */
while (fix)
{
the next mini-pool. */
if (last_barrier != NULL)
{
- /* Reduce the refcount for those fixes that won't go into this
+ /* Reduce the refcount for those fixes that won't go into this
pool after all. */
for (fdel = last_barrier->next;
fdel && fdel != ftmp;
if (GET_CODE (this_fix->insn) != BARRIER)
{
rtx addr
- = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
+ = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
minipool_vector_label),
this_fix->minipool->offset);
*this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
{
REAL_VALUE_TYPE r;
int i;
-
+
if (!fp_consts_inited)
init_fp_table ();
-
+
REAL_VALUE_FROM_CONST_DOUBLE (r, x);
for (i = 0; i < 8; i++)
if (REAL_VALUES_EQUAL (r, values_fp[i]))
MASK is the ARM register set mask of which only bits 0-15 are important.
REG is the base register, either the frame pointer or the stack pointer,
INSTR is the possibly suffixed load or store instruction. */
+
static void
-print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
+print_multi_reg (FILE *stream, const char *instr, unsigned reg,
+ unsigned long mask)
{
- int i;
- int not_first = FALSE;
+ unsigned i;
+ bool not_first = FALSE;
fputc ('\t', stream);
asm_fprintf (stream, instr, reg);
fputs (", {", stream);
-
+
for (i = 0; i <= LAST_ARM_REGNUM; i++)
if (mask & (1 << i))
{
if (not_first)
fprintf (stream, ", ");
-
+
asm_fprintf (stream, "%r", i);
not_first = TRUE;
}
const char *
output_call (rtx *operands)
{
- /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
+ if (arm_arch5)
+ abort (); /* Patterns should call blx <reg> directly. */
+ /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
if (REGNO (operands[0]) == LR_REGNUM)
{
operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
output_asm_insn ("mov%?\t%0, %|lr", operands);
}
-
+
output_asm_insn ("mov%?\t%|lr, %|pc", operands);
-
- if (TARGET_INTERWORK)
+
+ if (TARGET_INTERWORK || arm_arch4t)
output_asm_insn ("bx%?\t%0", operands);
else
output_asm_insn ("mov%?\t%|pc, %0", operands);
-
+
return "";
}
const char *
output_call_mem (rtx *operands)
{
- if (TARGET_INTERWORK)
+ if (TARGET_INTERWORK && !arm_arch5)
{
output_asm_insn ("ldr%?\t%|ip, %0", operands);
output_asm_insn ("mov%?\t%|lr, %|pc", operands);
first instruction. It's safe to use IP as the target of the
load since the call will kill it anyway. */
output_asm_insn ("ldr%?\t%|ip, %0", operands);
- output_asm_insn ("mov%?\t%|lr, %|pc", operands);
- output_asm_insn ("mov%?\t%|pc, %|ip", operands);
+ if (arm_arch5)
+ output_asm_insn ("blx%?\t%|ip", operands);
+ else
+ {
+ output_asm_insn ("mov%?\t%|lr, %|pc", operands);
+ if (arm_arch4t)
+ output_asm_insn ("bx%?\t%|ip", operands);
+ else
+ output_asm_insn ("mov%?\t%|pc, %|ip", operands);
+ }
}
else
{
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
-
+
output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
-
+
return "";
}
if (arm_reg0 == IP_REGNUM)
abort ();
-
+
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
int reg0 = REGNO (operands[0]);
otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
-
+
if (code1 == REG)
{
int reg1 = REGNO (operands[1]);
operands[1] = GEN_INT (hint);
break;
-
+
default:
abort ();
}
otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
}
-
+
output_mov_immediate (operands);
output_mov_immediate (otherops);
}
avoid a conflict. */
otherops[1] = XEXP (XEXP (operands[1], 0), 1);
otherops[2] = XEXP (XEXP (operands[1], 0), 0);
-
+
}
/* If both registers conflict, it will usually
have been fixed by a splitter. */
}
else
output_asm_insn ("sub%?\t%0, %1, %2", otherops);
-
+
return "ldm%?ia\t%0, %M0";
}
else
}
}
}
-
+
return "";
}
mnem = "lsr";
break;
+ case ROTATE:
+ if (*amountp == -1)
+ abort ();
+ *amountp = 32 - *amountp;
+
+ /* Fall through. */
+
case ROTATERT:
mnem = "ror";
break;
shift. >=32 is not a valid shift for "asl", so we must try and
output a shift that produces the correct arithmetical result.
Using lsr #32 is identical except for the fact that the carry bit
- is not set correctly if we set the flags; but we never use the
+ is not set correctly if we set the flags; but we never use the
carry bit from such an operation, so we can ignore that. */
if (code == ROTATERT)
/* Rotate is just modulo 32. */
/* Shifts of 0 are no-ops. */
if (*amountp == 0)
return NULL;
- }
+ }
return mnem;
}
return shift;
}
-/* Output a .ascii pseudo-op, keeping track of lengths. This is because
- /bin/as is horribly restrictive. */
+/* Output a .ascii pseudo-op, keeping track of lengths. This is
+ because /bin/as is horribly restrictive. The judgement about
+ whether or not each character is 'printable' (and can be output as
+ is) or not (and must be printed with an octal escape) must be made
+ with reference to the *host* character set -- the situation is
+ similar to that discussed in the comments above pp_c_char in
+ c-pretty-print.c. */
+
#define MAX_ASCII_LEN 51
void
int len_so_far = 0;
fputs ("\t.ascii\t\"", stream);
-
+
for (i = 0; i < len; i++)
{
int c = p[i];
len_so_far = 0;
}
- switch (c)
+ if (ISPRINT (c))
{
- case TARGET_TAB:
- fputs ("\\t", stream);
- len_so_far += 2;
- break;
-
- case TARGET_FF:
- fputs ("\\f", stream);
- len_so_far += 2;
- break;
-
- case TARGET_BS:
- fputs ("\\b", stream);
- len_so_far += 2;
- break;
-
- case TARGET_CR:
- fputs ("\\r", stream);
- len_so_far += 2;
- break;
-
- case TARGET_NEWLINE:
- fputs ("\\n", stream);
- c = p [i + 1];
- if ((c >= ' ' && c <= '~')
- || c == TARGET_TAB)
- /* This is a good place for a line break. */
- len_so_far = MAX_ASCII_LEN;
- else
- len_so_far += 2;
- break;
-
- case '\"':
- case '\\':
- putc ('\\', stream);
- len_so_far++;
- /* Drop through. */
-
- default:
- if (c >= ' ' && c <= '~')
+ if (c == '\\' || c == '\"')
{
- putc (c, stream);
+ putc ('\\', stream);
len_so_far++;
}
- else
- {
- fprintf (stream, "\\%03o", c);
- len_so_far += 4;
- }
- break;
+ putc (c, stream);
+ len_so_far++;
+ }
+ else
+ {
+ fprintf (stream, "\\%03o", c);
+ len_so_far += 4;
}
}
fputs ("\"\n", stream);
}
\f
-/* Compute the register sabe mask for registers 0 through 12
+/* Compute the register save mask for registers 0 through 12
inclusive. This code is used by arm_compute_save_reg_mask. */
+
static unsigned long
arm_compute_save_reg0_reg12_mask (void)
{
unsigned long func_type = arm_current_func_type ();
- unsigned int save_reg_mask = 0;
+ unsigned long save_reg_mask = 0;
unsigned int reg;
if (IS_INTERRUPT (func_type))
max_reg = 7;
else
max_reg = 12;
-
+
for (reg = 0; reg <= max_reg; reg++)
if (regs_ever_live[reg]
|| (! current_function_is_leaf && call_used_regs [reg]))
save_reg_mask |= (1 << reg);
+
+ /* Also save the pic base register if necessary. */
+ if (flag_pic
+ && !TARGET_SINGLE_PIC_BASE
+ && current_function_uses_pic_offset_table)
+ save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
}
else
{
/* If we aren't loading the PIC register,
don't stack it even though it may be live. */
if (flag_pic
- && ! TARGET_SINGLE_PIC_BASE
- && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+ && !TARGET_SINGLE_PIC_BASE
+ && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
+ || current_function_uses_pic_offset_table))
save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
}
+ /* Save registers so the exception handler can modify them. */
+ if (current_function_calls_eh_return)
+ {
+ unsigned int i;
+
+ for (i = 0; ; i++)
+ {
+ reg = EH_RETURN_DATA_REGNO (i);
+ if (reg == INVALID_REGNUM)
+ break;
+ save_reg_mask |= 1 << reg;
+ }
+ }
+
return save_reg_mask;
}
if (regs_ever_live [LR_REGNUM]
|| (save_reg_mask
&& optimize_size
- && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
+ && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
+ && !current_function_calls_eh_return))
save_reg_mask |= 1 << LR_REGNUM;
if (cfun->machine->lr_save_eliminated)
}
+/* Compute a bit mask of which registers need to be
+ saved on the stack for the current function. */
+static unsigned long
+thumb_compute_save_reg_mask (void)
+{
+ unsigned long mask;
+ unsigned reg;
+
+ mask = 0;
+ for (reg = 0; reg < 12; reg ++)
+ if (regs_ever_live[reg] && !call_used_regs[reg])
+ mask |= 1 << reg;
+
+ if (flag_pic && !TARGET_SINGLE_PIC_BASE)
+ mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
+
+ if (TARGET_SINGLE_PIC_BASE)
+ mask &= ~(1 << arm_pic_register);
+
+ /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
+ if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
+ mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
+
+ /* LR will also be pushed if any lo regs are pushed. */
+ if (mask & 0xff || thumb_force_lr_save ())
+ mask |= (1 << LR_REGNUM);
+
+ /* Make sure we have a low work register if we need one.
+ We will need one if we are going to push a high register,
+ but we are not currently intending to push a low register. */
+ if ((mask & 0xff) == 0
+ && ((mask & 0x0f00) || TARGET_BACKTRACE))
+ {
+ /* Use thumb_find_work_register to choose which register
+ we will use. If the register is live then we will
+ have to push it. Use LAST_LO_REGNUM as our fallback
+ choice for the register to select. */
+ reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
+
+ if (! call_used_regs[reg])
+ mask |= 1 << reg;
+ }
+
+ return mask;
+}
+
+
/* Return the number of bytes required to save VFP registers. */
static int
arm_get_vfp_saved_size (void)
{
char conditional[10];
char instr[100];
- int reg;
+ unsigned reg;
unsigned long live_regs_mask;
unsigned long func_type;
arm_stack_offsets *offsets;
if (really_return)
{
rtx ops[2];
-
+
/* Otherwise, trap an attempted return by aborting. */
ops[0] = operand;
- ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
+ ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
: "abort");
assemble_external_libcall (ops[1]);
output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
}
-
+
return "";
}
{
const char * return_reg;
- /* If we do not have any special requirements for function exit
- (eg interworking, or ISR) then we can load the return address
+ /* If we do not have any special requirements for function exit
+ (e.g. interworking, or ISR) then we can load the return address
directly into the PC. Otherwise we must load it into LR. */
if (really_return
&& ! TARGET_INTERWORK)
we have to use LDM to load the PC so that the CPSR is also
restored. */
for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
- {
- if (live_regs_mask == (unsigned int)(1 << reg))
- break;
- }
+ if (live_regs_mask == (1U << reg))
+ break;
+
if (reg <= LAST_ARM_REGNUM
&& (reg != LR_REGNUM
- || ! really_return
+ || ! really_return
|| ! IS_INTERRUPT (func_type)))
{
- sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
+ sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
(reg == LR_REGNUM) ? return_reg : reg_names[reg]);
}
else
sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
else
{
- /* If we can't use ldmib (SA110 bug), then try to pop r3
- instead. */
+ /* If we can't use ldmib (SA110 bug),
+ then try to pop r3 instead. */
if (stack_adjust)
live_regs_mask |= 1 << 3;
sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
memcpy (p + 2, reg_names[reg], l);
p += l + 2;
}
-
+
if (live_regs_mask & (1 << LR_REGNUM))
{
sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
break;
default:
- /* ARMv5 implementations always provide BX, so interworking
- is the default. */
- if ((insn_flags & FL_ARCH5) != 0)
- sprintf (instr, "bx%s\t%%|lr", conditional);
+ /* Use bx if it's available. */
+ if (arm_arch5 || arm_arch4t)
+ sprintf (instr, "bx%s\t%%|lr", conditional);
else
sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
break;
length = strlen (name) + 1;
alignlength = ROUND_UP_WORD (length);
-
+
ASM_OUTPUT_ASCII (stream, name, length);
ASM_OUTPUT_ALIGN (stream, 2);
x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
thumb_output_function_prologue (f, frame_size);
return;
}
-
+
/* Sanity check. */
if (arm_ccfsm_state || arm_target_insn)
abort ();
func_type = arm_current_func_type ();
-
+
switch ((int) ARM_FUNC_TYPE (func_type))
{
default:
case ARM_FT_INTERWORKED:
asm_fprintf (f, "\t%@ Function supports interworking.\n");
break;
- case ARM_FT_EXCEPTION_HANDLER:
- asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
- break;
case ARM_FT_ISR:
asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
break;
asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
break;
}
-
+
if (IS_NAKED (func_type))
asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
if (IS_NESTED (func_type))
asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
-
+
asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
current_function_args_size,
current_function_pretend_args_size, frame_size);
if (cfun->machine->lr_save_eliminated)
asm_fprintf (f, "\t%@ link register save eliminated.\n");
+ if (current_function_calls_eh_return)
+ asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
+
#ifdef AOF_ASSEMBLER
if (flag_pic)
asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
#endif
- return_used_this_function = 0;
+ return_used_this_function = 0;
}
const char *
int reg;
unsigned long saved_regs_mask;
unsigned long func_type;
- /* Floats_offset is the offset from the "virtual" frame. In an APCS
+ /* Floats_offset is the offset from the "virtual" frame. In an APCS
frame that is $fp + 4 for a non-variadic function. */
int floats_offset = 0;
rtx operands[3];
FILE * f = asm_out_file;
- rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
unsigned int lrm_count = 0;
int really_return = (sibling == NULL);
int start_reg;
if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
{
rtx op;
-
+
/* A volatile function should never return. Call abort. */
op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
assemble_external_libcall (op);
output_asm_insn ("bl\t%a0", &op);
-
+
return "";
}
- if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
+ if (current_function_calls_eh_return
&& ! really_return)
/* If we are throwing an exception, then we really must
be doing a return, so we can't tail-call. */
abort ();
-
+
offsets = arm_get_frame_offsets ();
saved_regs_mask = arm_compute_save_reg_mask ();
for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
if (saved_regs_mask & (1 << reg))
floats_offset += 4;
-
+
if (frame_pointer_needed)
{
/* This variable is for the Virtual Frame Pointer, not VFP regs. */
if (regs_ever_live[reg] && !call_used_regs[reg])
{
floats_offset += 12;
- asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
+ asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
reg, FP_REGNUM, floats_offset - vfp_offset);
}
}
if (regs_ever_live[reg] && !call_used_regs[reg])
{
floats_offset += 12;
-
+
/* We can't unstack more than four registers at once. */
if (start_reg - reg == 3)
{
We can ignore floats_offset since that was already included in
the live_regs_mask. */
lrm_count += (lrm_count % 2 ? 2 : 1);
-
+
for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
if (regs_ever_live[reg] && !call_used_regs[reg])
{
- asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
+ asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
reg, FP_REGNUM, lrm_count * 4);
- lrm_count += 2;
+ lrm_count += 2;
}
}
only need to restore the LR register (the return address), but to
save time we can load it directly into the PC, unless we need a
special function exit sequence, or we are not really returning. */
- if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
+ if (really_return
+ && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
+ && !current_function_calls_eh_return)
/* Delete the LR from the register mask, so that the LR on
the stack is loaded into the PC in the register mask. */
saved_regs_mask &= ~ (1 << LR_REGNUM);
asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
start_reg, reg - start_reg,
SP_REGNUM);
-
+
start_reg = reg + 1;
}
}
if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
&& really_return
&& current_function_pretend_args_size == 0
- && saved_regs_mask & (1 << LR_REGNUM))
+ && saved_regs_mask & (1 << LR_REGNUM)
+ && !current_function_calls_eh_return)
{
saved_regs_mask &= ~ (1 << LR_REGNUM);
saved_regs_mask |= (1 << PC_REGNUM);
to load use the LDR instruction - it is faster. */
if (saved_regs_mask == (1 << LR_REGNUM))
{
- /* The exception handler ignores the LR, so we do
- not really need to load it off the stack. */
- if (eh_ofs)
- asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
- else
- asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
+ asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
}
else if (saved_regs_mask)
{
if (saved_regs_mask & (1 << SP_REGNUM))
/* Note - write back to the stack register is not enabled
- (ie "ldmfd sp!..."). We know that the stack pointer is
+ (i.e. "ldmfd sp!..."). We know that the stack pointer is
in the list of registers and if we add writeback the
instruction becomes UNPREDICTABLE. */
print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
}
/* We may have already restored PC directly from the stack. */
- if (! really_return
- || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
- && current_function_pretend_args_size == 0
- && saved_regs_mask & (1 << PC_REGNUM)))
+ if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
return "";
+ /* Stack adjustment for exception handler. */
+ if (current_function_calls_eh_return)
+ asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
+ ARM_EH_STACKADJ_REGNUM);
+
/* Generate the return instruction. */
switch ((int) ARM_FUNC_TYPE (func_type))
{
- case ARM_FT_EXCEPTION_HANDLER:
- asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
- break;
-
case ARM_FT_ISR:
case ARM_FT_FIQ:
asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
break;
default:
- asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
+ if (arm_arch5 || arm_arch4t)
+ asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
+ else
+ asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
break;
}
if (TARGET_THUMB)
{
+ int regno;
+
+ /* Emit any call-via-reg trampolines that are needed for v4t support
+ of call_reg and call_value_reg type insns. */
+ for (regno = 0; regno < SP_REGNUM; regno++)
+ {
+ rtx label = cfun->machine->call_via[regno];
+
+ if (label != NULL)
+ {
+ function_section (current_function_decl);
+ targetm.asm_out.internal_label (asm_out_file, "L",
+ CODE_LABEL_NUMBER (label));
+ asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
+ }
+ }
+
/* ??? Probably not safe to set this here, since it assumes that a
function will be emitted as assembly immediately after we generate
RTL for it. This does not happen for inline functions. */
semantics of the operation, we need to annotate the insn for the benefit
of DWARF2 frame unwind information. */
static rtx
-emit_multi_reg_push (int mask)
+emit_multi_reg_push (unsigned long mask)
{
int num_regs = 0;
int num_dwarf_regs;
by the push_multi pattern in the arm.md file. The insn looks
something like this:
- (parallel [
+ (parallel [
(set (mem:BLK (pre_dec:BLK (reg:SI sp)))
(unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
(use (reg:SI 11 fp))
stack decrement per instruction. The RTL we generate for the note looks
something like this:
- (sequence [
+ (sequence [
(set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
(set (mem:SI (reg:SI sp)) (reg:SI r4))
(set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
This sequence is used both by the code to support stack unwinding for
exceptions handlers and the code to generate dwarf2 frame debugging. */
-
+
par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
dwarf_par_index = 1;
}
par = emit_insn (par);
-
+
tmp = gen_rtx_SET (SImode,
stack_pointer_rtx,
gen_rtx_PLUS (SImode,
GEN_INT (-4 * num_regs)));
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, 0) = tmp;
-
+
REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
REG_NOTES (par));
return par;
int i;
par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
- dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
reg = gen_rtx_REG (XFmode, base_reg++);
XVECEXP (par, 0, 0)
- = gen_rtx_SET (VOIDmode,
+ = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (BLKmode,
gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
gen_rtvec (1, reg),
UNSPEC_PUSH_MULT));
- tmp
- = gen_rtx_SET (VOIDmode,
- gen_rtx_MEM (XFmode,
- gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
- reg);
+ tmp = gen_rtx_SET (VOIDmode,
+ gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, count - 1) = tmp;
-
+ XVECEXP (dwarf, 0, 1) = tmp;
+
for (i = 1; i < count; i++)
{
reg = gen_rtx_REG (XFmode, base_reg++);
XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
- tmp = gen_rtx_SET (VOIDmode,
+ tmp = gen_rtx_SET (VOIDmode,
gen_rtx_MEM (XFmode,
- gen_rtx_PRE_DEC (BLKmode,
- stack_pointer_rtx)),
+ plus_constant (stack_pointer_rtx,
+ i * 12)),
reg);
RTX_FRAME_RELATED_P (tmp) = 1;
- XVECEXP (dwarf, 0, count - i - 1) = tmp;
+ XVECEXP (dwarf, 0, i + 1) = tmp;
}
+ tmp = gen_rtx_SET (VOIDmode,
+ stack_pointer_rtx,
+ gen_rtx_PLUS (SImode,
+ stack_pointer_rtx,
+ GEN_INT (-12 * count)));
+ RTX_FRAME_RELATED_P (tmp) = 1;
+ XVECEXP (dwarf, 0, 0) = tmp;
+
par = emit_insn (par);
REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
REG_NOTES (par));
/* Compute the distance from register FROM to register TO.
These can be the arg pointer (26), the soft frame pointer (25),
the stack pointer (13) or the hard frame pointer (11).
+ In thumb mode r7 is used as the soft frame pointer, if needed.
Typical stack layout looks like this:
old stack pointer -> | |
HOST_WIDE_INT frame_size;
offsets = &cfun->machine->stack_offsets;
-
+
/* We need to know if we are a leaf function. Unfortunately, it
is possible to be called after start_sequence has been called,
which causes get_insns to return the insns for the sequence,
}
else /* TARGET_THUMB */
{
- int reg;
- int count_regs;
-
- saved = 0;
- count_regs = 0;
- for (reg = 8; reg < 13; reg ++)
- if (THUMB_REG_PUSHED_P (reg))
- count_regs ++;
- if (count_regs)
- saved += 4 * count_regs;
- count_regs = 0;
- for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
- if (THUMB_REG_PUSHED_P (reg))
- count_regs ++;
- if (count_regs || thumb_force_lr_save ())
- saved += 4 * (count_regs + 1);
+ saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
if (TARGET_BACKTRACE)
- {
- if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
- saved += 20;
- else
- saved += 16;
- }
+ saved += 16;
}
/* Saved registers include the stack frame. */
offsets->saved_regs = offsets->saved_args + saved;
- offsets->soft_frame = offsets->saved_regs;
+ offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
/* A leaf function does not need any stack alignment if it has nothing
on the stack. */
if (leaf && frame_size == 0)
/* Calculate the relative offsets for the different stack pointers. Positive
offsets are in the direction of stack growth. */
-unsigned int
+HOST_WIDE_INT
arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
{
arm_stack_offsets *offsets;
int fp_offset = 0;
int saved_pretend_args = 0;
int saved_regs = 0;
- unsigned int args_to_push;
+ unsigned HOST_WIDE_INT args_to_push;
arm_stack_offsets *offsets;
func_type = arm_current_func_type ();
/* Make a copy of c_f_p_a_s as we may need to modify it locally. */
args_to_push = current_function_pretend_args_size;
-
+
/* Compute which register we will have to save onto the stack. */
live_regs_mask = arm_compute_save_reg_mask ();
To get around this need to find somewhere to store IP
whilst the frame is being created. We try the following
places in order:
-
+
1. The last argument register.
2. A slot on the stack above the frame. (This only
works if the function is not a varargs function).
((0xf0 >> (args_to_push / 4)) & 0xf);
else
insn = emit_insn
- (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
+ (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
GEN_INT (- args_to_push)));
RTX_FRAME_RELATED_P (insn) = 1;
}
else
insn = gen_movsi (ip_rtx, stack_pointer_rtx);
-
+
insn = emit_insn (insn);
RTX_FRAME_RELATED_P (insn) = 1;
}
((0xf0 >> (args_to_push / 4)) & 0xf);
else
insn = emit_insn
- (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
+ (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
GEN_INT (- args_to_push)));
RTX_FRAME_RELATED_P (insn) = 1;
}
if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
&& (live_regs_mask & (1 << LR_REGNUM)) != 0
&& ! frame_pointer_needed)
- emit_insn (gen_rtx_SET (SImode,
+ emit_insn (gen_rtx_SET (SImode,
gen_rtx_REG (SImode, LR_REGNUM),
gen_rtx_PLUS (SImode,
gen_rtx_REG (SImode, LR_REGNUM),
insn = GEN_INT (-(4 + args_to_push + fp_offset));
insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
RTX_FRAME_RELATED_P (insn) = 1;
-
+
if (IS_NESTED (func_type))
{
/* Recover the static chain register. */
hard_frame_pointer_rtx));
}
+
+ if (flag_pic)
+ arm_load_pic_register (INVALID_REGNUM);
+
/* If we are profiling, make sure no instructions are scheduled before
the call to mcount. Similarly if the user has requested no
scheduling in the prolog. */
case '_':
fputs (user_label_prefix, stream);
return;
-
+
case '|':
fputs (REGISTER_PREFIX, stream);
return;
case '?':
if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
{
- if (TARGET_THUMB || current_insn_predicate != NULL)
- abort ();
+ if (TARGET_THUMB)
+ {
+ output_operand_lossage ("predicated Thumb instruction");
+ break;
+ }
+ if (current_insn_predicate != NULL)
+ {
+ output_operand_lossage
+ ("predicated instruction in conditional sequence");
+ break;
+ }
fputs (arm_condition_codes[arm_current_cc], stream);
}
enum arm_cond_code code;
if (TARGET_THUMB)
- abort ();
+ {
+ output_operand_lossage ("predicated Thumb instruction");
+ break;
+ }
code = get_arm_condition_code (current_insn_predicate);
fputs (arm_condition_codes[code], stream);
return;
/* An explanation of the 'Q', 'R' and 'H' register operands:
-
+
In a pair of registers containing a DI or DF value the 'Q'
operand returns the register number of the register containing
the least significant part of the value. The 'R' operand returns
the register number of the register containing the most
significant part of the value.
-
+
The 'H' operand returns the higher of the two register numbers.
On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
same as the 'Q' operand, since the most significant part of the
value is held in the lower number register. The reverse is true
on systems where WORDS_BIG_ENDIAN is false.
-
+
The purpose of these operands is to distinguish between cases
where the endian-ness of the values is important (for example
when they are added together), and cases where the endian-ness
of the memory location is actually held in one of the registers
being overwritten by the load. */
case 'Q':
- if (REGNO (x) > LAST_ARM_REGNUM)
- abort ();
+ if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
+
asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
return;
case 'R':
- if (REGNO (x) > LAST_ARM_REGNUM)
- abort ();
+ if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
+
asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
return;
case 'H':
- if (REGNO (x) > LAST_ARM_REGNUM)
- abort ();
+ if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
+
asm_fprintf (stream, "%r", REGNO (x) + 1);
return;
case 'm':
- asm_fprintf (stream, "%r",
+ asm_fprintf (stream, "%r",
GET_CODE (XEXP (x, 0)) == REG
? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
return;
/* CONST_TRUE_RTX means always -- that's the default. */
if (x == const_true_rtx)
return;
-
+
+ if (!COMPARISON_P (x))
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
+
fputs (arm_condition_codes[get_arm_condition_code (x)],
stream);
return;
case 'D':
- /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
+ /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
want to do that. */
if (x == const_true_rtx)
- abort ();
+ {
+ output_operand_lossage ("instruction never exectued");
+ return;
+ }
+ if (!COMPARISON_P (x))
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
(get_arm_condition_code (x))],
int mode = GET_MODE (x);
if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
- abort ();
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
fprintf (stream, "mv%s%s",
mode == DFmode ? "d"
|| REGNO (x) < FIRST_IWMMXT_GR_REGNUM
|| REGNO (x) > LAST_IWMMXT_GR_REGNUM)
/* Bad value for wCG register number. */
- abort ();
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
+
else
fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
return;
|| INTVAL (x) < 0
|| INTVAL (x) >= 16)
/* Bad value for wC register number. */
- abort ();
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
+
else
{
static const char * wc_reg_names [16] =
"wCGR0", "wCGR1", "wCGR2", "wCGR3",
"wC12", "wC13", "wC14", "wC15"
};
-
+
fprintf (stream, wc_reg_names [INTVAL (x)]);
}
return;
int num;
if (mode != DImode && mode != DFmode)
- abort ();
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
if (GET_CODE (x) != REG
|| !IS_VFP_REGNUM (REGNO (x)))
- abort ();
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
num = REGNO(x) - FIRST_VFP_REGNUM;
if (num & 1)
- abort ();
+ {
+ output_operand_lossage ("invalid operand for code '%c'", code);
+ return;
+ }
fprintf (stream, "d%d", num >> 1);
}
default:
if (x == 0)
- abort ();
+ {
+ output_operand_lossage ("missing operand");
+ return;
+ }
if (GET_CODE (x) == REG)
asm_fprintf (stream, "%r", REGNO (x));
return true;
}
- if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
+ if (arm_vector_mode_supported_p (GET_MODE (x)))
{
int i, units;
case GEU: return ARM_CC;
default: abort ();
}
-
+
case CCmode:
switch (comp_code)
{
means that we have to grub around within the jump expression to find
out what the conditions are when the jump isn't taken. */
int jump_clobbers = 0;
-
+
/* If we start with a return insn, we only succeed if we find another one. */
int seeking_return = 0;
-
+
/* START_INSN will hold the insn from where we start looking. This is the
first insn after the following code_label if REVERSE is true. */
rtx start_insn = insn;
if (GET_CODE (insn) != JUMP_INSN)
return;
- /* This jump might be paralleled with a clobber of the condition codes
+ /* This jump might be paralleled with a clobber of the condition codes
the jump should always come first */
if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
body = XVECEXP (body, 0, 0);
int then_not_else = TRUE;
rtx this_insn = start_insn, label = 0;
- /* If the jump cannot be done with one instruction, we cannot
+ /* If the jump cannot be done with one instruction, we cannot
conditionally execute the instruction in the inverse case. */
if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
{
jump_clobbers = 1;
return;
}
-
+
/* Register the insn jumped to. */
if (reverse)
{
case BARRIER:
/* Succeed if the following insn is the target label.
- Otherwise fail.
- If return insns are used then the last insn in a function
+ Otherwise fail.
+ If return insns are used then the last insn in a function
will be a barrier. */
this_insn = next_nonnote_insn (this_insn);
if (this_insn && this_insn == label)
break;
case CALL_INSN:
+ /* The AAPCS says that conditional calls should not be
+ used since they make interworking inefficient (the
+ linker can't transform BL<cond> into BLX). That's
+ only a problem if the machine has BLX. */
+ if (arm_arch5)
+ {
+ fail = TRUE;
+ break;
+ }
+
/* Succeed if the following insn is the target label, or
if the following two insns are a barrier and the
target label. */
else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
fail = TRUE;
}
- /* Fail if a conditional return is undesirable (eg on a
+ /* Fail if a conditional return is undesirable (e.g. on a
StrongARM), but still allow this if optimizing for size. */
else if (GET_CODE (scanbody) == RETURN
&& !use_return_insn (TRUE, NULL)
}
}
else
- fail = TRUE; /* Unrecognized jump (eg epilogue). */
+ fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
break;
{
if (reverse)
abort ();
- arm_current_cc =
+ arm_current_cc =
get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
0), 0), 1));
if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
if (reverse || then_not_else)
arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
}
-
+
/* Restore recog_data (getting the attributes of other insns can
destroy this array, but final.c assumes that it remains intact
across this call; since the insn has been recognized already we
}
/* Returns true if REGNO is a valid register
- for holding a quantity of tyoe MODE. */
+ for holding a quantity of type MODE. */
int
arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
{
if (GET_MODE_CLASS (mode) == MODE_CC)
return regno == CC_REGNUM || regno == VFPCC_REGNUM;
-
+
if (TARGET_THUMB)
/* For the Thumb we only allow values bigger than SImode in
registers 0 - 6, so that there is always a second low
|| regno == FRAME_POINTER_REGNUM
|| regno == ARG_POINTER_REGNUM)
return GENERAL_REGS;
-
+
if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
return NO_REGS;
an offset of 0 is correct. */
if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
return 0;
-
+
/* If we are using the stack pointer to point at the
argument, then an offset of 0 is correct. */
if ((TARGET_THUMB || !frame_pointer_needed)
&& REGNO (addr) == SP_REGNUM)
return 0;
-
+
/* Oh dear. The argument is pointed to by a register rather
than being held in a register, or being stored at a known
offset from the frame pointer. Since GDB only understands
looking to see where this register gets its value. If the
register is initialized from the frame pointer plus an offset
then we are in luck and we can continue, otherwise we give up.
-
+
This code is exercised by producing debugging information
for a function with arguments like this:
-
+
double func (double a, double b, int c, double d) {return d;}
-
+
Without this code the stab for parameter 'd' will be set to
an offset of 0 from the frame pointer, rather than 8. */
a constant integer
then... */
-
+
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
- if ( GET_CODE (insn) == INSN
+ if ( GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) == SET
&& REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
&& GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
)
{
value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
-
+
break;
}
}
-
+
if (value == 0)
{
debug_rtx (addr);
do \
{ \
if ((MASK) & insn_flags) \
- builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
+ lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
+ BUILT_IN_MD, NULL, NULL_TREE); \
} \
while (0)
#define IWMMXT_BUILTIN2(code, builtin) \
{ FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
-
+
IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
return 0;
emit_insn (pat);
return target;
-
+
case ARM_BUILTIN_WZERO:
target = gen_reg_rtx (DImode);
emit_insn (gen_iwmmxt_clrdi (target));
for (; block; block = BLOCK_CHAIN (block))
{
tree sym;
-
+
if (!TREE_USED (block))
continue;
SET_DECL_RTL (sym, new);
}
-
+
replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
}
}
the least significant set bit in MASK. */
inline static int
-number_of_first_bit_set (int mask)
+number_of_first_bit_set (unsigned mask)
{
int bit;
return bit;
}
+/* Emit code to push or pop registers to or from the stack. F is the
+ assembly file. MASK is the registers to push or pop. PUSH is
+ nonzero if we should push, and zero if we should pop. For debugging
+ output, if pushing, adjust CFA_OFFSET by the amount of space added
+ to the stack. REAL_REGS should have the same number of bits set as
+ MASK, and will be used instead (in the same order) to describe which
+ registers were saved - this is used to mark the save slots when we
+ push high registers after moving them to low registers. */
+static void
+thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
+ unsigned long real_regs)
+{
+ int regno;
+ int lo_mask = mask & 0xFF;
+ int pushed_words = 0;
+
+ if (mask == 0)
+ abort ();
+
+ if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
+ {
+ /* Special case. Do not generate a POP PC statement here, do it in
+ thumb_exit() */
+ thumb_exit (f, -1);
+ return;
+ }
+
+ fprintf (f, "\t%s\t{", push ? "push" : "pop");
+
+ /* Look at the low registers first. */
+ for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
+ {
+ if (lo_mask & 1)
+ {
+ asm_fprintf (f, "%r", regno);
+
+ if ((lo_mask & ~1) != 0)
+ fprintf (f, ", ");
+
+ pushed_words++;
+ }
+ }
+
+ if (push && (mask & (1 << LR_REGNUM)))
+ {
+ /* Catch pushing the LR. */
+ if (mask & 0xFF)
+ fprintf (f, ", ");
+
+ asm_fprintf (f, "%r", LR_REGNUM);
+
+ pushed_words++;
+ }
+ else if (!push && (mask & (1 << PC_REGNUM)))
+ {
+ /* Catch popping the PC. */
+ if (TARGET_INTERWORK || TARGET_BACKTRACE
+ || current_function_calls_eh_return)
+ {
+ /* The PC is never poped directly, instead
+ it is popped into r3 and then BX is used. */
+ fprintf (f, "}\n");
+
+ thumb_exit (f, -1);
+
+ return;
+ }
+ else
+ {
+ if (mask & 0xFF)
+ fprintf (f, ", ");
+
+ asm_fprintf (f, "%r", PC_REGNUM);
+ }
+ }
+
+ fprintf (f, "}\n");
+
+ if (push && pushed_words && dwarf2out_do_frame ())
+ {
+ char *l = dwarf2out_cfi_label ();
+ int pushed_mask = real_regs;
+
+ *cfa_offset += pushed_words * 4;
+ dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
+
+ pushed_words = 0;
+ pushed_mask = real_regs;
+ for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
+ {
+ if (pushed_mask & 1)
+ dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
+ }
+ }
+}
+
/* Generate code to return from a thumb function.
If 'reg_containing_return_addr' is -1, then the return address is
actually on the stack, at the stack pointer. */
static void
-thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
+thumb_exit (FILE *f, int reg_containing_return_addr)
{
unsigned regs_available_for_popping;
unsigned regs_to_pop;
regs_to_pop = 0;
pops_needed = 0;
- /* There is an assumption here, that if eh_ofs is not NULL, the
- normal return address will have been pushed. */
- if (reg_containing_return_addr == -1 || eh_ofs)
+ if (reg_containing_return_addr == -1)
{
- /* When we are generating a return for __builtin_eh_return,
- reg_containing_return_addr must specify the return regno. */
- if (eh_ofs && reg_containing_return_addr == -1)
- abort ();
-
regs_to_pop |= 1 << LR_REGNUM;
++pops_needed;
}
return. */
if (pops_needed == 0)
{
- if (eh_ofs)
- asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
+ if (current_function_calls_eh_return)
+ asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
return;
just pop the return address straight into the PC. */
else if (!TARGET_INTERWORK
&& !TARGET_BACKTRACE
- && !is_called_in_ARM_mode (current_function_decl))
+ && !is_called_in_ARM_mode (current_function_decl)
+ && !current_function_calls_eh_return)
{
- if (eh_ofs)
- {
- asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
- asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
- asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
- }
- else
- asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
-
+ asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
return;
}
/* If returning via __builtin_eh_return, the bottom three registers
all contain information needed for the return. */
- if (eh_ofs)
+ if (current_function_calls_eh_return)
size = 12;
else
{
/* If we have any popping registers left over, remove them. */
if (available > 0)
regs_available_for_popping &= ~available;
-
+
/* Otherwise if we need another popping register we can use
the fourth argument register. */
else if (pops_needed)
/* Register a4 is being used to hold part of the return value,
but we have dire need of a free, low register. */
restore_a4 = TRUE;
-
+
asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
}
-
+
if (reg_containing_return_addr != LAST_ARG_REGNUM)
{
/* The fourth argument register is available. */
regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
-
+
--pops_needed;
}
}
{
/* The return address was popped into the lowest numbered register. */
regs_to_pop &= ~(1 << LR_REGNUM);
-
+
reg_containing_return_addr =
number_of_first_bit_set (regs_available_for_popping);
if (regs_available_for_popping)
{
int frame_pointer;
-
+
/* Work out which register currently contains the frame pointer. */
frame_pointer = number_of_first_bit_set (regs_available_for_popping);
/* (Temporarily) remove it from the mask of popped registers. */
regs_available_for_popping &= ~(1 << frame_pointer);
regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
-
+
if (regs_available_for_popping)
{
int stack_pointer;
-
+
/* We popped the stack pointer as well,
find the register that contains it. */
stack_pointer = number_of_first_bit_set (regs_available_for_popping);
/* Move it into the stack register. */
asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
-
+
/* At this point we have popped all necessary registers, so
do not worry about restoring regs_available_for_popping
to its correct value:
regs_available_for_popping |= (1 << frame_pointer);
}
}
-
+
/* If we still have registers left on the stack, but we no longer have
any registers into which we can pop them, then we must move the return
address into the link register and make available the register that
if (regs_available_for_popping == 0 && pops_needed > 0)
{
regs_available_for_popping |= 1 << reg_containing_return_addr;
-
+
asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
reg_containing_return_addr);
-
+
reg_containing_return_addr = LR_REGNUM;
}
{
int popped_into;
int move_to;
-
+
thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
regs_available_for_popping);
--pops_needed;
}
-
+
/* If we still have not popped everything then we must have only
had one register available to us and we are now popping the SP. */
if (pops_needed > 0)
{
int popped_into;
-
+
thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
regs_available_for_popping);
asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
reg_containing_return_addr = LR_REGNUM;
}
-
+
asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
}
- if (eh_ofs)
- asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
+ if (current_function_calls_eh_return)
+ asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
/* Return to caller. */
asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
}
-/* Emit code to push or pop registers to or from the stack. F is the
- assembly file. MASK is the registers to push or pop. PUSH is
- nonzero if we should push, and zero if we should pop. For debugging
- output, if pushing, adjust CFA_OFFSET by the amount of space added
- to the stack. REAL_REGS should have the same number of bits set as
- MASK, and will be used instead (in the same order) to describe which
- registers were saved - this is used to mark the save slots when we
- push high registers after moving them to low registers. */
-static void
-thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
-{
- int regno;
- int lo_mask = mask & 0xFF;
- int pushed_words = 0;
-
- if (lo_mask == 0 && !push && (mask & (1 << 15)))
- {
- /* Special case. Do not generate a POP PC statement here, do it in
- thumb_exit() */
- thumb_exit (f, -1, NULL_RTX);
- return;
- }
-
- fprintf (f, "\t%s\t{", push ? "push" : "pop");
-
- /* Look at the low registers first. */
- for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
- {
- if (lo_mask & 1)
- {
- asm_fprintf (f, "%r", regno);
-
- if ((lo_mask & ~1) != 0)
- fprintf (f, ", ");
-
- pushed_words++;
- }
- }
-
- if (push && (mask & (1 << LR_REGNUM)))
- {
- /* Catch pushing the LR. */
- if (mask & 0xFF)
- fprintf (f, ", ");
-
- asm_fprintf (f, "%r", LR_REGNUM);
-
- pushed_words++;
- }
- else if (!push && (mask & (1 << PC_REGNUM)))
- {
- /* Catch popping the PC. */
- if (TARGET_INTERWORK || TARGET_BACKTRACE)
- {
- /* The PC is never poped directly, instead
- it is popped into r3 and then BX is used. */
- fprintf (f, "}\n");
-
- thumb_exit (f, -1, NULL_RTX);
-
- return;
- }
- else
- {
- if (mask & 0xFF)
- fprintf (f, ", ");
-
- asm_fprintf (f, "%r", PC_REGNUM);
- }
- }
-
- fprintf (f, "}\n");
-
- if (push && pushed_words && dwarf2out_do_frame ())
- {
- char *l = dwarf2out_cfi_label ();
- int pushed_mask = real_regs;
-
- *cfa_offset += pushed_words * 4;
- dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
-
- pushed_words = 0;
- pushed_mask = real_regs;
- for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
- {
- if (pushed_mask & 1)
- dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
- }
- }
-}
\f
void
thumb_final_prescan_insn (rtx insn)
if (val == 0) /* XXX */
return 0;
-
+
for (i = 0; i < 25; i++)
if ((val & (mask << i)) == val)
return 1;
/* This test is only important for leaf functions. */
/* assert (!leaf_function_p ()); */
-
+
/* If we have already decided that far jumps may be used,
do not bother checking again, and always return true even if
it turns out that they are not being used. Once we have made
return 1;
}
}
-
+
return 0;
}
if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
return TRUE;
-#ifdef ARM_PE
+#ifdef ARM_PE
return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
#else
return FALSE;
thumb_unexpanded_epilogue (void)
{
int regno;
- int live_regs_mask = 0;
+ unsigned long live_regs_mask = 0;
int high_regs_pushed = 0;
int had_to_push_lr;
- rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
+ int size;
+ int mode;
if (return_used_this_function)
return "";
if (IS_NAKED (arm_current_func_type ()))
return "";
- for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
- if (THUMB_REG_PUSHED_P (regno))
- live_regs_mask |= 1 << regno;
+ live_regs_mask = thumb_compute_save_reg_mask ();
+ high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
+
+ /* If we can deduce the registers used from the function's return value.
+ This is more reliable that examining regs_ever_live[] because that
+ will be set if the register is ever used in the function, not just if
+ the register is used to hold a return value. */
+
+ if (current_function_return_rtx != 0)
+ mode = GET_MODE (current_function_return_rtx);
+ else
+ mode = DECL_MODE (DECL_RESULT (current_function_decl));
- for (regno = 8; regno < 13; regno++)
- if (THUMB_REG_PUSHED_P (regno))
- high_regs_pushed++;
+ size = GET_MODE_SIZE (mode);
/* The prolog may have pushed some high registers to use as
- work registers. eg the testsuite file:
+ work registers. e.g. the testsuite file:
gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
compiles to produce:
push {r4, r5, r6, r7, lr}
mov r6, r8
push {r6, r7}
as part of the prolog. We have to undo that pushing here. */
-
+
if (high_regs_pushed)
{
- int mask = live_regs_mask;
+ unsigned long mask = live_regs_mask & 0xff;
int next_hi_reg;
- int size;
- int mode;
-
- /* If we can deduce the registers used from the function's return value.
- This is more reliable that examining regs_ever_live[] because that
- will be set if the register is ever used in the function, not just if
- the register is used to hold a return value. */
-
- if (current_function_return_rtx != 0)
- mode = GET_MODE (current_function_return_rtx);
- else
- mode = DECL_MODE (DECL_RESULT (current_function_decl));
- size = GET_MODE_SIZE (mode);
-
- /* Unless we are returning a type of size > 12 register r3 is
- available. */
- if (size < 13)
+ /* The available low registers depend on the size of the value we are
+ returning. */
+ if (size <= 12)
mask |= 1 << 3;
+ if (size <= 8)
+ mask |= 1 << 2;
if (mask == 0)
/* Oh dear! We have no low registers into which we can pop
high registers! */
internal_error
("no low registers available for popping high registers");
-
+
for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
- if (THUMB_REG_PUSHED_P (next_hi_reg))
+ if (live_regs_mask & (1 << next_hi_reg))
break;
while (high_regs_pushed)
{
asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
regno);
-
+
for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
- if (THUMB_REG_PUSHED_P (next_hi_reg))
+ if (live_regs_mask & (1 << next_hi_reg))
break;
}
}
}
+ live_regs_mask &= ~0x0f00;
}
- had_to_push_lr = (live_regs_mask || thumb_force_lr_save ());
-
- if (TARGET_BACKTRACE
- && ((live_regs_mask & 0xFF) == 0)
- && regs_ever_live [LAST_ARG_REGNUM] != 0)
- {
- /* The stack backtrace structure creation code had to
- push R7 in order to get a work register, so we pop
- it now. */
- live_regs_mask |= (1 << LAST_LO_REGNUM);
- }
-
+ had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
+ live_regs_mask &= 0xff;
+
if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
{
- if (had_to_push_lr
- && !is_called_in_ARM_mode (current_function_decl)
- && !eh_ofs)
+ /* Pop the return address into the PC. */
+ if (had_to_push_lr)
live_regs_mask |= 1 << PC_REGNUM;
/* Either no argument registers were pushed or a backtrace
if (live_regs_mask)
thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
live_regs_mask);
-
- if (eh_ofs)
- thumb_exit (asm_out_file, 2, eh_ofs);
+
/* We have either just popped the return address into the
- PC or it is was kept in LR for the entire function or
- it is still on the stack because we do not want to
- return by doing a pop {pc}. */
- else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
- thumb_exit (asm_out_file,
- (had_to_push_lr
- && is_called_in_ARM_mode (current_function_decl)) ?
- -1 : LR_REGNUM, NULL_RTX);
+ PC or it is was kept in LR for the entire function. */
+ if (!had_to_push_lr)
+ thumb_exit (asm_out_file, LR_REGNUM);
}
else
{
/* Pop everything but the return address. */
- live_regs_mask &= ~(1 << PC_REGNUM);
-
if (live_regs_mask)
thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
live_regs_mask);
if (had_to_push_lr)
- /* Get the return address into a temporary register. */
- thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
- 1 << LAST_ARG_REGNUM);
-
+ {
+ if (size > 12)
+ {
+ /* We have no free low regs, so save one. */
+ asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
+ LAST_ARG_REGNUM);
+ }
+
+ /* Get the return address into a temporary register. */
+ thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
+ 1 << LAST_ARG_REGNUM);
+
+ if (size > 12)
+ {
+ /* Move the return address to lr. */
+ asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
+ LAST_ARG_REGNUM);
+ /* Restore the low register. */
+ asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
+ IP_REGNUM);
+ regno = LR_REGNUM;
+ }
+ else
+ regno = LAST_ARG_REGNUM;
+ }
+ else
+ regno = LR_REGNUM;
+
/* Remove the argument registers that were pushed onto the stack. */
asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
SP_REGNUM, SP_REGNUM,
current_function_pretend_args_size);
-
- if (eh_ofs)
- thumb_exit (asm_out_file, 2, eh_ofs);
- else
- thumb_exit (asm_out_file,
- had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
+
+ thumb_exit (asm_out_file, regno);
}
return "";
struct machine_function *machine;
machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
-#if ARM_FT_UNKNOWN != 0
+#if ARM_FT_UNKNOWN != 0
machine->func_type = ARM_FT_UNKNOWN;
#endif
return machine;
{
/* Arrange to initialize and mark the machine per-function status. */
init_machine_status = arm_init_machine_status;
+
+ /* This is to stop the combine pass optimizing away the alignment
+ adjustment of va_arg. */
+ /* ??? It is claimed that this should not be necessary. */
+ if (cfun)
+ mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
}
arm_stack_offsets *offsets;
unsigned long func_type;
int regno;
+ unsigned long live_regs_mask;
func_type = arm_current_func_type ();
-
+
/* Naked functions don't have prologues. */
if (IS_NAKED (func_type))
return;
return;
}
+ live_regs_mask = thumb_compute_save_reg_mask ();
+ /* Load the pic register before setting the frame pointer,
+ so we can use r7 as a temporary work register. */
+ if (flag_pic)
+ arm_load_pic_register (thumb_find_work_register (live_regs_mask));
+
offsets = arm_get_frame_offsets ();
if (frame_pointer_needed)
stack_pointer_rtx));
RTX_FRAME_RELATED_P (insn) = 1;
}
+ else if (CALLER_INTERWORKING_SLOT_SIZE > 0)
+ emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
+ stack_pointer_rtx);
amount = offsets->outgoing_args - offsets->saved_regs;
if (amount)
been pushed at the start of the prologue and so we can corrupt
it now. */
for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
- if (THUMB_REG_PUSHED_P (regno)
+ if (live_regs_mask & (1 << regno)
&& !(frame_pointer_needed
&& (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
break;
RTX_FRAME_RELATED_P (insn) = 1;
dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
plus_constant (stack_pointer_rtx,
- GEN_INT (- amount)));
+ -amount));
RTX_FRAME_RELATED_P (dwarf) = 1;
REG_NOTES (insn)
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
/* Restore the low register's original value. */
emit_insn (gen_movsi (reg, spare));
-
+
/* Emit a USE of the restored scratch register, so that flow
analysis will not consider the restore redundant. The
register won't be used again in this function and isn't
RTX_FRAME_RELATED_P (insn) = 1;
dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
plus_constant (stack_pointer_rtx,
- GEN_INT (- amount)));
+ -amount));
RTX_FRAME_RELATED_P (dwarf) = 1;
REG_NOTES (insn)
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
emit_insn (gen_stack_tie (stack_pointer_rtx,
hard_frame_pointer_rtx));
}
-
- if (current_function_profile || TARGET_NO_SCHED_PRO)
- emit_insn (gen_blockage ());
- cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
- for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
- {
- if (THUMB_REG_PUSHED_P (regno))
- {
- cfun->machine->lr_save_eliminated = 0;
- break;
- }
- }
+ if (current_function_profile || TARGET_NO_SCHED_PRO)
+ emit_insn (gen_blockage ());
+
+ cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
+ if (live_regs_mask & 0xff)
+ cfun->machine->lr_save_eliminated = 0;
/* If the link register is being kept alive, with the return address in it,
then make sure that it does not get reused by the ce2 pass. */
emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
}
+
void
thumb_expand_epilogue (void)
{
emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
}
}
-
+
/* Emit a USE (stack_pointer_rtx), so that
the stack adjustment will not be deleted. */
emit_insn (gen_prologue_use (stack_pointer_rtx));
static void
thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
- int live_regs_mask = 0;
- int high_regs_pushed = 0;
+ unsigned long live_regs_mask = 0;
+ unsigned long l_mask;
+ unsigned high_regs_pushed = 0;
int cfa_offset = 0;
int regno;
if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
abort ();
name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
-
+
/* Generate code sequence to switch us into Thumb mode. */
/* The .code 32 directive has already been emitted by
ASM_DECLARE_FUNCTION_NAME. */
is called from a Thumb encoded function elsewhere in the
same file. Hence the definition of STUB_NAME here must
agree with the definition in gas/config/tc-arm.c. */
-
+
#define STUB_NAME ".real_start_of"
-
+
fprintf (f, "\t.code\t16\n");
#ifdef ARM_PE
if (arm_dllexport_name_p (name))
name = arm_strip_name_encoding (name);
-#endif
+#endif
asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
fprintf (f, "\t.thumb_func\n");
asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
}
-
+
if (current_function_pretend_args_size)
{
if (cfun->machine->uses_anonymous_args)
{
int num_pushes;
-
+
fprintf (f, "\tpush\t{");
num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
-
+
for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
regno <= LAST_ARG_REGNUM;
regno++)
fprintf (f, "}\n");
}
else
- asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
+ asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
SP_REGNUM, SP_REGNUM,
current_function_pretend_args_size);
if (dwarf2out_do_frame ())
{
char *l = dwarf2out_cfi_label ();
+
cfa_offset = cfa_offset + current_function_pretend_args_size;
dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
}
}
- for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
- if (THUMB_REG_PUSHED_P (regno))
- live_regs_mask |= 1 << regno;
-
- if (live_regs_mask || thumb_force_lr_save ())
- live_regs_mask |= 1 << LR_REGNUM;
+ /* Get the registers we are going to push. */
+ live_regs_mask = thumb_compute_save_reg_mask ();
+ /* Extract a mask of the ones we can give to the Thumb's push instruction. */
+ l_mask = live_regs_mask & 0x40ff;
+ /* Then count how many other high registers will need to be pushed. */
+ high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
if (TARGET_BACKTRACE)
{
- int offset;
- int work_register = 0;
- int wr;
-
+ unsigned offset;
+ unsigned work_register;
+
/* We have been asked to create a stack backtrace structure.
The code looks like this:
-
+
0 .align 2
0 func:
0 sub SP, #16 Reserve space for 4 registers.
- 2 push {R7} Get a work register.
+ 2 push {R7} Push low registers.
4 add R7, SP, #20 Get the stack pointer before the push.
6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
8 mov R7, PC Get hold of the start of this code plus 12.
20 add R7, SP, #16 Point at the start of the backtrace structure.
22 mov FP, R7 Put this value into the frame pointer. */
- if ((live_regs_mask & 0xFF) == 0)
- {
- /* See if the a4 register is free. */
-
- if (regs_ever_live [LAST_ARG_REGNUM] == 0)
- work_register = LAST_ARG_REGNUM;
- else /* We must push a register of our own. */
- live_regs_mask |= (1 << LAST_LO_REGNUM);
- }
+ work_register = thumb_find_work_register (live_regs_mask);
- if (work_register == 0)
- {
- /* Select a register from the list that will be pushed to
- use as our work register. */
- for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
- if ((1 << work_register) & live_regs_mask)
- break;
- }
-
asm_fprintf
(f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
SP_REGNUM, SP_REGNUM);
if (dwarf2out_do_frame ())
{
char *l = dwarf2out_cfi_label ();
+
cfa_offset = cfa_offset + 16;
dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
}
- if (live_regs_mask)
- thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
-
- for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
- if (wr & live_regs_mask)
- offset += 4;
-
+ if (l_mask)
+ {
+ thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
+ offset = bit_count (l_mask);
+ }
+ else
+ offset = 0;
+
asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
offset + 16 + current_function_pretend_args_size);
-
+
asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
offset + 4);
/* Make sure that the instruction fetching the PC is in the right place
to calculate "start of backtrace creation code + 12". */
- if (live_regs_mask)
+ if (l_mask)
{
asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
offset + 12);
}
-
+
asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
offset + 8);
asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
ARM_HARD_FRAME_POINTER_REGNUM, work_register);
}
- else if (live_regs_mask)
- thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
-
- for (regno = 8; regno < 13; regno++)
- if (THUMB_REG_PUSHED_P (regno))
- high_regs_pushed++;
+ /* Optimisation: If we are not pushing any low registers but we are going
+ to push some high registers then delay our first push. This will just
+ be a push of LR and we can combine it with the push of the first high
+ register. */
+ else if ((l_mask & 0xff) != 0
+ || (high_regs_pushed == 0 && l_mask))
+ thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
if (high_regs_pushed)
{
- int pushable_regs = 0;
- int mask = live_regs_mask & 0xff;
- int next_hi_reg;
+ unsigned pushable_regs;
+ unsigned next_hi_reg;
for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
- if (THUMB_REG_PUSHED_P (next_hi_reg))
+ if (live_regs_mask & (1 << next_hi_reg))
break;
- pushable_regs = mask;
+ pushable_regs = l_mask & 0xff;
if (pushable_regs == 0)
- {
- /* Desperation time -- this probably will never happen. */
- if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
- asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
- mask = 1 << LAST_ARG_REGNUM;
- }
+ pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
while (high_regs_pushed > 0)
{
- int real_regs_mask = 0;
+ unsigned long real_regs_mask = 0;
- for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
+ for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
{
- if (mask & (1 << regno))
+ if (pushable_regs & (1 << regno))
{
asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
-
- high_regs_pushed--;
+
+ high_regs_pushed --;
real_regs_mask |= (1 << next_hi_reg);
-
+
if (high_regs_pushed)
{
- for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
- next_hi_reg--)
- if (THUMB_REG_PUSHED_P (next_hi_reg))
+ for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
+ next_hi_reg --)
+ if (live_regs_mask & (1 << next_hi_reg))
break;
}
else
{
- mask &= ~((1 << regno) - 1);
+ pushable_regs &= ~((1 << regno) - 1);
break;
}
}
}
- thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
+ /* If we had to find a work register and we have not yet
+ saved the LR then add it to the list of regs to push. */
+ if (l_mask == (1 << LR_REGNUM))
+ {
+ thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
+ 1, &cfa_offset,
+ real_regs_mask | (1 << LR_REGNUM));
+ l_mask = 0;
+ }
+ else
+ thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
}
-
- if (pushable_regs == 0
- && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
- asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
}
}
rtx offset;
rtx arg1;
rtx arg2;
-
+
if (GET_CODE (operands[0]) != REG)
abort ();
-
+
if (GET_CODE (operands[1]) != MEM)
abort ();
/* Get the memory address. */
addr = XEXP (operands[1], 0);
-
+
/* Work out how the memory address is computed. */
switch (GET_CODE (addr))
{
output_asm_insn ("ldr\t%H0, %2", operands);
}
break;
-
+
case CONST:
/* Compute <address> + 4 for the high order load. */
operands[2] = gen_rtx_MEM (SImode,
plus_constant (XEXP (operands[1], 0), 4));
-
+
output_asm_insn ("ldr\t%0, %1", operands);
output_asm_insn ("ldr\t%H0, %2", operands);
break;
-
+
case PLUS:
arg1 = XEXP (addr, 0);
arg2 = XEXP (addr, 1);
-
+
if (CONSTANT_P (arg1))
base = arg2, offset = arg1;
else
base = arg1, offset = arg2;
-
+
if (GET_CODE (base) != REG)
abort ();
int reg_offset = REGNO (offset);
int reg_base = REGNO (base);
int reg_dest = REGNO (operands[0]);
-
+
/* Add the base and offset registers together into the
higher destination register. */
asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
reg_dest + 1, reg_base, reg_offset);
-
+
/* Load the lower destination register from the address in
the higher destination register. */
asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
reg_dest, reg_dest + 1);
-
+
/* Load the higher destination register from its own address
plus 4. */
asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
/* Compute <address> + 4 for the high order load. */
operands[2] = gen_rtx_MEM (SImode,
plus_constant (XEXP (operands[1], 0), 4));
-
+
/* If the computed address is held in the low order register
then load the high order register first, otherwise always
load the low order register first. */
directly. */
operands[2] = gen_rtx_MEM (SImode,
plus_constant (XEXP (operands[1], 0), 4));
-
+
output_asm_insn ("ldr\t%H0, %2", operands);
output_asm_insn ("ldr\t%0, %1", operands);
break;
-
+
default:
abort ();
break;
}
-
+
return "";
}
operands[4] = operands[5];
operands[5] = tmp;
}
-
+
output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
break;
return "";
}
+/* Output a call-via instruction for thumb state. */
+const char *
+thumb_call_via_reg (rtx reg)
+{
+ int regno = REGNO (reg);
+ rtx *labelp;
+
+ gcc_assert (regno < SP_REGNUM);
+
+ /* If we are in the normal text section we can use a single instance
+ per compilation unit. If we are doing function sections, then we need
+ an entry per section, since we can't rely on reachability. */
+ if (in_text_section ())
+ {
+ thumb_call_reg_needed = 1;
+
+ if (thumb_call_via_label[regno] == NULL)
+ thumb_call_via_label[regno] = gen_label_rtx ();
+ labelp = thumb_call_via_label + regno;
+ }
+ else
+ {
+ if (cfun->machine->call_via[regno] == NULL)
+ cfun->machine->call_via[regno] = gen_label_rtx ();
+ labelp = cfun->machine->call_via + regno;
+ }
+
+ output_asm_insn ("bl\t%a0", labelp);
+ return "";
+}
+
/* Routines for generating rtl. */
void
-thumb_expand_movstrqi (rtx *operands)
+thumb_expand_movmemqi (rtx *operands)
{
rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
emit_insn (gen_movmem12b (out, in, out, in));
len -= 12;
}
-
+
if (len >= 8)
{
emit_insn (gen_movmem8b (out, in, out, in));
len -= 8;
}
-
+
if (len >= 4)
{
rtx reg = gen_reg_rtx (SImode);
len -= 4;
offset += 4;
}
-
+
if (len >= 2)
{
rtx reg = gen_reg_rtx (HImode);
- emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
+ emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
plus_constant (in, offset))));
emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
reg));
len -= 2;
offset += 2;
}
-
+
if (len)
{
rtx reg = gen_reg_rtx (QImode);
}
}
-int
-thumb_cmp_operand (rtx op, enum machine_mode mode)
-{
- return ((GET_CODE (op) == CONST_INT
- && INTVAL (op) < 256
- && INTVAL (op) >= 0)
- || s_register_operand (op, mode));
-}
-
-int
-thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return (GET_CODE (op) == CONST_INT
- && INTVAL (op) < 0
- && INTVAL (op) > -256);
-}
-
-/* Return TRUE if a result can be stored in OP without clobbering the
- condition code register. Prior to reload we only accept a
- register. After reload we have to be able to handle memory as
- well, since a pseudo may not get a hard reg and reload cannot
- handle output-reloads on jump insns.
-
- We could possibly handle mem before reload as well, but that might
- complicate things with the need to handle increment
- side-effects. */
-
-int
-thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
-{
- return (s_register_operand (op, mode)
- || ((reload_in_progress || reload_completed)
- && memory_operand (op, mode)));
-}
-
-/* Handle storing a half-word to memory during reload. */
void
thumb_reload_out_hi (rtx *operands)
{
emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
}
-/* Handle reading a half-word from memory during reload. */
+/* Handle reading a half-word from memory during reload. */
void
thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
{
switch (c)
{
ARM_NAME_ENCODING_LENGTHS
- default: return 0;
+ default: return 0;
}
}
arm_strip_name_encoding (const char *name)
{
int skip;
-
+
while ((skip = arm_get_strip_length (* name)))
name += skip;
asm_fprintf (stream, "%U%s", name);
}
+static void
+arm_file_end (void)
+{
+ int regno;
+
+ if (! thumb_call_reg_needed)
+ return;
+
+ text_section ();
+ asm_fprintf (asm_out_file, "\t.code 16\n");
+ ASM_OUTPUT_ALIGN (asm_out_file, 1);
+
+ for (regno = 0; regno < SP_REGNUM; regno++)
+ {
+ rtx label = thumb_call_via_label[regno];
+
+ if (label != 0)
+ {
+ targetm.asm_out.internal_label (asm_out_file, "L",
+ CODE_LABEL_NUMBER (label));
+ asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
+ }
+ }
+}
+
rtx aof_pic_label;
#ifdef AOF_ASSEMBLER
PIC_OFFSET_TABLE_REGNUM,
PIC_OFFSET_TABLE_REGNUM);
fputs ("|x$adcons|\n", f);
-
+
for (chain = aof_pic_chain; chain; chain = chain->next)
{
fputs ("\tDCD\t", f);
{
if (flag_pic)
aof_dump_pic_table (asm_out_file);
+ arm_file_end ();
aof_dump_imports (asm_out_file);
fputs ("\tEND\n", asm_out_file);
}
#endif /* AOF_ASSEMBLER */
-#ifdef OBJECT_FORMAT_ELF
-/* Switch to an arbitrary section NAME with attributes as specified
- by FLAGS. ALIGN specifies any known alignment requirements for
- the section; 0 if the default should be used.
-
- Differs from the default elf version only in the prefix character
- used before the section type. */
-
-static void
-arm_elf_asm_named_section (const char *name, unsigned int flags)
-{
- char flagchars[10], *f = flagchars;
-
- if (! named_section_first_declaration (name))
- {
- fprintf (asm_out_file, "\t.section\t%s\n", name);
- return;
- }
-
- if (!(flags & SECTION_DEBUG))
- *f++ = 'a';
- if (flags & SECTION_WRITE)
- *f++ = 'w';
- if (flags & SECTION_CODE)
- *f++ = 'x';
- if (flags & SECTION_SMALL)
- *f++ = 's';
- if (flags & SECTION_MERGE)
- *f++ = 'M';
- if (flags & SECTION_STRINGS)
- *f++ = 'S';
- if (flags & SECTION_TLS)
- *f++ = 'T';
- *f = '\0';
-
- fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
-
- if (!(flags & SECTION_NOTYPE))
- {
- const char *type;
-
- if (flags & SECTION_BSS)
- type = "nobits";
- else
- type = "progbits";
-
- fprintf (asm_out_file, ",%%%s", type);
-
- if (flags & SECTION_ENTSIZE)
- fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
- }
-
- putc ('\n', asm_out_file);
-}
-#endif
-
#ifndef ARM_PE
/* Symbols in the text segment can be accessed without indirecting via the
constant pool; it may take an extra binary operation, but this is still
/* If we are referencing a function that is weak then encode a long call
flag in the function name, otherwise if the function is static or
or known to be defined in this file then encode a short call flag. */
- if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
+ if (first && DECL_P (decl))
{
if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
rtx offset;
rtx wcgr;
rtx sum;
-
+
if (GET_CODE (operands [1]) != MEM
|| GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
|| GET_CODE (reg = XEXP (sum, 0)) != REG
|| GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
|| ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
return "wldrw%?\t%0, %1";
-
- /* Fix up an out-of-range load of a GR register. */
+
+ /* Fix up an out-of-range load of a GR register. */
output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
wcgr = operands[0];
operands[0] = reg;
if (GET_CODE (addr) == PARALLEL)
addr = XVECEXP (addr, 0, 0);
addr = XEXP (addr, 0);
-
+
return !reg_overlap_mentioned_p (value, addr);
}
if (GET_CODE (op) == PARALLEL)
op = XVECEXP (op, 0, 0);
op = XEXP (op, 1);
-
+
early_op = XEXP (op, 0);
/* This is either an actual independent shift, or a shift applied to
the first operand of another operation. We want the whole shift
if (GET_CODE (op) == PARALLEL)
op = XVECEXP (op, 0, 0);
op = XEXP (op, 1);
-
+
early_op = XEXP (op, 0);
/* This is either an actual independent shift, or a shift applied to
shifted, in either case. */
if (GET_CODE (early_op) != REG)
early_op = XEXP (early_op, 0);
-
+
return !reg_overlap_mentioned_p (value, early_op);
}
if (GET_CODE (op) == PARALLEL)
op = XVECEXP (op, 0, 0);
op = XEXP (op, 1);
-
+
return (GET_CODE (op) == PLUS
&& !reg_overlap_mentioned_p (value, XEXP (op, 0)));
}
{
return TARGET_AAPCS_BASED;
}
+
+
+/* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
+
+static tree
+arm_cxx_guard_type (void)
+{
+ return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
+}
+
+
+/* The EABI says test the least significan bit of a guard variable. */
+
+static bool
+arm_cxx_guard_mask_bit (void)
+{
+ return TARGET_AAPCS_BASED;
+}
+
+
+/* The EABI specifies that all array cookies are 8 bytes long. */
+
+static tree
+arm_get_cookie_size (tree type)
+{
+ tree size;
+
+ if (!TARGET_AAPCS_BASED)
+ return default_cxx_get_cookie_size (type);
+
+ size = build_int_cst (sizetype, 8);
+ return size;
+}
+
+
+/* The EABI says that array cookies should also contain the element size. */
+
+static bool
+arm_cookie_has_size (void)
+{
+ return TARGET_AAPCS_BASED;
+}
+
+
+/* The EABI says constructors and destructors should return a pointer to
+ the object constructed/destroyed. */
+
+static bool
+arm_cxx_cdtor_returns_this (void)
+{
+ return TARGET_AAPCS_BASED;
+}
+
+/* The EABI says that an inline function may never be the key
+ method. */
+
+static bool
+arm_cxx_key_method_may_be_inline (void)
+{
+ return !TARGET_AAPCS_BASED;
+}
+
+/* The EABI says that the virtual table, etc., for a class must be
+ exported if it has a key method. The EABI does not specific the
+ behavior if there is no key method, but there is no harm in
+ exporting the class data in that case too. */
+
+static bool
+arm_cxx_export_class_data (void)
+{
+ return TARGET_AAPCS_BASED;
+}
+
+void
+arm_set_return_address (rtx source, rtx scratch)
+{
+ arm_stack_offsets *offsets;
+ HOST_WIDE_INT delta;
+ rtx addr;
+ unsigned long saved_regs;
+
+ saved_regs = arm_compute_save_reg_mask ();
+
+ if ((saved_regs & (1 << LR_REGNUM)) == 0)
+ emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
+ else
+ {
+ if (frame_pointer_needed)
+ addr = plus_constant(hard_frame_pointer_rtx, -4);
+ else
+ {
+ /* LR will be the first saved register. */
+ offsets = arm_get_frame_offsets ();
+ delta = offsets->outgoing_args - (offsets->frame + 4);
+
+
+ if (delta >= 4096)
+ {
+ emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
+ GEN_INT (delta & ~4095)));
+ addr = scratch;
+ delta &= 4095;
+ }
+ else
+ addr = stack_pointer_rtx;
+
+ addr = plus_constant (addr, delta);
+ }
+ emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
+ }
+}
+
+
+void
+thumb_set_return_address (rtx source, rtx scratch)
+{
+ arm_stack_offsets *offsets;
+ HOST_WIDE_INT delta;
+ int reg;
+ rtx addr;
+ unsigned long mask;
+
+ emit_insn (gen_rtx_USE (VOIDmode, source));
+
+ mask = thumb_compute_save_reg_mask ();
+ if (mask & (1 << LR_REGNUM))
+ {
+ offsets = arm_get_frame_offsets ();
+
+ /* Find the saved regs. */
+ if (frame_pointer_needed)
+ {
+ delta = offsets->soft_frame - offsets->saved_args;
+ reg = THUMB_HARD_FRAME_POINTER_REGNUM;
+ }
+ else
+ {
+ delta = offsets->outgoing_args - offsets->saved_args;
+ reg = SP_REGNUM;
+ }
+ /* Allow for the stack frame. */
+ if (TARGET_BACKTRACE)
+ delta -= 16;
+ /* The link register is always the first saved register. */
+ delta -= 4;
+
+ /* Construct the address. */
+ addr = gen_rtx_REG (SImode, reg);
+ if ((reg != SP_REGNUM && delta >= 128)
+ || delta >= 1024)
+ {
+ emit_insn (gen_movsi (scratch, GEN_INT (delta)));
+ emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
+ addr = scratch;
+ }
+ else
+ addr = plus_constant (addr, delta);
+
+ emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
+ }
+ else
+ emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
+}
+
+/* Implements target hook vector_mode_supported_p. */
+bool
+arm_vector_mode_supported_p (enum machine_mode mode)
+{
+ if ((mode == V2SImode)
+ || (mode == V4HImode)
+ || (mode == V8QImode))
+ return true;
+
+ return false;
+}
+
+/* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
+ ARM insns and therefore guarantee that the shift count is modulo 256.
+ DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
+ guarantee no particular behavior for out-of-range counts. */
+
+static unsigned HOST_WIDE_INT
+arm_shift_truncation_mask (enum machine_mode mode)
+{
+ return mode == SImode ? 255 : 0;
+}
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