OSDN Git Service

2010-12-09 Yao Qi <yao@codesourcery.com>
[pf3gnuchains/gcc-fork.git] / gcc / config / arm / arm.c
index 9d2c6dd..ac25365 100644 (file)
@@ -248,6 +248,7 @@ static bool arm_builtin_support_vector_misalignment (enum machine_mode mode,
                                                     int misalignment,
                                                     bool is_packed);
 static void arm_conditional_register_usage (void);
+static reg_class_t arm_preferred_rename_class (reg_class_t class);
 
 \f
 /* Table of machine attributes.  */
@@ -585,6 +586,10 @@ static const struct default_options arm_option_optimization_table[] =
 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
   arm_builtin_support_vector_misalignment
 
+#undef TARGET_PREFERRED_RENAME_CLASS
+#define TARGET_PREFERRED_RENAME_CLASS \
+  arm_preferred_rename_class
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 \f
 /* Obstack for minipool constant handling.  */
@@ -23467,4 +23472,16 @@ arm_conditional_register_usage (void)
   SUBTARGET_CONDITIONAL_REGISTER_USAGE
 }
 
+static reg_class_t
+arm_preferred_rename_class (reg_class_t class)
+{
+  /* Thumb-2 instructions using LO_REGS may be smaller than instructions
+     using GENERIC_REGS.  During register rename pass, we prefer LO_REGS,
+     and code size can be reduced.  */
+  if (TARGET_THUMB2 && class == GENERAL_REGS)
+    return LO_REGS;
+  else
+    return NO_REGS;
+}
+
 #include "gt-arm.h"