static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
+#ifdef OBJECT_FORMAT_ELF
+static void arm_elf_asm_constructor (rtx, int);
+#endif
#ifndef ARM_PE
static void arm_encode_section_info (tree, rtx, int);
#endif
static bool arm_promote_prototypes (tree);
static bool arm_default_short_enums (void);
static bool arm_align_anon_bitfield (void);
+static bool arm_return_in_msb (tree);
+static bool arm_must_pass_in_stack (enum machine_mode, tree);
static tree arm_cxx_guard_type (void);
static bool arm_cxx_guard_mask_bit (void);
static bool arm_cookie_has_size (void);
static bool arm_cxx_cdtor_returns_this (void);
static bool arm_cxx_key_method_may_be_inline (void);
-static bool arm_cxx_export_class_data (void);
+static void arm_cxx_determine_class_data_visibility (tree);
+static bool arm_cxx_class_data_always_comdat (void);
+static bool arm_cxx_use_aeabi_atexit (void);
static void arm_init_libfuncs (void);
+static bool arm_handle_option (size_t, const char *, int);
static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
\f
/* Initialize the GCC target structure. */
#undef TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
+#undef TARGET_DEFAULT_TARGET_FLAGS
+#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
+#undef TARGET_HANDLE_OPTION
+#define TARGET_HANDLE_OPTION arm_handle_option
+
#undef TARGET_COMP_TYPE_ATTRIBUTES
#define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
#undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
#define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
-#undef TARGET_CXX_EXPORT_CLASS_DATA
-#define TARGET_CXX_EXPORT_CLASS_DATA arm_cxx_export_class_data
+#undef TARGET_CXX_USE_AEABI_ATEXIT
+#define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
+
+#undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
+#define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
+ arm_cxx_determine_class_data_visibility
+
+#undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
+#define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
+
+#undef TARGET_RETURN_IN_MSB
+#define TARGET_RETURN_IN_MSB arm_return_in_msb
+
+#undef TARGET_MUST_PASS_IN_STACK
+#define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
struct gcc_target targetm = TARGET_INITIALIZER;
\f
enum arm_abi_type arm_abi;
/* Set by the -mfpu=... option. */
-const char * target_fpu_name = NULL;
+static const char * target_fpu_name = NULL;
/* Set by the -mfpe=... option. */
-const char * target_fpe_name = NULL;
+static const char * target_fpe_name = NULL;
/* Set by the -mfloat-abi=... option. */
-const char * target_float_abi_name = NULL;
-
-/* Set by the legacy -mhard-float and -msoft-float options. */
-const char * target_float_switch = NULL;
+static const char * target_float_abi_name = NULL;
/* Set by the -mabi=... option. */
-const char * target_abi_name = NULL;
+static const char * target_abi_name = NULL;
/* Used to parse -mstructure_size_boundary command line option. */
-const char * structure_size_string = NULL;
+static const char * structure_size_string = NULL;
int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
/* Used for Thumb call_via trampolines. */
enum machine_mode output_memory_reference_mode;
/* The register number to be used for the PIC offset register. */
-const char * arm_pic_register_string = NULL;
+static const char * arm_pic_register_string = NULL;
int arm_pic_register = INVALID_REGNUM;
/* Set to 1 when a return insn is output, this means that the epilogue
{NULL, arm_none, NULL, 0 , NULL}
};
+struct arm_cpu_select
+{
+ const char * string;
+ const char * name;
+ const struct processors * processors;
+};
+
/* This is a magic structure. The 'string' field is magically filled in
with a pointer to the value specified by the user on the command line
assuming that the user has specified such a value. */
-struct arm_cpu_select arm_select[] =
+static struct arm_cpu_select arm_select[] =
{
/* string name processors */
{ NULL, "-mcpu=", all_cores },
{ NULL, "-mtune=", all_cores }
};
+/* Defines representing the indexes into the above table. */
+#define ARM_OPT_SET_CPU 0
+#define ARM_OPT_SET_ARCH 1
+#define ARM_OPT_SET_TUNE 2
/* The name of the proprocessor macro to define for this architecture. */
set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
+
+ /* We don't have mod libcalls. Fortunately gcc knows how to use the
+ divmod libcalls instead. */
+ set_optab_libfunc (smod_optab, DImode, NULL);
+ set_optab_libfunc (umod_optab, DImode, NULL);
+ set_optab_libfunc (smod_optab, SImode, NULL);
+ set_optab_libfunc (umod_optab, SImode, NULL);
+}
+
+/* Implement TARGET_HANDLE_OPTION. */
+
+static bool
+arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
+{
+ switch (code)
+ {
+ case OPT_mabi_:
+ target_abi_name = arg;
+ return true;
+
+ case OPT_march_:
+ arm_select[1].string = arg;
+ return true;
+
+ case OPT_mcpu_:
+ arm_select[0].string = arg;
+ return true;
+
+ case OPT_mfloat_abi_:
+ target_float_abi_name = arg;
+ return true;
+
+ case OPT_mfp_:
+ case OPT_mfpe_:
+ target_fpe_name = arg;
+ return true;
+
+ case OPT_mfpu_:
+ target_fpu_name = arg;
+ return true;
+
+ case OPT_mhard_float:
+ target_float_abi_name = "hard";
+ return true;
+
+ case OPT_mpic_register_:
+ arm_pic_register_string = arg;
+ return true;
+
+ case OPT_msoft_float:
+ target_float_abi_name = "soft";
+ return true;
+
+ case OPT_mstructure_size_boundary_:
+ structure_size_string = arg;
+ return true;
+
+ case OPT_mtune_:
+ arm_select[2].string = arg;
+ return true;
+
+ default:
+ return true;
+ }
}
/* Fix up any incompatible options that the user has specified.
arm_override_options (void)
{
unsigned i;
+ enum processor_type target_arch_cpu = arm_none;
/* Set up the flags based on the cpu/architecture selected by the user. */
for (i = ARRAY_SIZE (arm_select); i--;)
if (streq (ptr->string, sel->name))
{
/* Set the architecture define. */
- if (i != 2)
+ if (i != ARM_OPT_SET_TUNE)
sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
/* Determine the processor core for which we should
tune code-generation. */
if (/* -mcpu= is a sensible default. */
- i == 0
- /* If -march= is used, and -mcpu= has not been used,
- assume that we should tune for a representative
- CPU from that architecture. */
- || i == 1
+ i == ARM_OPT_SET_CPU
/* -mtune= overrides -mcpu= and -march=. */
- || i == 2)
+ || i == ARM_OPT_SET_TUNE)
arm_tune = (enum processor_type) (sel - ptr->processors);
- if (i != 2)
+ /* Remember the CPU associated with this architecture.
+ If no other option is used to set the CPU type,
+ we'll use this to guess the most suitable tuning
+ options. */
+ if (i == ARM_OPT_SET_ARCH)
+ target_arch_cpu = sel->core;
+
+ if (i != ARM_OPT_SET_TUNE)
{
/* If we have been given an architecture and a processor
make sure that they are compatible. We only generate
a warning though, and we prefer the CPU over the
architecture. */
if (insn_flags != 0 && (insn_flags ^ sel->flags))
- warning ("switch -mcpu=%s conflicts with -march= switch",
+ warning (0, "switch -mcpu=%s conflicts with -march= switch",
ptr->string);
insn_flags = sel->flags;
}
}
+ /* Guess the tuning options from the architecture if necessary. */
+ if (arm_tune == arm_none)
+ arm_tune = target_arch_cpu;
+
/* If the user did not specify a processor, choose one for them. */
if (insn_flags == 0)
{
}
}
- if (best_fit == NULL)
- abort ();
- else
- sel = best_fit;
+ gcc_assert (best_fit);
+ sel = best_fit;
}
insn_flags = sel->flags;
/* The processor for which we should tune should now have been
chosen. */
- if (arm_tune == arm_none)
- abort ();
+ gcc_assert (arm_tune != arm_none);
tune_flags = all_cores[(int)arm_tune].flags;
if (optimize_size)
other command line choices. */
if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
{
- warning ("target CPU does not support interworking" );
- target_flags &= ~ARM_FLAG_INTERWORK;
+ warning (0, "target CPU does not support interworking" );
+ target_flags &= ~MASK_INTERWORK;
}
if (TARGET_THUMB && !(insn_flags & FL_THUMB))
{
- warning ("target CPU does not support THUMB instructions");
- target_flags &= ~ARM_FLAG_THUMB;
+ warning (0, "target CPU does not support THUMB instructions");
+ target_flags &= ~MASK_THUMB;
}
if (TARGET_APCS_FRAME && TARGET_THUMB)
{
- /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
- target_flags &= ~ARM_FLAG_APCS_FRAME;
+ /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
+ target_flags &= ~MASK_APCS_FRAME;
}
/* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
from here where no function is being compiled currently. */
- if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
- && TARGET_ARM)
- warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
+ if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
+ warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
- warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
+ warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
- warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
+ warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
{
- warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
- target_flags |= ARM_FLAG_APCS_FRAME;
+ warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
+ target_flags |= MASK_APCS_FRAME;
}
if (TARGET_POKE_FUNCTION_NAME)
- target_flags |= ARM_FLAG_APCS_FRAME;
+ target_flags |= MASK_APCS_FRAME;
if (TARGET_APCS_REENT && flag_pic)
error ("-fpic and -mapcs-reent are incompatible");
if (TARGET_APCS_REENT)
- warning ("APCS reentrant code not supported. Ignored");
+ warning (0, "APCS reentrant code not supported. Ignored");
/* If this target is normally configured to use APCS frames, warn if they
are turned off and debugging is turned on. */
if (TARGET_ARM
&& write_symbols != NO_DEBUG
&& !TARGET_APCS_FRAME
- && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
- warning ("-g with -mno-apcs-frame may not give sensible debugging");
+ && (TARGET_DEFAULT & MASK_APCS_FRAME))
+ warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
/* If stack checking is disabled, we can use r10 as the PIC register,
which keeps r9 available. */
arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
if (TARGET_APCS_FLOAT)
- warning ("passing floating point arguments in fp regs not yet supported");
+ warning (0, "passing floating point arguments in fp regs not yet supported");
/* Initialize boolean versions of the flags, for use in the arm.md file. */
arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
arm_cpp_interwork = 1;
if (arm_arch5)
- target_flags &= ~ARM_FLAG_INTERWORK;
+ target_flags &= ~MASK_INTERWORK;
if (target_abi_name)
{
else
arm_fpu_tune = arm_fpu_arch;
arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
- if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
- abort ();
+ gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
}
if (target_float_abi_name != NULL)
error ("invalid floating point abi: -mfloat-abi=%s",
target_float_abi_name);
}
- else if (target_float_switch)
- {
- /* This is a bit of a hack to avoid needing target flags for these. */
- if (target_float_switch[0] == 'h')
- arm_float_abi = ARM_FLOAT_ABI_HARD;
- else
- arm_float_abi = ARM_FLOAT_ABI_SOFT;
- }
else
arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
|| (ARM_DOUBLEWORD_ALIGN && size == 64))
arm_structure_size_boundary = size;
else
- warning ("structure size boundary can only be set to %s",
+ warning (0, "structure size boundary can only be set to %s",
ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
}
int pic_register = decode_reg_name (arm_pic_register_string);
if (!flag_pic)
- warning ("-mpic-register= is useless without -fpic");
+ warning (0, "-mpic-register= is useless without -fpic");
/* Prevent the user from choosing an obviously stupid PIC register. */
else if (pic_register < 0 || call_used_regs[pic_register]
tree a;
tree attr;
- if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
- abort ();
+ gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
/* Decide if the current function is volatile. Such functions
never return, and many memory cycles can be saved by not storing
argument ... */
if (sibling)
{
- if (GET_CODE (sibling) != CALL_INSN)
- abort ();
+ gcc_assert (GET_CODE (sibling) == CALL_INSN);
if (find_regno_fusage (sibling, USE, 3))
return 0;
int
const_ok_for_arm (HOST_WIDE_INT i)
{
- unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
-
+ int lowbit;
+
/* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
be all zero, or all one. */
if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
& ~(unsigned HOST_WIDE_INT) 0xffffffff)))
return FALSE;
- /* Fast return for 0 and powers of 2 */
- if ((i & (i - 1)) == 0)
+ i &= (unsigned HOST_WIDE_INT) 0xffffffff;
+
+ /* Fast return for 0 and small values. We must do this for zero, since
+ the code below can't handle that one case. */
+ if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
return TRUE;
- do
- {
- if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
- return TRUE;
- mask =
- (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
- >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
- }
- while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
+ /* Get the number of trailing zeros, rounded down to the nearest even
+ number. */
+ lowbit = (ffs ((int) i) - 1) & ~1;
+
+ if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
+ return TRUE;
+ else if (lowbit <= 4
+ && ((i & ~0xc000003f) == 0
+ || (i & ~0xf000000f) == 0
+ || (i & ~0xfc000003) == 0))
+ return TRUE;
return FALSE;
}
return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
default:
- abort ();
+ gcc_unreachable ();
}
}
gen_rtx_SET (VOIDmode, target, source));
return 1;
}
- if (remainder == 0xffffffff)
- {
- if (generate)
- emit_constant_insn (cond,
- gen_rtx_SET (VOIDmode, target,
- gen_rtx_NOT (mode, source)));
- return 1;
- }
-
- /* We don't know how to handle this yet below. */
- abort ();
+
+ /* We don't know how to handle other cases yet. */
+ gcc_assert (remainder == 0xffffffff);
+
+ if (generate)
+ emit_constant_insn (cond,
+ gen_rtx_SET (VOIDmode, target,
+ gen_rtx_NOT (mode, source)));
+ return 1;
case MINUS:
/* We treat MINUS as (val - source), since (source - val) is always
break;
default:
- abort ();
+ gcc_unreachable ();
}
/* If we can do it in one insn get out quickly. */
}
}
+ /* See if we can calculate the value as the difference between two
+ valid immediates. */
+ if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
+ {
+ int topshift = clear_sign_bit_copies & ~1;
+
+ temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
+ & (0xff000000 >> topshift));
+
+ /* If temp1 is zero, then that means the 9 most significant
+ bits of remainder were 1 and we've caused it to overflow.
+ When topshift is 0 we don't need to do anything since we
+ can borrow from 'bit 32'. */
+ if (temp1 == 0 && topshift != 0)
+ temp1 = 0x80000000 >> (topshift - 1);
+
+ temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
+
+ if (const_ok_for_arm (temp2))
+ {
+ if (generate)
+ {
+ rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
+ emit_constant_insn (cond,
+ gen_rtx_SET (VOIDmode, new_src,
+ GEN_INT (temp1)));
+ emit_constant_insn (cond,
+ gen_addsi3 (target, new_src,
+ GEN_INT (-temp2)));
+ }
+
+ return 2;
+ }
+ }
+
/* See if we can generate this by setting the bottom (or the top)
16 bits, and then shifting these into the other half of the
word. We only look for the simplest cases, to do more would cost
break;
default:
- abort ();
+ gcc_unreachable ();
}
return code;
int unsignedp ATTRIBUTE_UNUSED;
rtx r ATTRIBUTE_UNUSED;
-
mode = TYPE_MODE (type);
/* Promote integer types. */
if (INTEGRAL_TYPE_P (type))
PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
+
+ /* Promotes small structs returned in a register to full-word size
+ for big-endian AAPCS. */
+ if (arm_return_in_msb (type))
+ {
+ HOST_WIDE_INT size = int_size_in_bytes (type);
+ if (size % UNITS_PER_WORD != 0)
+ {
+ size += UNITS_PER_WORD - size % UNITS_PER_WORD;
+ mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
+ }
+ }
+
return LIBCALL_VALUE(mode);
}
HOST_WIDE_INT size;
if (!AGGREGATE_TYPE_P (type) &&
+ (TREE_CODE (type) != VECTOR_TYPE) &&
!(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
/* All simple types are returned in registers.
For AAPCS, complex types are treated the same as aggregates. */
return (size < 0 || size > UNITS_PER_WORD);
}
+ /* To maximize backwards compatibility with previous versions of gcc,
+ return vectors up to 4 words in registers. */
+ if (TREE_CODE (type) == VECTOR_TYPE)
+ return (size < 0 || size > (4 * UNITS_PER_WORD));
+
/* For the arm-wince targets we choose to be compatible with Microsoft's
ARM and Thumb compilers, which always return aggregates in memory. */
#ifndef ARM_WINCE
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
- warning ("%qs attribute only applies to functions",
+ warning (0, "%qs attribute only applies to functions",
IDENTIFIER_POINTER (name));
*no_add_attrs = true;
}
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
- warning ("%qs attribute only applies to functions",
+ warning (0, "%qs attribute only applies to functions",
IDENTIFIER_POINTER (name));
*no_add_attrs = true;
}
{
if (arm_isr_value (args) == ARM_FT_UNKNOWN)
{
- warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
+ warning (0, "%qs attribute ignored", IDENTIFIER_POINTER (name));
*no_add_attrs = true;
}
}
}
else
{
- warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
+ warning (0, "%qs attribute ignored", IDENTIFIER_POINTER (name));
}
}
}
if (reg == 0)
{
- if (no_new_pseudos)
- abort ();
- else
- reg = gen_reg_rtx (Pmode);
+ gcc_assert (!no_new_pseudos);
+ reg = gen_reg_rtx (Pmode);
subregs = 1;
}
if (reg == 0)
{
- if (no_new_pseudos)
- abort ();
- else
- reg = gen_reg_rtx (Pmode);
+ gcc_assert (!no_new_pseudos);
+ reg = gen_reg_rtx (Pmode);
}
- if (GET_CODE (XEXP (orig, 0)) == PLUS)
- {
- base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
- offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
- base == reg ? 0 : reg);
- }
- else
- abort ();
+ gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
+
+ base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
+ offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
+ base == reg ? 0 : reg);
if (GET_CODE (offset) == CONST_INT)
{
test the index for the appropriate mode. */
if (!arm_legitimate_index_p (mode, offset, SET, 0))
{
- if (!no_new_pseudos)
- offset = force_reg (Pmode, offset);
- else
- abort ();
+ gcc_assert (!no_new_pseudos);
+ offset = force_reg (Pmode, offset);
}
if (GET_CODE (offset) == CONST_INT)
/* Something went wrong - thumb_compute_save_reg_mask()
should have arranged for a suitable register to be pushed. */
- abort ();
+ gcc_unreachable ();
}
if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
return;
- if (!flag_pic)
- abort ();
+ gcc_assert (flag_pic);
l1 = gen_label_rtx ();
case MULT:
/* This should have been handled by the CPU specific routines. */
- abort ();
+ gcc_unreachable ();
case TRUNCATE:
if (arm_arch3m && mode == SImode
return 1;
default:
- break;
+ gcc_unreachable ();
}
- abort ();
+ gcc_unreachable ();
case CONST_INT:
if (const_ok_for_arm (INTVAL (x)))
return GENERAL_REGS;
}
+/* Values which must be returned in the most-significant end of the return
+ register. */
+
+static bool
+arm_return_in_msb (tree valtype)
+{
+ return (TARGET_AAPCS_BASED
+ && BYTES_BIG_ENDIAN
+ && (AGGREGATE_TYPE_P (valtype)
+ || TREE_CODE (valtype) == COMPLEX_TYPE));
+}
/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
Use by the Cirrus Maverick code which has to workaround
{
enum attr_cirrus attr;
- /* get_attr aborts on USE and CLOBBER. */
+ /* get_attr cannot accept USE or CLOBBER. */
if (!insn
|| GET_CODE (insn) != INSN
|| GET_CODE (PATTERN (insn)) == USE
/* Get Arm register number for ldr insn. */
if (GET_CODE (lhs) == REG)
arm_regno = REGNO (lhs);
- else if (GET_CODE (rhs) == REG)
- arm_regno = REGNO (rhs);
else
- abort ();
+ {
+ gcc_assert (GET_CODE (rhs) == REG);
+ arm_regno = REGNO (rhs);
+ }
/* Next insn. */
first = next_nonnote_insn (first);
}
}
- /* get_attr aborts on USE and CLOBBER. */
+ /* get_attr cannot accept USE or CLOBBER. */
if (!first
|| GET_CODE (first) != INSN
|| GET_CODE (PATTERN (first)) == USE
{
enum rtx_code code = GET_CODE (x);
- if (code == SMAX)
- return GE;
- else if (code == SMIN)
- return LE;
- else if (code == UMIN)
- return LEU;
- else if (code == UMAX)
- return GEU;
-
- abort ();
+ switch (code)
+ {
+ case SMAX:
+ return GE;
+ case SMIN:
+ return LE;
+ case UMIN:
+ return LEU;
+ case UMAX:
+ return GEU;
+ default:
+ gcc_unreachable ();
+ }
}
/* Return 1 if memory locations are adjacent. */
/* Can only handle 2, 3, or 4 insns at present,
though could be easily extended if required. */
- if (nops < 2 || nops > 4)
- abort ();
+ gcc_assert (nops >= 2 && nops <= 4);
/* Loop over the operands and check that the memory references are
suitable (i.e. immediate offsets from the same base register). At
if (GET_CODE (operands[nops + i]) == SUBREG)
operands[nops + i] = alter_subreg (operands + (nops + i));
- if (GET_CODE (operands[nops + i]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[nops + i]) == MEM);
/* Don't reorder volatile memory references; it doesn't seem worth
looking for the case where the order is ok anyway. */
break;
default:
- abort ();
+ gcc_unreachable ();
}
sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
/* Can only handle 2, 3, or 4 insns at present, though could be easily
extended if required. */
- if (nops < 2 || nops > 4)
- abort ();
+ gcc_assert (nops >= 2 && nops <= 4);
/* Loop over the operands and check that the memory references are
suitable (i.e. immediate offsets from the same base register). At
if (GET_CODE (operands[nops + i]) == SUBREG)
operands[nops + i] = alter_subreg (operands + (nops + i));
- if (GET_CODE (operands[nops + i]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[nops + i]) == MEM);
/* Don't reorder volatile memory references; it doesn't seem worth
looking for the case where the order is ok anyway. */
break;
default:
- abort ();
+ gcc_unreachable ();
}
sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
emit_move_insn (mem, sreg);
in_words_to_go--;
- if (in_words_to_go) /* Sanity check */
- abort ();
+ gcc_assert (!in_words_to_go); /* Sanity check */
}
if (in_words_to_go)
{
- if (in_words_to_go < 0)
- abort ();
+ gcc_assert (in_words_to_go > 0);
mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
part_bytes_reg = copy_to_mode_reg (SImode, mem);
}
- if (last_bytes && part_bytes_reg == NULL)
- abort ();
+ gcc_assert (!last_bytes || part_bytes_reg);
if (BYTES_BIG_ENDIAN && last_bytes)
{
switch (cond1)
{
case EQ:
- if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
+ if (cond_or == DOM_CC_X_AND_Y)
return CC_DEQmode;
switch (cond2)
{
+ case EQ: return CC_DEQmode;
case LE: return CC_DLEmode;
case LEU: return CC_DLEUmode;
case GE: return CC_DGEmode;
case GEU: return CC_DGEUmode;
- default: break;
+ default: gcc_unreachable ();
}
- break;
-
case LT:
- if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
+ if (cond_or == DOM_CC_X_AND_Y)
return CC_DLTmode;
- if (cond2 == LE)
- return CC_DLEmode;
- if (cond2 == NE)
- return CC_DNEmode;
- break;
+
+ switch (cond2)
+ {
+ case LT:
+ return CC_DLTmode;
+ case LE:
+ return CC_DLEmode;
+ case NE:
+ return CC_DNEmode;
+ default:
+ gcc_unreachable ();
+ }
case GT:
- if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
+ if (cond_or == DOM_CC_X_AND_Y)
return CC_DGTmode;
- if (cond2 == GE)
- return CC_DGEmode;
- if (cond2 == NE)
- return CC_DNEmode;
- break;
+
+ switch (cond2)
+ {
+ case GT:
+ return CC_DGTmode;
+ case GE:
+ return CC_DGEmode;
+ case NE:
+ return CC_DNEmode;
+ default:
+ gcc_unreachable ();
+ }
case LTU:
- if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
+ if (cond_or == DOM_CC_X_AND_Y)
return CC_DLTUmode;
- if (cond2 == LEU)
- return CC_DLEUmode;
- if (cond2 == NE)
- return CC_DNEmode;
- break;
+
+ switch (cond2)
+ {
+ case LTU:
+ return CC_DLTUmode;
+ case LEU:
+ return CC_DLEUmode;
+ case NE:
+ return CC_DNEmode;
+ default:
+ gcc_unreachable ();
+ }
case GTU:
- if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
+ if (cond_or == DOM_CC_X_AND_Y)
return CC_DGTUmode;
- if (cond2 == GEU)
- return CC_DGEUmode;
- if (cond2 == NE)
- return CC_DNEmode;
- break;
+
+ switch (cond2)
+ {
+ case GTU:
+ return CC_DGTUmode;
+ case GEU:
+ return CC_DGEUmode;
+ case NE:
+ return CC_DNEmode;
+ default:
+ gcc_unreachable ();
+ }
/* The remaining cases only occur when both comparisons are the
same. */
case NE:
+ gcc_assert (cond1 == cond2);
return CC_DNEmode;
case LE:
+ gcc_assert (cond1 == cond2);
return CC_DLEmode;
case GE:
+ gcc_assert (cond1 == cond2);
return CC_DGEmode;
case LEU:
+ gcc_assert (cond1 == cond2);
return CC_DLEUmode;
case GEU:
+ gcc_assert (cond1 == cond2);
return CC_DGEUmode;
default:
- break;
+ gcc_unreachable ();
}
-
- abort ();
}
enum machine_mode
return CCFPEmode;
default:
- abort ();
+ gcc_unreachable ();
}
}
^ (HOST_WIDE_INT) 0x80000000)
- (HOST_WIDE_INT) 0x80000000);
- if (hi + lo != offset)
- abort ();
+ gcc_assert (hi + lo == offset);
if (hi != 0)
{
^ (HOST_WIDE_INT) 0x80000000)
- (HOST_WIDE_INT) 0x80000000);
- if (hi + lo != offset)
- abort ();
+ gcc_assert (hi + lo == offset);
if (hi != 0)
{
gen_lowpart (QImode, scratch)));
}
}
+
+/* Return true if a type must be passed in memory. For AAPCS, small aggregates
+ (padded to the size of a word) should be passed in a register. */
+
+static bool
+arm_must_pass_in_stack (enum machine_mode mode, tree type)
+{
+ if (TARGET_AAPCS_BASED)
+ return must_pass_in_stack_var_size (mode, type);
+ else
+ return must_pass_in_stack_var_size_or_pad (mode, type);
+}
+
+
+/* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
+ Return true if an argument passed on the stack should be padded upwards,
+ i.e. if the least-significant byte has useful data. */
+
+bool
+arm_pad_arg_upward (enum machine_mode mode, tree type)
+{
+ if (!TARGET_AAPCS_BASED)
+ return DEFAULT_FUNCTION_ARG_PADDING(mode, type);
+
+ if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
+ return false;
+
+ return true;
+}
+
+
+/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
+ For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
+ byte of the register has useful data, and return the opposite if the
+ most significant byte does.
+ For AAPCS, small aggregates and small complex types are always padded
+ upwards. */
+
+bool
+arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
+ tree type, int first ATTRIBUTE_UNUSED)
+{
+ if (TARGET_AAPCS_BASED
+ && BYTES_BIG_ENDIAN
+ && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
+ && int_size_in_bytes (type) <= 4)
+ return true;
+
+ /* Otherwise, use default padding. */
+ return !BYTES_BIG_ENDIAN;
+}
+
+
\f
/* Print a symbolic form of X to the debug file, F. */
static void
move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
HOST_WIDE_INT max_address)
{
- /* This should never be true and the code below assumes these are
- different. */
- if (mp == max_mp)
- abort ();
+ /* The code below assumes these are different. */
+ gcc_assert (mp != max_mp);
if (max_mp == NULL)
{
{
HOST_WIDE_INT offset;
- /* This should never be true, and the code below assumes these are
- different. */
- if (mp == min_mp)
- abort ();
+ /* The code below assumes these are different. */
+ gcc_assert (mp != min_mp);
if (min_mp == NULL)
{
#endif
default:
- abort ();
- break;
+ gcc_unreachable ();
}
}
/* This code shouldn't have been called if there was a natural barrier
within range. */
- if (GET_CODE (from) == BARRIER)
- abort ();
+ gcc_assert (GET_CODE (from) != BARRIER);
/* Count the length of this insn. */
count += get_attr_length (from);
fix->minipool = NULL;
/* If an insn doesn't have a range defined for it, then it isn't
- expecting to be reworked by this code. Better to abort now than
+ expecting to be reworked by this code. Better to stop now than
to generate duff assembly code. */
- if (fix->forwards == 0 && fix->backwards == 0)
- abort ();
+ gcc_assert (fix->forwards || fix->backwards);
/* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
So there might be an empty word before the start of the pool.
/* The first insn must always be a note, or the code below won't
scan it properly. */
insn = get_insns ();
- if (GET_CODE (insn) != NOTE)
- abort ();
+ gcc_assert (GET_CODE (insn) == NOTE);
/* Scan all the insns and record the operands that will need fixing. */
for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
/* The last item on the list of fixes must be a barrier, so
we can never run off the end of the list of fixes without
last_barrier being set. */
- if (ftmp == NULL)
- abort ();
+ gcc_assert (ftmp);
max_address = minipool_vector_head->max_address;
/* Check that there isn't another fix that is in range that
if (REAL_VALUES_EQUAL (r, values_fp[i]))
return strings_fp[i];
- abort ();
+ gcc_unreachable ();
}
/* As for fp_immediate_constant, but value is passed directly, not in rtx. */
if (REAL_VALUES_EQUAL (*r, values_fp[i]))
return strings_fp[i];
- abort ();
+ gcc_unreachable ();
}
/* Output the operands of a LDM/STM instruction to STREAM.
strcpy (pattern, "fstmfdx\t%m0!, {%P1");
p = strlen (pattern);
- if (GET_CODE (operands[1]) != REG)
- abort ();
+ gcc_assert (GET_CODE (operands[1]) == REG);
base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
for (i = 1; i < XVECLEN (operands[2], 0); i++)
const char *
output_call (rtx *operands)
{
- if (arm_arch5)
- abort (); /* Patterns should call blx <reg> directly. */
+ gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
/* Handle calls to lr using ip (which may be clobbered in subr anyway). */
if (REGNO (operands[0]) == LR_REGNUM)
int arm_reg0 = REGNO (operands[1]);
rtx ops[3];
- if (arm_reg0 == IP_REGNUM)
- abort ();
+ gcc_assert (arm_reg0 != IP_REGNUM);
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
int arm_reg0 = REGNO (operands[0]);
rtx ops[3];
- if (arm_reg0 == IP_REGNUM)
- abort ();
+ gcc_assert (arm_reg0 != IP_REGNUM);
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
int arm_reg0 = REGNO (operands[1]);
rtx ops[2];
- if (arm_reg0 == IP_REGNUM)
- abort ();
+ gcc_assert (arm_reg0 != IP_REGNUM);
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
int arm_reg0 = REGNO (operands[0]);
rtx ops[2];
- if (arm_reg0 == IP_REGNUM)
- abort ();
+ gcc_assert (arm_reg0 != IP_REGNUM);
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
- if (code1 == MEM)
+ gcc_assert (code1 == MEM); /* Constraints should ensure this. */
+
+ switch (GET_CODE (XEXP (operands[1], 0)))
{
- switch (GET_CODE (XEXP (operands[1], 0)))
+ case REG:
+ output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
+ break;
+
+ case PRE_INC:
+ gcc_assert (TARGET_LDRD);
+ output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
+ break;
+
+ case PRE_DEC:
+ output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
+ break;
+
+ case POST_INC:
+ output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
+ break;
+
+ case POST_DEC:
+ gcc_assert (TARGET_LDRD);
+ output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
+ break;
+
+ case PRE_MODIFY:
+ case POST_MODIFY:
+ otherops[0] = operands[0];
+ otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
+ otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
+
+ if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
{
- case REG:
- output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
- break;
-
- case PRE_INC:
- if (!TARGET_LDRD)
- abort (); /* Should never happen now. */
- output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
- break;
-
- case PRE_DEC:
- output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
- break;
-
- case POST_INC:
- output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
- break;
-
- case POST_DEC:
- if (!TARGET_LDRD)
- abort (); /* Should never happen now. */
- output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
- break;
-
- case PRE_MODIFY:
- case POST_MODIFY:
- otherops[0] = operands[0];
- otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
- otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
-
- if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
+ if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
{
- if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
- {
- /* Registers overlap so split out the increment. */
- output_asm_insn ("add%?\t%1, %1, %2", otherops);
- output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
- }
- else
- output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
+ /* Registers overlap so split out the increment. */
+ output_asm_insn ("add%?\t%1, %1, %2", otherops);
+ output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
}
else
+ output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
+ }
+ else
+ {
+ /* We only allow constant increments, so this is safe. */
+ output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
+ }
+ break;
+
+ case LABEL_REF:
+ case CONST:
+ output_asm_insn ("adr%?\t%0, %1", operands);
+ output_asm_insn ("ldm%?ia\t%0, %M0", operands);
+ break;
+
+ default:
+ if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
+ GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
+ {
+ otherops[0] = operands[0];
+ otherops[1] = XEXP (XEXP (operands[1], 0), 0);
+ otherops[2] = XEXP (XEXP (operands[1], 0), 1);
+
+ if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
{
- /* We only allow constant increments, so this is safe. */
- output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
- }
- break;
-
- case LABEL_REF:
- case CONST:
- output_asm_insn ("adr%?\t%0, %1", operands);
- output_asm_insn ("ldm%?ia\t%0, %M0", operands);
- break;
-
- default:
- if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
- GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
- {
- otherops[0] = operands[0];
- otherops[1] = XEXP (XEXP (operands[1], 0), 0);
- otherops[2] = XEXP (XEXP (operands[1], 0), 1);
-
- if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
+ if (GET_CODE (otherops[2]) == CONST_INT)
{
- if (GET_CODE (otherops[2]) == CONST_INT)
+ switch ((int) INTVAL (otherops[2]))
{
- switch ((int) INTVAL (otherops[2]))
- {
- case -8:
- output_asm_insn ("ldm%?db\t%1, %M0", otherops);
- return "";
- case -4:
- output_asm_insn ("ldm%?da\t%1, %M0", otherops);
- return "";
- case 4:
- output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
- return "";
- }
+ case -8:
+ output_asm_insn ("ldm%?db\t%1, %M0", otherops);
+ return "";
+ case -4:
+ output_asm_insn ("ldm%?da\t%1, %M0", otherops);
+ return "";
+ case 4:
+ output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
+ return "";
}
- if (TARGET_LDRD
- && (GET_CODE (otherops[2]) == REG
- || (GET_CODE (otherops[2]) == CONST_INT
- && INTVAL (otherops[2]) > -256
- && INTVAL (otherops[2]) < 256)))
+ }
+ if (TARGET_LDRD
+ && (GET_CODE (otherops[2]) == REG
+ || (GET_CODE (otherops[2]) == CONST_INT
+ && INTVAL (otherops[2]) > -256
+ && INTVAL (otherops[2]) < 256)))
+ {
+ if (reg_overlap_mentioned_p (otherops[0],
+ otherops[2]))
{
- if (reg_overlap_mentioned_p (otherops[0],
- otherops[2]))
- {
- /* Swap base and index registers over to
- avoid a conflict. */
- otherops[1] = XEXP (XEXP (operands[1], 0), 1);
- otherops[2] = XEXP (XEXP (operands[1], 0), 0);
-
- }
- /* If both registers conflict, it will usually
- have been fixed by a splitter. */
- if (reg_overlap_mentioned_p (otherops[0],
- otherops[2]))
- {
- output_asm_insn ("add%?\t%1, %1, %2", otherops);
- output_asm_insn ("ldr%?d\t%0, [%1]",
- otherops);
- return "";
- }
- else
- {
- output_asm_insn ("ldr%?d\t%0, [%1, %2]",
- otherops);
- return "";
- }
+ /* Swap base and index registers over to
+ avoid a conflict. */
+ otherops[1] = XEXP (XEXP (operands[1], 0), 1);
+ otherops[2] = XEXP (XEXP (operands[1], 0), 0);
+
}
- if (GET_CODE (otherops[2]) == CONST_INT)
+ /* If both registers conflict, it will usually
+ have been fixed by a splitter. */
+ if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
{
- if (!(const_ok_for_arm (INTVAL (otherops[2]))))
- output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
- else
- output_asm_insn ("add%?\t%0, %1, %2", otherops);
+ output_asm_insn ("add%?\t%1, %1, %2", otherops);
+ output_asm_insn ("ldr%?d\t%0, [%1]",
+ otherops);
}
else
- output_asm_insn ("add%?\t%0, %1, %2", otherops);
+ output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
+ return "";
}
- else
- output_asm_insn ("sub%?\t%0, %1, %2", otherops);
-
- return "ldm%?ia\t%0, %M0";
- }
- else
- {
- otherops[1] = adjust_address (operands[1], SImode, 4);
- /* Take care of overlapping base/data reg. */
- if (reg_mentioned_p (operands[0], operands[1]))
+
+ if (GET_CODE (otherops[2]) == CONST_INT)
{
- output_asm_insn ("ldr%?\t%0, %1", otherops);
- output_asm_insn ("ldr%?\t%0, %1", operands);
+ if (!(const_ok_for_arm (INTVAL (otherops[2]))))
+ output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
+ else
+ output_asm_insn ("add%?\t%0, %1, %2", otherops);
}
else
- {
- output_asm_insn ("ldr%?\t%0, %1", operands);
- output_asm_insn ("ldr%?\t%0, %1", otherops);
- }
+ output_asm_insn ("add%?\t%0, %1, %2", otherops);
+ }
+ else
+ output_asm_insn ("sub%?\t%0, %1, %2", otherops);
+
+ return "ldm%?ia\t%0, %M0";
+ }
+ else
+ {
+ otherops[1] = adjust_address (operands[1], SImode, 4);
+ /* Take care of overlapping base/data reg. */
+ if (reg_mentioned_p (operands[0], operands[1]))
+ {
+ output_asm_insn ("ldr%?\t%0, %1", otherops);
+ output_asm_insn ("ldr%?\t%0, %1", operands);
+ }
+ else
+ {
+ output_asm_insn ("ldr%?\t%0, %1", operands);
+ output_asm_insn ("ldr%?\t%0, %1", otherops);
}
}
}
- else
- abort (); /* Constraints should prevent this. */
}
- else if (code0 == MEM && code1 == REG)
+ else
{
- if (REGNO (operands[1]) == IP_REGNUM)
- abort ();
+ /* Constraints should ensure this. */
+ gcc_assert (code0 == MEM && code1 == REG);
+ gcc_assert (REGNO (operands[1]) != IP_REGNUM);
switch (GET_CODE (XEXP (operands[0], 0)))
{
break;
case PRE_INC:
- if (!TARGET_LDRD)
- abort (); /* Should never happen now. */
+ gcc_assert (TARGET_LDRD);
output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
break;
break;
case POST_DEC:
- if (!TARGET_LDRD)
- abort (); /* Should never happen now. */
+ gcc_assert (TARGET_LDRD);
output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
break;
output_asm_insn ("str%?\t%1, %0", otherops);
}
}
- else
- /* Constraints should prevent this. */
- abort ();
return "";
}
return "and";
default:
- abort ();
+ gcc_unreachable ();
}
}
const char * mnem;
enum rtx_code code = GET_CODE (op);
- if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
- *amountp = -1;
- else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
- *amountp = INTVAL (XEXP (op, 1));
- else
- abort ();
+ switch (GET_CODE (XEXP (op, 1)))
+ {
+ case REG:
+ case SUBREG:
+ *amountp = -1;
+ break;
+
+ case CONST_INT:
+ *amountp = INTVAL (XEXP (op, 1));
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
switch (code)
{
break;
case ROTATE:
- if (*amountp == -1)
- abort ();
+ gcc_assert (*amountp != -1);
*amountp = 32 - *amountp;
/* Fall through. */
case MULT:
/* We never have to worry about the amount being other than a
power of 2, since this case can never be reloaded from a reg. */
- if (*amountp != -1)
- *amountp = int_log2 (*amountp);
- else
- abort ();
+ gcc_assert (*amountp != -1);
+ *amountp = int_log2 (*amountp);
return "asl";
default:
- abort ();
+ gcc_unreachable ();
}
if (*amountp != -1)
while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
{
- if (shift > 31)
- abort ();
+ gcc_assert (shift <= 31);
shift++;
}
return "";
}
- if (current_function_calls_alloca && !really_return)
- abort ();
+ gcc_assert (!current_function_calls_alloca || really_return);
sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
live_regs_mask |= (1 << SP_REGNUM);
}
else
- {
- if (! IS_INTERRUPT (func_type)
- && ! TARGET_REALLY_IWMMXT)
- abort ();
- }
+ gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
}
/* On some ARM architectures it is faster to use LDR rather than
offsets = arm_get_frame_offsets ();
stack_adjust = offsets->outgoing_args - offsets->saved_regs;
- if (stack_adjust != 0 && stack_adjust != 4)
- abort ();
+ gcc_assert (stack_adjust == 0 || stack_adjust == 4);
if (stack_adjust && arm_arch5)
sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
}
/* Sanity check. */
- if (arm_ccfsm_state || arm_target_insn)
- abort ();
+ gcc_assert (!arm_ccfsm_state && !arm_target_insn);
func_type = arm_current_func_type ();
return "";
}
- if (current_function_calls_eh_return
- && ! really_return)
- /* If we are throwing an exception, then we really must
- be doing a return, so we can't tail-call. */
- abort ();
+ /* If we are throwing an exception, then we really must be doing a
+ return, so we can't tail-call. */
+ gcc_assert (!current_function_calls_eh_return || really_return);
offsets = arm_get_frame_offsets ();
saved_regs_mask = arm_compute_save_reg_mask ();
frame generation actually contains the old stack pointer. So a
quick way to unwind the stack is just pop the IP register directly
into the stack pointer. */
- if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
- abort ();
+ gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
saved_regs_mask &= ~ (1 << IP_REGNUM);
saved_regs_mask |= (1 << SP_REGNUM);
/* We need to take into account any stack-frame rounding. */
offsets = arm_get_frame_offsets ();
- if (use_return_insn (FALSE, NULL)
- && return_used_this_function
- && offsets->saved_regs != offsets->outgoing_args
- && !frame_pointer_needed)
- abort ();
+ gcc_assert (!use_return_insn (FALSE, NULL)
+ || !return_used_this_function
+ || offsets->saved_regs == offsets->outgoing_args
+ || frame_pointer_needed);
/* Reset the ARM-specific per-function variables. */
after_arm_reorg = 0;
if (mask & (1 << i))
num_regs++;
- if (num_regs == 0 || num_regs > 16)
- abort ();
+ gcc_assert (num_regs && num_regs <= 16);
/* We don't record the PC in the dwarf frame information. */
num_dwarf_regs = num_regs;
/* Ensure SP remains doubleword aligned. */
if (offsets->outgoing_args & 7)
offsets->outgoing_args += 4;
- if (offsets->outgoing_args & 7)
- abort ();
+ gcc_assert (!(offsets->outgoing_args & 7));
}
return offsets;
return offsets->outgoing_args - (offsets->saved_args + 4);
default:
- abort ();
+ gcc_unreachable ();
}
- break;
+ gcc_unreachable ();
case FRAME_POINTER_REGNUM:
switch (to)
return offsets->outgoing_args - offsets->soft_frame;
default:
- abort ();
+ gcc_unreachable ();
}
- break;
+ gcc_unreachable ();
default:
/* You cannot eliminate from the stack pointer.
pointer to the stack pointer, but this will never
happen, since if a stack frame is not needed the
hard frame pointer will never be used. */
- abort ();
+ gcc_unreachable ();
}
}
stack decrement per function, and this is not it. If
this instruction is labeled as being part of the frame
creation sequence then dwarf2out_frame_debug_expr will
- abort when it encounters the assignment of IP to FP
+ die when it encounters the assignment of IP to FP
later on, since the use of SP here establishes SP as
the CFA register and not IP.
/* If we are profiling, make sure no instructions are scheduled before
the call to mcount. Similarly if the user has requested no
scheduling in the prolog. */
- if (current_function_profile || TARGET_NO_SCHED_PRO)
+ if (current_function_profile || !TARGET_SCHED_PROLOG)
emit_insn (gen_blockage ());
/* If the link register is being kept alive, with the return address in it,
case 'X': /* Cirrus register in D mode. */
case 'Y': /* Cirrus register in FX mode. */
case 'Z': /* Cirrus register in DX mode. */
- if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
- abort ();
+ gcc_assert (GET_CODE (x) == REG
+ && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
fprintf (stream, "mv%s%s",
code == 'W' ? "f"
return;
}
- if (GET_CODE (x) == REG)
- asm_fprintf (stream, "%r", REGNO (x));
- else if (GET_CODE (x) == MEM)
+ switch (GET_CODE (x))
{
+ case REG:
+ asm_fprintf (stream, "%r", REGNO (x));
+ break;
+
+ case MEM:
output_memory_reference_mode = GET_MODE (x);
output_address (XEXP (x, 0));
- }
- else if (GET_CODE (x) == CONST_DOUBLE)
- fprintf (stream, "#%s", fp_immediate_constant (x));
- else if (GET_CODE (x) == NEG)
- abort (); /* This should never happen now. */
- else
- {
+ break;
+
+ case CONST_DOUBLE:
+ fprintf (stream, "#%s", fp_immediate_constant (x));
+ break;
+
+ default:
+ gcc_assert (GET_CODE (x) != NEG);
fputc ('#', stream);
output_addr_const (stream, x);
+ break;
}
}
}
{
int i, units;
- if (GET_CODE (x) != CONST_VECTOR)
- abort ();
+ gcc_assert (GET_CODE (x) == CONST_VECTOR);
units = CONST_VECTOR_NUNITS (x);
case V4HImode: size = 2; break;
case V8QImode: size = 1; break;
default:
- abort ();
+ gcc_unreachable ();
}
for (i = 0; i < units; i++)
return default_assemble_integer (x, size, aligned_p);
}
+
+
+/* Add a function to the list of static constructors. */
+
+static void
+arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
+{
+ if (!TARGET_AAPCS_BASED)
+ {
+ default_named_section_asm_out_constructor (symbol, priority);
+ return;
+ }
+
+ /* Put these in the .init_array section, using a special relocation. */
+ ctors_section ();
+ assemble_align (POINTER_SIZE);
+ fputs ("\t.word\t", asm_out_file);
+ output_addr_const (asm_out_file, symbol);
+ fputs ("(target1)\n", asm_out_file);
+}
#endif
\f
/* A finite state machine takes care of noticing whether or not instructions
case CC_DLTUmode: code = ARM_CC;
dominance:
- if (comp_code != EQ && comp_code != NE)
- abort ();
+ gcc_assert (comp_code == EQ || comp_code == NE);
if (comp_code == EQ)
return ARM_INVERSE_CONDITION_CODE (code);
case EQ: return ARM_EQ;
case GE: return ARM_PL;
case LT: return ARM_MI;
- default: abort ();
+ default: gcc_unreachable ();
}
case CC_Zmode:
{
case NE: return ARM_NE;
case EQ: return ARM_EQ;
- default: abort ();
+ default: gcc_unreachable ();
}
case CC_Nmode:
{
case NE: return ARM_MI;
case EQ: return ARM_PL;
- default: abort ();
+ default: gcc_unreachable ();
}
case CCFPEmode:
/* UNEQ and LTGT do not have a representation. */
case UNEQ: /* Fall through. */
case LTGT: /* Fall through. */
- default: abort ();
+ default: gcc_unreachable ();
}
case CC_SWPmode:
case GTU: return ARM_CC;
case LEU: return ARM_CS;
case LTU: return ARM_HI;
- default: abort ();
+ default: gcc_unreachable ();
}
case CC_Cmode:
{
case LTU: return ARM_CS;
case GEU: return ARM_CC;
- default: abort ();
+ default: gcc_unreachable ();
}
case CCmode:
case GTU: return ARM_HI;
case LEU: return ARM_LS;
case LTU: return ARM_CC;
- default: abort ();
+ default: gcc_unreachable ();
}
- default: abort ();
+ default: gcc_unreachable ();
}
-
- abort ();
}
void
return;
}
- if (arm_ccfsm_state != 0 && !reverse)
- abort ();
+ gcc_assert (!arm_ccfsm_state || reverse);
if (GET_CODE (insn) != JUMP_INSN)
return;
then_not_else = FALSE;
}
else
- abort ();
+ gcc_unreachable ();
/* See how many insns this branch skips, and what kind of insns. If all
insns are okay, and the label or unconditional branch to the same
{
if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
arm_target_label = CODE_LABEL_NUMBER (label);
- else if (seeking_return || arm_ccfsm_state == 2)
+ else
{
+ gcc_assert (seeking_return || arm_ccfsm_state == 2);
+
while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
{
this_insn = next_nonnote_insn (this_insn);
- if (this_insn && (GET_CODE (this_insn) == BARRIER
- || GET_CODE (this_insn) == CODE_LABEL))
- abort ();
+ gcc_assert (!this_insn
+ || (GET_CODE (this_insn) != BARRIER
+ && GET_CODE (this_insn) != CODE_LABEL));
}
if (!this_insn)
{
}
arm_target_insn = this_insn;
}
- else
- abort ();
if (jump_clobbers)
{
- if (reverse)
- abort ();
+ gcc_assert (!reverse);
arm_current_cc =
get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
0), 0), 1));
if (value == 0)
{
debug_rtx (addr);
- warning ("unable to compute real location of stacked parameter");
+ warning (0, "unable to compute real location of stacked parameter");
value = 8; /* XXX magic hack */
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
def_mbuiltin (d->mask, d->name, type, d->code);
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
- /* In case the insn wants input operands in modes different from
- the result, abort. */
- if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
- abort ();
+ gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
int lo_mask = mask & 0xFF;
int pushed_words = 0;
- if (mask == 0)
- abort ();
+ gcc_assert (mask);
if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
{
int
is_called_in_ARM_mode (tree func)
{
- if (TREE_CODE (func) != FUNCTION_DECL)
- abort ();
+ gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
- /* Ignore the problem about functions whoes address is taken. */
+ /* Ignore the problem about functions whose address is taken. */
if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
return TRUE;
return offsets->saved_regs - offsets->saved_args;
default:
- abort();
+ gcc_unreachable ();
}
break;
return offsets->saved_regs - offsets->soft_frame;
default:
- abort();
+ gcc_unreachable ();
}
break;
default:
- abort ();
+ gcc_unreachable ();
}
}
hard_frame_pointer_rtx));
}
- if (current_function_profile || TARGET_NO_SCHED_PRO)
+ if (current_function_profile || !TARGET_SCHED_PROLOG)
emit_insn (gen_blockage ());
cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
the stack adjustment will not be deleted. */
emit_insn (gen_prologue_use (stack_pointer_rtx));
- if (current_function_profile || TARGET_NO_SCHED_PRO)
+ if (current_function_profile || !TARGET_SCHED_PROLOG)
emit_insn (gen_blockage ());
/* Emit a clobber for each insn that will be restored in the epilogue,
{
const char * name;
- if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
- abort ();
- if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
- abort ();
+ gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
+ gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
+ == SYMBOL_REF);
name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
/* Generate code sequence to switch us into Thumb mode. */
rtx arg1;
rtx arg2;
- if (GET_CODE (operands[0]) != REG)
- abort ();
-
- if (GET_CODE (operands[1]) != MEM)
- abort ();
+ gcc_assert (GET_CODE (operands[0]) == REG);
+ gcc_assert (GET_CODE (operands[1]) == MEM);
/* Get the memory address. */
addr = XEXP (operands[1], 0);
else
base = arg1, offset = arg2;
- if (GET_CODE (base) != REG)
- abort ();
+ gcc_assert (GET_CODE (base) == REG);
/* Catch the case of <address> = <reg> + <reg> */
if (GET_CODE (offset) == REG)
break;
default:
- abort ();
- break;
+ gcc_unreachable ();
}
return "";
break;
default:
- abort ();
+ gcc_unreachable ();
}
return "";
void
thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
{
- abort ();
+ gcc_unreachable ();
}
/* Return the length of a function name prefix
int i;
const char * pattern;
- if (GET_CODE (x) != CONST_VECTOR)
- abort ();
+ gcc_assert (GET_CODE (x) == CONST_VECTOR);
switch (GET_MODE (x))
{
case V2SImode: pattern = "%08x"; break;
case V4HImode: pattern = "%04x"; break;
case V8QImode: pattern = "%02x"; break;
- default: abort ();
+ default: gcc_unreachable ();
}
fprintf (file, "0x");
return !TARGET_AAPCS_BASED;
}
-/* The EABI says that the virtual table, etc., for a class must be
- exported if it has a key method. The EABI does not specific the
- behavior if there is no key method, but there is no harm in
- exporting the class data in that case too. */
+static void
+arm_cxx_determine_class_data_visibility (tree decl)
+{
+ if (!TARGET_AAPCS_BASED)
+ return;
+
+ /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
+ is exported. However, on systems without dynamic vague linkage,
+ \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
+ if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
+ DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
+ else
+ DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
+ DECL_VISIBILITY_SPECIFIED (decl) = 1;
+}
+
+static bool
+arm_cxx_class_data_always_comdat (void)
+{
+ /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
+ vague linkage if the class has no key function. */
+ return !TARGET_AAPCS_BASED;
+}
+
+
+/* The EABI says __aeabi_atexit should be used to register static
+ destructors. */
static bool
-arm_cxx_export_class_data (void)
+arm_cxx_use_aeabi_atexit (void)
{
return TARGET_AAPCS_BASED;
}
+
void
arm_set_return_address (rtx source, rtx scratch)
{
if (IS_IWMMXT_REGNUM (regno))
return 112 + regno - FIRST_IWMMXT_REGNUM;
- abort ();
+ gcc_unreachable ();
}
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