;; Machine description for DEC Alpha for GNU C compiler
;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-;; 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+;; 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
+;; Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 2, or (at your option)
+;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
(define_constants
[(UNSPEC_ARG_HOME 0)
+ (UNSPEC_LDGP1 1)
(UNSPEC_INSXH 2)
(UNSPEC_MSKXH 3)
(UNSPEC_CVTQL 4)
(UNSPEC_IMPLVER 25)
(UNSPEC_PERR 26)
(UNSPEC_COPYSIGN 27)
+
+ ;; Atomic operations
+ (UNSPEC_MB 28)
+ (UNSPEC_ATOMIC 31)
+ (UNSPEC_CMPXCHG 32)
+ (UNSPEC_XCHG 33)
])
;; UNSPEC_VOLATILE:
(UNSPECV_SET_TP 12)
(UNSPECV_RPCC 13)
(UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
- (UNSPECV_MB 15)
- (UNSPECV_LL 16) ; load-locked
- (UNSPECV_SC 17) ; store-conditional
- (UNSPECV_ATOMIC 18)
- (UNSPECV_CMPXCHG 19)
- (UNSPECV_XCHG 20)
+ (UNSPECV_LL 15) ; load-locked
+ (UNSPECV_SC 16) ; store-conditional
])
+;; On non-BWX targets, CQImode must be handled the similarly to HImode
+;; when generating reloads.
+(define_mode_iterator RELOAD12 [QI HI CQI])
+(define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")])
+
+;; Other mode iterators
+(define_mode_iterator I12MODE [QI HI])
+(define_mode_iterator I48MODE [SI DI])
+(define_mode_attr modesuffix [(SI "l") (DI "q")])
+
;; Where necessary, the suffixes _le and _be are used to distinguish between
;; little-endian and big-endian patterns.
;;
;; enumeration in alpha.h.
(define_attr "tune" "ev4,ev5,ev6"
- (const (symbol_ref "alpha_tune")))
+ (const (symbol_ref "((enum attr_tune) alpha_tune)")))
;; Define an insn type attribute. This is used in function unit delay
;; computations, among other purposes. For the most part, we use the names
(cond [(eq_attr "type" "ldsym,jsr")
(const_string "yes")
(eq_attr "type" "ild,fld,ist,fst")
- (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
+ (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))")
]
(const_string "no")))
(include "ev6.md")
\f
-;; Include predicate definitions
+;; Operand and operator predicates and constraints
(include "predicates.md")
+(include "constraints.md")
\f
;; First define the arithmetic insns. Note that the 32-bit forms also
(sign_extend:DI (match_dup 1)))]
"")
-;; Don't say we have addsi3 if optimizing. This generates better code. We
-;; have the anonymous addsi3 pattern below in case combine wants to make it.
-(define_expand "addsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
- (match_operand:SI 2 "add_operand" "")))]
- "! optimize"
- "")
-
-(define_insn "*addsi_internal"
+(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
(match_operand:SI 2 "add_operand" "rI,O,K,L")))]
&& INTVAL (operands[2])
< (0x7fff8000
- FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
- - ALPHA_ROUND(current_function_outgoing_args_size)
+ - ALPHA_ROUND(crtl->outgoing_args_size)
- (ALPHA_ROUND (get_frame_size ()
+ max_reg_num () * UNITS_PER_WORD
- + current_function_pretend_args_size)
- - current_function_pretend_args_size))"
+ + crtl->args.pretend_args_size)
+ - crtl->args.pretend_args_size))"
"@
lda %0,%2(%1)
ldah %0,%h2(%1)
HOST_WIDE_INT val = INTVAL (operands[2]);
HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
HOST_WIDE_INT rest = val - low;
+ rtx rest_rtx = GEN_INT (rest);
operands[4] = GEN_INT (low);
- if (CONST_OK_FOR_LETTER_P (rest, 'L'))
- operands[3] = GEN_INT (rest);
- else if (! no_new_pseudos)
+ if (satisfies_constraint_L (rest_rtx))
+ operands[3] = rest_rtx;
+ else if (can_create_pseudo_p ())
{
operands[3] = gen_reg_rtx (DImode);
emit_move_insn (operands[3], operands[2]);
""
"subqv $31,%1,%0")
-(define_expand "subsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
- (match_operand:SI 2 "reg_or_8bit_operand" "")))]
- "! optimize"
- "")
-
-(define_insn "*subsi_internal"
+(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
- "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
+ "#"
"&& reload_completed"
[(parallel [(set (match_dup 0)
(sign_extend:DI (match_dup 3)))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
- "jsr $23,($27),__%E3%J5"
+ "jsr $23,($27),__%E3%j5"
[(set_attr "type" "jsr")
(set_attr "length" "4")])
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
- "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
+ "#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (match_dup 3))
(use (match_dup 0))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
- "jsr $23,($27),__%E3%J5"
+ "jsr $23,($27),__%E3%j5"
[(set_attr "type" "jsr")
(set_attr "length" "4")])
"TARGET_CIX"
"ctpop %1,%0"
[(set_attr "type" "mvi")])
+
+(define_expand "bswapsi2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (bswap:SI (match_operand:SI 1 "register_operand" "")))]
+ "!optimize_size"
+{
+ rtx t0, t1;
+
+ t0 = gen_reg_rtx (DImode);
+ t1 = gen_reg_rtx (DImode);
+
+ emit_insn (gen_insxh (t0, gen_lowpart (DImode, operands[1]),
+ GEN_INT (32), GEN_INT (WORDS_BIG_ENDIAN ? 0 : 7)));
+ emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]),
+ GEN_INT (24)));
+ emit_insn (gen_iordi3 (t1, t0, t1));
+ emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
+ emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5)));
+ emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa)));
+ emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0),
+ gen_lowpart (SImode, t1)));
+ DONE;
+})
+
+(define_expand "bswapdi2"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (bswap:DI (match_operand:DI 1 "register_operand" "")))]
+ "!optimize_size"
+{
+ rtx t0, t1;
+
+ t0 = gen_reg_rtx (DImode);
+ t1 = gen_reg_rtx (DImode);
+
+ /* This method of shifting and masking is not specific to Alpha, but
+ is only profitable on Alpha because of our handy byte zap insn. */
+
+ emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32)));
+ emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32)));
+ emit_insn (gen_iordi3 (t1, t0, t1));
+
+ emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16)));
+ emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16)));
+ emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc)));
+ emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33)));
+ emit_insn (gen_iordi3 (t1, t0, t1));
+
+ emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8)));
+ emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8)));
+ emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa)));
+ emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55)));
+ emit_insn (gen_iordi3 (operands[0], t0, t1));
+ DONE;
+})
\f
;; Next come the shifts and the various extract and insert operations.
if (unaligned_memory_operand (operands[1], QImode))
{
- rtx seq
- = gen_unaligned_extendqidi (operands[0],
- get_unaligned_address (operands[1], 1));
-
+ rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
alpha_set_memflags (seq, operands[1]);
emit_insn (seq);
DONE;
if (unaligned_memory_operand (operands[1], HImode))
{
- rtx seq
- = gen_unaligned_extendhidi (operands[0],
- get_unaligned_address (operands[1], 2));
+ rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
alpha_set_memflags (seq, operands[1]);
emit_insn (seq);
;; as a pattern saves one instruction. The code is similar to that for
;; the unaligned loads (see below).
;;
-;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
+;; Operand 1 is the address, operand 0 is the result.
(define_expand "unaligned_extendqidi"
[(use (match_operand:QI 0 "register_operand" ""))
(use (match_operand:DI 1 "address_operand" ""))]
""
{
+ operands[0] = gen_lowpart (DImode, operands[0]);
if (WORDS_BIG_ENDIAN)
emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
else
})
(define_expand "unaligned_extendqidi_le"
- [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
- (set (match_dup 3)
- (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
- (const_int -8))))
+ [(set (match_dup 3)
+ (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
(set (match_dup 4)
(ashift:DI (match_dup 3)
(minus:DI (const_int 64)
(ashift:DI
(and:DI (match_dup 2) (const_int 7))
(const_int 3)))))
- (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
+ (set (match_operand:DI 0 "register_operand" "")
(ashiftrt:DI (match_dup 4) (const_int 56)))]
"! WORDS_BIG_ENDIAN"
{
- operands[2] = gen_reg_rtx (DImode);
+ operands[2] = get_unaligned_offset (operands[1], 1);
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
})
(define_expand "unaligned_extendqidi_be"
- [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
- (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
+ [(set (match_dup 3)
+ (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
(set (match_dup 4)
- (mem:DI (and:DI (match_dup 3)
- (const_int -8))))
- (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
- (set (match_dup 6)
- (ashift:DI (match_dup 4)
+ (ashift:DI (match_dup 3)
(ashift:DI
(and:DI
- (plus:DI (match_dup 5) (const_int 1))
+ (plus:DI (match_dup 2) (const_int 1))
(const_int 7))
(const_int 3))))
- (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
- (ashiftrt:DI (match_dup 6) (const_int 56)))]
+ (set (match_operand:DI 0 "register_operand" "")
+ (ashiftrt:DI (match_dup 4) (const_int 56)))]
"WORDS_BIG_ENDIAN"
{
- operands[2] = gen_reg_rtx (DImode);
+ operands[2] = get_unaligned_offset (operands[1], -1);
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
- operands[5] = gen_reg_rtx (DImode);
- operands[6] = gen_reg_rtx (DImode);
})
(define_expand "unaligned_extendhidi"
""
{
operands[0] = gen_lowpart (DImode, operands[0]);
- emit_insn ((WORDS_BIG_ENDIAN
- ? gen_unaligned_extendhidi_be
- : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
+ if (WORDS_BIG_ENDIAN)
+ emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
+ else
+ emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
DONE;
})
(define_expand "unaligned_extendhidi_le"
- [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
- (set (match_dup 3)
- (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
- (const_int -8))))
+ [(set (match_dup 3)
+ (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
(set (match_dup 4)
(ashift:DI (match_dup 3)
(minus:DI (const_int 64)
(ashiftrt:DI (match_dup 4) (const_int 48)))]
"! WORDS_BIG_ENDIAN"
{
- operands[2] = gen_reg_rtx (DImode);
+ operands[2] = get_unaligned_offset (operands[1], 2);
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
})
(define_expand "unaligned_extendhidi_be"
- [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
- (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
+ [(set (match_dup 3)
+ (mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
(set (match_dup 4)
- (mem:DI (and:DI (match_dup 3)
- (const_int -8))))
- (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
- (set (match_dup 6)
- (ashift:DI (match_dup 4)
+ (ashift:DI (match_dup 3)
(ashift:DI
(and:DI
- (plus:DI (match_dup 5) (const_int 1))
+ (plus:DI (match_dup 2) (const_int 1))
(const_int 7))
(const_int 3))))
(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_dup 6) (const_int 48)))]
+ (ashiftrt:DI (match_dup 4) (const_int 48)))]
"WORDS_BIG_ENDIAN"
{
- operands[2] = gen_reg_rtx (DImode);
+ operands[2] = get_unaligned_offset (operands[1], -1);
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (DImode);
- operands[5] = gen_reg_rtx (DImode);
- operands[6] = gen_reg_rtx (DImode);
})
(define_insn "*extxl_const"
"insbl %1,%s2,%0"
[(set_attr "type" "shift")])
-(define_insn "*inswl_const"
+(define_insn "inswl_const"
[(set (match_operand:DI 0 "register_operand" "=r")
(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
(match_operand:DI 2 "mul8_operand" "I")))]
(match_operand:DI 2 "mul8_operand" "I"))
(match_operand:DI 3 "immediate_operand" "i")))]
"HOST_BITS_PER_WIDE_INT == 64
- && GET_CODE (operands[3]) == CONST_INT
+ && CONST_INT_P (operands[3])
&& (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
|| ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
(match_operator:DF 1 "alpha_fp_comparison_operator"
[(match_operand:DF 2 "reg_or_0_operand" "fG")
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
- "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
-(define_insn "*cmpdf_ieee_ext1"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(float_extend:DF
- (match_operand:SF 2 "reg_or_0_operand" "fG"))
- (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
+ "TARGET_FP"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "trap" "yes")
(set_attr "trap_suffix" "su")])
-(define_insn "*cmpdf_ieee_ext2"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(match_operand:DF 2 "reg_or_0_operand" "fG")
- (float_extend:DF
- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
(define_insn "*cmpdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
(set_attr "trap" "yes")
(set_attr "trap_suffix" "su")])
-(define_insn "*cmpdf_ieee_ext3"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(float_extend:DF
- (match_operand:SF 2 "reg_or_0_operand" "fG"))
- (float_extend:DF
- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
(define_insn "*cmpdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
(match_operand:DF 2 "const0_operand" "G,G")])
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:DF 1 "reg_or_0_operand" "fG,0")
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:SF 1 "reg_or_0_operand" "fG,0")
(match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
{
operands[3] = gen_reg_rtx (DFmode);
operands[4] = CONST0_RTX (DFmode);
(set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
{
operands[3] = gen_reg_rtx (DFmode);
operands[4] = CONST0_RTX (DFmode);
;; These are the main define_expand's used to make conditional branches
;; and compares.
-(define_expand "cmpdf"
- [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
- (match_operand:DF 1 "reg_or_0_operand" "")))]
+(define_expand "cbranchdf4"
+ [(use (match_operator 0 "alpha_cbranch_operator"
+ [(match_operand:DF 1 "reg_or_0_operand" "")
+ (match_operand:DF 2 "reg_or_0_operand" "")]))
+ (use (match_operand 3 ""))]
"TARGET_FP"
-{
- alpha_compare.op0 = operands[0];
- alpha_compare.op1 = operands[1];
- alpha_compare.fp_p = 1;
- DONE;
-})
+ { alpha_emit_conditional_branch (operands, DFmode); DONE; })
-(define_expand "cmptf"
- [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
- (match_operand:TF 1 "general_operand" "")))]
+(define_expand "cbranchtf4"
+ [(use (match_operator 0 "alpha_cbranch_operator"
+ [(match_operand:TF 1 "general_operand")
+ (match_operand:TF 2 "general_operand")]))
+ (use (match_operand 3 ""))]
"TARGET_HAS_XFLOATING_LIBS"
-{
- alpha_compare.op0 = operands[0];
- alpha_compare.op1 = operands[1];
- alpha_compare.fp_p = 1;
- DONE;
-})
+ { alpha_emit_conditional_branch (operands, TFmode); DONE; })
-(define_expand "cmpdi"
- [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
- (match_operand:DI 1 "some_operand" "")))]
+(define_expand "cbranchdi4"
+ [(use (match_operator 0 "alpha_cbranch_operator"
+ [(match_operand:DI 1 "some_operand")
+ (match_operand:DI 2 "some_operand")]))
+ (use (match_operand 3 ""))]
""
-{
- alpha_compare.op0 = operands[0];
- alpha_compare.op1 = operands[1];
- alpha_compare.fp_p = 0;
- DONE;
-})
-
-(define_expand "beq"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
-
-(define_expand "bne"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (NE); }")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (LT); }")
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (LE); }")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (GT); }")
-
-(define_expand "bge"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (GE); }")
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
-
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
-
-(define_expand "bunordered"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
-
-(define_expand "bordered"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
-
-(define_expand "seq"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
+ { alpha_emit_conditional_branch (operands, DImode); DONE; })
-(define_expand "sne"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
-
-(define_expand "slt"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
-
-(define_expand "sle"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
-
-(define_expand "sgt"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
-
-(define_expand "sge"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
-
-(define_expand "sltu"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
-
-(define_expand "sleu"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
-
-(define_expand "sgtu"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
-
-(define_expand "sgeu"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
+(define_expand "cstoredf4"
+ [(use (match_operator:DI 1 "alpha_cbranch_operator"
+ [(match_operand:DF 2 "reg_or_0_operand")
+ (match_operand:DF 3 "reg_or_0_operand")]))
+ (clobber (match_operand:DI 0 "register_operand"))]
+ "TARGET_FP"
+ { if (!alpha_emit_setcc (operands, DFmode)) FAIL; else DONE; })
-(define_expand "sunordered"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
- ""
- "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
+(define_expand "cstoretf4"
+ [(use (match_operator:DI 1 "alpha_cbranch_operator"
+ [(match_operand:TF 2 "general_operand")
+ (match_operand:TF 3 "general_operand")]))
+ (clobber (match_operand:DI 0 "register_operand"))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ { if (!alpha_emit_setcc (operands, TFmode)) FAIL; else DONE; })
-(define_expand "sordered"
- [(set (match_operand:DI 0 "register_operand" "")
- (match_dup 1))]
+(define_expand "cstoredi4"
+ [(use (match_operator:DI 1 "alpha_cbranch_operator"
+ [(match_operand:DI 2 "some_operand")
+ (match_operand:DI 3 "some_operand")]))
+ (clobber (match_operand:DI 0 "register_operand"))]
""
- "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
+ { if (!alpha_emit_setcc (operands, DImode)) FAIL; else DONE; })
\f
;; These are the main define_expand's used to make conditional moves.
register since that is more likely to match (and to produce better code
if both would). */
- if (code == EQ && GET_CODE (operands[3]) == CONST_INT
+ if (code == EQ && CONST_INT_P (operands[3])
&& rtx_equal_p (operands[4], operands[3]))
operands[4] = operands[2];
- else if (code == NE && GET_CODE (operands[3]) == CONST_INT
+ else if (code == NE && CONST_INT_P (operands[3])
&& rtx_equal_p (operands[5], operands[3]))
operands[5] = operands[2];
|| (extended_count (operands[2], DImode, unsignedp) >= 1
&& extended_count (operands[3], DImode, unsignedp) >= 1))
{
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
operands[7] = gen_rtx_PLUS (DImode, operands[2],
GEN_INT (- INTVAL (operands[3])));
else
&& extended_count (operands[3], DImode, unsignedp) >= 1)))
FAIL;
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
tem = gen_rtx_PLUS (SImode, operands[2],
GEN_INT (- INTVAL (operands[3])));
else
(clobber (match_scratch:DI 5 "=r"))]
""
"#"
- "! no_new_pseudos || reload_completed"
+ ""
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
(plus:DI (mult:DI (match_dup 5) (match_dup 3))
(match_dup 4)))]
{
- if (! no_new_pseudos)
+ if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
operands[5] = operands[0];
(match_operand:SI 3 "const48_operand" "I")
(const_int 0))
(match_operand:SI 4 "sext_add_operand" "rIO")))
- (clobber (match_scratch:SI 5 "=r"))]
+ (clobber (match_scratch:DI 5 "=r"))]
""
"#"
- "! no_new_pseudos || reload_completed"
+ ""
[(set (match_dup 5)
- (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
+ (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (plus:SI (mult:SI (match_dup 5) (match_dup 3))
+ (plus:SI (mult:SI (match_dup 6) (match_dup 3))
(match_dup 4)))]
{
- if (! no_new_pseudos)
+ if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
- operands[5] = operands[0];
+ operands[5] = gen_lowpart (DImode, operands[0]);
+
+ operands[6] = gen_lowpart (SImode, operands[5]);
})
(define_insn_and_split "*cmp_sadd_sidi"
(match_operand:SI 3 "const48_operand" "I")
(const_int 0))
(match_operand:SI 4 "sext_add_operand" "rIO"))))
- (clobber (match_scratch:SI 5 "=r"))]
+ (clobber (match_scratch:DI 5 "=r"))]
""
"#"
- "! no_new_pseudos || reload_completed"
+ ""
[(set (match_dup 5)
- (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
+ (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
+ (sign_extend:DI (plus:SI (mult:SI (match_dup 6) (match_dup 3))
(match_dup 4))))]
{
- if (! no_new_pseudos)
+ if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
operands[5] = operands[0];
+
+ operands[6] = gen_lowpart (SImode, operands[5]);
})
(define_insn_and_split "*cmp_ssub_di"
(clobber (match_scratch:DI 5 "=r"))]
""
"#"
- "! no_new_pseudos || reload_completed"
+ ""
[(set (match_dup 5)
(match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
(minus:DI (mult:DI (match_dup 5) (match_dup 3))
(match_dup 4)))]
{
- if (! no_new_pseudos)
+ if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
operands[5] = operands[0];
(match_operand:SI 3 "const48_operand" "I")
(const_int 0))
(match_operand:SI 4 "reg_or_8bit_operand" "rI")))
- (clobber (match_scratch:SI 5 "=r"))]
+ (clobber (match_scratch:DI 5 "=r"))]
""
"#"
- "! no_new_pseudos || reload_completed"
+ ""
[(set (match_dup 5)
- (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
+ (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (minus:SI (mult:SI (match_dup 5) (match_dup 3))
+ (minus:SI (mult:SI (match_dup 6) (match_dup 3))
(match_dup 4)))]
{
- if (! no_new_pseudos)
+ if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
- operands[5] = operands[0];
+ operands[5] = gen_lowpart (DImode, operands[0]);
+
+ operands[6] = gen_lowpart (SImode, operands[5]);
})
(define_insn_and_split "*cmp_ssub_sidi"
(match_operand:SI 3 "const48_operand" "I")
(const_int 0))
(match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
- (clobber (match_scratch:SI 5 "=r"))]
+ (clobber (match_scratch:DI 5 "=r"))]
""
"#"
- "! no_new_pseudos || reload_completed"
+ ""
[(set (match_dup 5)
- (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
+ (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
(set (match_dup 0)
- (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
+ (sign_extend:DI (minus:SI (mult:SI (match_dup 6) (match_dup 3))
(match_dup 4))))]
{
- if (! no_new_pseudos)
+ if (can_create_pseudo_p ())
operands[5] = gen_reg_rtx (DImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
operands[5] = operands[0];
+
+ operands[6] = gen_lowpart (SImode, operands[5]);
})
\f
;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
})
(clobber (reg:DI 26))])]
""
{
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
if (! call_operand (operands[0], Pmode))
(clobber (reg:DI 26))])]
""
{
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
- if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
+ if (GET_CODE (operands[0]) != SYMBOL_REF && !REG_P (operands[0]))
operands[0] = force_reg (DImode, operands[0]);
})
(clobber (reg:DI 26))])]
""
{
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
/* Always load the address of the called function into a register;
load the CIW in $25. */
operands[0] = XEXP (operands[0], 0);
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = force_reg (DImode, operands[0]);
emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
(clobber (reg:DI 27))])]
""
{
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
operands[0] = XEXP (operands[0], 0);
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
})
(clobber (reg:DI 26))])]
""
{
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
if (! call_operand (operands[1], Pmode))
(clobber (reg:DI 26))])]
""
{
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
- if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
+ if (GET_CODE (operands[1]) != SYMBOL_REF && !REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
})
(clobber (reg:DI 27))])]
""
{
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
(clobber (reg:DI 26))])]
""
{
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
operands[1] = XEXP (operands[1], 0);
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
})
+(define_insn "*call_osf_1_er_noreturn"
+ [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
+ (match_operand 1 "" ""))
+ (use (reg:DI 29))
+ (clobber (reg:DI 26))]
+ "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
+ && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
+ "@
+ jsr $26,($27),0
+ bsr $26,%0\t\t!samegp
+ ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#"
+ [(set_attr "type" "jsr")
+ (set_attr "length" "*,*,8")])
+
(define_insn "*call_osf_1_er"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
(match_operand 1 "" ""))
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
[(parallel [(call (mem:DI (match_dup 2))
(match_dup 1))
- (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
+ (use (reg:DI 29))
(use (match_dup 0))
- (use (match_dup 3))])]
+ (use (match_dup 3))
+ (clobber (reg:DI 26))])]
{
if (CONSTANT_P (operands[0]))
{
|| find_reg_note (insn, REG_NORETURN, NULL_RTX))"
[(parallel [(call (mem:DI (match_dup 2))
(match_dup 1))
- (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
+ (set (match_dup 5)
+ (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1))
(use (match_dup 0))
- (use (match_dup 4))])
- (set (reg:DI 29)
- (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
- (set (reg:DI 29)
- (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
+ (use (match_dup 4))
+ (clobber (reg:DI 26))])
+ (set (match_dup 5)
+ (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))]
{
if (CONSTANT_P (operands[0]))
{
operands[4] = const0_rtx;
}
operands[3] = GEN_INT (alpha_next_sequence_number++);
+ operands[5] = pic_offset_table_rtx;
})
-;; We add a blockage unspec_volatile to prevent insns from moving down
-;; from above the call to in between the call and the ldah gpdisp.
+(define_insn "*call_osf_2_er_nogp"
+ [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
+ (match_operand 1 "" ""))
+ (use (reg:DI 29))
+ (use (match_operand 2 "" ""))
+ (use (match_operand 3 "const_int_operand" ""))
+ (clobber (reg:DI 26))]
+ "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
+ "jsr $26,(%0),%2%J3"
+ [(set_attr "type" "jsr")])
(define_insn "*call_osf_2_er"
[(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
(match_operand 1 "" ""))
- (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
+ (set (reg:DI 29)
+ (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand" "")]
+ UNSPEC_LDGP1))
(use (match_operand 2 "" ""))
- (use (match_operand 3 "const_int_operand" ""))]
+ (use (match_operand 3 "const_int_operand" ""))
+ (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
- "jsr $26,(%0),%2%J3"
+ "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
[(set_attr "type" "jsr")
- (set_attr "cannot_copy" "true")])
-
-;; We output a nop after noreturn calls at the very end of the function to
-;; ensure that the return address always remains in the caller's code range,
-;; as not doing so might confuse unwinding engines.
-;;
-;; The potential change in insn length is not reflected in the length
-;; attributes at this stage. Since the extra space is only actually added at
-;; the very end of the compilation process (via final/print_operand), it
-;; really seems harmless and not worth the trouble of some extra computation
-;; cost and complexity.
+ (set_attr "cannot_copy" "true")
+ (set_attr "length" "8")])
(define_insn "*call_osf_1_noreturn"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
"@
- jsr $26,($27),0%+
- bsr $26,$%0..ng%+
- jsr $26,%0%+"
+ jsr $26,($27),0
+ bsr $26,$%0..ng
+ jsr $26,%0"
[(set_attr "type" "jsr")
(set_attr "length" "*,*,8")])
[(set_attr "type" "jsr")
(set_attr "length" "12,*,16")])
-;; Note that the DEC assembler expands "jmp foo" with $at, which
-;; doesn't do what we want.
(define_insn "*sibcall_osf_1_er"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
(match_operand 1 "" ""))
[(set_attr "type" "jsr")
(set_attr "length" "*,8")])
+;; Note that the DEC assembler expands "jmp foo" with $at, which
+;; doesn't do what we want.
(define_insn "*sibcall_osf_1"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
(match_operand 1 "" ""))
"jmp $31,(%0),0"
[(set_attr "type" "ibr")])
-;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
+;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't
;; want to have to include pal.h in our .s file.
-;;
-;; Technically the type for call_pal is jsr, but we use that for determining
-;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
-;; characteristics.
(define_insn "imb"
[(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
""
return "call_pal 0x9f";
}
[(set_attr "type" "callpal")])
+
+;; Special builtins for establishing and reverting VMS condition handlers.
+
+(define_expand "builtin_establish_vms_condition_handler"
+ [(set (reg:DI 0) (match_operand:DI 0 "register_operand" ""))
+ (use (match_operand:DI 1 "address_operand" ""))]
+ "TARGET_ABI_OPEN_VMS"
+{
+ alpha_expand_builtin_establish_vms_condition_handler (operands[0],
+ operands[1]);
+})
+
+(define_expand "builtin_revert_vms_condition_handler"
+ [(set (reg:DI 0) (match_operand:DI 0 "register_operand" ""))]
+ "TARGET_ABI_OPEN_VMS"
+{
+ alpha_expand_builtin_revert_vms_condition_handler (operands[0]);
+})
\f
;; Finally, we have the basic data motion insns. The byte and word insns
;; are done via define_expand. Start with the floating-point insns, since
[(set (match_dup 0) (match_dup 2))
(set (match_dup 1) (match_dup 3))]
{
- alpha_split_tfmode_pair (operands);
- if (reg_overlap_mentioned_p (operands[0], operands[3]))
- {
- rtx tmp;
- tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
- tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
- }
+ alpha_split_tmode_pair (operands, TFmode, true);
})
(define_expand "movsf"
(match_operand:SF 1 "general_operand" ""))]
""
{
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& ! reg_or_0_operand (operands[1], SFmode))
operands[1] = force_reg (SFmode, operands[1]);
})
(match_operand:DF 1 "general_operand" ""))]
""
{
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& ! reg_or_0_operand (operands[1], DFmode))
operands[1] = force_reg (DFmode, operands[1]);
})
(match_operand:TF 1 "general_operand" ""))]
""
{
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& ! reg_or_0_operand (operands[1], TFmode))
operands[1] = force_reg (TFmode, operands[1]);
})
;; Split the load of an address into a four-insn sequence on Unicos/Mk.
;; Always generate a REG_EQUAL note for the last instruction to facilitate
-;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
-;; notes and update LABEL_NUSES because this is not done automatically.
-;; Labels may be incorrectly deleted if we don't do this.
+;; optimizations. If the symbolic operand is a label_ref, generate
+;; REG_LABEL_OPERAND notes and update LABEL_NUSES because this is not done
+;; automatically. Labels may be incorrectly deleted if we don't do this.
;;
;; Describing what the individual instructions do correctly is too complicated
;; so use UNSPECs for each of the three parts of an address.
emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
- REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
- REG_NOTES (insn3));
+ set_unique_reg_note (insn3, REG_EQUAL, operands[1]);
+
if (GET_CODE (operands[1]) == LABEL_REF)
{
rtx label;
label = XEXP (operands[1], 0);
- REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
- REG_NOTES (insn1));
- REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
- REG_NOTES (insn2));
- REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
- REG_NOTES (insn3));
+ add_reg_note (insn1, REG_LABEL_OPERAND, label);
+ add_reg_note (insn2, REG_LABEL_OPERAND, label);
+ add_reg_note (insn3, REG_LABEL_OPERAND, label);
LABEL_NUSES (label) += 3;
}
DONE;
FAIL;
})
+;; We need to prevent reload from splitting TImode moves, because it
+;; might decide to overwrite a pointer with the value it points to.
+;; In that case we have to do the loads in the appropriate order so
+;; that the pointer is not destroyed too early.
+
+(define_insn_and_split "*movti_internal"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
+ (match_operand:TI 1 "input_operand" "roJ,rJ"))]
+ "(register_operand (operands[0], TImode)
+ /* Prevent rematerialization of constants. */
+ && ! CONSTANT_P (operands[1]))
+ || reg_or_0_operand (operands[1], TImode)"
+ "#"
+ "reload_completed"
+ [(set (match_dup 0) (match_dup 2))
+ (set (match_dup 1) (match_dup 3))]
+{
+ alpha_split_tmode_pair (operands, TImode, true);
+})
+
+(define_expand "movti"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (match_operand:TI 1 "general_operand" ""))]
+ ""
+{
+ if (MEM_P (operands[0])
+ && ! reg_or_0_operand (operands[1], TImode))
+ operands[1] = force_reg (TImode, operands[1]);
+
+ if (operands[1] == const0_rtx)
+ ;
+ /* We must put 64-bit constants in memory. We could keep the
+ 32-bit constants in TImode and rely on the splitter, but
+ this doesn't seem to be worth the pain. */
+ else if (CONST_INT_P (operands[1])
+ || GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ rtx in[2], out[2], target;
+
+ gcc_assert (can_create_pseudo_p ());
+
+ split_double (operands[1], &in[0], &in[1]);
+
+ if (in[0] == const0_rtx)
+ out[0] = const0_rtx;
+ else
+ {
+ out[0] = gen_reg_rtx (DImode);
+ emit_insn (gen_movdi (out[0], in[0]));
+ }
+
+ if (in[1] == const0_rtx)
+ out[1] = const0_rtx;
+ else
+ {
+ out[1] = gen_reg_rtx (DImode);
+ emit_insn (gen_movdi (out[1], in[1]));
+ }
+
+ if (!REG_P (operands[0]))
+ target = gen_reg_rtx (TImode);
+ else
+ target = operands[0];
+
+ emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0]));
+ emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1]));
+
+ if (target != operands[0])
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], target));
+
+ DONE;
+ }
+})
+
;; These are the partial-word cases.
;;
;; First we have the code to load an aligned word. Operand 0 is the register
(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
(const_int -8))))
(set (match_operand:DI 2 "register_operand" "")
- (plus:DI (match_dup 0) (const_int 1)))
+ (plus:DI (match_dup 5) (const_int 1)))
(set (match_dup 3)
(and:DI (not:DI (ashift:DI
(const_int 65535)
(set (mem:DI (and:DI (match_dup 0) (const_int -8)))
(match_dup 4))]
"WORDS_BIG_ENDIAN"
- "")
+ "operands[5] = force_reg (DImode, operands[0]);")
\f
;; Here are the define_expand's for QI and HI moves that use the above
;; patterns. We have the normal sets, plus the ones that need scratch
DONE;
})
-;; Here are the versions for reload. Note that in the unaligned cases
-;; we know that the operand must not be a pseudo-register because stack
-;; slots are always aligned references.
-
-(define_expand "reload_inqi"
- [(parallel [(match_operand:QI 0 "register_operand" "=r")
- (match_operand:QI 1 "any_memory_operand" "m")
- (match_operand:TI 2 "register_operand" "=&r")])]
- "! TARGET_BWX"
+;; We need to hook into the extra support that we have for HImode
+;; reloads when BWX insns are not available.
+(define_expand "movcqi"
+ [(set (match_operand:CQI 0 "nonimmediate_operand" "")
+ (match_operand:CQI 1 "general_operand" ""))]
+ "!TARGET_BWX"
{
- rtx scratch, seq;
-
- if (aligned_memory_operand (operands[1], QImode))
+ if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT)
+ ;
+ else if (!any_memory_operand (operands[0], CQImode))
{
- seq = gen_reload_inqi_help (operands[0], operands[1],
- gen_rtx_REG (SImode, REGNO (operands[2])));
+ if (!any_memory_operand (operands[1], CQImode))
+ {
+ emit_move_insn (gen_lowpart (HImode, operands[0]),
+ gen_lowpart (HImode, operands[1]));
+ DONE;
+ }
+ if (aligned_memory_operand (operands[1], CQImode))
+ {
+ bool done;
+ do_aligned1:
+ operands[1] = gen_lowpart (HImode, operands[1]);
+ do_aligned2:
+ operands[0] = gen_lowpart (HImode, operands[0]);
+ done = alpha_expand_mov_nobwx (HImode, operands);
+ gcc_assert (done);
+ DONE;
+ }
}
- else
+ else if (aligned_memory_operand (operands[0], CQImode))
{
- rtx addr;
-
- /* It is possible that one of the registers we got for operands[2]
- might coincide with that of operands[0] (which is why we made
- it TImode). Pick the other one to use as our scratch. */
- if (REGNO (operands[0]) == REGNO (operands[2]))
- scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
- else
- scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
-
- addr = get_unaligned_address (operands[1], 0);
- operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
- seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
- alpha_set_memflags (seq, operands[1]);
+ if (MEM_P (operands[1]))
+ {
+ rtx x = gen_reg_rtx (HImode);
+ emit_move_insn (gen_lowpart (CQImode, x), operands[1]);
+ operands[1] = x;
+ goto do_aligned2;
+ }
+ goto do_aligned1;
}
- emit_insn (seq);
+
+ gcc_assert (!reload_in_progress);
+ emit_move_complex_parts (operands[0], operands[1]);
DONE;
})
-(define_expand "reload_inhi"
- [(parallel [(match_operand:HI 0 "register_operand" "=r")
- (match_operand:HI 1 "any_memory_operand" "m")
+;; Here are the versions for reload.
+;;
+;; The aligned input case is recognized early in alpha_secondary_reload
+;; in order to avoid allocating an unnecessary scratch register.
+;;
+;; Note that in the unaligned cases we know that the operand must not be
+;; a pseudo-register because stack slots are always aligned references.
+
+(define_expand "reload_in<mode>"
+ [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r")
+ (match_operand:RELOAD12 1 "any_memory_operand" "m")
(match_operand:TI 2 "register_operand" "=&r")])]
- "! TARGET_BWX"
+ "!TARGET_BWX"
{
- rtx scratch, seq;
+ rtx scratch, seq, addr;
+ unsigned regno = REGNO (operands[2]);
- if (aligned_memory_operand (operands[1], HImode))
- {
- seq = gen_reload_inhi_help (operands[0], operands[1],
- gen_rtx_REG (SImode, REGNO (operands[2])));
- }
- else
- {
- rtx addr;
+ /* It is possible that one of the registers we got for operands[2]
+ might coincide with that of operands[0] (which is why we made
+ it TImode). Pick the other one to use as our scratch. */
+ if (regno == REGNO (operands[0]))
+ regno++;
+ scratch = gen_rtx_REG (DImode, regno);
- /* It is possible that one of the registers we got for operands[2]
- might coincide with that of operands[0] (which is why we made
- it TImode). Pick the other one to use as our scratch. */
- if (REGNO (operands[0]) == REGNO (operands[2]))
- scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
- else
- scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
+ addr = get_unaligned_address (operands[1]);
+ operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
+ seq = gen_unaligned_load<reloadmode> (operands[0], addr,
+ scratch, operands[0]);
+ alpha_set_memflags (seq, operands[1]);
- addr = get_unaligned_address (operands[1], 0);
- operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
- seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
- alpha_set_memflags (seq, operands[1]);
- }
emit_insn (seq);
DONE;
})
-(define_expand "reload_outqi"
- [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
- (match_operand:QI 1 "register_operand" "r")
+(define_expand "reload_out<mode>"
+ [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m")
+ (match_operand:RELOAD12 1 "register_operand" "r")
(match_operand:TI 2 "register_operand" "=&r")])]
"! TARGET_BWX"
{
- if (aligned_memory_operand (operands[0], QImode))
- {
- emit_insn (gen_reload_outqi_help
- (operands[0], operands[1],
- gen_rtx_REG (SImode, REGNO (operands[2])),
- gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
- }
- else
- {
- rtx addr = get_unaligned_address (operands[0], 0);
- rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
- rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
- rtx scratch3 = scratch1;
- rtx seq;
+ unsigned regno = REGNO (operands[2]);
- if (GET_CODE (addr) == REG)
- scratch1 = addr;
-
- seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
- scratch2, scratch3);
- alpha_set_memflags (seq, operands[0]);
- emit_insn (seq);
+ if (<MODE>mode == CQImode)
+ {
+ operands[0] = gen_lowpart (HImode, operands[0]);
+ operands[1] = gen_lowpart (HImode, operands[1]);
}
- DONE;
-})
-(define_expand "reload_outhi"
- [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
- (match_operand:HI 1 "register_operand" "r")
- (match_operand:TI 2 "register_operand" "=&r")])]
- "! TARGET_BWX"
-{
- if (aligned_memory_operand (operands[0], HImode))
+ if (aligned_memory_operand (operands[0], <MODE>mode))
{
- emit_insn (gen_reload_outhi_help
+ emit_insn (gen_reload_out<reloadmode>_aligned
(operands[0], operands[1],
- gen_rtx_REG (SImode, REGNO (operands[2])),
- gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
+ gen_rtx_REG (SImode, regno),
+ gen_rtx_REG (SImode, regno + 1)));
}
else
{
- rtx addr = get_unaligned_address (operands[0], 0);
- rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
- rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
+ rtx addr = get_unaligned_address (operands[0]);
+ rtx scratch1 = gen_rtx_REG (DImode, regno);
+ rtx scratch2 = gen_rtx_REG (DImode, regno + 1);
rtx scratch3 = scratch1;
rtx seq;
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
scratch1 = addr;
- seq = gen_unaligned_storehi (addr, operands[1], scratch1,
- scratch2, scratch3);
+ seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1,
+ scratch2, scratch3);
alpha_set_memflags (seq, operands[0]);
emit_insn (seq);
}
;; always get a proper address for a stack slot during reload_foo
;; expansion, so we must delay our address manipulations until after.
-(define_insn_and_split "reload_inqi_help"
- [(set (match_operand:QI 0 "register_operand" "=r")
- (match_operand:QI 1 "memory_operand" "m"))
- (clobber (match_operand:SI 2 "register_operand" "=r"))]
- "! TARGET_BWX && (reload_in_progress || reload_completed)"
- "#"
- "! TARGET_BWX && reload_completed"
- [(const_int 0)]
-{
- rtx aligned_mem, bitnum;
- get_aligned_mem (operands[1], &aligned_mem, &bitnum);
- operands[0] = gen_lowpart (DImode, operands[0]);
- emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
- operands[2]));
- DONE;
-})
-
-(define_insn_and_split "reload_inhi_help"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (match_operand:HI 1 "memory_operand" "m"))
- (clobber (match_operand:SI 2 "register_operand" "=r"))]
- "! TARGET_BWX && (reload_in_progress || reload_completed)"
+(define_insn_and_split "reload_in<mode>_aligned"
+ [(set (match_operand:I12MODE 0 "register_operand" "=r")
+ (match_operand:I12MODE 1 "memory_operand" "m"))]
+ "!TARGET_BWX && (reload_in_progress || reload_completed)"
"#"
- "! TARGET_BWX && reload_completed"
+ "!TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
get_aligned_mem (operands[1], &aligned_mem, &bitnum);
- operands[0] = gen_lowpart (DImode, operands[0]);
- emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
- operands[2]));
+ emit_insn (gen_aligned_load<reloadmode>
+ (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum,
+ gen_rtx_REG (SImode, REGNO (operands[0]))));
DONE;
})
-(define_insn_and_split "reload_outqi_help"
- [(set (match_operand:QI 0 "memory_operand" "=m")
- (match_operand:QI 1 "register_operand" "r"))
+(define_insn_and_split "reload_out<mode>_aligned"
+ [(set (match_operand:I12MODE 0 "memory_operand" "=m")
+ (match_operand:I12MODE 1 "register_operand" "r"))
(clobber (match_operand:SI 2 "register_operand" "=r"))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
- "! TARGET_BWX && (reload_in_progress || reload_completed)"
+ "!TARGET_BWX && (reload_in_progress || reload_completed)"
"#"
- "! TARGET_BWX && reload_completed"
- [(const_int 0)]
-{
- rtx aligned_mem, bitnum;
- get_aligned_mem (operands[0], &aligned_mem, &bitnum);
- emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
- operands[2], operands[3]));
- DONE;
-})
-
-(define_insn_and_split "reload_outhi_help"
- [(set (match_operand:HI 0 "memory_operand" "=m")
- (match_operand:HI 1 "register_operand" "r"))
- (clobber (match_operand:SI 2 "register_operand" "=r"))
- (clobber (match_operand:SI 3 "register_operand" "=r"))]
- "! TARGET_BWX && (reload_in_progress || reload_completed)"
- "#"
- "! TARGET_BWX && reload_completed"
+ "!TARGET_BWX && reload_completed"
[(const_int 0)]
{
rtx aligned_mem, bitnum;
\f
;; Vector operations
-(define_mode_macro VEC [V8QI V4HI V2SI])
+(define_mode_iterator VEC [V8QI V4HI V2SI])
(define_expand "mov<mode>"
[(set (match_operand:VEC 0 "nonimmediate_operand" "")
""
"eqv %1,%2,%0"
[(set_attr "type" "ilog")])
+
+(define_expand "vec_shl_<mode>"
+ [(set (match_operand:VEC 0 "register_operand" "")
+ (ashift:DI (match_operand:VEC 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+ ""
+{
+ operands[0] = gen_lowpart (DImode, operands[0]);
+ operands[1] = gen_lowpart (DImode, operands[1]);
+})
+
+(define_expand "vec_shr_<mode>"
+ [(set (match_operand:VEC 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+ ""
+{
+ operands[0] = gen_lowpart (DImode, operands[0]);
+ operands[1] = gen_lowpart (DImode, operands[1]);
+})
\f
;; Bit field extract patterns which use ext[wlq][lh]
/* From mips.md: extract_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[1]) != MEM)
+ if (!MEM_P (operands[1]))
FAIL;
/* The bit number is relative to the mode of operand 1 which is
&& INTVAL (operands[2]) != 64))
FAIL;
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
{
int ofs;
- /* Fail 8 bit fields, falling back on a simple byte load. */
+ /* Fail 8-bit fields, falling back on a simple byte load. */
if (INTVAL (operands[2]) == 8)
FAIL;
/* From mips.md: store_bit_field doesn't verify that our source
matches the predicate, so we force it to be a MEM here. */
- if (GET_CODE (operands[0]) != MEM)
+ if (!MEM_P (operands[0]))
FAIL;
/* The bit number is relative to the mode of operand 1 which is
(clobber (reg:DI 27))])]
"TARGET_ABI_OPEN_VMS"
{
- operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
- alpha_need_linkage (XSTR (operands[4], 0), 0);
+ operands[4] = alpha_need_linkage ("OTS$MOVE", 0);
})
(define_insn "*movmemdi_1"
[(set_attr "type" "multi")
(set_attr "length" "28")])
-(define_expand "clrmemqi"
+(define_expand "setmemqi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (const_int 0))
+ (match_operand 2 "const_int_operand" ""))
(use (match_operand:DI 1 "immediate_operand" ""))
- (use (match_operand:DI 2 "immediate_operand" ""))])]
+ (use (match_operand:DI 3 "immediate_operand" ""))])]
""
{
+ /* If value to set is not zero, use the library routine. */
+ if (operands[2] != const0_rtx)
+ FAIL;
+
if (alpha_expand_block_clear (operands))
DONE;
else
FAIL;
})
-(define_expand "clrmemdi"
+(define_expand "setmemdi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (const_int 0))
+ (match_operand 2 "const_int_operand" ""))
(use (match_operand:DI 1 "immediate_operand" ""))
- (use (match_operand:DI 2 "immediate_operand" ""))
- (use (match_dup 3))
+ (use (match_operand:DI 3 "immediate_operand" ""))
+ (use (match_dup 4))
(clobber (reg:DI 25))
(clobber (reg:DI 16))
(clobber (reg:DI 17))
(clobber (reg:DI 27))])]
"TARGET_ABI_OPEN_VMS"
{
- operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
- alpha_need_linkage (XSTR (operands[3], 0), 0);
+ /* If value to set is not zero, use the library routine. */
+ if (operands[2] != const0_rtx)
+ FAIL;
+
+ operands[4] = alpha_need_linkage ("OTS$ZERO", 0);
})
(define_insn "*clrmemdi_1"
(match_dup 2))]
""
{
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& INTVAL (operands[1]) < 32768)
{
if (INTVAL (operands[1]) >= 4096)
rtx loop_label = gen_label_rtx ();
rtx want = gen_reg_rtx (Pmode);
rtx tmp = gen_reg_rtx (Pmode);
- rtx memref;
+ rtx memref, test;
emit_insn (gen_subdi3 (want, stack_pointer_rtx,
force_reg (Pmode, operands[1])));
emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
- if (GET_CODE (operands[1]) != CONST_INT)
+ if (!CONST_INT_P (operands[1]))
{
out_label = gen_label_rtx ();
- emit_insn (gen_cmpdi (want, tmp));
- emit_jump_insn (gen_bgeu (out_label));
+ test = gen_rtx_GEU (VOIDmode, want, tmp);
+ emit_jump_insn (gen_cbranchdi4 (test, want, tmp, out_label));
}
emit_label (loop_label);
MEM_VOLATILE_P (memref) = 1;
emit_move_insn (memref, const0_rtx);
emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
- emit_insn (gen_cmpdi (tmp, want));
- emit_jump_insn (gen_bgtu (loop_label));
+ test = gen_rtx_GTU (VOIDmode, tmp, want);
+ emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label));
memref = gen_rtx_MEM (DImode, want);
MEM_VOLATILE_P (memref) = 1;
emit_move_insn (hard_frame_pointer_rtx, fp);
emit_move_insn (pv, lab);
emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
- emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+ emit_use (hard_frame_pointer_rtx);
+ emit_use (stack_pointer_rtx);
/* Load the label we are jumping through into $27 so that we know
where to look for it when we get back to setjmp's function for
"br $27,$LSJ%=\n$LSJ%=:"
[(set_attr "type" "ibr")])
+;; When flag_reorder_blocks_and_partition is in effect, compiler puts
+;; exception landing pads in a cold section. To prevent inter-section offset
+;; calculation, a jump to original landing pad is emitted in the place of the
+;; original landing pad. Since landing pad is moved, RA-relative GP
+;; calculation in the prologue of landing pad breaks. To solve this problem,
+;; we use alternative GP load approach, as in the case of TARGET_LD_BUGGY_LDGP.
+
(define_expand "exception_receiver"
[(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
"TARGET_ABI_OSF"
{
- if (TARGET_LD_BUGGY_LDGP)
+ if (TARGET_LD_BUGGY_LDGP || flag_reorder_blocks_and_partition)
operands[0] = alpha_gp_save_rtx ();
else
operands[0] = const0_rtx;
(define_insn "*exception_receiver_2"
[(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
- "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
+ "TARGET_ABI_OSF
+ && (TARGET_LD_BUGGY_LDGP || flag_reorder_blocks_and_partition)"
"ldq $29,%0"
[(set_attr "type" "ild")])
(match_operand:DI 1 "reg_or_cint_operand" "")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
[(const_int 0)]
{
rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
- if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
+ if (HOST_BITS_PER_WIDE_INT >= 64 || CONST_INT_P (mask))
operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
else
{
(match_operand:DI 1 "reg_or_cint_operand" "")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
;; The call patterns are at the end of the file because their
;; wildcard operand0 interferes with nice recognition.
+(define_insn "*call_value_osf_1_er_noreturn"
+ [(set (match_operand 0 "" "")
+ (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
+ (match_operand 2 "" "")))
+ (use (reg:DI 29))
+ (clobber (reg:DI 26))]
+ "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
+ && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
+ "@
+ jsr $26,($27),0
+ bsr $26,%1\t\t!samegp
+ ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#"
+ [(set_attr "type" "jsr")
+ (set_attr "length" "*,*,8")])
+
(define_insn "*call_value_osf_1_er"
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(match_dup 2)))
- (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
+ (use (reg:DI 29))
(use (match_dup 1))
- (use (match_dup 4))])]
+ (use (match_dup 4))
+ (clobber (reg:DI 26))])]
{
if (CONSTANT_P (operands[1]))
{
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(match_dup 2)))
- (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
+ (set (match_dup 6)
+ (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1))
(use (match_dup 1))
- (use (match_dup 5))])
- (set (reg:DI 29)
- (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
- (set (reg:DI 29)
- (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
+ (use (match_dup 5))
+ (clobber (reg:DI 26))])
+ (set (match_dup 6)
+ (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))]
{
if (CONSTANT_P (operands[1]))
{
operands[5] = const0_rtx;
}
operands[4] = GEN_INT (alpha_next_sequence_number++);
+ operands[6] = pic_offset_table_rtx;
})
-;; We add a blockage unspec_volatile to prevent insns from moving down
-;; from above the call to in between the call and the ldah gpdisp.
-(define_insn "*call_value_osf_2_er"
+(define_insn "*call_value_osf_2_er_nogp"
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "register_operand" "c"))
(match_operand 2 "" "")))
- (set (reg:DI 26)
- (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
+ (use (reg:DI 29))
(use (match_operand 3 "" ""))
- (use (match_operand 4 "" ""))]
+ (use (match_operand 4 "" ""))
+ (clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%1),%3%J4"
+ [(set_attr "type" "jsr")])
+
+(define_insn "*call_value_osf_2_er"
+ [(set (match_operand 0 "" "")
+ (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
+ (match_operand 2 "" "")))
+ (set (reg:DI 29)
+ (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand" "")]
+ UNSPEC_LDGP1))
+ (use (match_operand 3 "" ""))
+ (use (match_operand 4 "" ""))
+ (clobber (reg:DI 26))]
+ "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
+ "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
[(set_attr "type" "jsr")
- (set_attr "cannot_copy" "true")])
+ (set_attr "cannot_copy" "true")
+ (set_attr "length" "8")])
(define_insn "*call_value_osf_1_noreturn"
[(set (match_operand 0 "" "")
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
"@
- jsr $26,($27),0%+
- bsr $26,$%1..ng%+
- jsr $26,%1%+"
+ jsr $26,($27),0
+ bsr $26,$%1..ng
+ jsr $26,%1"
[(set_attr "type" "jsr")
(set_attr "length" "*,*,8")])
(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(const_int 0)))
- (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
+ (set (match_dup 5)
+ (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
(use (match_dup 1))
- (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
- (set (match_dup 5)
- (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
+ (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))
+ (clobber (reg:DI 26))])
(set (match_dup 5)
(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
{
(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(const_int 0)))
- (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
- (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
+ (set (match_dup 5)
+ (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
(use (match_dup 1))
- (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
- (set (reg:DI 29)
- (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
- (set (reg:DI 29)
- (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
+ (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))
+ (clobber (reg:DI 26))])
+ (set (match_dup 5)
+ (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
{
operands[3] = gen_rtx_REG (Pmode, 27);
operands[4] = GEN_INT (alpha_next_sequence_number++);
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