/* Optimize by combining instructions for GNU compiler.
Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
This file is part of GCC.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
+Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+02110-1301, USA. */
/* This module is essentially the "combiner" phase of the U. of Arizona
Portable Optimizer, but redone to work on our list-structured
flow.c aren't completely updated:
- reg_live_length is not updated
+ - reg_n_refs is not adjusted in the rare case when a register is
+ no longer required in a computation
+ - there are extremely rare cases (see distribute_notes) when a
+ REG_DEAD note is lost
- a LOG_LINKS entry that refers to an insn with multiple SETs may be
removed because there is no way to know which register it was
linking
#include "real.h"
#include "toplev.h"
#include "target.h"
+#include "optabs.h"
+#include "insn-codes.h"
#include "rtlhooks-def.h"
/* Include output.h for dump_file. */
#include "output.h"
#include "params.h"
+#include "timevar.h"
+#include "tree-pass.h"
/* Number of attempts to combine instructions in this function. */
unsigned HOST_WIDE_INT last_set_nonzero_bits;
char last_set_sign_bit_copies;
- ENUM_BITFIELD(machine_mode) last_set_mode : 8;
+ ENUM_BITFIELD(machine_mode) last_set_mode : 8;
/* Set nonzero if references to register n in expressions should not be
used. last_set_invalid is set nonzero when this register is being
unsigned char sign_bit_copies;
unsigned HOST_WIDE_INT nonzero_bits;
+
+ /* Record the value of the label_tick when the last truncation
+ happened. The field truncated_to_mode is only valid if
+ truncation_label == label_tick. */
+
+ int truncation_label;
+
+ /* Record the last truncation seen for this register. If truncation
+ is not a nop to this mode we might be able to save an explicit
+ truncation if we know that value already contains a truncated
+ value. */
+
+ ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
};
static struct reg_stat *reg_stat;
\f
/* Record one modification to rtl structure
- to be undone by storing old_contents into *where.
- is_int is 1 if the contents are an int. */
+ to be undone by storing old_contents into *where. */
struct undo
{
struct undo *next;
- int is_int;
- union {rtx r; int i;} old_contents;
- union {rtx *r; int *i;} where;
+ enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
+ union { rtx r; int i; enum machine_mode m; } old_contents;
+ union { rtx *r; int *i; } where;
};
/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
static rtx make_compound_operation (rtx, enum rtx_code);
static int get_pos_from_mask (unsigned HOST_WIDE_INT,
unsigned HOST_WIDE_INT *);
+static rtx canon_reg_for_combine (rtx, rtx);
static rtx force_to_mode (rtx, enum machine_mode,
- unsigned HOST_WIDE_INT, rtx, int);
+ unsigned HOST_WIDE_INT, int);
static rtx if_then_else_cond (rtx, rtx *, rtx *);
static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
static int rtx_equal_for_field_assignment_p (rtx, rtx);
static rtx make_field_assignment (rtx);
static rtx apply_distributive_law (rtx);
+static rtx distribute_and_simplify_rtx (rtx, int);
+static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
+ unsigned HOST_WIDE_INT);
static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
unsigned HOST_WIDE_INT);
static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
HOST_WIDE_INT, enum machine_mode, int *);
-static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
+static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
+static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
int);
static int recog_for_combine (rtx *, rtx, rtx *);
static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
-static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
static void update_table_tick (rtx);
static void record_value_for_reg (rtx, rtx, rtx);
-static void check_promoted_subreg (rtx, rtx);
+static void check_conversions (rtx, rtx);
static void record_dead_and_set_regs_1 (rtx, rtx, void *);
static void record_dead_and_set_regs (rtx);
static int get_last_value_validate (rtx *, rtx, int, int);
static int reg_dead_at_p (rtx, rtx);
static void move_deaths (rtx, rtx, int, rtx, rtx *);
static int reg_bitfield_target_p (rtx, rtx);
-static void distribute_notes (rtx, rtx, rtx, rtx);
+static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
static void distribute_links (rtx);
static void mark_used_regs_combine (rtx);
static int insn_cuid (rtx);
static void record_promoted_value (rtx, rtx);
-static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
-static enum rtx_code combine_reversed_comparison_code (rtx);
static int unmentioned_reg_p_1 (rtx *, void *);
static bool unmentioned_reg_p (rtx, rtx);
+static void record_truncated_value (rtx);
+static bool reg_truncated_to_mode (enum machine_mode, rtx);
+static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
\f
/* It is not safe to use ordinary gen_lowpart in combine.
#undef RTL_HOOKS_GEN_LOWPART
#define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
+/* Our implementation of gen_lowpart never emits a new pseudo. */
+#undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
+#define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
+
#undef RTL_HOOKS_REG_NONZERO_REG_BITS
#define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
else
buf = xmalloc (sizeof (struct undo));
- buf->is_int = 0;
+ buf->kind = UNDO_RTX;
buf->where.r = into;
buf->old_contents.r = oldval;
*into = newval;
else
buf = xmalloc (sizeof (struct undo));
- buf->is_int = 1;
+ buf->kind = UNDO_INT;
buf->where.i = into;
buf->old_contents.i = oldval;
*into = newval;
}
#define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
+
+/* Similar to SUBST, but just substitute the mode. This is used when
+ changing the mode of a pseudo-register, so that any other
+ references to the entry in the regno_reg_rtx array will change as
+ well. */
+
+static void
+do_SUBST_MODE (rtx *into, enum machine_mode newval)
+{
+ struct undo *buf;
+ enum machine_mode oldval = GET_MODE (*into);
+
+ if (oldval == newval)
+ return;
+
+ if (undobuf.frees)
+ buf = undobuf.frees, undobuf.frees = buf->next;
+ else
+ buf = xmalloc (sizeof (struct undo));
+
+ buf->kind = UNDO_MODE;
+ buf->where.r = into;
+ buf->old_contents.m = oldval;
+ PUT_MODE (*into, newval);
+
+ buf->next = undobuf.undos, undobuf.undos = buf;
+}
+
+#define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
\f
/* Subroutine of try_combine. Determine whether the combine replacement
patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
Return nonzero if the combiner has turned an indirect jump
instruction into a direct jump. */
-int
+static int
combine_instructions (rtx f, unsigned int nregs)
{
rtx insn, next;
rtx prev;
#endif
int i;
+ unsigned int j = 0;
rtx links, nextlinks;
+ sbitmap_iterator sbi;
int new_direct_jump_p = 0;
{
/* See if we know about function return values before this
insn based upon SUBREG flags. */
- check_promoted_subreg (insn, PATTERN (insn));
+ check_conversions (insn, PATTERN (insn));
/* Try this insn with each insn it links back to. */
rtx temp = XEXP (links, 0);
if ((set = single_set (temp)) != 0
&& (note = find_reg_equal_equiv_note (temp)) != 0
- && GET_CODE (XEXP (note, 0)) != EXPR_LIST
+ && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
/* Avoid using a register that may already been marked
dead by an earlier instruction. */
- && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
+ && ! unmentioned_reg_p (note, SET_SRC (set))
+ && (GET_MODE (note) == VOIDmode
+ ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
+ : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
{
/* Temporarily replace the set's source with the
contents of the REG_EQUAL note. The insn will
be deleted or recognized by try_combine. */
rtx orig = SET_SRC (set);
- SET_SRC (set) = XEXP (note, 0);
+ SET_SRC (set) = note;
next = try_combine (insn, temp, NULL_RTX,
&new_direct_jump_p);
if (next)
}
clear_bb_flags ();
- EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
- BASIC_BLOCK (i)->flags |= BB_DIRTY);
- new_direct_jump_p |= purge_all_dead_edges (0);
+ EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
+ BASIC_BLOCK (j)->flags |= BB_DIRTY;
+ new_direct_jump_p |= purge_all_dead_edges ();
delete_noop_moves ();
update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
/* If this register is undefined at the start of the file, we can't
say what its contents were. */
- && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
+ && ! REGNO_REG_SET_P
+ (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
&& GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
{
if (set == 0 || GET_CODE (set) == CLOBBER)
/* If the clobber represents an earlyclobber operand, we must not
substitute an expression containing the clobbered register.
- As we do not analyse the constraint strings here, we have to
+ As we do not analyze the constraint strings here, we have to
make the conservative assumption. However, if the register is
a fixed hard reg, the clobber cannot represent any operand;
we leave it up to the machine description to either accept or
if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
return 0;
- /* If INSN or I2 contains an autoincrement or autodecrement,
- make sure that register is not used between there and I3,
- and not already used in I3 either.
+ /* If INSN contains an autoincrement or autodecrement, make sure that
+ register is not used between there and I3, and not already used in
+ I3 either. Neither must it be used in PRED or SUCC, if they exist.
Also insist that I3 not be a jump; if it were one
and the incremented register were spilled, we would lose. */
if (REG_NOTE_KIND (link) == REG_INC
&& (JUMP_P (i3)
|| reg_used_between_p (XEXP (link, 0), insn, i3)
+ || (pred != NULL_RTX
+ && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
+ || (succ != NULL_RTX
+ && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
|| reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
return 0;
#endif
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
rtx inner_dest = dest;
+ rtx subdest;
while (GET_CODE (inner_dest) == STRICT_LOW_PART
|| GET_CODE (inner_dest) == SUBREG
|| (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
return 0;
- /* If DEST is used in I3, it is being killed in this insn,
- so record that for later.
+ /* If DEST is used in I3, it is being killed in this insn, so
+ record that for later. We have to consider paradoxical
+ subregs here, since they kill the whole register, but we
+ ignore partial subregs, STRICT_LOW_PART, etc.
Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
STACK_POINTER_REGNUM, since these are always considered to be
live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
- if (pi3dest_killed && REG_P (dest)
- && reg_referenced_p (dest, PATTERN (i3))
- && REGNO (dest) != FRAME_POINTER_REGNUM
+ subdest = dest;
+ if (GET_CODE (subdest) == SUBREG
+ && (GET_MODE_SIZE (GET_MODE (subdest))
+ >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
+ subdest = SUBREG_REG (subdest);
+ if (pi3dest_killed
+ && REG_P (subdest)
+ && reg_referenced_p (subdest, PATTERN (i3))
+ && REGNO (subdest) != FRAME_POINTER_REGNUM
#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
- && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
+ && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
#endif
#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
- && (REGNO (dest) != ARG_POINTER_REGNUM
- || ! fixed_regs [REGNO (dest)])
+ && (REGNO (subdest) != ARG_POINTER_REGNUM
+ || ! fixed_regs [REGNO (subdest)])
#endif
- && REGNO (dest) != STACK_POINTER_REGNUM)
+ && REGNO (subdest) != STACK_POINTER_REGNUM)
{
if (*pi3dest_killed)
return 0;
- *pi3dest_killed = dest;
+ *pi3dest_killed = subdest;
}
}
/* Never combine loads and stores involving hard regs that are likely
to be spilled. The register allocator can usually handle such
reg-reg moves by tying. If we allow the combiner to make
- substitutions of likely-spilled regs, we may abort in reload.
+ substitutions of likely-spilled regs, reload might die.
As an exception, we allow combinations involving fixed regs; these are
not available to the register allocator so there's no risk involved. */
return 0;
}
+struct likely_spilled_retval_info
+{
+ unsigned regno, nregs;
+ unsigned mask;
+};
+
+/* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
+ hard registers that are known to be written to / clobbered in full. */
+static void
+likely_spilled_retval_1 (rtx x, rtx set, void *data)
+{
+ struct likely_spilled_retval_info *info = data;
+ unsigned regno, nregs;
+ unsigned new_mask;
+
+ if (!REG_P (XEXP (set, 0)))
+ return;
+ regno = REGNO (x);
+ if (regno >= info->regno + info->nregs)
+ return;
+ nregs = hard_regno_nregs[regno][GET_MODE (x)];
+ if (regno + nregs <= info->regno)
+ return;
+ new_mask = (2U << (nregs - 1)) - 1;
+ if (regno < info->regno)
+ new_mask >>= info->regno - regno;
+ else
+ new_mask <<= regno - info->regno;
+ info->mask &= new_mask;
+}
+
+/* Return nonzero iff part of the return value is live during INSN, and
+ it is likely spilled. This can happen when more than one insn is needed
+ to copy the return value, e.g. when we consider to combine into the
+ second copy insn for a complex value. */
+
+static int
+likely_spilled_retval_p (rtx insn)
+{
+ rtx use = BB_END (this_basic_block);
+ rtx reg, p;
+ unsigned regno, nregs;
+ /* We assume here that no machine mode needs more than
+ 32 hard registers when the value overlaps with a register
+ for which FUNCTION_VALUE_REGNO_P is true. */
+ unsigned mask;
+ struct likely_spilled_retval_info info;
+
+ if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
+ return 0;
+ reg = XEXP (PATTERN (use), 0);
+ if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
+ return 0;
+ regno = REGNO (reg);
+ nregs = hard_regno_nregs[regno][GET_MODE (reg)];
+ if (nregs == 1)
+ return 0;
+ mask = (2U << (nregs - 1)) - 1;
+
+ /* Disregard parts of the return value that are set later. */
+ info.regno = regno;
+ info.nregs = nregs;
+ info.mask = mask;
+ for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
+ note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
+ mask = info.mask;
+
+ /* Check if any of the (probably) live return value registers is
+ likely spilled. */
+ nregs --;
+ do
+ {
+ if ((mask & 1 << nregs)
+ && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
+ return 1;
+ } while (nregs--);
+ return 0;
+}
+
/* Adjust INSN after we made a change to its destination.
Changing the destination can invalidate notes that say something about
distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
}
+/* Return TRUE if combine can reuse reg X in mode MODE.
+ ADDED_SETS is nonzero if the original set is still required. */
+static bool
+can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
+{
+ unsigned int regno;
+
+ if (!REG_P(x))
+ return false;
+
+ regno = REGNO (x);
+ /* Allow hard registers if the new mode is legal, and occupies no more
+ registers than the old mode. */
+ if (regno < FIRST_PSEUDO_REGISTER)
+ return (HARD_REGNO_MODE_OK (regno, mode)
+ && (hard_regno_nregs[regno][GET_MODE (x)]
+ >= hard_regno_nregs[regno][mode]));
+
+ /* Or a pseudo that is only used once. */
+ return (REG_N_SETS (regno) == 1 && !added_sets
+ && !REG_USERVAR_P (x));
+}
+
+
+/* Check whether X, the destination of a set, refers to part of
+ the register specified by REG. */
+
+static bool
+reg_subword_p (rtx x, rtx reg)
+{
+ /* Check that reg is an integer mode register. */
+ if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
+ return false;
+
+ if (GET_CODE (x) == STRICT_LOW_PART
+ || GET_CODE (x) == ZERO_EXTRACT)
+ x = XEXP (x, 0);
+
+ return GET_CODE (x) == SUBREG
+ && SUBREG_REG (x) == reg
+ && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
+}
+
+
/* Try to combine the insns I1 and I2 into I3.
Here I1 and I2 appear earlier than I3.
I1 can be zero; then we combine just I2 into I3.
{
/* New patterns for I3 and I2, respectively. */
rtx newpat, newi2pat = 0;
+ rtvec newpat_vec_with_clobbers = 0;
int substed_i2 = 0, substed_i1 = 0;
/* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
int added_sets_1, added_sets_2;
rtx i2pat;
/* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
+ int i2dest_killed = 0, i1dest_killed = 0;
int i1_feeds_i3 = 0;
/* Notes that must be added to REG_NOTES in I3 and I2. */
rtx new_i3_notes, new_i2_notes;
if (cant_combine_insn_p (i3)
|| cant_combine_insn_p (i2)
|| (i1 && cant_combine_insn_p (i1))
+ || likely_spilled_retval_p (i3)
/* We also can't do anything if I3 has a
REG_LIBCALL note since we don't want to disrupt the contiguity of a
libcall. */
added_sets_2 = added_sets_1 = 0;
i2dest = SET_SRC (PATTERN (i3));
+ i2dest_killed = dead_or_set_p (i2, i2dest);
/* Replace the dest in I2 with our dest and make the resulting
insn the new pattern for I3. Then skip to where we
}
}
- /* If I2 is setting a double-word pseudo to a constant and I3 is setting
- one of those words to another constant, merge them by making a new
+ /* If I2 is setting a pseudo to a constant and I3 is setting some
+ sub-part of it to another constant, merge them by making a new
constant. */
if (i1 == 0
&& (temp = single_set (i2)) != 0
&& (GET_CODE (SET_SRC (temp)) == CONST_INT
|| GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
- && REG_P (SET_DEST (temp))
- && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
- && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
&& GET_CODE (PATTERN (i3)) == SET
- && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
- && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
- && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
- && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
- && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
+ && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
+ || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
+ && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
{
- HOST_WIDE_INT lo, hi;
+ rtx dest = SET_DEST (PATTERN (i3));
+ int offset = -1;
+ int width = 0;
- if (GET_CODE (SET_SRC (temp)) == CONST_INT)
- lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
- else
+ if (GET_CODE (dest) == STRICT_LOW_PART)
{
- lo = CONST_DOUBLE_LOW (SET_SRC (temp));
- hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
+ width = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)));
+ offset = 0;
}
-
- if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
+ else if (GET_CODE (dest) == ZERO_EXTRACT)
{
- /* We don't handle the case of the target word being wider
- than a host wide int. */
- gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
+ if (GET_CODE (XEXP (dest, 1)) == CONST_INT
+ && GET_CODE (XEXP (dest, 2)) == CONST_INT)
+ {
+ width = INTVAL (XEXP (dest, 1));
+ offset = INTVAL (XEXP (dest, 2));
- lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
- lo |= (INTVAL (SET_SRC (PATTERN (i3)))
- & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
+ if (BITS_BIG_ENDIAN)
+ offset = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)))
+ - width - offset;
+ }
}
- else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
- hi = INTVAL (SET_SRC (PATTERN (i3)));
- else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
+ else if (subreg_lowpart_p (dest))
{
- int sign = -(int) ((unsigned HOST_WIDE_INT) lo
- >> (HOST_BITS_PER_WIDE_INT - 1));
-
- lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
- (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
- lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
- (INTVAL (SET_SRC (PATTERN (i3)))));
- if (hi == sign)
- hi = lo < 0 ? -1 : 0;
+ width = GET_MODE_BITSIZE (GET_MODE (dest));
+ offset = 0;
+ }
+ /* ??? Preserve the original logic to handle setting the high word
+ of double-word pseudos, where inner is half the size of outer
+ but not the lowpart. This could be generalized by handling
+ SUBREG_BYTE, WORDS_BIG_ENDIAN and BYTES_BIG_ENDIAN ourselves.
+ Unfortunately this logic is tricky to get right and probably
+ not worth the effort. */
+ else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
+ == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
+ {
+ width = GET_MODE_BITSIZE (GET_MODE (dest));
+ offset = width;
}
- else
- /* We don't handle the case of the higher word not fitting
- entirely in either hi or lo. */
- gcc_unreachable ();
- combine_merges++;
- subst_insn = i3;
- subst_low_cuid = INSN_CUID (i2);
- added_sets_2 = added_sets_1 = 0;
- i2dest = SET_DEST (temp);
+ if (offset >= 0)
+ {
+ HOST_WIDE_INT mhi, ohi, ihi;
+ HOST_WIDE_INT mlo, olo, ilo;
+ rtx inner = SET_SRC (PATTERN (i3));
+ rtx outer = SET_SRC (temp);
+
+ if (GET_CODE (outer) == CONST_INT)
+ {
+ olo = INTVAL (outer);
+ ohi = olo < 0 ? -1 : 0;
+ }
+ else
+ {
+ olo = CONST_DOUBLE_LOW (outer);
+ ohi = CONST_DOUBLE_HIGH (outer);
+ }
+
+ if (GET_CODE (inner) == CONST_INT)
+ {
+ ilo = INTVAL (inner);
+ ihi = ilo < 0 ? -1 : 0;
+ }
+ else
+ {
+ ilo = CONST_DOUBLE_LOW (inner);
+ ihi = CONST_DOUBLE_HIGH (inner);
+ }
+
+ if (width < HOST_BITS_PER_WIDE_INT)
+ {
+ mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
+ mhi = 0;
+ }
+ else if (width < HOST_BITS_PER_WIDE_INT * 2)
+ {
+ mhi = ((unsigned HOST_WIDE_INT) 1
+ << (width - HOST_BITS_PER_WIDE_INT)) - 1;
+ mlo = -1;
+ }
+ else
+ {
+ mlo = -1;
+ mhi = -1;
+ }
+
+ ilo &= mlo;
+ ihi &= mhi;
+
+ if (offset >= HOST_BITS_PER_WIDE_INT)
+ {
+ mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
+ mlo = 0;
+ ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
+ ilo = 0;
+ }
+ else if (offset > 0)
+ {
+ mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
+ >> (HOST_BITS_PER_WIDE_INT - offset));
+ mlo = mlo << offset;
+ ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
+ >> (HOST_BITS_PER_WIDE_INT - offset));
+ ilo = ilo << offset;
+ }
- SUBST (SET_SRC (temp),
- immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
+ olo = (olo & ~mlo) | ilo;
+ ohi = (ohi & ~mhi) | ihi;
- newpat = PATTERN (i2);
- goto validate_replacement;
+ combine_merges++;
+ subst_insn = i3;
+ subst_low_cuid = INSN_CUID (i2);
+ added_sets_2 = added_sets_1 = 0;
+ i2dest = SET_DEST (temp);
+ i2dest_killed = dead_or_set_p (i2, i2dest);
+
+ SUBST (SET_SRC (temp),
+ immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
+
+ newpat = PATTERN (i2);
+ goto validate_replacement;
+ }
}
#ifndef HAVE_cc0
i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
+ i2dest_killed = dead_or_set_p (i2, i2dest);
+ i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
/* See if I1 directly feeds into I3. It does if I1DEST is not used
in I2SRC. */
subst_insn = i3;
- /* It is possible that the source of I2 or I1 may be performing an
- unneeded operation, such as a ZERO_EXTEND of something that is known
- to have the high part zero. Handle that case by letting subst look at
- the innermost one of them.
-
- Another way to do this would be to have a function that tries to
- simplify a single insn instead of merging two or more insns. We don't
- do this because of the potential of infinite loops and because
- of the potential extra memory required. However, doing it the way
- we are is a bit of a kludge and doesn't catch all cases.
-
- But only do this if -fexpensive-optimizations since it slows things down
- and doesn't usually win. */
-
- if (flag_expensive_optimizations)
- {
- /* Pass pc_rtx so no substitutions are done, just simplifications. */
- if (i1)
- {
- subst_low_cuid = INSN_CUID (i1);
- i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
- }
- else
- {
- subst_low_cuid = INSN_CUID (i2);
- i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
- }
- }
-
#ifndef HAVE_cc0
/* Many machines that don't use CC0 have insns that can both perform an
arithmetic operation and set the condition code. These operations will
i2src, const0_rtx))
!= GET_MODE (SET_DEST (newpat))))
{
- unsigned int regno = REGNO (SET_DEST (newpat));
- rtx new_dest = gen_rtx_REG (compare_mode, regno);
-
- if (regno < FIRST_PSEUDO_REGISTER
- || (REG_N_SETS (regno) == 1 && ! added_sets_2
- && ! REG_USERVAR_P (SET_DEST (newpat))))
+ if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
+ compare_mode))
{
- if (regno >= FIRST_PSEUDO_REGISTER)
- SUBST (regno_reg_rtx[regno], new_dest);
+ unsigned int regno = REGNO (SET_DEST (newpat));
+ rtx new_dest;
+
+ if (regno < FIRST_PSEUDO_REGISTER)
+ new_dest = gen_rtx_REG (compare_mode, regno);
+ else
+ {
+ SUBST_MODE (regno_reg_rtx[regno], compare_mode);
+ new_dest = regno_reg_rtx[regno];
+ }
SUBST (SET_DEST (newpat), new_dest);
SUBST (XEXP (*cc_use, 0), new_dest);
else
#endif
{
+ /* It is possible that the source of I2 or I1 may be performing
+ an unneeded operation, such as a ZERO_EXTEND of something
+ that is known to have the high part zero. Handle that case
+ by letting subst look at the innermost one of them.
+
+ Another way to do this would be to have a function that tries
+ to simplify a single insn instead of merging two or more
+ insns. We don't do this because of the potential of infinite
+ loops and because of the potential extra memory required.
+ However, doing it the way we are is a bit of a kludge and
+ doesn't catch all cases.
+
+ But only do this if -fexpensive-optimizations since it slows
+ things down and doesn't usually win.
+
+ This is not done in the COMPARE case above because the
+ unmodified I2PAT is used in the PARALLEL and so a pattern
+ with a modified I2SRC would not match. */
+
+ if (flag_expensive_optimizations)
+ {
+ /* Pass pc_rtx so no substitutions are done, just
+ simplifications. */
+ if (i1)
+ {
+ subst_low_cuid = INSN_CUID (i1);
+ i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
+ }
+ else
+ {
+ subst_low_cuid = INSN_CUID (i2);
+ i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
+ }
+ }
+
n_occurrences = 0; /* `subst' counts here */
/* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
|| (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
&& (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
> 1))
- /* Fail if we tried to make a new register (we used to abort, but there's
- really no reason to). */
+ /* Fail if we tried to make a new register. */
|| max_reg_num () != maxreg
/* Fail if we couldn't do something and have a CLOBBER. */
|| GET_CODE (newpat) == CLOBBER
/* Note which hard regs this insn has as inputs. */
mark_used_regs_combine (newpat);
+ /* If recog_for_combine fails, it strips existing clobbers. If we'll
+ consider splitting this pattern, we might need these clobbers. */
+ if (i1 && GET_CODE (newpat) == PARALLEL
+ && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
+ {
+ int len = XVECLEN (newpat, 0);
+
+ newpat_vec_with_clobbers = rtvec_alloc (len);
+ for (i = 0; i < len; i++)
+ RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
+ }
+
/* Is the result of combination a valid instruction? */
insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
&& asm_noperands (newpat) < 0)
{
rtx m_split, *split;
- rtx ni2dest = i2dest;
/* See if the MD file can split NEWPAT. If it can't, see if letting it
use I2DEST as a scratch register will help. In the latter case,
possible to try that as a scratch reg. This would require adding
more code to make it work though. */
- if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
+ if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
{
- /* If I2DEST is a hard register or the only use of a pseudo,
- we can change its mode. */
- if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
- && GET_MODE (SET_DEST (newpat)) != VOIDmode
- && REG_P (i2dest)
- && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
- || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
- && ! REG_USERVAR_P (i2dest))))
- ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
- REGNO (i2dest));
+ enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
+ /* First try to split using the original register as a
+ scratch register. */
m_split = split_insns (gen_rtx_PARALLEL
(VOIDmode,
gen_rtvec (2, newpat,
gen_rtx_CLOBBER (VOIDmode,
- ni2dest))),
+ i2dest))),
i3);
- /* If the split with the mode-changed register didn't work, try
- the original register. */
- if (! m_split && ni2dest != i2dest)
+
+ /* If that didn't work, try changing the mode of I2DEST if
+ we can. */
+ if (m_split == 0
+ && new_mode != GET_MODE (i2dest)
+ && new_mode != VOIDmode
+ && can_change_dest_mode (i2dest, added_sets_2, new_mode))
{
- ni2dest = i2dest;
+ enum machine_mode old_mode = GET_MODE (i2dest);
+ rtx ni2dest;
+
+ if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
+ ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
+ else
+ {
+ SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
+ ni2dest = regno_reg_rtx[REGNO (i2dest)];
+ }
+
m_split = split_insns (gen_rtx_PARALLEL
(VOIDmode,
gen_rtvec (2, newpat,
gen_rtx_CLOBBER (VOIDmode,
- i2dest))),
+ ni2dest))),
i3);
+
+ if (m_split == 0
+ && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
+ {
+ struct undo *buf;
+
+ PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
+ buf = undobuf.undos;
+ undobuf.undos = buf->next;
+ buf->next = undobuf.frees;
+ undobuf.frees = buf;
+ }
}
}
+ /* If recog_for_combine has discarded clobbers, try to use them
+ again for the split. */
+ if (m_split == 0 && newpat_vec_with_clobbers)
+ m_split
+ = split_insns (gen_rtx_PARALLEL (VOIDmode,
+ newpat_vec_with_clobbers), i3);
+
if (m_split && NEXT_INSN (m_split) == NULL_RTX)
{
m_split = PATTERN (m_split);
i3set = single_set (NEXT_INSN (m_split));
i2set = single_set (m_split);
- /* In case we changed the mode of I2DEST, replace it in the
- pseudo-register table here. We can't do it above in case this
- code doesn't get executed and we do a split the other way. */
-
- if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
- SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
-
i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
/* If I2 or I3 has multiple SETs, we won't know how to track
&& REG_P (i2dest)
#endif
/* We need I2DEST in the proper mode. If it is a hard register
- or the only use of a pseudo, we can change its mode. */
+ or the only use of a pseudo, we can change its mode.
+ Make sure we don't change a hard register to have a mode that
+ isn't valid for it, or change the number of registers. */
&& (GET_MODE (*split) == GET_MODE (i2dest)
|| GET_MODE (*split) == VOIDmode
- || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
- || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
- && ! REG_USERVAR_P (i2dest)))
+ || can_change_dest_mode (i2dest, added_sets_2,
+ GET_MODE (*split)))
&& (next_real_insn (i2) == i3
|| ! use_crosses_set_p (*split, INSN_CUID (i2)))
/* We can't overwrite I2DEST if its value is still used by
rtx newdest = i2dest;
enum rtx_code split_code = GET_CODE (*split);
enum machine_mode split_mode = GET_MODE (*split);
+ bool subst_done = false;
+ newi2pat = NULL_RTX;
/* Get NEWDEST as a register in the proper mode. We have already
validated that we can do this. */
if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
{
- newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
-
- if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
- SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
+ if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
+ newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
+ else
+ {
+ SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
+ newdest = regno_reg_rtx[REGNO (i2dest)];
+ }
}
/* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
}
#endif
- newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
- SUBST (*split, newdest);
+ /* Attempt to split binary operators using arithmetic identities. */
+ if (BINARY_P (SET_SRC (newpat))
+ && split_mode == GET_MODE (SET_SRC (newpat))
+ && ! side_effects_p (SET_SRC (newpat)))
+ {
+ rtx setsrc = SET_SRC (newpat);
+ enum machine_mode mode = GET_MODE (setsrc);
+ enum rtx_code code = GET_CODE (setsrc);
+ rtx src_op0 = XEXP (setsrc, 0);
+ rtx src_op1 = XEXP (setsrc, 1);
+
+ /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
+ if (rtx_equal_p (src_op0, src_op1))
+ {
+ newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
+ SUBST (XEXP (setsrc, 0), newdest);
+ SUBST (XEXP (setsrc, 1), newdest);
+ subst_done = true;
+ }
+ /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
+ else if ((code == PLUS || code == MULT)
+ && GET_CODE (src_op0) == code
+ && GET_CODE (XEXP (src_op0, 0)) == code
+ && (INTEGRAL_MODE_P (mode)
+ || (FLOAT_MODE_P (mode)
+ && flag_unsafe_math_optimizations)))
+ {
+ rtx p = XEXP (XEXP (src_op0, 0), 0);
+ rtx q = XEXP (XEXP (src_op0, 0), 1);
+ rtx r = XEXP (src_op0, 1);
+ rtx s = src_op1;
+
+ /* Split both "((X op Y) op X) op Y" and
+ "((X op Y) op Y) op X" as "T op T" where T is
+ "X op Y". */
+ if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
+ || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
+ {
+ newi2pat = gen_rtx_SET (VOIDmode, newdest,
+ XEXP (src_op0, 0));
+ SUBST (XEXP (setsrc, 0), newdest);
+ SUBST (XEXP (setsrc, 1), newdest);
+ subst_done = true;
+ }
+ /* Split "((X op X) op Y) op Y)" as "T op T" where
+ T is "X op Y". */
+ else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
+ {
+ rtx tmp = simplify_gen_binary (code, mode, p, r);
+ newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
+ SUBST (XEXP (setsrc, 0), newdest);
+ SUBST (XEXP (setsrc, 1), newdest);
+ subst_done = true;
+ }
+ }
+ }
+
+ if (!subst_done)
+ {
+ newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
+ SUBST (*split, newdest);
+ }
+
i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
+ /* recog_for_combine might have added CLOBBERs to newi2pat.
+ Make sure NEWPAT does not depend on the clobbered regs. */
+ if (GET_CODE (newi2pat) == PARALLEL)
+ for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
+ if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
+ {
+ rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
+ if (reg_overlap_mentioned_p (reg, newpat))
+ {
+ undo_all ();
+ return 0;
+ }
+ }
+
/* If the split point was a MULT and we didn't have one before,
don't use one now. */
if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
distribute_notes (new_other_notes, undobuf.other_insn,
- undobuf.other_insn, NULL_RTX);
+ undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
}
#ifdef HAVE_cc0
/* If I2 is the CC0 setter and I3 is the CC0 user then check whether
rtx i3links, i2links, i1links = 0;
rtx midnotes = 0;
unsigned int regno;
+ /* Compute which registers we expect to eliminate. newi2pat may be setting
+ either i3dest or i2dest, so we must check it. Also, i1dest may be the
+ same as i3dest, in which case newi2pat may be setting i1dest. */
+ rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
+ || i2dest_in_i2src || i2dest_in_i1src
+ || !i2dest_killed
+ ? 0 : i2dest);
+ rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
+ || (newi2pat && reg_set_p (i1dest, newi2pat))
+ || !i1dest_killed
+ ? 0 : i1dest);
/* Get the old REG_NOTES and LOG_LINKS from all our insns and
clear them. */
/* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
if (i3notes)
- distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
+ distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
+ elim_i2, elim_i1);
if (i2notes)
- distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
+ distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
+ elim_i2, elim_i1);
if (i1notes)
- distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
+ distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
+ elim_i2, elim_i1);
if (midnotes)
- distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
+ distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
+ elim_i2, elim_i1);
/* Distribute any notes added to I2 or I3 by recog_for_combine. We
know these are REG_UNUSED and want them to go to the desired insn,
if (REG_P (XEXP (temp, 0)))
REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
- distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
+ distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
}
if (new_i3_notes)
if (REG_P (XEXP (temp, 0)))
REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
- distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
+ distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
}
/* If I3DEST was used in I3SRC, it really died in I3. We may need to
if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
NULL_RTX),
- NULL_RTX, i2, NULL_RTX);
+ NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
else
distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
NULL_RTX),
- NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
+ NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
+ elim_i2, elim_i1);
}
if (i2dest_in_i2src)
if (newi2pat && reg_set_p (i2dest, newi2pat))
distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
- NULL_RTX, i2, NULL_RTX);
+ NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
else
distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
- NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
+ NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
+ NULL_RTX, NULL_RTX);
}
if (i1dest_in_i1src)
if (newi2pat && reg_set_p (i1dest, newi2pat))
distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
- NULL_RTX, i2, NULL_RTX);
+ NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
else
distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
- NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
+ NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
+ NULL_RTX, NULL_RTX);
}
distribute_links (i3links);
for (undo = undobuf.undos; undo; undo = next)
{
next = undo->next;
- if (undo->is_int)
- *undo->where.i = undo->old_contents.i;
- else
- *undo->where.r = undo->old_contents.r;
+ switch (undo->kind)
+ {
+ case UNDO_RTX:
+ *undo->where.r = undo->old_contents.r;
+ break;
+ case UNDO_INT:
+ *undo->where.i = undo->old_contents.i;
+ break;
+ case UNDO_MODE:
+ PUT_MODE (*undo->where.r, undo->old_contents.m);
+ break;
+ default:
+ gcc_unreachable ();
+ }
undo->next = undobuf.frees;
undobuf.frees = undo;
rtx dest = XEXP (SET_DEST (x), 0);
enum machine_mode mode = GET_MODE (dest);
unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
+ rtx or_mask;
if (BITS_BIG_ENDIAN)
pos = GET_MODE_BITSIZE (mode) - len - pos;
+ or_mask = gen_int_mode (src << pos, mode);
if (src == mask)
SUBST (SET_SRC (x),
- gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
+ simplify_gen_binary (IOR, mode, dest, or_mask));
else
- SUBST (SET_SRC (x),
- gen_binary (IOR, mode,
- gen_binary (AND, mode, dest,
- gen_int_mode (~(mask << pos),
- mode)),
- GEN_INT (src << pos)));
+ {
+ rtx negmask = gen_int_mode (~(mask << pos), mode);
+ SUBST (SET_SRC (x),
+ simplify_gen_binary (IOR, mode,
+ simplify_gen_binary (AND, mode,
+ dest, negmask),
+ or_mask));
+ }
SUBST (SET_DEST (x), dest);
enum rtx_code code = GET_CODE (x);
enum machine_mode mode = GET_MODE (x);
rtx temp;
- rtx reversed;
int i;
/* If this is a commutative operation, put a constant last and a complex
SUBST (XEXP (x, 1), temp);
}
- /* If this is a PLUS, MINUS, or MULT, and the first operand is the
- sign extension of a PLUS with a constant, reverse the order of the sign
- extension and the addition. Note that this not the same as the original
- code, but overflow is undefined for signed values. Also note that the
- PLUS will have been partially moved "inside" the sign-extension, so that
- the first operand of X will really look like:
- (ashiftrt (plus (ashift A C4) C5) C4).
- We convert this to
- (plus (ashiftrt (ashift A C4) C2) C4)
- and replace the first operand of X with that expression. Later parts
- of this function may simplify the expression further.
-
- For example, if we start with (mult (sign_extend (plus A C1)) C2),
- we swap the SIGN_EXTEND and PLUS. Later code will apply the
- distributive law to produce (plus (mult (sign_extend X) C1) C3).
-
- We do this to simplify address expressions. */
-
- if ((code == PLUS || code == MINUS || code == MULT)
- && GET_CODE (XEXP (x, 0)) == ASHIFTRT
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
- && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
- && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
- && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
- && (temp = simplify_binary_operation (ASHIFTRT, mode,
- XEXP (XEXP (XEXP (x, 0), 0), 1),
- XEXP (XEXP (x, 0), 1))) != 0)
- {
- rtx new
- = simplify_shift_const (NULL_RTX, ASHIFT, mode,
- XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
- INTVAL (XEXP (XEXP (x, 0), 1)));
-
- new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
- INTVAL (XEXP (XEXP (x, 0), 1)));
-
- SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
- }
-
/* If this is a simple operation applied to an IF_THEN_ELSE, try
applying it to the arms of the IF_THEN_ELSE. This often simplifies
things. Check for cases where both arms are testing the same
/* If the result values are STORE_FLAG_VALUE and zero, we can
just make the comparison operation. */
if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
- x = gen_binary (cond_code, mode, cond, cop1);
+ x = simplify_gen_relational (cond_code, mode, VOIDmode,
+ cond, cop1);
else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
&& ((reversed = reversed_comparison_code_parts
(cond_code, cond, cop1, NULL))
!= UNKNOWN))
- x = gen_binary (reversed, mode, cond, cop1);
+ x = simplify_gen_relational (reversed, mode, VOIDmode,
+ cond, cop1);
/* Likewise, we can make the negate of a comparison operation
if the result values are - STORE_FLAG_VALUE and zero. */
&& INTVAL (true_rtx) == - STORE_FLAG_VALUE
&& false_rtx == const0_rtx)
x = simplify_gen_unary (NEG, mode,
- gen_binary (cond_code, mode, cond,
- cop1),
+ simplify_gen_relational (cond_code,
+ mode, VOIDmode,
+ cond, cop1),
mode);
else if (GET_CODE (false_rtx) == CONST_INT
&& INTVAL (false_rtx) == - STORE_FLAG_VALUE
(cond_code, cond, cop1, NULL))
!= UNKNOWN))
x = simplify_gen_unary (NEG, mode,
- gen_binary (reversed, mode,
- cond, cop1),
+ simplify_gen_relational (reversed,
+ mode, VOIDmode,
+ cond, cop1),
mode);
else
return gen_rtx_IF_THEN_ELSE (mode,
- gen_binary (cond_code, VOIDmode,
- cond, cop1),
+ simplify_gen_relational (cond_code,
+ mode,
+ VOIDmode,
+ cond,
+ cop1),
true_rtx, false_rtx);
code = GET_CODE (x);
}
if (inner)
- return gen_binary (code, mode, other, inner);
+ return simplify_gen_binary (code, mode, other, inner);
}
}
break;
- case NOT:
- if (GET_CODE (XEXP (x, 0)) == SUBREG
- && subreg_lowpart_p (XEXP (x, 0))
- && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
- < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
- && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
- && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
- {
- enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
-
- x = gen_rtx_ROTATE (inner_mode,
- simplify_gen_unary (NOT, inner_mode, const1_rtx,
- inner_mode),
- XEXP (SUBREG_REG (XEXP (x, 0)), 1));
- return gen_lowpart (mode, x);
- }
-
- /* Apply De Morgan's laws to reduce number of patterns for machines
- with negating logical insns (and-not, nand, etc.). If result has
- only one NOT, put it first, since that is how the patterns are
- coded. */
-
- if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
- {
- rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
- enum machine_mode op_mode;
-
- op_mode = GET_MODE (in1);
- in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
-
- op_mode = GET_MODE (in2);
- if (op_mode == VOIDmode)
- op_mode = mode;
- in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
-
- if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
- {
- rtx tem = in2;
- in2 = in1; in1 = tem;
- }
-
- return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
- mode, in1, in2);
- }
- break;
-
case NEG:
- /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
- if (GET_CODE (XEXP (x, 0)) == XOR
- && XEXP (XEXP (x, 0), 1) == const1_rtx
- && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
- return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
-
temp = expand_compound_operation (XEXP (x, 0));
/* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
if (GET_CODE (temp) == ASHIFTRT
&& GET_CODE (XEXP (temp, 1)) == CONST_INT
&& INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
- return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
+ return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
INTVAL (XEXP (temp, 1)));
/* If X has only a single bit that might be nonzero, say, bit I, convert
GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
SUBST (XEXP (x, 0),
force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
- GET_MODE_MASK (mode), NULL_RTX, 0));
-
- /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
- if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
- || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
- && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
- return XEXP (XEXP (x, 0), 0);
-
- /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
- (OP:SI foo:SI) if OP is NEG or ABS. */
- if ((GET_CODE (XEXP (x, 0)) == ABS
- || GET_CODE (XEXP (x, 0)) == NEG)
- && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
- || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
- && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
- return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
- XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
-
- /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
- (truncate:SI x). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
- && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
- && subreg_lowpart_p (XEXP (x, 0)))
- return SUBREG_REG (XEXP (x, 0));
+ GET_MODE_MASK (mode), 0));
- /* If we know that the value is already truncated, we can
- replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
- is nonzero for the corresponding modes. But don't do this
- for an (LSHIFTRT (MULT ...)) since this will cause problems
- with the umulXi3_highpart patterns. */
- if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
- GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
- && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
- >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
- && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
- return gen_lowpart (mode, XEXP (x, 0));
-
- /* A truncate of a comparison can be replaced with a subreg if
- STORE_FLAG_VALUE permits. This is like the previous test,
- but it works even if the comparison is done in a mode larger
- than HOST_BITS_PER_WIDE_INT. */
- if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
- && COMPARISON_P (XEXP (x, 0))
- && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
- return gen_lowpart (mode, XEXP (x, 0));
-
- /* Similarly, a truncate of a register whose value is a
- comparison can be replaced with a subreg if STORE_FLAG_VALUE
- permits. */
+ /* Similarly to what we do in simplify-rtx.c, a truncate of a register
+ whose value is a comparison can be replaced with a subreg if
+ STORE_FLAG_VALUE permits. */
if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
&& ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
&& (temp = get_last_value (XEXP (x, 0)))
&& COMPARISON_P (temp))
return gen_lowpart (mode, XEXP (x, 0));
-
- break;
-
- case FLOAT_TRUNCATE:
- /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
- if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
- && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
- return XEXP (XEXP (x, 0), 0);
-
- /* (float_truncate:SF (float_truncate:DF foo:XF))
- = (float_truncate:SF foo:XF).
- This may eliminate double rounding, so it is unsafe.
-
- (float_truncate:SF (float_extend:XF foo:DF))
- = (float_truncate:SF foo:DF).
-
- (float_truncate:DF (float_extend:XF foo:SF))
- = (float_extend:SF foo:DF). */
- if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
- && flag_unsafe_math_optimizations)
- || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
- return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
- 0)))
- > GET_MODE_SIZE (mode)
- ? FLOAT_TRUNCATE : FLOAT_EXTEND,
- mode,
- XEXP (XEXP (x, 0), 0), mode);
-
- /* (float_truncate (float x)) is (float x) */
- if (GET_CODE (XEXP (x, 0)) == FLOAT
- && (flag_unsafe_math_optimizations
- || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
- >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
- - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
- GET_MODE (XEXP (XEXP (x, 0), 0)))))))
- return simplify_gen_unary (FLOAT, mode,
- XEXP (XEXP (x, 0), 0),
- GET_MODE (XEXP (XEXP (x, 0), 0)));
-
- /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
- (OP:SF foo:SF) if OP is NEG or ABS. */
- if ((GET_CODE (XEXP (x, 0)) == ABS
- || GET_CODE (XEXP (x, 0)) == NEG)
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
- && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
- return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
- XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
-
- /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
- is (float_truncate:SF x). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
- && subreg_lowpart_p (XEXP (x, 0))
- && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
- return SUBREG_REG (XEXP (x, 0));
break;
- case FLOAT_EXTEND:
- /* (float_extend (float_extend x)) is (float_extend x)
-
- (float_extend (float x)) is (float x) assuming that double
- rounding can't happen.
- */
- if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
- || (GET_CODE (XEXP (x, 0)) == FLOAT
- && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
- >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
- - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
- GET_MODE (XEXP (XEXP (x, 0), 0)))))))
- return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
- XEXP (XEXP (x, 0), 0),
- GET_MODE (XEXP (XEXP (x, 0), 0)));
- break;
#ifdef HAVE_cc0
case COMPARE:
/* Convert (compare FOO (const_int 0)) to FOO unless we aren't
#endif
case PLUS:
- /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
- */
- if (GET_CODE (XEXP (x, 0)) == MULT
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
- {
- rtx in1, in2;
-
- in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
- in2 = XEXP (XEXP (x, 0), 1);
- return gen_binary (MINUS, mode, XEXP (x, 1),
- gen_binary (MULT, mode, in1, in2));
- }
-
- /* If we have (plus (plus (A const) B)), associate it so that CONST is
- outermost. That's because that's the way indexed addresses are
- supposed to appear. This code used to check many more cases, but
- they are now checked elsewhere. */
- if (GET_CODE (XEXP (x, 0)) == PLUS
- && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
- return gen_binary (PLUS, mode,
- gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
- XEXP (x, 1)),
- XEXP (XEXP (x, 0), 1));
-
/* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
when c is (const_int (pow2 + 1) / 2) is a sign extension of a
bit-field and can be replaced by either a sign_extend or a
GET_MODE_BITSIZE (mode) - (i + 1)),
GET_MODE_BITSIZE (mode) - (i + 1));
- /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
- C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
- is 1. This produces better code than the alternative immediately
- below. */
- if (COMPARISON_P (XEXP (x, 0))
- && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
- || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
- && (reversed = reversed_comparison (XEXP (x, 0), mode,
- XEXP (XEXP (x, 0), 0),
- XEXP (XEXP (x, 0), 1))))
- return
- simplify_gen_unary (NEG, mode, reversed, mode);
-
/* If only the low-order bit of X is possibly nonzero, (plus x -1)
can become (ashiftrt (ashift (xor x 1) C) C) where C is
the bitsize of the mode - 1. This allows simplification of
& nonzero_bits (XEXP (x, 1), mode)) == 0)
{
/* Try to simplify the expression further. */
- rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
+ rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
temp = combine_simplify_rtx (tor, mode, in_dest);
/* If we could, great. If not, do not go ahead with the IOR
break;
case MINUS:
- /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
- by reversing the comparison code if valid. */
- if (STORE_FLAG_VALUE == 1
- && XEXP (x, 0) == const1_rtx
- && COMPARISON_P (XEXP (x, 1))
- && (reversed = reversed_comparison (XEXP (x, 1), mode,
- XEXP (XEXP (x, 1), 0),
- XEXP (XEXP (x, 1), 1))))
- return reversed;
-
/* (minus <foo> (and <foo> (const_int -pow2))) becomes
(and <foo> (const_int pow2-1)) */
if (GET_CODE (XEXP (x, 1)) == AND
&& rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
-INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
-
- /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
- */
- if (GET_CODE (XEXP (x, 1)) == MULT
- && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
- {
- rtx in1, in2;
-
- in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
- in2 = XEXP (XEXP (x, 1), 1);
- return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
- XEXP (x, 0));
- }
-
- /* Canonicalize (minus (neg A) (mult B C)) to
- (minus (mult (neg B) C) A). */
- if (GET_CODE (XEXP (x, 1)) == MULT
- && GET_CODE (XEXP (x, 0)) == NEG)
- {
- rtx in1, in2;
-
- in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
- in2 = XEXP (XEXP (x, 1), 1);
- return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
- XEXP (XEXP (x, 0), 0));
- }
-
- /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
- integers. */
- if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
- return gen_binary (MINUS, mode,
- gen_binary (MINUS, mode, XEXP (x, 0),
- XEXP (XEXP (x, 1), 0)),
- XEXP (XEXP (x, 1), 1));
break;
case MULT:
if (GET_CODE (XEXP (x, 0)) == PLUS)
{
- x = apply_distributive_law
- (gen_binary (PLUS, mode,
- gen_binary (MULT, mode,
- XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
- gen_binary (MULT, mode,
- XEXP (XEXP (x, 0), 1),
- copy_rtx (XEXP (x, 1)))));
-
- if (GET_CODE (x) != MULT)
- return x;
+ rtx result = distribute_and_simplify_rtx (x, 0);
+ if (result)
+ return result;
}
+
/* Try simplify a*(b/c) as (a*b)/c. */
if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
&& GET_CODE (XEXP (x, 0)) == DIV)
XEXP (XEXP (x, 0), 0),
XEXP (x, 1));
if (tem)
- return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
+ return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
}
break;
&& nonzero_bits (op0, mode) == 1)
{
op0 = expand_compound_operation (op0);
- return gen_binary (XOR, mode,
- gen_lowpart (mode, op0),
- const1_rtx);
+ return simplify_gen_binary (XOR, mode,
+ gen_lowpart (mode, op0),
+ const1_rtx);
}
else if (STORE_FLAG_VALUE == 1
case AND:
case IOR:
- case XOR:
return simplify_logical (x);
- case ABS:
- /* (abs (neg <foo>)) -> (abs <foo>) */
- if (GET_CODE (XEXP (x, 0)) == NEG)
- SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
-
- /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
- do nothing. */
- if (GET_MODE (XEXP (x, 0)) == VOIDmode)
- break;
-
- /* If operand is something known to be positive, ignore the ABS. */
- if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
- || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
- <= HOST_BITS_PER_WIDE_INT)
- && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
- & ((HOST_WIDE_INT) 1
- << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
- == 0)))
- return XEXP (x, 0);
-
- /* If operand is known to be only -1 or 0, convert ABS to NEG. */
- if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
- return gen_rtx_NEG (mode, XEXP (x, 0));
-
- break;
-
- case FFS:
- /* (ffs (*_extend <X>)) = (ffs <X>) */
- if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
- || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
- SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
- break;
-
- case POPCOUNT:
- case PARITY:
- /* (pop* (zero_extend <X>)) = (pop* <X>) */
- if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
- SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
- break;
-
- case FLOAT:
- /* (float (sign_extend <X>)) = (float <X>). */
- if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
- SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
- break;
-
case ASHIFT:
case LSHIFTRT:
case ASHIFTRT:
((HOST_WIDE_INT) 1
<< exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
- 1,
- NULL_RTX, 0));
- break;
-
- case VEC_SELECT:
- {
- rtx op0 = XEXP (x, 0);
- rtx op1 = XEXP (x, 1);
- int len;
-
- gcc_assert (GET_CODE (op1) == PARALLEL);
- len = XVECLEN (op1, 0);
- if (len == 1
- && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
- && GET_CODE (op0) == VEC_CONCAT)
- {
- int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
-
- /* Try to find the element in the VEC_CONCAT. */
- for (;;)
- {
- if (GET_MODE (op0) == GET_MODE (x))
- return op0;
- if (GET_CODE (op0) == VEC_CONCAT)
- {
- HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
- if (op0_size < offset)
- op0 = XEXP (op0, 0);
- else
- {
- offset -= op0_size;
- op0 = XEXP (op0, 1);
- }
- }
- else
- break;
- }
- }
- }
-
+ 0));
break;
default:
/* Simplify storing of the truth value. */
if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
- return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
+ return simplify_gen_relational (true_code, mode, VOIDmode,
+ XEXP (cond, 0), XEXP (cond, 1));
/* Also when the truth value has to be reversed. */
if (comparison_p
&& true_rtx == const0_rtx && false_rtx == const_true_rtx
- && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
- XEXP (cond, 1))))
+ && (reversed = reversed_comparison (cond, mode)))
return reversed;
/* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
comparisons and see if that says anything about the value of each arm. */
if (comparison_p
- && ((false_code = combine_reversed_comparison_code (cond))
+ && ((false_code = reversed_comparison_code (cond, NULL))
!= UNKNOWN)
&& REG_P (XEXP (cond, 0)))
{
the false arm is more complicated than the true arm. */
if (comparison_p
- && combine_reversed_comparison_code (cond) != UNKNOWN
+ && reversed_comparison_code (cond, NULL) != UNKNOWN
&& (true_rtx == pc_rtx
|| (CONSTANT_P (true_rtx)
&& GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
|| rtx_equal_p (false_rtx, XEXP (cond, 0))))
{
true_code = reversed_comparison_code (cond, NULL);
- SUBST (XEXP (x, 0),
- reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
- XEXP (cond, 1)));
-
+ SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
SUBST (XEXP (x, 1), false_rtx);
SUBST (XEXP (x, 2), true_rtx);
{
case GE:
case GT:
- return gen_binary (SMAX, mode, true_rtx, false_rtx);
+ return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
case LE:
case LT:
- return gen_binary (SMIN, mode, true_rtx, false_rtx);
+ return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
case GEU:
case GTU:
- return gen_binary (UMAX, mode, true_rtx, false_rtx);
+ return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
case LEU:
case LTU:
- return gen_binary (UMIN, mode, true_rtx, false_rtx);
+ return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
default:
break;
}
if (z)
{
- temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
+ temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
+ cond_op0, cond_op1),
pc_rtx, pc_rtx, 0, 0);
- temp = gen_binary (MULT, m, temp,
- gen_binary (MULT, m, c1, const_true_rtx));
+ temp = simplify_gen_binary (MULT, m, temp,
+ simplify_gen_binary (MULT, m, c1,
+ const_true_rtx));
temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
- temp = gen_binary (op, m, gen_lowpart (m, z), temp);
+ temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
if (extend_op != UNKNOWN)
temp = simplify_gen_unary (extend_op, mode, temp, m);
if (GET_MODE_CLASS (mode) == MODE_INT
&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
{
- src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
+ src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
SUBST (SET_SRC (x), src);
}
which case we can safely change its mode. */
if (compare_mode != GET_MODE (dest))
{
- unsigned int regno = REGNO (dest);
- rtx new_dest = gen_rtx_REG (compare_mode, regno);
-
- if (regno < FIRST_PSEUDO_REGISTER
- || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
+ if (can_change_dest_mode (dest, 0, compare_mode))
{
- if (regno >= FIRST_PSEUDO_REGISTER)
- SUBST (regno_reg_rtx[regno], new_dest);
+ unsigned int regno = REGNO (dest);
+ rtx new_dest;
+
+ if (regno < FIRST_PSEUDO_REGISTER)
+ new_dest = gen_rtx_REG (compare_mode, regno);
+ else
+ {
+ SUBST_MODE (regno_reg_rtx[regno], compare_mode);
+ new_dest = regno_reg_rtx[regno];
+ }
SUBST (SET_DEST (x), new_dest);
SUBST (XEXP (*cc_use, 0), new_dest);
PUT_CODE (*cc_use, old_code);
other_changed = 0;
- op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
+ op0 = simplify_gen_binary (XOR, GET_MODE (op0),
+ op0, GEN_INT (mask));
}
}
}
SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
src = SET_SRC (x);
}
+ else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
+ {
+ SUBST(SET_SRC (x), op0);
+ src = SET_SRC (x);
+ }
else
{
/* Otherwise, update the COMPARE if needed. */
&& rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
- term2 = gen_binary (AND, GET_MODE (src),
- XEXP (XEXP (src, 0), 0), true_rtx);
- term3 = gen_binary (AND, GET_MODE (src),
- simplify_gen_unary (NOT, GET_MODE (src),
- XEXP (XEXP (src, 0), 0),
- GET_MODE (src)),
- false_rtx);
+ term2 = simplify_gen_binary (AND, GET_MODE (src),
+ XEXP (XEXP (src, 0), 0), true_rtx);
+ term3 = simplify_gen_binary (AND, GET_MODE (src),
+ simplify_gen_unary (NOT, GET_MODE (src),
+ XEXP (XEXP (src, 0), 0),
+ GET_MODE (src)),
+ false_rtx);
SUBST (SET_SRC (x),
- gen_binary (IOR, GET_MODE (src),
- gen_binary (IOR, GET_MODE (src), term1, term2),
- term3));
+ simplify_gen_binary (IOR, GET_MODE (src),
+ simplify_gen_binary (IOR, GET_MODE (src),
+ term1, term2),
+ term3));
src = SET_SRC (x);
}
enum machine_mode mode = GET_MODE (x);
rtx op0 = XEXP (x, 0);
rtx op1 = XEXP (x, 1);
- rtx reversed;
switch (GET_CODE (x))
{
case AND:
- /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
- insn (and may simplify more). */
- if (GET_CODE (op0) == XOR
- && rtx_equal_p (XEXP (op0, 0), op1)
- && ! side_effects_p (op1))
- x = gen_binary (AND, mode,
- simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
- op1);
-
- if (GET_CODE (op0) == XOR
- && rtx_equal_p (XEXP (op0, 1), op1)
- && ! side_effects_p (op1))
- x = gen_binary (AND, mode,
- simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
- op1);
-
- /* Similarly for (~(A ^ B)) & A. */
- if (GET_CODE (op0) == NOT
- && GET_CODE (XEXP (op0, 0)) == XOR
- && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
- && ! side_effects_p (op1))
- x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
-
- if (GET_CODE (op0) == NOT
- && GET_CODE (XEXP (op0, 0)) == XOR
- && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
- && ! side_effects_p (op1))
- x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
-
/* We can call simplify_and_const_int only if we don't lose
any (sign) bits when converting INTVAL (op1) to
"unsigned HOST_WIDE_INT". */
|| INTVAL (op1) > 0))
{
x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
-
- /* If we have (ior (and (X C1) C2)) and the next restart would be
- the last, simplify this by making C1 as small as possible
- and then exit. Only do this if C1 actually changes: for now
- this only saves memory but, should this transformation be
- moved to simplify-rtx.c, we'd risk unbounded recursion there. */
- if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
- && GET_CODE (XEXP (op0, 1)) == CONST_INT
- && GET_CODE (op1) == CONST_INT
- && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
- return gen_binary (IOR, mode,
- gen_binary (AND, mode, XEXP (op0, 0),
- GEN_INT (INTVAL (XEXP (op0, 1))
- & ~INTVAL (op1))), op1);
-
if (GET_CODE (x) != AND)
return x;
op1 = XEXP (x, 1);
}
- /* Convert (A | B) & A to A. */
- if (GET_CODE (op0) == IOR
- && (rtx_equal_p (XEXP (op0, 0), op1)
- || rtx_equal_p (XEXP (op0, 1), op1))
- && ! side_effects_p (XEXP (op0, 0))
- && ! side_effects_p (XEXP (op0, 1)))
- return op1;
-
- /* In the following group of tests (and those in case IOR below),
- we start with some combination of logical operations and apply
- the distributive law followed by the inverse distributive law.
- Most of the time, this results in no change. However, if some of
- the operands are the same or inverses of each other, simplifications
- will result.
-
- For example, (and (ior A B) (not B)) can occur as the result of
- expanding a bit field assignment. When we apply the distributive
- law to this, we get (ior (and (A (not B))) (and (B (not B)))),
- which then simplifies to (and (A (not B))).
-
- If we have (and (ior A B) C), apply the distributive law and then
- the inverse distributive law to see if things simplify. */
-
+ /* If we have any of (and (ior A B) C) or (and (xor A B) C),
+ apply the distributive law and then the inverse distributive
+ law to see if things simplify. */
if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
{
- x = apply_distributive_law
- (gen_binary (GET_CODE (op0), mode,
- gen_binary (AND, mode, XEXP (op0, 0), op1),
- gen_binary (AND, mode, XEXP (op0, 1),
- copy_rtx (op1))));
- if (GET_CODE (x) != AND)
- return x;
+ rtx result = distribute_and_simplify_rtx (x, 0);
+ if (result)
+ return result;
}
-
if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
- return apply_distributive_law
- (gen_binary (GET_CODE (op1), mode,
- gen_binary (AND, mode, XEXP (op1, 0), op0),
- gen_binary (AND, mode, XEXP (op1, 1),
- copy_rtx (op0))));
-
- /* Similarly, taking advantage of the fact that
- (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
-
- if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
- return apply_distributive_law
- (gen_binary (XOR, mode,
- gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
- gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
- XEXP (op1, 1))));
-
- else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
- return apply_distributive_law
- (gen_binary (XOR, mode,
- gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
- gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
+ {
+ rtx result = distribute_and_simplify_rtx (x, 1);
+ if (result)
+ return result;
+ }
break;
case IOR:
- /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
- if (GET_CODE (op1) == CONST_INT
- && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
- && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
- return op1;
-
- /* Convert (A & B) | A to A. */
- if (GET_CODE (op0) == AND
- && (rtx_equal_p (XEXP (op0, 0), op1)
- || rtx_equal_p (XEXP (op0, 1), op1))
- && ! side_effects_p (XEXP (op0, 0))
- && ! side_effects_p (XEXP (op0, 1)))
- return op1;
-
/* If we have (ior (and A B) C), apply the distributive law and then
the inverse distributive law to see if things simplify. */
if (GET_CODE (op0) == AND)
{
- rtx tmp = apply_distributive_law
- (gen_binary (AND, mode,
- gen_binary (IOR, mode, XEXP (op0, 0), op1),
- gen_binary (IOR, mode, XEXP (op0, 1),
- copy_rtx (op1))));
-
- if (GET_CODE (tmp) != IOR
- && rtx_cost (tmp, SET) < rtx_cost (x, SET))
- return tmp;
+ rtx result = distribute_and_simplify_rtx (x, 0);
+ if (result)
+ return result;
}
if (GET_CODE (op1) == AND)
{
- rtx tmp = apply_distributive_law
- (gen_binary (AND, mode,
- gen_binary (IOR, mode, XEXP (op1, 0), op0),
- gen_binary (IOR, mode, XEXP (op1, 1),
- copy_rtx (op0))));
-
- if (GET_CODE (tmp) != IOR
- && rtx_cost (tmp, SET) < rtx_cost (x, SET))
- return tmp;
- }
-
- /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
- mode size to (rotate A CX). */
-
- if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
- || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
- && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
- && GET_CODE (XEXP (op0, 1)) == CONST_INT
- && GET_CODE (XEXP (op1, 1)) == CONST_INT
- && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
- == GET_MODE_BITSIZE (mode)))
- return gen_rtx_ROTATE (mode, XEXP (op0, 0),
- (GET_CODE (op0) == ASHIFT
- ? XEXP (op0, 1) : XEXP (op1, 1)));
-
- /* If OP0 is (ashiftrt (plus ...) C), it might actually be
- a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
- does not affect any of the bits in OP1, it can really be done
- as a PLUS and we can associate. We do this by seeing if OP1
- can be safely shifted left C bits. */
- if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
- && GET_CODE (XEXP (op0, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
- && GET_CODE (XEXP (op0, 1)) == CONST_INT
- && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
- {
- int count = INTVAL (XEXP (op0, 1));
- HOST_WIDE_INT mask = INTVAL (op1) << count;
-
- if (mask >> count == INTVAL (op1)
- && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
- {
- SUBST (XEXP (XEXP (op0, 0), 1),
- GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
- return op0;
- }
+ rtx result = distribute_and_simplify_rtx (x, 1);
+ if (result)
+ return result;
}
break;
- case XOR:
- /* If we are XORing two things that have no bits in common,
- convert them into an IOR. This helps to detect rotation encoded
- using those methods and possibly other simplifications. */
-
- if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
- && (nonzero_bits (op0, mode)
- & nonzero_bits (op1, mode)) == 0)
- return (gen_binary (IOR, mode, op0, op1));
-
- /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
- Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
- (NOT y). */
- {
- int num_negated = 0;
-
- if (GET_CODE (op0) == NOT)
- num_negated++, op0 = XEXP (op0, 0);
- if (GET_CODE (op1) == NOT)
- num_negated++, op1 = XEXP (op1, 0);
-
- if (num_negated == 2)
- {
- SUBST (XEXP (x, 0), op0);
- SUBST (XEXP (x, 1), op1);
- }
- else if (num_negated == 1)
- return
- simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
- mode);
- }
-
- /* Convert (xor (and A B) B) to (and (not A) B). The latter may
- correspond to a machine insn or result in further simplifications
- if B is a constant. */
-
- if (GET_CODE (op0) == AND
- && rtx_equal_p (XEXP (op0, 1), op1)
- && ! side_effects_p (op1))
- return gen_binary (AND, mode,
- simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
- op1);
-
- else if (GET_CODE (op0) == AND
- && rtx_equal_p (XEXP (op0, 0), op1)
- && ! side_effects_p (op1))
- return gen_binary (AND, mode,
- simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
- op1);
-
- /* (xor (comparison foo bar) (const_int 1)) can become the reversed
- comparison if STORE_FLAG_VALUE is 1. */
- if (STORE_FLAG_VALUE == 1
- && op1 == const1_rtx
- && COMPARISON_P (op0)
- && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
- XEXP (op0, 1))))
- return reversed;
-
- /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
- is (lt foo (const_int 0)), so we can perform the above
- simplification if STORE_FLAG_VALUE is 1. */
-
- if (STORE_FLAG_VALUE == 1
- && op1 == const1_rtx
- && GET_CODE (op0) == LSHIFTRT
- && GET_CODE (XEXP (op0, 1)) == CONST_INT
- && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
- return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
-
- /* (xor (comparison foo bar) (const_int sign-bit))
- when STORE_FLAG_VALUE is the sign bit. */
- if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
- && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
- == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
- && op1 == const_true_rtx
- && COMPARISON_P (op0)
- && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
- XEXP (op0, 1))))
- return reversed;
-
- break;
-
default:
gcc_unreachable ();
}
rtx inner;
rtx pos; /* Always counts from low bit. */
int len;
- rtx mask;
+ rtx mask, cleared, masked;
enum machine_mode compute_mode;
/* Loop until we find something we can't simplify. */
/* If position is ADJUST - X, new position is X. */
pos = XEXP (pos, 0);
else
- pos = gen_binary (MINUS, GET_MODE (pos),
- GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
- - len),
- pos);
+ pos = simplify_gen_binary (MINUS, GET_MODE (pos),
+ GEN_INT (GET_MODE_BITSIZE (
+ GET_MODE (inner))
+ - len),
+ pos);
}
}
}
/* Compute a mask of LEN bits, if we can do this on the host machine. */
- if (len < HOST_BITS_PER_WIDE_INT)
- mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
- else
+ if (len >= HOST_BITS_PER_WIDE_INT)
break;
/* Now compute the equivalent expression. Make a copy of INNER
for the SET_DEST in case it is a MEM into which we will substitute;
we don't want shared RTL in that case. */
- x = gen_rtx_SET
- (VOIDmode, copy_rtx (inner),
- gen_binary (IOR, compute_mode,
- gen_binary (AND, compute_mode,
- simplify_gen_unary (NOT, compute_mode,
- gen_binary (ASHIFT,
- compute_mode,
- mask, pos),
- compute_mode),
- inner),
- gen_binary (ASHIFT, compute_mode,
- gen_binary (AND, compute_mode,
- gen_lowpart
- (compute_mode, SET_SRC (x)),
- mask),
- pos)));
+ mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
+ cleared = simplify_gen_binary (AND, compute_mode,
+ simplify_gen_unary (NOT, compute_mode,
+ simplify_gen_binary (ASHIFT,
+ compute_mode,
+ mask, pos),
+ compute_mode),
+ inner);
+ masked = simplify_gen_binary (ASHIFT, compute_mode,
+ simplify_gen_binary (
+ AND, compute_mode,
+ gen_lowpart (compute_mode, SET_SRC (x)),
+ mask),
+ pos);
+
+ x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
+ simplify_gen_binary (IOR, compute_mode,
+ cleared, masked));
}
return x;
&& ! (spans_byte && inner_mode != tmode)
&& ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
&& !MEM_P (inner)
+ && (inner_mode == tmode
+ || !REG_P (inner)
+ || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
+ GET_MODE_BITSIZE (inner_mode))
+ || reg_truncated_to_mode (tmode, inner))
&& (! in_dest
|| (REG_P (inner)
&& have_insn_for (STRICT_LOW_PART, tmode))))
/* Avoid creating invalid subregs, for example when
simplifying (x>>32)&255. */
- if (final_word >= GET_MODE_SIZE (inner_mode))
+ if (!validate_subreg (tmode, inner_mode, inner, final_word))
return NULL_RTX;
new = gen_rtx_SUBREG (tmode, inner, final_word);
len >= HOST_BITS_PER_WIDE_INT
? ~(unsigned HOST_WIDE_INT) 0
: ((unsigned HOST_WIDE_INT) 1 << len) - 1,
- NULL_RTX, 0);
+ 0);
/* If this extraction is going into the destination of a SET,
make a STRICT_LOW_PART unless we made a MEM. */
&& GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
- /* If this is a constant position, we can move to the desired byte. */
+ /* If this is a constant position, we can move to the desired byte.
+ Be careful not to go beyond the original object and maintain the
+ natural alignment of the memory. */
if (pos_rtx == 0)
{
- offset += pos / BITS_PER_UNIT;
- pos %= GET_MODE_BITSIZE (wanted_inner_mode);
+ enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
+ offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
+ pos %= GET_MODE_BITSIZE (bfmode);
}
if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
? ~(unsigned HOST_WIDE_INT) 0
: ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
<< orig_pos),
- NULL_RTX, 0);
+ 0);
}
/* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
if (GET_CODE (XEXP (x, 1)) == CONST_INT
&& (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
&& (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
- return gen_binary (code, mode, tem,
- GEN_INT (INTVAL (XEXP (x, 1)) >> count));
+ return simplify_gen_binary (code, mode, tem,
+ GEN_INT (INTVAL (XEXP (x, 1)) >> count));
break;
what it originally did, do this SUBREG as a force_to_mode. */
tem = make_compound_operation (SUBREG_REG (x), in_code);
- if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
- && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
- && subreg_lowpart_p (x))
- {
- rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
- NULL_RTX, 0);
- /* If we have something other than a SUBREG, we might have
- done an expansion, so rerun ourselves. */
- if (GET_CODE (newer) != SUBREG)
- newer = make_compound_operation (newer, in_code);
+ {
+ rtx simplified;
+ simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
+ SUBREG_BYTE (x));
- return newer;
- }
+ if (simplified)
+ tem = simplified;
- /* If this is a paradoxical subreg, and the new code is a sign or
- zero extension, omit the subreg and widen the extension. If it
- is a regular subreg, we can still get rid of the subreg by not
- widening so much, or in fact removing the extension entirely. */
- if ((GET_CODE (tem) == SIGN_EXTEND
- || GET_CODE (tem) == ZERO_EXTEND)
- && subreg_lowpart_p (x))
- {
- if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
- || (GET_MODE_SIZE (mode) >
- GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
- {
- if (! SCALAR_INT_MODE_P (mode))
- break;
- tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
- }
- else
- tem = gen_lowpart (mode, XEXP (tem, 0));
+ if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
+ && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
+ && subreg_lowpart_p (x))
+ {
+ rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
+ 0);
+
+ /* If we have something other than a SUBREG, we might have
+ done an expansion, so rerun ourselves. */
+ if (GET_CODE (newer) != SUBREG)
+ newer = make_compound_operation (newer, in_code);
+
+ return newer;
+ }
+
+ if (simplified)
return tem;
- }
+ }
break;
default:
code = GET_CODE (x);
}
- /* Now recursively process each operand of this operation. */
- fmt = GET_RTX_FORMAT (code);
- for (i = 0; i < GET_RTX_LENGTH (code); i++)
- if (fmt[i] == 'e')
- {
- new = make_compound_operation (XEXP (x, i), next_code);
- SUBST (XEXP (x, i), new);
- }
+ /* Now recursively process each operand of this operation. */
+ fmt = GET_RTX_FORMAT (code);
+ for (i = 0; i < GET_RTX_LENGTH (code); i++)
+ if (fmt[i] == 'e')
+ {
+ new = make_compound_operation (XEXP (x, i), next_code);
+ SUBST (XEXP (x, i), new);
+ }
+
+ /* If this is a commutative operation, the changes to the operands
+ may have made it noncanonical. */
+ if (COMMUTATIVE_ARITH_P (x)
+ && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
+ {
+ tem = XEXP (x, 0);
+ SUBST (XEXP (x, 0), XEXP (x, 1));
+ SUBST (XEXP (x, 1), tem);
+ }
+
+ return x;
+}
+\f
+/* Given M see if it is a value that would select a field of bits
+ within an item, but not the entire word. Return -1 if not.
+ Otherwise, return the starting position of the field, where 0 is the
+ low-order bit.
+
+ *PLEN is set to the length of the field. */
+
+static int
+get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
+{
+ /* Get the bit number of the first 1 bit from the right, -1 if none. */
+ int pos = exact_log2 (m & -m);
+ int len = 0;
+
+ if (pos >= 0)
+ /* Now shift off the low-order zero bits and see if we have a
+ power of two minus 1. */
+ len = exact_log2 ((m >> pos) + 1);
+
+ if (len <= 0)
+ pos = -1;
+
+ *plen = len;
+ return pos;
+}
+\f
+/* If X refers to a register that equals REG in value, replace these
+ references with REG. */
+static rtx
+canon_reg_for_combine (rtx x, rtx reg)
+{
+ rtx op0, op1, op2;
+ const char *fmt;
+ int i;
+ bool copied;
+
+ enum rtx_code code = GET_CODE (x);
+ switch (GET_RTX_CLASS (code))
+ {
+ case RTX_UNARY:
+ op0 = canon_reg_for_combine (XEXP (x, 0), reg);
+ if (op0 != XEXP (x, 0))
+ return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
+ GET_MODE (reg));
+ break;
+
+ case RTX_BIN_ARITH:
+ case RTX_COMM_ARITH:
+ op0 = canon_reg_for_combine (XEXP (x, 0), reg);
+ op1 = canon_reg_for_combine (XEXP (x, 1), reg);
+ if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
+ return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
+ break;
+
+ case RTX_COMPARE:
+ case RTX_COMM_COMPARE:
+ op0 = canon_reg_for_combine (XEXP (x, 0), reg);
+ op1 = canon_reg_for_combine (XEXP (x, 1), reg);
+ if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
+ return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
+ GET_MODE (op0), op0, op1);
+ break;
+
+ case RTX_TERNARY:
+ case RTX_BITFIELD_OPS:
+ op0 = canon_reg_for_combine (XEXP (x, 0), reg);
+ op1 = canon_reg_for_combine (XEXP (x, 1), reg);
+ op2 = canon_reg_for_combine (XEXP (x, 2), reg);
+ if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
+ return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
+ GET_MODE (op0), op0, op1, op2);
+
+ case RTX_OBJ:
+ if (REG_P (x))
+ {
+ if (rtx_equal_p (get_last_value (reg), x)
+ || rtx_equal_p (reg, get_last_value (x)))
+ return reg;
+ else
+ break;
+ }
+
+ /* fall through */
+
+ default:
+ fmt = GET_RTX_FORMAT (code);
+ copied = false;
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ if (fmt[i] == 'e')
+ {
+ rtx op = canon_reg_for_combine (XEXP (x, i), reg);
+ if (op != XEXP (x, i))
+ {
+ if (!copied)
+ {
+ copied = true;
+ x = copy_rtx (x);
+ }
+ XEXP (x, i) = op;
+ }
+ }
+ else if (fmt[i] == 'E')
+ {
+ int j;
+ for (j = 0; j < XVECLEN (x, i); j++)
+ {
+ rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
+ if (op != XVECEXP (x, i, j))
+ {
+ if (!copied)
+ {
+ copied = true;
+ x = copy_rtx (x);
+ }
+ XVECEXP (x, i, j) = op;
+ }
+ }
+ }
+
+ break;
+ }
return x;
}
-\f
-/* Given M see if it is a value that would select a field of bits
- within an item, but not the entire word. Return -1 if not.
- Otherwise, return the starting position of the field, where 0 is the
- low-order bit.
- *PLEN is set to the length of the field. */
+/* Return X converted to MODE. If the value is already truncated to
+ MODE we can just return a subreg even though in the general case we
+ would need an explicit truncation. */
-static int
-get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
+static rtx
+gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
{
- /* Get the bit number of the first 1 bit from the right, -1 if none. */
- int pos = exact_log2 (m & -m);
- int len = 0;
-
- if (pos >= 0)
- /* Now shift off the low-order zero bits and see if we have a
- power of two minus 1. */
- len = exact_log2 ((m >> pos) + 1);
-
- if (len <= 0)
- pos = -1;
-
- *plen = len;
- return pos;
+ if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
+ || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
+ GET_MODE_BITSIZE (GET_MODE (x)))
+ || (REG_P (x) && reg_truncated_to_mode (mode, x)))
+ return gen_lowpart (mode, x);
+ else
+ return gen_rtx_TRUNCATE (mode, x);
}
-\f
+
/* See if X can be simplified knowing that we will only refer to it in
MODE and will only refer to those bits that are nonzero in MASK.
If other bits are being computed or if masking operations are done
Return a possibly simplified expression, but always convert X to
MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
- Also, if REG is nonzero and X is a register equal in value to REG,
- replace X with REG.
-
If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
are all off in X. This is used when X will be complemented, by either
NOT, NEG, or XOR. */
static rtx
force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
- rtx reg, int just_select)
+ int just_select)
{
enum rtx_code code = GET_CODE (x);
int next_select = just_select || code == XOR || code == NOT || code == NEG;
within that boundary, we don't need the USE any more. */
if (! BITS_BIG_ENDIAN
&& (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
- return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
+ return force_to_mode (XEXP (x, 0), mode, mask, next_select);
break;
case SIGN_EXTEND:
case SIGN_EXTRACT:
x = expand_compound_operation (x);
if (GET_CODE (x) != code)
- return force_to_mode (x, mode, mask, reg, next_select);
- break;
-
- case REG:
- if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
- || rtx_equal_p (reg, get_last_value (x))))
- x = reg;
+ return force_to_mode (x, mode, mask, next_select);
break;
case SUBREG:
|| (0 == (mask
& GET_MODE_MASK (GET_MODE (x))
& ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
- return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
+ return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
break;
case AND:
&& (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
cval |= (HOST_WIDE_INT) -1 << width;
- y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
+ y = simplify_gen_binary (AND, GET_MODE (x),
+ XEXP (x, 0), GEN_INT (cval));
if (rtx_cost (y, SET) < rtx_cost (x, SET))
x = y;
}
&& (INTVAL (XEXP (x, 1)) & ~smask) != 0)
return force_to_mode (plus_constant (XEXP (x, 0),
(INTVAL (XEXP (x, 1)) & smask)),
- mode, smask, reg, next_select);
+ mode, smask, next_select);
}
/* ... fall through ... */
{
x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
GET_MODE (x));
- return force_to_mode (x, mode, mask, reg, next_select);
+ return force_to_mode (x, mode, mask, next_select);
}
/* Similarly, if C contains every bit in the fuller_mask, then we may
{
x = simplify_gen_unary (NOT, GET_MODE (x),
XEXP (x, 1), GET_MODE (x));
- return force_to_mode (x, mode, mask, reg, next_select);
+ return force_to_mode (x, mode, mask, next_select);
}
mask = fuller_mask;
{
temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
<< INTVAL (XEXP (XEXP (x, 0), 1)));
- temp = gen_binary (GET_CODE (x), GET_MODE (x),
- XEXP (XEXP (x, 0), 0), temp);
- x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
- XEXP (XEXP (x, 0), 1));
- return force_to_mode (x, mode, mask, reg, next_select);
+ temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
+ XEXP (XEXP (x, 0), 0), temp);
+ x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
+ XEXP (XEXP (x, 0), 1));
+ return force_to_mode (x, mode, mask, next_select);
}
binop:
/* For most binary operations, just propagate into the operation and
change the mode if we have an operation of that mode. */
- op0 = gen_lowpart (op_mode,
- force_to_mode (XEXP (x, 0), mode, mask,
- reg, next_select));
- op1 = gen_lowpart (op_mode,
- force_to_mode (XEXP (x, 1), mode, mask,
- reg, next_select));
+ op0 = gen_lowpart_or_truncate (op_mode,
+ force_to_mode (XEXP (x, 0), mode, mask,
+ next_select));
+ op1 = gen_lowpart_or_truncate (op_mode,
+ force_to_mode (XEXP (x, 1), mode, mask,
+ next_select));
if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
- x = gen_binary (code, op_mode, op0, op1);
+ x = simplify_gen_binary (code, op_mode, op0, op1);
break;
case ASHIFT:
else
mask = fuller_mask;
- op0 = gen_lowpart (op_mode,
- force_to_mode (XEXP (x, 0), op_mode,
- mask, reg, next_select));
+ op0 = gen_lowpart_or_truncate (op_mode,
+ force_to_mode (XEXP (x, 0), op_mode,
+ mask, next_select));
if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
- x = gen_binary (code, op_mode, op0, XEXP (x, 1));
+ x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
break;
case LSHIFTRT:
if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
op_mode = GET_MODE (x);
- inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
+ inner = force_to_mode (inner, op_mode, inner_mask, next_select);
if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
- x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
+ x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
}
/* If we have (and (lshiftrt FOO C1) C2) where the combination of the
/* Must be more sign bit copies than the mask needs. */
&& ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
>= exact_log2 (mask + 1)))
- x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
- GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
- - exact_log2 (mask + 1)));
+ x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
+ GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
+ - exact_log2 (mask + 1)));
goto shiftrt;
if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
&& (mask == ((unsigned HOST_WIDE_INT) 1
<< (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
- return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
+ return force_to_mode (XEXP (x, 0), mode, mask, next_select);
/* If this is a shift by a constant, get a mask that contains those bits
that are not copies of the sign bit. We then have two cases: If
if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
&& INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
{
- int i = -1;
+ int i;
/* If the considered data is wider than HOST_WIDE_INT, we can't
represent a mask for all its bits in a single scalar.
nonzero >>= INTVAL (XEXP (x, 1));
}
- if ((mask & ~nonzero) == 0
- || (i = exact_log2 (mask)) >= 0)
+ if ((mask & ~nonzero) == 0)
+ {
+ x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
+ XEXP (x, 0), INTVAL (XEXP (x, 1)));
+ if (GET_CODE (x) != ASHIFTRT)
+ return force_to_mode (x, mode, mask, next_select);
+ }
+
+ else if ((i = exact_log2 (mask)) >= 0)
{
x = simplify_shift_const
- (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
- i < 0 ? INTVAL (XEXP (x, 1))
- : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
+ (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
+ GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
if (GET_CODE (x) != ASHIFTRT)
- return force_to_mode (x, mode, mask, reg, next_select);
+ return force_to_mode (x, mode, mask, next_select);
}
}
/* If MASK is 1, convert this to an LSHIFTRT. This can be done
even if the shift count isn't a constant. */
if (mask == 1)
- x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
+ x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
+ XEXP (x, 0), XEXP (x, 1));
shiftrt:
&& GET_CODE (XEXP (x, 0)) == ASHIFT
&& XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
- reg, next_select);
+ next_select);
break;
if (temp && GET_CODE (temp) == CONST_INT)
SUBST (XEXP (x, 0),
force_to_mode (XEXP (x, 0), GET_MODE (x),
- INTVAL (temp), reg, next_select));
+ INTVAL (temp), next_select));
}
break;
/* If we just want the low-order bit, the NEG isn't needed since it
won't change the low-order bit. */
if (mask == 1)
- return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
+ return force_to_mode (XEXP (x, 0), mode, mask, just_select);
/* We need any bits less significant than the most significant bit in
MASK since carries from those bits will affect the bits we are
{
temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
GET_MODE (x));
- temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
- x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
+ temp = simplify_gen_binary (XOR, GET_MODE (x),
+ XEXP (XEXP (x, 0), 0), temp);
+ x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
+ temp, XEXP (XEXP (x, 0), 1));
- return force_to_mode (x, mode, mask, reg, next_select);
+ return force_to_mode (x, mode, mask, next_select);
}
/* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
mask = fuller_mask;
unop:
- op0 = gen_lowpart (op_mode,
- force_to_mode (XEXP (x, 0), mode, mask,
- reg, next_select));
+ op0 = gen_lowpart_or_truncate (op_mode,
+ force_to_mode (XEXP (x, 0), mode, mask,
+ next_select));
if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
x = simplify_gen_unary (code, op_mode, op0, op_mode);
break;
&& exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
&& (nonzero_bits (XEXP (x, 0), mode)
== (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
- return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
+ return force_to_mode (XEXP (x, 0), mode, mask, next_select);
break;
written in a narrower mode. We play it safe and do not do so. */
SUBST (XEXP (x, 1),
- gen_lowpart (GET_MODE (x),
+ gen_lowpart_or_truncate (GET_MODE (x),
force_to_mode (XEXP (x, 1), mode,
- mask, reg, next_select)));
+ mask, next_select)));
SUBST (XEXP (x, 2),
- gen_lowpart (GET_MODE (x),
+ gen_lowpart_or_truncate (GET_MODE (x),
force_to_mode (XEXP (x, 2), mode,
- mask, reg, next_select)));
+ mask, next_select)));
break;
default:
}
/* Ensure we return a value of the proper mode. */
- return gen_lowpart (mode, x);
+ return gen_lowpart_or_truncate (mode, x);
}
\f
/* Return nonzero if X is an expression that has one of two values depending on
else if (cond1 == 0)
true1 = copy_rtx (true1);
- *ptrue = gen_binary (code, mode, true0, true1);
- *pfalse = gen_binary (code, mode, false0, false1);
+ if (COMPARISON_P (x))
+ {
+ *ptrue = simplify_gen_relational (code, mode, VOIDmode,
+ true0, true1);
+ *pfalse = simplify_gen_relational (code, mode, VOIDmode,
+ false0, false1);
+ }
+ else
+ {
+ *ptrue = simplify_gen_binary (code, mode, true0, true1);
+ *pfalse = simplify_gen_binary (code, mode, false0, false1);
+ }
+
return cond0 ? cond0 : cond1;
}
if (COMPARISON_P (cond0)
&& COMPARISON_P (cond1)
- && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
+ && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
|| ((swap_condition (GET_CODE (cond0))
- == combine_reversed_comparison_code (cond1))
+ == reversed_comparison_code (cond1, NULL))
&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
&& ! side_effects_p (x))
{
- *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
- *pfalse = gen_binary (MULT, mode,
- (code == MINUS
- ? simplify_gen_unary (NEG, mode, op1,
- mode)
- : op1),
- const_true_rtx);
+ *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
+ *pfalse = simplify_gen_binary (MULT, mode,
+ (code == MINUS
+ ? simplify_gen_unary (NEG, mode,
+ op1, mode)
+ : op1),
+ const_true_rtx);
return cond0;
}
}
if (COMPARISON_P (cond0)
&& COMPARISON_P (cond1)
- && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
+ && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
|| ((swap_condition (GET_CODE (cond0))
- == combine_reversed_comparison_code (cond1))
+ == reversed_comparison_code (cond1, NULL))
&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
&& ! side_effects_p (x))
if (comparison_dominates_p (cond, code))
return const_true_rtx;
- code = combine_reversed_comparison_code (x);
+ code = reversed_comparison_code (x, NULL);
if (code != UNKNOWN
&& comparison_dominates_p (cond, code))
return const0_rtx;
return x;
}
- else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
- && subreg_lowpart_p (XEXP (src, 0))
- && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
- < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
- && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
- && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
- && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
- && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
+ if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
+ && subreg_lowpart_p (XEXP (src, 0))
+ && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
+ < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
+ && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
+ && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
+ && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
+ && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
{
assign = make_extraction (VOIDmode, dest, 0,
XEXP (SUBREG_REG (XEXP (src, 0)), 1),
/* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
one-bit field. */
- else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
- && XEXP (XEXP (src, 0), 0) == const1_rtx
- && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
+ if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
+ && XEXP (XEXP (src, 0), 0) == const1_rtx
+ && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
{
assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
1, 1, 1, 0);
return x;
}
+ /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
+ SRC is an AND with all bits of that field set, then we can discard
+ the AND. */
+ if (GET_CODE (dest) == ZERO_EXTRACT
+ && GET_CODE (XEXP (dest, 1)) == CONST_INT
+ && GET_CODE (src) == AND
+ && GET_CODE (XEXP (src, 1)) == CONST_INT)
+ {
+ HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
+ unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
+ unsigned HOST_WIDE_INT ze_mask;
+
+ if (width >= HOST_BITS_PER_WIDE_INT)
+ ze_mask = -1;
+ else
+ ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
+
+ /* Complete overlap. We can remove the source AND. */
+ if ((and_mask & ze_mask) == ze_mask)
+ return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
+
+ /* Partial overlap. We can reduce the source AND. */
+ if ((and_mask & ze_mask) != and_mask)
+ {
+ mode = GET_MODE (src);
+ src = gen_rtx_AND (mode, XEXP (src, 0),
+ gen_int_mode (and_mask & ze_mask, mode));
+ return gen_rtx_SET (VOIDmode, dest, src);
+ }
+ }
+
/* The other case we handle is assignments into a constant-position
field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
a mask that has all one bits except for a group of zero bits and
/* Shift OTHER right POS places and make it the source, restricting it
to the proper length and mode. */
- src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
- GET_MODE (src), other, pos),
- mode,
+ src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
+ GET_MODE (src),
+ other, pos),
+ dest);
+ src = force_to_mode (src, mode,
GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
? ~(unsigned HOST_WIDE_INT) 0
: ((unsigned HOST_WIDE_INT) 1 << len) - 1,
- dest, 0);
+ 0);
/* If SRC is masked by an AND that does not make a difference in
the value being stored, strip it. */
break;
case SUBREG:
- /* Non-paradoxical SUBREGs distributes over all operations, provided
- the inner modes and byte offsets are the same, this is an extraction
- of a low-order part, we don't convert an fp operation to int or
- vice versa, and we would not be converting a single-word
- operation into a multi-word operation. The latter test is not
- required, but it prevents generating unneeded multi-word operations.
- Some of the previous tests are redundant given the latter test, but
- are retained because they are required for correctness.
+ /* Non-paradoxical SUBREGs distributes over all operations,
+ provided the inner modes and byte offsets are the same, this
+ is an extraction of a low-order part, we don't convert an fp
+ operation to int or vice versa, this is not a vector mode,
+ and we would not be converting a single-word operation into a
+ multi-word operation. The latter test is not required, but
+ it prevents generating unneeded multi-word operations. Some
+ of the previous tests are redundant given the latter test,
+ but are retained because they are required for correctness.
We produce the result slightly differently in this case. */
!= GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
|| (GET_MODE_SIZE (GET_MODE (lhs))
> GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
- || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
+ || VECTOR_MODE_P (GET_MODE (lhs))
+ || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
+ /* Result might need to be truncated. Don't change mode if
+ explicit truncation is needed. */
+ || !TRULY_NOOP_TRUNCATION
+ (GET_MODE_BITSIZE (GET_MODE (x)),
+ GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
return x;
- tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
- SUBREG_REG (lhs), SUBREG_REG (rhs));
+ tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
+ SUBREG_REG (lhs), SUBREG_REG (rhs));
return gen_lowpart (GET_MODE (x), tem);
default:
return x;
/* Form the new inner operation, seeing if it simplifies first. */
- tem = gen_binary (code, GET_MODE (x), lhs, rhs);
+ tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
/* There is one exception to the general way of distributing:
(a | c) ^ (b | c) -> (a ^ b) & ~c */
/* We may be able to continuing distributing the result, so call
ourselves recursively on the inner operation before forming the
outer operation, which we return. */
- return gen_binary (inner_code, GET_MODE (x),
- apply_distributive_law (tem), other);
+ return simplify_gen_binary (inner_code, GET_MODE (x),
+ apply_distributive_law (tem), other);
}
-\f
-/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
- in MODE.
- Return an equivalent form, if different from X. Otherwise, return X. If
- X is zero, we are to always construct the equivalent form. */
+/* See if X is of the form (* (+ A B) C), and if so convert to
+ (+ (* A C) (* B C)) and try to simplify.
+
+ Most of the time, this results in no change. However, if some of
+ the operands are the same or inverses of each other, simplifications
+ will result.
+
+ For example, (and (ior A B) (not B)) can occur as the result of
+ expanding a bit field assignment. When we apply the distributive
+ law to this, we get (ior (and (A (not B))) (and (B (not B)))),
+ which then simplifies to (and (A (not B))).
+
+ Note that no checks happen on the validity of applying the inverse
+ distributive law. This is pointless since we can do it in the
+ few places where this routine is called.
+
+ N is the index of the term that is decomposed (the arithmetic operation,
+ i.e. (+ A B) in the first example above). !N is the index of the term that
+ is distributed, i.e. of C in the first example above. */
+static rtx
+distribute_and_simplify_rtx (rtx x, int n)
+{
+ enum machine_mode mode;
+ enum rtx_code outer_code, inner_code;
+ rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
+
+ decomposed = XEXP (x, n);
+ if (!ARITHMETIC_P (decomposed))
+ return NULL_RTX;
+
+ mode = GET_MODE (x);
+ outer_code = GET_CODE (x);
+ distributed = XEXP (x, !n);
+
+ inner_code = GET_CODE (decomposed);
+ inner_op0 = XEXP (decomposed, 0);
+ inner_op1 = XEXP (decomposed, 1);
+
+ /* Special case (and (xor B C) (not A)), which is equivalent to
+ (xor (ior A B) (ior A C)) */
+ if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
+ {
+ distributed = XEXP (distributed, 0);
+ outer_code = IOR;
+ }
+
+ if (n == 0)
+ {
+ /* Distribute the second term. */
+ new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
+ new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
+ }
+ else
+ {
+ /* Distribute the first term. */
+ new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
+ new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
+ }
+
+ tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
+ new_op0, new_op1));
+ if (GET_CODE (tmp) != outer_code
+ && rtx_cost (tmp, SET) < rtx_cost (x, SET))
+ return tmp;
+
+ return NULL_RTX;
+}
+\f
+/* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
+ in MODE. Return an equivalent form, if different from (and VAROP
+ (const_int CONSTOP)). Otherwise, return NULL_RTX. */
static rtx
-simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
- unsigned HOST_WIDE_INT constop)
+simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
+ unsigned HOST_WIDE_INT constop)
{
unsigned HOST_WIDE_INT nonzero;
+ unsigned HOST_WIDE_INT orig_constop;
+ rtx orig_varop;
int i;
+ orig_varop = varop;
+ orig_constop = constop;
+ if (GET_CODE (varop) == CLOBBER)
+ return NULL_RTX;
+
/* Simplify VAROP knowing that we will be only looking at some of the
bits in it.
CONSTOP are not significant and will never be examined. We must
ensure that is the case by explicitly masking out those bits
before returning. */
- varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
+ varop = force_to_mode (varop, mode, constop, 0);
/* If VAROP is a CLOBBER, we will fail so return it. */
if (GET_CODE (varop) == CLOBBER)
/* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
to VAROP and return the new constant. */
if (GET_CODE (varop) == CONST_INT)
- return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
+ return gen_int_mode (INTVAL (varop) & constop, mode);
/* See what bits may be nonzero in VAROP. Unlike the general case of
a call to nonzero_bits, here we don't care about bits outside
gen_lowpart
(mode,
apply_distributive_law
- (gen_binary (GET_CODE (varop), GET_MODE (varop),
- simplify_and_const_int (NULL_RTX, GET_MODE (varop),
- XEXP (varop, 0), constop),
- simplify_and_const_int (NULL_RTX, GET_MODE (varop),
- XEXP (varop, 1), constop))));
-
- /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
+ (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
+ simplify_and_const_int (NULL_RTX,
+ GET_MODE (varop),
+ XEXP (varop, 0),
+ constop),
+ simplify_and_const_int (NULL_RTX,
+ GET_MODE (varop),
+ XEXP (varop, 1),
+ constop))));
+
+ /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
the AND and see if one of the operands simplifies to zero. If so, we
may eliminate it. */
return o0;
}
- /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
- if we already had one (just check for the simplest cases). */
- if (x && GET_CODE (XEXP (x, 0)) == SUBREG
- && GET_MODE (XEXP (x, 0)) == mode
- && SUBREG_REG (XEXP (x, 0)) == varop)
- varop = XEXP (x, 0);
- else
- varop = gen_lowpart (mode, varop);
-
- /* If we can't make the SUBREG, try to return what we were given. */
- if (GET_CODE (varop) == CLOBBER)
- return x ? x : varop;
+ /* Make a SUBREG if necessary. If we can't make it, fail. */
+ varop = gen_lowpart (mode, varop);
+ if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
+ return NULL_RTX;
/* If we are only masking insignificant bits, return VAROP. */
if (constop == nonzero)
- x = varop;
- else
- {
- /* Otherwise, return an AND. */
- constop = trunc_int_for_mode (constop, mode);
- /* See how much, if any, of X we can use. */
- if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
- x = gen_binary (AND, mode, varop, GEN_INT (constop));
+ return varop;
- else
- {
- if (GET_CODE (XEXP (x, 1)) != CONST_INT
- || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
- SUBST (XEXP (x, 1), GEN_INT (constop));
+ if (varop == orig_varop && constop == orig_constop)
+ return NULL_RTX;
- SUBST (XEXP (x, 0), varop);
- }
- }
+ /* Otherwise, return an AND. */
+ constop = trunc_int_for_mode (constop, mode);
+ return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
+}
+
+
+/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
+ in MODE.
+
+ Return an equivalent form, if different from X. Otherwise, return X. If
+ X is zero, we are to always construct the equivalent form. */
+
+static rtx
+simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
+ unsigned HOST_WIDE_INT constop)
+{
+ rtx tem = simplify_and_const_int_1 (mode, varop, constop);
+ if (tem)
+ return tem;
+ if (!x)
+ x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
+ if (GET_MODE (x) != mode)
+ x = gen_lowpart (mode, x);
return x;
}
\f
&& (reg_stat[REGNO (x)].last_set_label == label_tick
|| (REGNO (x) >= FIRST_PSEUDO_REGISTER
&& REG_N_SETS (REGNO (x)) == 1
- && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
- REGNO (x))))
+ && ! REGNO_REG_SET_P
+ (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
+ REGNO (x))))
&& INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
{
*nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
&& (reg_stat[REGNO (x)].last_set_label == label_tick
|| (REGNO (x) >= FIRST_PSEUDO_REGISTER
&& REG_N_SETS (REGNO (x)) == 1
- && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
- REGNO (x))))
+ && ! REGNO_REG_SET_P
+ (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
+ REGNO (x))))
&& INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
{
*result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
}
\f
/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
- The result of the shift is RESULT_MODE. X, if nonzero, is an expression
- that we started with.
+ The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
+ simplify it. Otherwise, return a simplified value.
The shift is normally computed in the widest mode we find in VAROP, as
long as it isn't a different number of words than RESULT_MODE. Exceptions
- are ASHIFTRT and ROTATE, which are always done in their original mode, */
+ are ASHIFTRT and ROTATE, which are always done in their original mode. */
static rtx
-simplify_shift_const (rtx x, enum rtx_code code,
- enum machine_mode result_mode, rtx varop,
- int orig_count)
+simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
+ rtx varop, int orig_count)
{
enum rtx_code orig_code = code;
- unsigned int count;
- int signed_count;
+ rtx orig_varop = varop;
+ int count;
enum machine_mode mode = result_mode;
enum machine_mode shift_mode, tmode;
unsigned int mode_words
/* We form (outer_op (code varop count) (outer_const)). */
enum rtx_code outer_op = UNKNOWN;
HOST_WIDE_INT outer_const = 0;
- rtx const_rtx;
int complement_p = 0;
- rtx new;
+ rtx new, x;
/* Make sure and truncate the "natural" shift on the way in. We don't
want to do this inside the loop as it makes it more difficult to
what was requested. */
if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
- {
- if (x)
- return x;
-
- return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
- }
+ return NULL_RTX;
count = orig_count;
while (count != 0)
{
- /* If we have an operand of (clobber (const_int 0)), just return that
- value. */
+ /* If we have an operand of (clobber (const_int 0)), fail. */
if (GET_CODE (varop) == CLOBBER)
- return varop;
+ return NULL_RTX;
/* If we discovered we had to complement VAROP, leave. Making a NOT
here would cause an infinite loop. */
multiple operations, each of which are defined, we know what the
result is supposed to be. */
- if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
+ if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
{
if (code == ASHIFTRT)
count = GET_MODE_BITSIZE (shift_mode) - 1;
&& exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
{
varop
- = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
- GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
+ = simplify_gen_binary (ASHIFT, GET_MODE (varop),
+ XEXP (varop, 0),
+ GEN_INT (exact_log2 (
+ INTVAL (XEXP (varop, 1)))));
continue;
}
break;
&& exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
{
varop
- = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
- GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
+ = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
+ XEXP (varop, 0),
+ GEN_INT (exact_log2 (
+ INTVAL (XEXP (varop, 1)))));
continue;
}
break;
interpreted as the sign bit in a narrower mode, so, if
the result is narrower, don't discard the shift. */
if (code == LSHIFTRT
- && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
+ && count == (GET_MODE_BITSIZE (result_mode) - 1)
&& (GET_MODE_BITSIZE (result_mode)
>= GET_MODE_BITSIZE (GET_MODE (varop))))
{
(ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
This simplifies certain SIGN_EXTEND operations. */
if (code == ASHIFT && first_code == ASHIFTRT
- && count == (unsigned int)
- (GET_MODE_BITSIZE (result_mode)
+ && count == (GET_MODE_BITSIZE (result_mode)
- GET_MODE_BITSIZE (GET_MODE (varop))))
{
/* C3 has the low-order C1 bits zero. */
> first_count))
{
varop = XEXP (varop, 0);
-
- signed_count = count - first_count;
- if (signed_count < 0)
- count = -signed_count, code = ASHIFT;
- else
- count = signed_count;
+ count -= first_count;
+ if (count < 0)
+ {
+ count = -count;
+ code = ASHIFT;
+ }
continue;
}
mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
mask_rtx
- = simplify_binary_operation (code, result_mode, mask_rtx,
- GEN_INT (count));
+ = simplify_const_binary_operation (code, result_mode, mask_rtx,
+ GEN_INT (count));
/* Give up if we can't compute an outer operation to use. */
if (mask_rtx == 0
/* If the shifts are in the same direction, we add the
counts. Otherwise, we subtract them. */
- signed_count = count;
if ((code == ASHIFTRT || code == LSHIFTRT)
== (first_code == ASHIFTRT || first_code == LSHIFTRT))
- signed_count += first_count;
+ count += first_count;
else
- signed_count -= first_count;
+ count -= first_count;
/* If COUNT is positive, the new shift is usually CODE,
except for the two exceptions below, in which case it is
FIRST_CODE. If the count is negative, FIRST_CODE should
always be used */
- if (signed_count > 0
+ if (count > 0
&& ((first_code == ROTATE && code == ASHIFT)
|| (first_code == ASHIFTRT && code == LSHIFTRT)))
- code = first_code, count = signed_count;
- else if (signed_count < 0)
- code = first_code, count = -signed_count;
- else
- count = signed_count;
+ code = first_code;
+ else if (count < 0)
+ code = first_code, count = -count;
varop = XEXP (varop, 0);
continue;
B is not a constant. */
else if (GET_CODE (varop) == code
- && GET_CODE (XEXP (varop, 1)) != CONST_INT
- && 0 != (new
- = simplify_binary_operation (code, mode,
- XEXP (varop, 0),
- GEN_INT (count))))
+ && GET_CODE (XEXP (varop, 0)) == CONST_INT
+ && GET_CODE (XEXP (varop, 1)) != CONST_INT)
{
+ rtx new = simplify_const_binary_operation (code, mode,
+ XEXP (varop, 0),
+ GEN_INT (count));
varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
count = 0;
continue;
&& XEXP (XEXP (varop, 0), 1) == constm1_rtx
&& (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
&& (code == LSHIFTRT || code == ASHIFTRT)
- && count == (unsigned int)
- (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
+ && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
&& rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
{
count = 0;
&& !(code == ASHIFTRT && GET_CODE (varop) == XOR
&& 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
shift_mode))
- && (new = simplify_binary_operation (code, result_mode,
- XEXP (varop, 1),
- GEN_INT (count))) != 0
+ && (new = simplify_const_binary_operation (code, result_mode,
+ XEXP (varop, 1),
+ GEN_INT (count))) != 0
&& GET_CODE (new) == CONST_INT
&& merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
INTVAL (new), result_mode, &complement_p))
rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
XEXP (varop, 1), count);
- varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
+ varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
+ lhs, rhs);
varop = apply_distributive_law (varop);
count = 0;
if (code == LSHIFTRT
&& XEXP (varop, 1) == const0_rtx
&& GET_MODE (XEXP (varop, 0)) == result_mode
- && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
+ && count == (GET_MODE_BITSIZE (result_mode) - 1)
&& GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
- && ((STORE_FLAG_VALUE
- & ((HOST_WIDE_INT) 1
- < (GET_MODE_BITSIZE (result_mode) - 1))))
+ && STORE_FLAG_VALUE == -1
&& nonzero_bits (XEXP (varop, 0), result_mode) == 1
&& merge_outer_ops (&outer_op, &outer_const, XOR,
(HOST_WIDE_INT) 1, result_mode,
/* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
than the number of bits in the mode is equivalent to A. */
if (code == LSHIFTRT
- && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
+ && count == (GET_MODE_BITSIZE (result_mode) - 1)
&& nonzero_bits (XEXP (varop, 0), result_mode) == 1)
{
varop = XEXP (varop, 0);
is one less than the number of bits in the mode is
equivalent to (xor A 1). */
if (code == LSHIFTRT
- && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
+ && count == (GET_MODE_BITSIZE (result_mode) - 1)
&& XEXP (varop, 1) == constm1_rtx
&& nonzero_bits (XEXP (varop, 0), result_mode) == 1
&& merge_outer_ops (&outer_op, &outer_const, XOR,
/* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
if (code == ASHIFT
&& GET_CODE (XEXP (varop, 1)) == CONST_INT
- && (new = simplify_binary_operation (ASHIFT, result_mode,
- XEXP (varop, 1),
- GEN_INT (count))) != 0
+ && (new = simplify_const_binary_operation (ASHIFT, result_mode,
+ XEXP (varop, 1),
+ GEN_INT (count))) != 0
&& GET_CODE (new) == CONST_INT
&& merge_outer_ops (&outer_op, &outer_const, PLUS,
INTVAL (new), result_mode, &complement_p))
if (code == LSHIFTRT
&& GET_CODE (XEXP (varop, 1)) == CONST_INT
&& mode_signbit_p (result_mode, XEXP (varop, 1))
- && (new = simplify_binary_operation (code, result_mode,
- XEXP (varop, 1),
- GEN_INT (count))) != 0
+ && (new = simplify_const_binary_operation (code, result_mode,
+ XEXP (varop, 1),
+ GEN_INT (count))) != 0
&& GET_CODE (new) == CONST_INT
&& merge_outer_ops (&outer_op, &outer_const, XOR,
INTVAL (new), result_mode, &complement_p))
if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
&& GET_CODE (XEXP (varop, 0)) == ASHIFTRT
- && count == (unsigned int)
- (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
+ && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
&& (code == LSHIFTRT || code == ASHIFTRT)
&& GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
- == count
+ && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
&& rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
{
count = 0;
a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
to the result of the shift. OUTER_CONST is the relevant constant,
- but we must turn off all bits turned off in the shift.
-
- If we were passed a value for X, see if we can use any pieces of
- it. If not, make new rtx. */
+ but we must turn off all bits turned off in the shift. */
- if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
- && GET_CODE (XEXP (x, 1)) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
- const_rtx = XEXP (x, 1);
- else
- const_rtx = GEN_INT (count);
-
- if (x && GET_CODE (XEXP (x, 0)) == SUBREG
- && GET_MODE (XEXP (x, 0)) == shift_mode
- && SUBREG_REG (XEXP (x, 0)) == varop)
- varop = XEXP (x, 0);
- else if (GET_MODE (varop) != shift_mode)
- varop = gen_lowpart (shift_mode, varop);
-
- /* If we can't make the SUBREG, try to return what we were given. */
- if (GET_CODE (varop) == CLOBBER)
- return x ? x : varop;
+ if (outer_op == UNKNOWN
+ && orig_code == code && orig_count == count
+ && varop == orig_varop
+ && shift_mode == GET_MODE (varop))
+ return NULL_RTX;
- new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
- if (new != 0)
- x = new;
- else
- x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
+ /* Make a SUBREG if necessary. If we can't make it, fail. */
+ varop = gen_lowpart (shift_mode, varop);
+ if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
+ return NULL_RTX;
/* If we have an outer operation and we just made a shift, it is
possible that we could have simplified the shift were it not
for the outer operation. So try to do the simplification
recursively. */
- if (outer_op != UNKNOWN && GET_CODE (x) == code
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
- x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
- INTVAL (XEXP (x, 1)));
+ if (outer_op != UNKNOWN)
+ x = simplify_shift_const_1 (code, shift_mode, varop, count);
+ else
+ x = NULL_RTX;
+
+ if (x == NULL_RTX)
+ x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
/* If we were doing an LSHIFTRT in a wider mode than it was originally,
turn off all the bits that the shift would have turned off. */
else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
else
- x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
+ x = simplify_gen_binary (outer_op, result_mode, x,
+ GEN_INT (outer_const));
}
return x;
}
+
+/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
+ The result of the shift is RESULT_MODE. If we cannot simplify it,
+ return X or, if it is NULL, synthesize the expression with
+ simplify_gen_binary. Otherwise, return a simplified value.
+
+ The shift is normally computed in the widest mode we find in VAROP, as
+ long as it isn't a different number of words than RESULT_MODE. Exceptions
+ are ASHIFTRT and ROTATE, which are always done in their original mode. */
+
+static rtx
+simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
+ rtx varop, int count)
+{
+ rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
+ if (tem)
+ return tem;
+
+ if (!x)
+ x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
+ if (GET_MODE (x) != result_mode)
+ x = gen_lowpart (result_mode, x);
+ return x;
+}
+
\f
/* Like recog, but we receive the address of a pointer to a new pattern.
We try to match the rtx that the pointer points to.
if (WORDS_BIG_ENDIAN)
offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
- /* Adjust the address so that the address-after-the-data is unchanged. */
+ /* Adjust the address so that the address-after-the-data is
+ unchanged. */
if (BYTES_BIG_ENDIAN)
offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
return gen_rtx_CLOBBER (imode, const0_rtx);
}
\f
-/* These routines make binary and unary operations by first seeing if they
- fold; if not, a new expression is allocated. */
-
-static rtx
-gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
-{
- rtx result;
- rtx tem;
-
- if (GET_CODE (op0) == CLOBBER)
- return op0;
- else if (GET_CODE (op1) == CLOBBER)
- return op1;
-
- if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
- && swap_commutative_operands_p (op0, op1))
- tem = op0, op0 = op1, op1 = tem;
-
- if (GET_RTX_CLASS (code) == RTX_COMPARE
- || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
- {
- enum machine_mode op_mode = GET_MODE (op0);
-
- /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
- just (REL_OP X Y). */
- if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
- {
- op1 = XEXP (op0, 1);
- op0 = XEXP (op0, 0);
- op_mode = GET_MODE (op0);
- }
-
- if (op_mode == VOIDmode)
- op_mode = GET_MODE (op1);
- result = simplify_relational_operation (code, mode, op_mode, op0, op1);
- }
- else
- result = simplify_binary_operation (code, mode, op0, op1);
-
- if (result)
- return result;
-
- /* Put complex operands first and constants second. */
- if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
- && swap_commutative_operands_p (op0, op1))
- return gen_rtx_fmt_ee (code, mode, op1, op0);
-
- /* If we are turning off bits already known off in OP0, we need not do
- an AND. */
- else if (code == AND && GET_CODE (op1) == CONST_INT
- && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
- && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
- return op0;
-
- return gen_rtx_fmt_ee (code, mode, op0, op1);
-}
-\f
/* Simplify a comparison between *POP0 and *POP1 where CODE is the
comparison code that will be tested.
op0 = force_to_mode (op0, mode,
((HOST_WIDE_INT) 1
<< (GET_MODE_BITSIZE (mode) - 1)),
- NULL_RTX, 0);
+ 0);
/* Now try cases based on the opcode of OP0. If none of the cases
does a "continue", we exit this loop immediately after the
break;
case SIGN_EXTEND:
- /* Can simplify (compare (zero/sign_extend FOO) CONST)
- to (compare FOO CONST) if CONST fits in FOO's mode and we
- are either testing inequality or have an unsigned comparison
- with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
- if (! unsigned_comparison_p
- && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
- <= HOST_BITS_PER_WIDE_INT)
+ /* Can simplify (compare (zero/sign_extend FOO) CONST) to
+ (compare FOO CONST) if CONST fits in FOO's mode and we
+ are either testing inequality or have an unsigned
+ comparison with ZERO_EXTEND or a signed comparison with
+ SIGN_EXTEND. But don't do it if we don't have a compare
+ insn of the given mode, since we'd have to revert it
+ later on, and then we wouldn't know whether to sign- or
+ zero-extend. */
+ mode = GET_MODE (XEXP (op0, 0));
+ if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
+ && ! unsigned_comparison_p
+ && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
&& ((unsigned HOST_WIDE_INT) const_op
- < (((unsigned HOST_WIDE_INT) 1
- << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
+ < (((unsigned HOST_WIDE_INT) 1
+ << (GET_MODE_BITSIZE (mode) - 1))))
+ && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
op0 = XEXP (op0, 0);
continue;
/* (A - C1) always sign-extends, like C2. */
&& num_sign_bit_copies (a, inner_mode)
> (unsigned int) (GET_MODE_BITSIZE (inner_mode)
- - mode_width - 1)))
+ - (mode_width - 1))))
{
op0 = SUBREG_REG (op0);
continue;
/* ... fall through ... */
case ZERO_EXTEND:
- if ((unsigned_comparison_p || equality_comparison_p)
- && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
- <= HOST_BITS_PER_WIDE_INT)
- && ((unsigned HOST_WIDE_INT) const_op
- < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
+ mode = GET_MODE (XEXP (op0, 0));
+ if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
+ && (unsigned_comparison_p || equality_comparison_p)
+ && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
+ && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
+ && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
op0 = XEXP (op0, 0);
continue;
if (code == LT || code == NE)
new_code = GET_CODE (op0);
else
- new_code = combine_reversed_comparison_code (op0);
+ new_code = reversed_comparison_code (op0, NULL);
if (new_code != UNKNOWN)
{
&& XEXP (XEXP (op0, 0), 0) == const1_rtx)
{
op0 = simplify_and_const_int
- (op0, mode, gen_rtx_LSHIFTRT (mode,
- XEXP (op0, 1),
- XEXP (XEXP (op0, 0), 1)),
+ (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
+ XEXP (op0, 1),
+ XEXP (XEXP (op0, 0), 1)),
(HOST_WIDE_INT) 1);
continue;
}
&& c1 != mask
&& c1 != GET_MODE_MASK (tmode))
{
- op0 = gen_binary (AND, tmode,
- SUBREG_REG (XEXP (op0, 0)),
- gen_int_mode (c1, tmode));
+ op0 = simplify_gen_binary (AND, tmode,
+ SUBREG_REG (XEXP (op0, 0)),
+ gen_int_mode (c1, tmode));
op0 = gen_lowpart (mode, op0);
continue;
}
{
rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
rtx add_const = XEXP (XEXP (op0, 0), 1);
- rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
- XEXP (op0, 1));
+ rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
+ add_const, XEXP (op0, 1));
- op0 = gen_binary (PLUS, tmode,
- gen_lowpart (tmode, inner),
- new_const);
+ op0 = simplify_gen_binary (PLUS, tmode,
+ gen_lowpart (tmode, inner),
+ new_const);
continue;
}
make a new AND in the proper mode. */
if (GET_CODE (op0) == AND
&& !have_insn_for (AND, mode))
- op0 = gen_binary (AND, tmode,
- gen_lowpart (tmode,
- XEXP (op0, 0)),
- gen_lowpart (tmode,
- XEXP (op0, 1)));
+ op0 = simplify_gen_binary (AND, tmode,
+ gen_lowpart (tmode,
+ XEXP (op0, 0)),
+ gen_lowpart (tmode,
+ XEXP (op0, 1)));
op0 = gen_lowpart (tmode, op0);
if (zero_extended && GET_CODE (op1) == CONST_INT)
if (op1 == const0_rtx && (code == LT || code == GE)
&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
{
- op0 = gen_binary (AND, tmode,
- gen_lowpart (tmode, op0),
- GEN_INT ((HOST_WIDE_INT) 1
- << (GET_MODE_BITSIZE (mode) - 1)));
+ op0 = simplify_gen_binary (AND, tmode,
+ gen_lowpart (tmode, op0),
+ GEN_INT ((HOST_WIDE_INT) 1
+ << (GET_MODE_BITSIZE (mode)
+ - 1)));
code = (code == LT) ? NE : EQ;
break;
}
return code;
}
\f
-/* Like jump.c' reversed_comparison_code, but use combine infrastructure for
- searching backward. */
-static enum rtx_code
-combine_reversed_comparison_code (rtx exp)
-{
- enum rtx_code code1 = reversed_comparison_code (exp, NULL);
- rtx x;
-
- if (code1 != UNKNOWN
- || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
- return code1;
- /* Otherwise try and find where the condition codes were last set and
- use that. */
- x = get_last_value (XEXP (exp, 0));
- if (!x || GET_CODE (x) != COMPARE)
- return UNKNOWN;
- return reversed_comparison_code_parts (GET_CODE (exp),
- XEXP (x, 0), XEXP (x, 1), NULL);
-}
-
-/* Return comparison with reversed code of EXP and operands OP0 and OP1.
- Return NULL_RTX in case we fail to do the reversal. */
-static rtx
-reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
-{
- enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
- if (reversed_code == UNKNOWN)
- return NULL_RTX;
- else
- return gen_binary (reversed_code, mode, op0, op1);
-}
-\f
/* Utility function for record_value_for_reg. Count number of
rtxs in X. */
static int
reg_stat[i].last_set_nonzero_bits = 0;
reg_stat[i].last_set_sign_bit_copies = 0;
reg_stat[i].last_death = 0;
+ reg_stat[i].truncated_to_mode = 0;
}
/* Mark registers that are being referenced in this value. */
for (i = regno; i < endregno; i++)
{
reg_stat[i].last_set_label = label_tick;
- if (value && reg_stat[i].last_set_table_tick == label_tick)
+ if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
reg_stat[i].last_set_invalid = 1;
else
reg_stat[i].last_set_invalid = 0;
if (GET_CODE (dest) == SUBREG)
dest = SUBREG_REG (dest);
+ if (!record_dead_insn)
+ {
+ if (REG_P (dest))
+ record_value_for_reg (dest, NULL_RTX, NULL_RTX);
+ return;
+ }
+
if (REG_P (dest))
{
/* If we are setting the whole register, we know its value. Otherwise
reg_stat[i].last_set_nonzero_bits = 0;
reg_stat[i].last_set_sign_bit_copies = 0;
reg_stat[i].last_death = 0;
+ reg_stat[i].truncated_to_mode = 0;
}
last_call_cuid = mem_last_set = INSN_CUID (insn);
- /* Don't bother recording what this insn does. It might set the
- return value register, but we can't combine into a call
- pattern anyway, so there's no point trying (and it may cause
- a crash, if e.g. we wind up asking for last_set_value of a
- SUBREG of the return value register). */
- return;
+ /* We can't combine into a call pattern. Remember, though, that
+ the return value register is set at this CUID. We could
+ still replace a register with the return value from the
+ wrong subroutine call! */
+ note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
}
-
- note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
+ else
+ note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
}
/* If a SUBREG has the promoted bit set, it is in fact a property of the
}
}
-/* Scan X for promoted SUBREGs. For each one found,
- note what it implies to the registers used in it. */
+/* Check if X, a register, is known to contain a value already
+ truncated to MODE. In this case we can use a subreg to refer to
+ the truncated value even though in the generic case we would need
+ an explicit truncation. */
+
+static bool
+reg_truncated_to_mode (enum machine_mode mode, rtx x)
+{
+ enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
+
+ if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
+ return false;
+ if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
+ return true;
+ if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
+ GET_MODE_BITSIZE (truncated)))
+ return true;
+ return false;
+}
+
+/* X is a REG or a SUBREG. If X is some sort of a truncation record
+ it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
+ a truncate into a subreg using this information. */
+
+static void
+record_truncated_value (rtx x)
+{
+ enum machine_mode truncated_mode;
+
+ if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
+ {
+ enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
+ truncated_mode = GET_MODE (x);
+
+ if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
+ return;
+
+ if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
+ GET_MODE_BITSIZE (original_mode)))
+ return;
+
+ x = SUBREG_REG (x);
+ }
+ /* ??? For hard-regs we now record everthing. We might be able to
+ optimize this using last_set_mode. */
+ else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
+ truncated_mode = GET_MODE (x);
+ else
+ return;
+
+ if (reg_stat[REGNO (x)].truncated_to_mode == 0
+ || reg_stat[REGNO (x)].truncation_label < label_tick
+ || (GET_MODE_SIZE (truncated_mode)
+ < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
+ {
+ reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
+ reg_stat[REGNO (x)].truncation_label = label_tick;
+ }
+}
+
+/* Scan X for promoted SUBREGs and truncated REGs. For each one
+ found, note what it implies to the registers used in it. */
static void
-check_promoted_subreg (rtx insn, rtx x)
+check_conversions (rtx insn, rtx x)
{
- if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
- && REG_P (SUBREG_REG (x)))
- record_promoted_value (insn, x);
+ if (GET_CODE (x) == SUBREG || REG_P (x))
+ {
+ if (GET_CODE (x) == SUBREG
+ && SUBREG_PROMOTED_VAR_P (x)
+ && REG_P (SUBREG_REG (x)))
+ record_promoted_value (insn, x);
+
+ record_truncated_value (x);
+ }
else
{
const char *format = GET_RTX_FORMAT (GET_CODE (x));
switch (format[i])
{
case 'e':
- check_promoted_subreg (insn, XEXP (x, i));
+ check_conversions (insn, XEXP (x, i));
break;
case 'V':
case 'E':
if (XVEC (x, i) != 0)
for (j = 0; j < XVECLEN (x, i); j++)
- check_promoted_subreg (insn, XVECEXP (x, i, j));
+ check_conversions (insn, XVECEXP (x, i, j));
break;
}
}
|| (! (regno >= FIRST_PSEUDO_REGISTER
&& REG_N_SETS (regno) == 1
&& (! REGNO_REG_SET_P
- (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
+ (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
+ regno)))
&& reg_stat[j].last_set_label > tick))
{
if (replace)
&& (regno < FIRST_PSEUDO_REGISTER
|| REG_N_SETS (regno) != 1
|| (REGNO_REG_SET_P
- (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
+ (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
+ regno)))))
return 0;
/* If the value was set in a later insn than the ones we are processing,
}
for (i = reg_dead_regno; i < reg_dead_endregno; i++)
- if (REGNO_REG_SET_P (block->global_live_at_start, i))
+ if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
return 0;
return 1;
as appropriate. I3 and I2 are the insns resulting from the combination
insns including FROM (I2 may be zero).
+ ELIM_I2 and ELIM_I1 are either zero or registers that we know will
+ not need REG_DEAD notes because they are being substituted for. This
+ saves searching in the most common cases.
+
Each note in the list is either ignored or placed on some insns, depending
on the type of note. */
static void
-distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
+distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
+ rtx elim_i1)
{
rtx note, next_note;
rtx tem;
{
rtx place = 0, place2 = 0;
- /* If this NOTE references a pseudo register, ensure it references
- the latest copy of that register. */
- if (XEXP (note, 0) && REG_P (XEXP (note, 0))
- && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
- XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
-
next_note = XEXP (note, 1);
switch (REG_NOTE_KIND (note))
{
}
break;
- case REG_ALWAYS_RETURN:
case REG_NORETURN:
case REG_SETJMP:
/* These notes must remain with the call. It should not be
&& reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
place = i2;
+ if (place == 0
+ && (rtx_equal_p (XEXP (note, 0), elim_i2)
+ || rtx_equal_p (XEXP (note, 0), elim_i1)))
+ break;
+
if (place == 0)
{
basic_block bb = this_basic_block;
+ /* You might think you could search back from FROM_INSN
+ rather than from I3, but combine tries to split invalid
+ combined instructions. This can result in the old I2
+ or I1 moving later in the insn sequence. */
for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
{
if (! INSN_P (tem))
PATTERN (tem) = pc_rtx;
REG_NOTES (tem) = NULL;
- distribute_notes (old_notes, tem, tem, NULL_RTX);
+ distribute_notes (old_notes, tem, tem, NULL_RTX,
+ NULL_RTX, NULL_RTX);
distribute_links (LOG_LINKS (tem));
SET_INSN_DELETED (tem);
REG_NOTES (cc0_setter) = NULL;
distribute_notes (old_notes, cc0_setter,
- cc0_setter, NULL_RTX);
+ cc0_setter, NULL_RTX,
+ NULL_RTX, NULL_RTX);
distribute_links (LOG_LINKS (cc0_setter));
SET_INSN_DELETED (cc0_setter);
|| (CALL_P (tem)
&& find_reg_fusage (tem, USE, XEXP (note, 0))))
{
+ /* This may not be the correct place for the death
+ note if FROM_INSN is before TEM, and the reg is
+ set between FROM_INSN and TEM. The reg might
+ die two or more times. An existing death note
+ means we are looking at the wrong live range. */
+ if (from_insn
+ && INSN_CUID (from_insn) < INSN_CUID (tem)
+ && find_regno_note (tem, REG_DEAD,
+ REGNO (XEXP (note, 0))))
+ {
+ tem = from_insn;
+ if (tem == BB_HEAD (bb))
+ break;
+ continue;
+ }
+
place = tem;
/* If we are doing a 3->2 combination, and we have a
was dead, there's nothing left to do. Otherwise, we'll
need to do a global life update after combine. */
if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
- && REGNO_REG_SET_P (bb->global_live_at_start,
+ && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
REGNO (XEXP (note, 0))))
SET_BIT (refresh_blocks, this_basic_block->index);
}
= gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
distribute_notes (new_note, place, place,
- NULL_RTX);
+ NULL_RTX, NULL_RTX, NULL_RTX);
}
else if (! refers_to_regno_p (i, i + 1,
PATTERN (place), 0)
void
dump_combine_stats (FILE *file)
{
- fnotice
+ fprintf
(file,
";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
combine_attempts, combine_merges, combine_extras, combine_successes);
void
dump_combine_total_stats (FILE *file)
{
- fnotice
+ fprintf
(file,
"\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
total_attempts, total_merges, total_extras, total_successes);
}
+\f
+
+static bool
+gate_handle_combine (void)
+{
+ return (optimize > 0);
+}
+
+/* Try combining insns through substitution. */
+static void
+rest_of_handle_combine (void)
+{
+ int rebuild_jump_labels_after_combine
+ = combine_instructions (get_insns (), max_reg_num ());
+
+ /* Combining insns may have turned an indirect jump into a
+ direct jump. Rebuild the JUMP_LABEL fields of jumping
+ instructions. */
+ if (rebuild_jump_labels_after_combine)
+ {
+ timevar_push (TV_JUMP);
+ rebuild_jump_labels (get_insns ());
+ timevar_pop (TV_JUMP);
+
+ delete_dead_jumptables ();
+ cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
+ }
+}
+
+struct tree_opt_pass pass_combine =
+{
+ "combine", /* name */
+ gate_handle_combine, /* gate */
+ rest_of_handle_combine, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_COMBINE, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ TODO_dump_func |
+ TODO_ggc_collect, /* todo_flags_finish */
+ 'c' /* letter */
+};
+
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