+2012-02-22 Richard Guenther <rguenther@suse.de>
+
+ PR middle-end/52329
+ * gimple-fold.c (fold_stmt_1): Also canonicalize ADDR_EXPRs
+ for GIMPLE_DEBUG stmts.
+
+2012-02-22 Martin Jambor <mjambor@suse.cz>
+
+ PR middle-end/51782
+ * emit-rtl.c (set_mem_attributes_minus_bitpos): Set address space
+ according to the base object.
+
+2012-02-22 Georg-Johann Lay <avr@gjlay.de>
+
+ PR rtl-optimization/50063
+ * config/avr/avr.md (movhi_sp_r): Handle -1 (unknown IRQ state)
+ and 2 (8-bit SP) in operand 2.
+ * config/avr/avr.c (avr_prologue_setup_frame): Adjust prologue
+ setup to use movhi_sp_r instead of vanilla move to write SP.
+ Adjust REG_CFA notes to superseed unspec.
+ (expand_epilogue): Adjust epilogue setup to use movhi_sp_r instead
+ of vanilla move.
+ As function body might contain CLI or SEI: Use irq_state 0 (IRQ
+ known to be off) only with TARGET_NO_INTERRUPTS. Never use
+ irq_state 1 (IRQ known to be on) here.
+
+2012-02-21 Bernd Schmidt <bernds@codesourcery.com>
+
+ * ira.c (check_allocation): Use REG_WORDS_BIG_ENDIAN, not
+ WORDS_BIG_ENDIAN.
+ * ira-color.c (setup_profitable_hard_regs, check_hard_reg_p,
+ assign_hard_reg): Likewise.
+
+2012-02-21 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.md (neghi2): Remove "!d,0" alternative. Tweak "r,0".
+
+2012-02-21 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.md
+ (*dec-and-branchhi!=-1.d.clobber): New text peephole.
+ (*dec-and-branchhi!=-1.l.clobber): New text peephole.
+
+2012-02-21 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr-protos.h (avr_accumulate_outgoing_args): Move
+ prototype from here to...
+ * config/avr/avr.h: ...here.
+
+2012-02-21 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/52294
+ * thumb2.md (thumb2_shiftsi3_short): Split register and
+ immediate shifts. For register shifts tie operands 0 and 1.
+ (peephole2 for above): Check that register-controlled shifts
+ have suitably tied operands.
+
+2012-02-21 Quentin Neill <quentin.neill@amd.com>
+
+ PR target/52137
+ * config/i386/bdver1.md (bdver1_call, bdver1_push,
+ bdver1_pop, bdver1_leave, bdver1_lea, bdver1_imul_DI, bdver1_imul,
+ bdver1_imul_mem_DI, bdver1_imul_mem, bdver1_idiv, bdver1_idiv_mem,
+ bdver1_str, bdver1_idirect, bdver1_ivector, bdver1_idirect_loadmov,
+ bdver1_idirect_load, bdver1_ivector_load, bdver1_idirect_movstore,
+ bdver1_idirect_both, bdver1_ivector_both, bdver1_idirect_store,
+ bdver1_ivector_store, bdver1_fldxf, bdver1_fld, bdver1_fstxf,
+ bdver1_fst, bdver1_fist, bdver1_fmov_bdver1, bdver1_fadd_load,
+ bdver1_fadd, bdver1_fmul_load, bdver1_fmul, bdver1_fsgn,
+ bdver1_fdiv_load, bdver1_fdiv, bdver1_fpspc_load, bdver1_fpspc,
+ bdver1_fcmov_load, bdver1_fcmov, bdver1_fcomi_load,
+ bdver1_fcomi, bdver1_fcom_load, bdver1_fcom,
+ bdver1_fxch, bdver1_ssevector_avx128_unaligned_load,
+ bdver1_ssevector_avx256_unaligned_load,
+ bdver1_ssevector_sse128_unaligned_load,
+ bdver1_ssevector_avx128_load, bdver1_ssevector_avx256_load,
+ bdver1_ssevector_sse128_load, bdver1_ssescalar_movq_load,
+ bdver1_ssescalar_vmovss_load, bdver1_ssescalar_sse128_load,
+ bdver1_mmxsse_load, bdver1_sse_store_avx256, bdver1_sse_store,
+ bdver1_mmxsse_store_short, bdver1_ssevector_avx256,
+ bdver1_movss_movsd, bdver1_mmxssemov, bdver1_sselog_load_256,
+ bdver1_sselog_256, bdver1_sselog_load, bdver1_sselog,
+ bdver1_ssecmp_load, bdver1_ssecmp, bdver1_ssecomi_load,
+ bdver1_ssecomi, bdver1_vcvtX2Y_avx256_load, bdver1_vcvtX2Y_avx256,
+ bdver1_ssecvt_cvtss2sd_load, bdver1_ssecvt_cvtss2sd,
+ bdver1_sseicvt_cvtsi2sd_load, bdver1_sseicvt_cvtsi2sd,
+ bdver1_ssecvt_cvtpd2ps_load, bdver1_ssecvt_cvtpd2ps,
+ bdver1_ssecvt_cvtdq2ps_load, bdver1_ssecvt_cvtdq2ps,
+ bdver1_ssecvt_cvtdq2pd_load, bdver1_ssecvt_cvtdq2pd,
+ bdver1_ssecvt_cvtps2pd_load, bdver1_ssecvt_cvtps2pd,
+ bdver1_ssecvt_cvtsX2si_load, bdver1_ssecvt_cvtsX2si,
+ bdver1_ssecvt_cvtpd2pi_load, bdver1_ssecvt_cvtpd2pi,
+ bdver1_ssecvt_cvtpd2dq_load, bdver1_ssecvt_cvtpd2dq,
+ bdver1_ssecvt_cvtps2pi_load, bdver1_ssecvt_cvtps2pi,
+ bdver1_ssemuladd_load_256, bdver1_ssemuladd_256,
+ bdver1_ssemuladd_load, bdver1_ssemuladd, bdver1_sseimul_load,
+ bdver1_sseimul, bdver1_sseiadd_load, bdver1_sseiadd,
+ bdver1_ssediv_double_load_256, bdver1_ssediv_double_256,
+ bdver1_ssediv_single_load_256, bdver1_ssediv_single_256,
+ bdver1_ssediv_double_load, bdver1_ssediv_double,
+ bdver1_ssediv_single_load, bdver1_ssediv_single, bdver1_sseins):
+ Add "bdver2" attribute.
+
+2012-02-21 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/s390/s390.c (s390_option_override): Make -mhard-dfp the
+ default if possible and not specified otherwise.
+
+2012-02-21 Richard Guenther <rguenther@suse.de>
+
+ PR middle-end/52314
+ * gimplify.c (create_tmp_from_val): Use the main variant type
+ for the type of the temporary we create.
+
+2012-02-21 Richard Guenther <rguenther@suse.de>
+
+ PR tree-optimization/52324
+ * gimplify.c (gimplify_expr): When re-gimplifying expressions
+ do not gimplify a MEM_REF address operand if it is already
+ in suitable form.
+
+2012-02-21 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * config/s390/s390.md ("fixuns_trunc<mode>si2"): Replace
+ TARGET_HARD_FLOAT with TARGET_HARD_DFP.
+
+2012-02-21 Richard Guenther <rguenther@suse.de>
+
+ * tree-vect-stmts.c (vectorizable_load): Use pre-computed
+ nested_in_vect_loop.
+
+2012-02-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/52318
+ * gimple-fold.c (gimplify_and_update_call_from_tree): Add
+ vdef also to non-pure/const call stmts in the sequence.
+
+2012-02-20 David S. Miller <davem@davemloft.net>
+
+ * config/sparc/sparc.md (load_pcrel_sym<P:mode>): Explain why we
+ don't use the "rd %pc" instruction on v9 for PIC register loads.
+
+2012-02-20 Aldy Hernandez <aldyh@redhat.com>
+
+ PR middle-end/52141
+ * trans-mem.c (ipa_tm_scan_irr_block): Error out on GIMPLE_ASM's
+ in a transaction safe function.
+
+2012-02-20 Kai Tietz <ktietz@redhat.com>
+
+ PR target/52238
+ * stor-layout.c (place_field): Handle desired_align for
+ ms-bitfields, too.
+
+2012-02-20 Richard Guenther <rguenther@suse.de>
+
+ PR tree-optimization/52298
+ * tree-vect-stmts.c (vectorizable_store): Properly use
+ STMT_VINFO_DR_STEP instead of DR_STEP when vectorizing
+ outer loops.
+ (vectorizable_load): Likewise.
+ * tree-vect-data-refs.c (vect_analyze_data_ref_access):
+ Access DR_STEP after ensuring it is not NULL.
+
+2012-02-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/52286
+ * fold-const.c (fold_binary_loc): For (X & C1) | C2
+ optimization use double_int_to_tree instead of build_int_cst_wide,
+ rewrite to use double_int vars.
+
+2012-02-20 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ PR target/50166
+ * acinclude.m4 (gcc_AC_INITFINI_ARRAY): Require gcc_SUN_LD_VERSION.
+ Define _start.
+ Remove -e 0 from $gcc_cv_ld invocation.
+ Only use __GLIBC_PREREQ if defined.
+ Enable on Solaris since Solaris 8 patch.
+ (gcc_SUN_LD_VERSION): New macro.
+ * configure.ac (ld_ver) <*-*-solaris2*>: Refer to
+ gcc_SUN_LD_VERSION for version number format.
+ * configure: Regenerate.
+ * varasm.c (get_elf_initfini_array_priority_section): Set
+ SECTION_NOTYPE for non-default priority.
+ Use get_section instead of get_unnamed_section to emit
+ .init_array/.fini_array with default priority.
+
+2012-02-19 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/mips/mips.c (mips_need_mips16_rdhwr_p): New variable.
+ (mips_get_tp): Set it. Record that __mips16_rdhwr binds locally.
+ (mips_start_unique_function, mips_output_mips16_rdhwr)
+ (mips_code_end): New functions.
+ (TARGET_ASM_CODE_END): Define.
+
+2012-02-19 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * config/mips/mips.c (mips16_build_call_stub): Add CFI information
+ to stubs with non-sibling calls.
+
+2012-02-18 Sandra Loosemore <sandra@codesourcery.com>
+
+ * doc/invoke.texi (-fira-* options): Copy-edit.
+ (ira-* parameters): Copy-edit.
+
+2012-02-17 Sandra Loosemore <sandra@codesourcery.com>
+
+ * doc/invoke.texi: Minor copy-edits to bring into conformance with
+ GCC coding conventions.
+
+2012-02-17 Sandra Loosemore <sandra@codesourcery.com>
+
+ * doc/invoke.texi: Consistently hyphenate "big-endian"/"little-endian"
+ when used as adjectives.
+
2012-02-16 Sandra Loosemore <sandra@codesourcery.com>
* doc/invoke.texi: Clean up "that"/"which" confusion.
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