+2007-09-14 Jan Hubicka <jh@suse.cz>
+
+ * config/i386/i386.md (*floatdi<mode>2_i387): Guard against
+ TARGET_64BIT.
+
+2007-09-14 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/33438
+ * config/i386/i386.md (fmodxf3): Copy operands[2] to temporary register
+ when operands[2] equals operands[1].
+ (remainderxf3): Ditto.
+
+2007-09-14 Sandra Loosemore <sandra@codesourcery.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * doc/tm.texi (LIBGCC2_UNWIND_ATTRIBUTE): Document.
+ * unwind-generic.h (LIBGCC2_UNWIND_ATTRIBUTE): Define.
+ (_Unwind_RaiseException): Add LIBGCC2_UNWIND_ATTRIBUTE to
+ declaration.
+ (_Unwind_ForcedUnwind): Likewise.
+ (_Unwind_Resume): Likewise.
+ (_Unwind_Resume_or_Rethrow): Likewise.
+ (_Unwind_Backtrace): Likewise.
+ (_Unwind_SjLj_RaiseException): Likewise.
+ (_Unwind_SjLj_ForcedUnwind): Likewise.
+ (_Unwind_SjLj_Resume): Likewise.
+ (_Unwind_SjLj_Resume_or_Rethrow): Likewise.
+ * unwind.inc (_Unwind_RaiseException): Add LIBGCC2_UNWIND_ATTRIBUTE
+ to definition.
+ (_Unwind_ForcedUnwind): Likewise.
+ (_Unwind_Resume): Likewise.
+ (_Unwind_Resume_or_Rethrow): Likewise.
+ (_Unwind_Backtrace): Likewise.
+ * unwind-compat.c (_Unwind_Backtrace): Likewise.
+ (_Unwind_ForcedUnwind): Likewise.
+ (_Unwind_RaiseException): Likewise.
+ (_Unwind_Resume): Likewise.
+ (_Unwind_Resume_or_Rethrow): Likewise.
+
+ * config/mips/mips.h (LIBGCC2_UNWIND_ATTRIBUTE): Define to force
+ nomips16 mode when IN_LIBGCC2 with hard float.
+
+2007-09-14 Richard Sandiford <rsandifo@nildram.co.uk>
+
+ * config/mips/sdemtk.opt: Update to GPLv3.
+ * config/mips/sdemtk.h: Likewise.
+
+2007-09-14 Nigel Stephens <nigel@mips.com>
+
+ * config.gcc (mips*-*-linux*): Recognise mipsisa32r2 and set
+ MIPS_ISA_DEFAULT appropriately. Don't make soft-float the default
+ for mipsisa32-*-linux*.
+
+2007-09-14 Nigel Stephens <nigel@mips.com>
+ David Ung <davidu@mips.com>
+ Thiemo Seufer <ths@mips.com>
+ Richard Sandiford <richard@codesourcery.com>
+
+ * config.gcc (mips*-sde-elf*): Add support for the SDE C libraries.
+ * configure.ac: Add a mipssde threading type.
+ * configure: Regenerate.
+ * config/mips/sdemtk.h: New file.
+ * config/mips/t-sdemtk: Likewise.
+ * config/mips/sdemtk.opt: Likewise.
+ * gthr-mipssde.h: Likewise.
+ * config/mips/sde.h (FUNCTION_PROFILER): Move to config/mips/sdemtk.h.
+ * config/mips/mips.h (MIPS_SAVE_REG_FOR_PROFILING_P): New macro.
+ (MIPS_ICACHE_SYNC): New macro, split from ...
+ * config/mips/mips.md (clear_cache): ...here.
+ * config/mips/mips.c (mips_save_reg_p): Check
+ MIPS_SAVE_REG_FOR_PROFILING_P on profiled functions.
+ (build_mips16_function_stub): Use targetm.strip_name_encoding.
+ (build_mips16_call_stub): Likewise.
+
+2007-09-14 Richard Sandiford <richard@codesourcery.com>
+
+ * Makefile.in (stmp-int-hdrs): Depend on fixinc_list.
+
+2007-09-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/32337
+ * config/ia64/ia64.c (find_gr_spill): Don't decrement
+ current_frame_info.n_local_regs. Don't return emitted local
+ regs.
+ (ia64_compute_frame_size): Improve unwind hack to put
+ RP, PFS, FP in that order by allowing some of the registers
+ been already emitted, as long as they are emitted to the
+ desired register.
+
+2007-09-14 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
+
+ * config/spu/vmx2spu.h (vec_extract, vec_insert, vec_lvlx,
+ vec_lvlxl, vec_lvrx, vec_lvrxl, vec_promote, vec_splats,
+ vec_stvlx, vec_stvlxl, vec_stvrx, vec_stvrxl): New intrinsics.
+
+2007-09-13 Eric Christopher <echristo@apple.com>
+ Kenneth Zadeck <zadeck@naturalbridge.com>
+
+ * dse.c (find_shift_sequence): New function.
+ (replace_read): Add case to remove read if it requires shift.
+ * config/i386/i386.c (ix86_expand_prologue): Fixed typo in comment.
+
+2007-09-13 Tom Tromey <tromey@redhat.com>
+
+ * c-common.c (fname_as_string): Update.
+ * c-parser.c (c_parser) <lex_untranslated_string>: New field.
+ (c_lex_one_token): Update. Add 'parser' argument.
+ (c_parser_simple_asm_expr): Update.
+ (c_parser_attributes): Update.
+ (c_parser_asm_statement): Update.
+ (c_parser_asm_operands): Update.
+ (c_parser_peek_token): Update.
+ (c_parser_peek_2nd_token): Update.
+ * c-lex.c (c_lex_string_translate): Remove.
+ (c_lex_return_raw_strings): Likewise.
+ (c_lex_with_flags): Added 'lex_flags' argument.
+ (lex_string): Added 'translate' argument.
+ * c-pragma.h (c_lex_with_flags): Update.
+ (c_lex_string_translate, c_lex_return_raw_strings): Remove.
+ (C_LEX_STRING_NO_TRANSLATE): New define.
+ (C_LEX_RAW_STRINGS): Likewise.
+
+2007-09-13 Bernd Schmidt <bernd.schmidt@analog.com>
+
+ From Jie Zhang:
+ * config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
+ BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
+ BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
+ (bfin_init_builtins): Initialize __builtin_bfin_ones,
+ __builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
+ __builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
+ __builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
+ __builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
+ __builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
+ (bdesc_1arg): Add __builtin_bfin_ones.
+ (bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
+ __builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
+ and __builtin_bfin_csqu_fr16.
+ * config/bfin/bfin.md (UNSPEC_ONES): New constant.
+ (ones): New define_insn.
+ (ssaddhi3_parts): New define_insn.
+ (sssubhi3_parts): New define_insn.
+ (flag_mulhi_parts): New define_insn.
+
+2007-09-13 Seongbae Park <seongbae.park@gmail.com>
+
+ * common.opt (femit-class-debug-always): Turn off by default.
+
+2007-09-13 Bernd Schmidt <bernd.schmidt@analog.com>
+
+ * config/bfin/bfin.md (reload_outpdi, reload_inpdi): New patterns.
+ * config/bfin/bfin.c (bfin_secondary_reload): Make sure we use them.
+
+2007-09-13 James E. Wilson <wilson@specifix.com>
+
+ PR tree-optimization/33389
+ * tree-ssa-operands.c (append_vuse): If ann->in_vdef_list true,
+ then set build_loads before returning.
+
+2007-09-13 Sandra Loosemore <sandra@codesourcery.com>
+ David Ung <davidu@mips.com>
+
+ * config/mips/mips.h (ASM_OUTPUT_REG_PUSH): Replace {d}subu with
+ {d}addiu and a negative immediate such that it works with MIPS16
+ instructions.
+
+2007-09-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR bootstrap/33418
+ * configure.ac (ld_vers): Support Linux linker.
+ * configure: Regenerated.
+
+2007-09-13 Richard Sandiford <richard@codesourcery.com>
+ Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/mips/mips.h (SYMBOL_FLAG_MIPS16_FUNC): Delete.
+ (SYMBOL_REF_MIPS16_FUNC_P): Delete.
+ * config/mips/mips.c (mips_attribute_table): Turn mips16 and
+ nomips16 into decl attributes.
+ (TARGET_INSERT_ATTRIBUTES): Override.
+ (TARGET_MERGE_DECL_ATTRIBUTES): Likewise.
+ (TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P): Always return true.
+ (mips_mips16_type_p, mips_nomips16_type_p): Delete in favor of...
+ (mips_mips16_decl_p, mips_nomips16_decl_p): ...these new functions.
+ (mips_comp_type_attributes): Remove mips16 and nomips16 handling.
+ (mips_use_mips16_mode_p): Reimplement as a function that takes
+ a decl and considers only decl attributes. If the decl is nested
+ function, use its parent attributes.
+ (mips_function_ok_for_sibcall): Use mips_use_mips16_mode_p
+ instead of SYMBOL_REF_MIPS16_FUNC_P.
+ (mips_set_mips16_mode): Move call to sorry here from old
+ mips_use_mips16_mode_p.
+ (mflip_mips16_entry): New structure.
+ (mflip_mips16_htab): New variable.
+ (mflip_mips16_htab_hash, mflip_mips16_htab_eq): New functions.
+ (mflip_mips16_use_mips16_p, mips_insert_attributes): Likewise.
+ (mips_merge_decl_attributes): New function.
+ (mips_set_current_function): Reinstate call to mips_set_mips16_mode.
+ Use mips_use_mips16_mode_p.
+ (mips_output_mi_thunk): Use mips_use_mips16_mode_p instead of
+ SYMBOL_REF_MIPS16_FUNC_P.
+ (mips_encode_section_info): Don't set SYMBOL_FLAG_MIPS16_FUNC.
+
+2007-09-13 Richard Sandiford <richard@codesourcery.com>
+
+ * c-parser.c (c_parser_struct_declaration): Check for a null return.
+
+2007-09-13 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
+
+ PR driver/33309
+ * gcc.c (xputenv): Make argument const, and use CONST_CAST.
+
+2007-09-12 Michael Meissner <michael.meissner@amd.com>
+ Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Tony Linthicum <tony.linthicum@amd.com>
+
+ * tree.h (function_args_iterator): New type to iterate over
+ function arguments.
+ (FOREACH_FUNCTION_ARGS_PTR): Iterator macros for iterating over
+ function arguments providing a pointer to the argument.
+ (FOREACH_FUNCTION_ARGS): Iterator macros for iterating over
+ function arguments providing the argument.
+ (function_args_iter_init): Inline function to initialize
+ function_args_iterator.
+ (function_args_iter_cond_ptr): Inline function to return the next
+ pointer to hold the argument.
+ (function_args_iter_cond): Inline function to return the next
+ argument.
+ (function_args_iter_cond_next): Advance the function args
+ iterator.
+ (stdarg_p): New function, return true if variable argument
+ function.
+ (prototype_p): New function, return true if function is
+ prototyped.
+ (function_args_count): New function, count the number of arguments
+ of a function.
+
+ * tree.c (stdarg_p): New function, return true if variable
+ argument function.
+ (prototype_p): New function, return true if function is
+ prototyped.
+
+ * config/i386/i386.h (TARGET_SSE5): New macro for SSE5.
+ (TARGET_ROUND): New macro for the round/ptest instructions which
+ are shared between SSE4.1 and SSE5.
+ (OPTION_MASK_ISA_ROUND): Ditto.
+ (OPTION_ISA_ROUND): Ditto.
+ (TARGET_FUSED_MADD): New macro for -mfused-madd swtich.
+ (TARGET_CPU_CPP_BUILTINS): Add SSE5 support.
+
+ * config/i386/i386.opt (-msse5): New switch for SSE5 support.
+ (-mfused-madd): New switch to give users control over whether the
+ compiler optimizes to use the multiply/add SSE5 instructions.
+
+ * config/i386/i386.c (m_AMD_MULTIPLE): Rename from
+ m_ATHLON_K8_AMDFAM10, and change all uses.
+ (enum pta_flags): Add PTA_SSE5.
+ (ix86_handle_option): Turn off 3dnow if -msse5.
+ (override_options): Add SSE5 support.
+ (print_operand): %Y prints comparison codes for SSE5 com/pcom
+ instructions.
+ (ix86_expand_sse_movcc): Add SSE5 support.
+ (ix86_expand_sse5_unpack): New function to use pperm to unpack a
+ vector type to the next largest size.
+ (ix86_expand_sse5_pack): New function to use pperm to pack a
+ vector type to the next smallest size.
+ (IX86_BUILTIN_FMADDSS): New for SSE5 intrinsic.
+ (IX86_BUILTIN_FMADDSD): Ditto.
+ (IX86_BUILTIN_FMADDPS): Ditto.
+ (IX86_BUILTIN_FMADDPD): Ditto.
+ (IX86_BUILTIN_FMSUBSS): Ditto.
+ (IX86_BUILTIN_FMSUBSD): Ditto.
+ (IX86_BUILTIN_FMSUBPS): Ditto.
+ (IX86_BUILTIN_FMSUBPD): Ditto.
+ (IX86_BUILTIN_FNMADDSS): Ditto.
+ (IX86_BUILTIN_FNMADDSD): Ditto.
+ (IX86_BUILTIN_FNMADDPS): Ditto.
+ (IX86_BUILTIN_FNMADDPD): Ditto.
+ (IX86_BUILTIN_FNMSUBSS): Ditto.
+ (IX86_BUILTIN_FNMSUBSD): Ditto.
+ (IX86_BUILTIN_FNMSUBPS): Ditto.
+ (IX86_BUILTIN_FNMSUBPD): Ditto.
+ (IX86_BUILTIN_PCMOV_V2DI): Ditto.
+ (IX86_BUILTIN_PCMOV_V4SI): Ditto.
+ (IX86_BUILTIN_PCMOV_V8HI): Ditto.
+ (IX86_BUILTIN_PCMOV_V16QI): Ditto.
+ (IX86_BUILTIN_PCMOV_V4SF): Ditto.
+ (IX86_BUILTIN_PCMOV_V2DF): Ditto.
+ (IX86_BUILTIN_PPERM): Ditto.
+ (IX86_BUILTIN_PERMPS): Ditto.
+ (IX86_BUILTIN_PERMPD): Ditto.
+ (IX86_BUILTIN_PMACSSWW): Ditto.
+ (IX86_BUILTIN_PMACSWW): Ditto.
+ (IX86_BUILTIN_PMACSSWD): Ditto.
+ (IX86_BUILTIN_PMACSWD): Ditto.
+ (IX86_BUILTIN_PMACSSDD): Ditto.
+ (IX86_BUILTIN_PMACSDD): Ditto.
+ (IX86_BUILTIN_PMACSSDQL): Ditto.
+ (IX86_BUILTIN_PMACSSDQH): Ditto.
+ (IX86_BUILTIN_PMACSDQL): Ditto.
+ (IX86_BUILTIN_PMACSDQH): Ditto.
+ (IX86_BUILTIN_PMADCSSWD): Ditto.
+ (IX86_BUILTIN_PMADCSWD): Ditto.
+ (IX86_BUILTIN_PHADDBW): Ditto.
+ (IX86_BUILTIN_PHADDBD): Ditto.
+ (IX86_BUILTIN_PHADDBQ): Ditto.
+ (IX86_BUILTIN_PHADDWD): Ditto.
+ (IX86_BUILTIN_PHADDWQ): Ditto.
+ (IX86_BUILTIN_PHADDDQ): Ditto.
+ (IX86_BUILTIN_PHADDUBW): Ditto.
+ (IX86_BUILTIN_PHADDUBD): Ditto.
+ (IX86_BUILTIN_PHADDUBQ): Ditto.
+ (IX86_BUILTIN_PHADDUWD): Ditto.
+ (IX86_BUILTIN_PHADDUWQ): Ditto.
+ (IX86_BUILTIN_PHADDUDQ): Ditto.
+ (IX86_BUILTIN_PHSUBBW): Ditto.
+ (IX86_BUILTIN_PHSUBWD): Ditto.
+ (IX86_BUILTIN_PHSUBDQ): Ditto.
+ (IX86_BUILTIN_PROTB): Ditto.
+ (IX86_BUILTIN_PROTW): Ditto.
+ (IX86_BUILTIN_PROTD): Ditto.
+ (IX86_BUILTIN_PROTQ): Ditto.
+ (IX86_BUILTIN_PROTB_IMM): Ditto.
+ (IX86_BUILTIN_PROTW_IMM): Ditto.
+ (IX86_BUILTIN_PROTD_IMM): Ditto.
+ (IX86_BUILTIN_PROTQ_IMM): Ditto.
+ (IX86_BUILTIN_PSHLB): Ditto.
+ (IX86_BUILTIN_PSHLW): Ditto.
+ (IX86_BUILTIN_PSHLD): Ditto.
+ (IX86_BUILTIN_PSHLQ): Ditto.
+ (IX86_BUILTIN_PSHAB): Ditto.
+ (IX86_BUILTIN_PSHAW): Ditto.
+ (IX86_BUILTIN_PSHAD): Ditto.
+ (IX86_BUILTIN_PSHAQ): Ditto.
+ (IX86_BUILTIN_FRCZSS): Ditto.
+ (IX86_BUILTIN_FRCZSD): Ditto.
+ (IX86_BUILTIN_FRCZPS): Ditto.
+ (IX86_BUILTIN_FRCZPD): Ditto.
+ (IX86_BUILTIN_CVTPH2PS): Ditto.
+ (IX86_BUILTIN_CVTPS2PH): Ditto.
+ (IX86_BUILTIN_COMEQSS): Ditto.
+ (IX86_BUILTIN_COMNESS): Ditto.
+ (IX86_BUILTIN_COMLTSS): Ditto.
+ (IX86_BUILTIN_COMLESS): Ditto.
+ (IX86_BUILTIN_COMGTSS): Ditto.
+ (IX86_BUILTIN_COMGESS): Ditto.
+ (IX86_BUILTIN_COMUEQSS): Ditto.
+ (IX86_BUILTIN_COMUNESS): Ditto.
+ (IX86_BUILTIN_COMULTSS): Ditto.
+ (IX86_BUILTIN_COMULESS): Ditto.
+ (IX86_BUILTIN_COMUGTSS): Ditto.
+ (IX86_BUILTIN_COMUGESS): Ditto.
+ (IX86_BUILTIN_COMORDSS): Ditto.
+ (IX86_BUILTIN_COMUNORDSS): Ditto.
+ (IX86_BUILTIN_COMFALSESS): Ditto.
+ (IX86_BUILTIN_COMTRUESS): Ditto.
+ (IX86_BUILTIN_COMEQSD): Ditto.
+ (IX86_BUILTIN_COMNESD): Ditto.
+ (IX86_BUILTIN_COMLTSD): Ditto.
+ (IX86_BUILTIN_COMLESD): Ditto.
+ (IX86_BUILTIN_COMGTSD): Ditto.
+ (IX86_BUILTIN_COMGESD): Ditto.
+ (IX86_BUILTIN_COMUEQSD): Ditto.
+ (IX86_BUILTIN_COMUNESD): Ditto.
+ (IX86_BUILTIN_COMULTSD): Ditto.
+ (IX86_BUILTIN_COMULESD): Ditto.
+ (IX86_BUILTIN_COMUGTSD): Ditto.
+ (IX86_BUILTIN_COMUGESD): Ditto.
+ (IX86_BUILTIN_COMORDSD): Ditto.
+ (IX86_BUILTIN_COMUNORDSD): Ditto.
+ (IX86_BUILTIN_COMFALSESD): Ditto.
+ (IX86_BUILTIN_COMTRUESD): Ditto.
+ (IX86_BUILTIN_COMEQPS): Ditto.
+ (IX86_BUILTIN_COMNEPS): Ditto.
+ (IX86_BUILTIN_COMLTPS): Ditto.
+ (IX86_BUILTIN_COMLEPS): Ditto.
+ (IX86_BUILTIN_COMGTPS): Ditto.
+ (IX86_BUILTIN_COMGEPS): Ditto.
+ (IX86_BUILTIN_COMUEQPS): Ditto.
+ (IX86_BUILTIN_COMUNEPS): Ditto.
+ (IX86_BUILTIN_COMULTPS): Ditto.
+ (IX86_BUILTIN_COMULEPS): Ditto.
+ (IX86_BUILTIN_COMUGTPS): Ditto.
+ (IX86_BUILTIN_COMUGEPS): Ditto.
+ (IX86_BUILTIN_COMORDPS): Ditto.
+ (IX86_BUILTIN_COMUNORDPS): Ditto.
+ (IX86_BUILTIN_COMFALSEPS): Ditto.
+ (IX86_BUILTIN_COMTRUEPS): Ditto.
+ (IX86_BUILTIN_COMEQPD): Ditto.
+ (IX86_BUILTIN_COMNEPD): Ditto.
+ (IX86_BUILTIN_COMLTPD): Ditto.
+ (IX86_BUILTIN_COMLEPD): Ditto.
+ (IX86_BUILTIN_COMGTPD): Ditto.
+ (IX86_BUILTIN_COMGEPD): Ditto.
+ (IX86_BUILTIN_COMUEQPD): Ditto.
+ (IX86_BUILTIN_COMUNEPD): Ditto.
+ (IX86_BUILTIN_COMULTPD): Ditto.
+ (IX86_BUILTIN_COMULEPD): Ditto.
+ (IX86_BUILTIN_COMUGTPD): Ditto.
+ (IX86_BUILTIN_COMUGEPD): Ditto.
+ (IX86_BUILTIN_COMORDPD): Ditto.
+ (IX86_BUILTIN_COMUNORDPD): Ditto.
+ (IX86_BUILTIN_COMFALSEPD): Ditto.
+ (IX86_BUILTIN_COMTRUEPD): Ditto.
+ (IX86_BUILTIN_PCOMEQUB): Ditto.
+ (IX86_BUILTIN_PCOMNEUB): Ditto.
+ (IX86_BUILTIN_PCOMLTUB): Ditto.
+ (IX86_BUILTIN_PCOMLEUB): Ditto.
+ (IX86_BUILTIN_PCOMGTUB): Ditto.
+ (IX86_BUILTIN_PCOMGEUB): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUB): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUB): Ditto.
+ (IX86_BUILTIN_PCOMEQUW): Ditto.
+ (IX86_BUILTIN_PCOMNEUW): Ditto.
+ (IX86_BUILTIN_PCOMLTUW): Ditto.
+ (IX86_BUILTIN_PCOMLEUW): Ditto.
+ (IX86_BUILTIN_PCOMGTUW): Ditto.
+ (IX86_BUILTIN_PCOMGEUW): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUW): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUW): Ditto.
+ (IX86_BUILTIN_PCOMEQUD): Ditto.
+ (IX86_BUILTIN_PCOMNEUD): Ditto.
+ (IX86_BUILTIN_PCOMLTUD): Ditto.
+ (IX86_BUILTIN_PCOMLEUD): Ditto.
+ (IX86_BUILTIN_PCOMGTUD): Ditto.
+ (IX86_BUILTIN_PCOMGEUD): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUD): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUD): Ditto.
+ (IX86_BUILTIN_PCOMEQUQ): Ditto.
+ (IX86_BUILTIN_PCOMNEUQ): Ditto.
+ (IX86_BUILTIN_PCOMLTUQ): Ditto.
+ (IX86_BUILTIN_PCOMLEUQ): Ditto.
+ (IX86_BUILTIN_PCOMGTUQ): Ditto.
+ (IX86_BUILTIN_PCOMGEUQ): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUQ): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUQ): Ditto.
+ (IX86_BUILTIN_PCOMEQB): Ditto.
+ (IX86_BUILTIN_PCOMNEB): Ditto.
+ (IX86_BUILTIN_PCOMLTB): Ditto.
+ (IX86_BUILTIN_PCOMLEB): Ditto.
+ (IX86_BUILTIN_PCOMGTB): Ditto.
+ (IX86_BUILTIN_PCOMGEB): Ditto.
+ (IX86_BUILTIN_PCOMFALSEB): Ditto.
+ (IX86_BUILTIN_PCOMTRUEB): Ditto.
+ (IX86_BUILTIN_PCOMEQW): Ditto.
+ (IX86_BUILTIN_PCOMNEW): Ditto.
+ (IX86_BUILTIN_PCOMLTW): Ditto.
+ (IX86_BUILTIN_PCOMLEW): Ditto.
+ (IX86_BUILTIN_PCOMGTW): Ditto.
+ (IX86_BUILTIN_PCOMGEW): Ditto.
+ (IX86_BUILTIN_PCOMFALSEW): Ditto.
+ (IX86_BUILTIN_PCOMTRUEW): Ditto.
+ (IX86_BUILTIN_PCOMEQD): Ditto.
+ (IX86_BUILTIN_PCOMNED): Ditto.
+ (IX86_BUILTIN_PCOMLTD): Ditto.
+ (IX86_BUILTIN_PCOMLED): Ditto.
+ (IX86_BUILTIN_PCOMGTD): Ditto.
+ (IX86_BUILTIN_PCOMGED): Ditto.
+ (IX86_BUILTIN_PCOMFALSED): Ditto.
+ (IX86_BUILTIN_PCOMTRUED): Ditto.
+ (IX86_BUILTIN_PCOMEQQ): Ditto.
+ (IX86_BUILTIN_PCOMNEQ): Ditto.
+ (IX86_BUILTIN_PCOMLTQ): Ditto.
+ (IX86_BUILTIN_PCOMLEQ): Ditto.
+ (IX86_BUILTIN_PCOMGTQ): Ditto.
+ (IX86_BUILTIN_PCOMGEQ): Ditto.
+ (IX86_BUILTIN_PCOMFALSEQ): Ditto.
+ (IX86_BUILTIN_PCOMTRUEQ): Ditto.
+ (bdesc_ptest): Change OPTION_MASK_ISA_SSE4_1 to
+ OPTION_MASK_ISA_ROUND for instructions that are shared between
+ SSE4.1 and SSE5.
+ (bdesc_2arg): Ditto.
+ (bdesc_sse_3arg): Ditto.
+ (enum multi_arg_type): New enum for describing the various SSE5
+ intrinsic argument types.
+ (bdesc_multi_arg): New table for SSE5 intrinsics.
+ (ix86_init_mmx_sse_builtins): Add SSE5 intrinsic support.
+ (ix86_expand_multi_arg_builtin): New function for creating SSE5
+ intrinsics.
+ (ix86_expand_builtin): Add SSE5 intrinsic support.
+ (ix86_sse5_valid_op_p): New function to validate SSE5 3 and 4
+ operand instructions.
+ (ix86_expand_sse5_multiple_memory): New function to split the
+ second memory reference from SSE5 instructions.
+ (type_has_variadic_args_p): Delete in favor of stdarg_p.
+ (ix86_return_pops_args): Use stdarg_p to determine if the function
+ has variable arguments.
+ (ix86_setup_incoming_varargs): Ditto.
+ (x86_this_parameter): Ditto.
+
+ * config/i386/i386-protos.h (ix86_expand_sse5_unpack): Add
+ declaration.
+ (ix86_expand_sse5_pack): Ditto.
+ (ix86_sse5_valid_op_p): Ditto.
+ (ix86_expand_sse5_multiple_memory): Ditto.
+
+ * config/i386/i386.md (UNSPEC_SSE5_INTRINSIC): Add new UNSPEC
+ constant for SSE5 support.
+ (UNSPEC_SSE5_UNSIGNED_CMP): Ditto.
+ (UNSPEC_SSE5_TRUEFALSE): Ditto.
+ (UNSPEC_SSE5_PERMUTE): Ditto.
+ (UNSPEC_SSE5_ASHIFT): Ditto.
+ (UNSPEC_SSE5_LSHIFT): Ditto.
+ (UNSPEC_FRCZ): Ditto.
+ (UNSPEC_CVTPH2PS): Ditto.
+ (UNSPEC_CVTPS2PH): Ditto.
+ (PCOM_FALSE): Add new constant for true/false SSE5 comparisons.
+ (PCOM_TRUE): Ditto.
+ (COM_FALSE_S): Ditto.
+ (COM_FALSE_P): Ditto.
+ (COM_TRUE_S): Ditto.
+ (COM_TRUE_P): Ditto.
+ (type attribute): Add ssemuladd, sseiadd1, ssecvt1, sse4arg types.
+ (unit attribute): Add support for ssemuladd, ssecvt1, sseiadd1 sse4arg
+ types.
+ (memory attribute): Ditto.
+ (sse4_1_round<mode>2): Use TARGET_ROUND instead of TARGET_SSE4_1.
+ Use SSE4_1_ROUND_* constants instead of hard coded numbers.
+ (rint<mode>2): Use TARGET_ROUND instead of TARGET_SSE4_1.
+ (floor<mode>2): Ditto.
+ (ceil<mode>2): Ditto.
+ (btrunc<mode>2): Ditto.
+ (nearbyintdf2): Ditto.
+ (nearbyintsf2): Ditto.
+ (sse_setccsf): Disable if SSE5.
+ (sse_setccdf): Ditto.
+ (sse5_setcc<mode>): New support for SSE5 conditional move.
+ (sse5_pcmov_<mode>): Ditto.
+
+ * config/i386/sse.md (SSEMODE1248): New mode iterator for SSE5.
+ (SSEMODEF4): Ditto.
+ (SSEMODEF2P): Ditto.
+ (ssemodesuffixf4): New mode attribute for SSE5.
+ (ssemodesuffixf2s): Ditto.
+ (ssemodesuffixf2c): Ditto.
+ (sserotatemax): Ditto.
+ (ssescalarmode): Ditto.
+ (sse_maskcmpv4sf3): Disable if SSE5.
+ (sse_maskcmpv2df3): Ditto.
+ (sse_vmmaskcmpv4sf3): Ditto.
+ (sse5_fmadd<mode>4): Add SSE5 floating point multiply/add
+ instructions.
+ (sse5_vmfmadd<mode>4): Ditto.
+ (sse5_fmsub<mode>4): Ditto.
+ (sse5_vmfmsub<mode>4): Ditto.
+ (sse5_fnmadd<mode>4): Ditto.
+ (sse5_vmfnmadd<mode>4): Ditto.
+ (sse5_fnmsub<mode>4): Ditto.
+ (sse5_vmfnmsub<mode>4): Ditto.
+ (sse5i_fmadd<mode>4): Ditto.
+ (sse5i_fmsub<mode>4): Ditto.
+ (sse5i_fnmadd<mode>4): Ditto.
+ (sse5i_fnmsub<mode>4): Ditto.
+ (sse5i_vmfmadd<mode>4): Ditto.
+ (sse5i_vmfmsub<mode>4): Ditto.
+ (sse5i_vmfnmadd<mode>4): Ditto.
+ (sse5i_vmfnmsub<mode>4): Ditto.
+ (mulv16qi3): Add SSE5 support.
+ (mulv4si3): Ditto.
+ (sse5_mulv4si3): New insn for 32-bit multiply support on SSE5.
+ (sse2_mulv4si3): Disable if SSE5.
+ (sse4_1_roundpd): Use TARGET_ROUND instead of TARGET_SSE4_1.
+ (sse4_1_roundps): Ditto.
+ (sse4_1_roundsd): Ditto.
+ (sse4_1_roundss): Ditto.
+ (sse_maskcmpv4sf3): Disable if SSE5 so the SSE5 instruction will
+ be generated.
+ (sse_maskcmpsf3): Ditto.
+ (sse_vmmaskcmpv4sf3): Ditto.
+ (sse2_maskcmpv2df3): Ditto.
+ (sse2_maskcmpdf3): Ditto.
+ (sse2_vmmaskcmpv2df3): Ditto.
+ (sse2_eq<mode>3): Ditto.
+ (sse2_gt<mode>3): Ditto.
+ (sse5_pcmov_<mode>): Add SSE5 support.
+ (vec_unpacku_hi_v16qi): Ditto.
+ (vec_unpacks_hi_v16qi): Ditto.
+ (vec_unpacku_lo_v16qi): Ditto.
+ (vec_unpacks_lo_v16qi): Ditto.
+ (vec_unpacku_hi_v8hi): Ditto.
+ (vec_unpacks_hi_v8hi): Ditto.
+ (vec_unpacku_lo_v8hi): Ditto.
+ (vec_unpacks_lo_v8hi): Ditto.
+ (vec_unpacku_hi_v4si): Ditto.
+ (vec_unpacks_hi_v4si): Ditto.
+ (vec_unpacku_lo_v4si): Ditto.
+ (vec_unpacks_lo_v4si): Ditto.
+ (sse5_pmacsww): New SSE5 intrinsic insn.
+ (sse5_pmacssww): Ditto.
+ (sse5_pmacsdd): Ditto.
+ (sse5_pmacssdd): Ditto.
+ (sse5_pmacssdql): Ditto.
+ (sse5_pmacssdqh): Ditto.
+ (sse5_pmacsdqh): Ditto.
+ (sse5_pmacsswd): Ditto.
+ (sse5_pmacswd): Ditto.
+ (sse5_pmadcsswd): Ditto.
+ (sse5_pmadcswd): Ditto.
+ (sse5_pcmov_<move>): Conditional move support on SSE5.
+ (sse5_phaddbw): New SSE5 intrinsic insn.
+ (sse5_phaddbd): Ditto.
+ (sse5_phaddbq): Ditto.
+ (sse5_phaddwd): Ditto.
+ (sse5_phaddwq): Ditto.
+ (sse5_phadddq): Ditto.
+ (sse5_phaddubw): Ditto.
+ (sse5_phaddubd): Ditto.
+ (sse5_phaddubq): Ditto.
+ (sse5_phadduwd): Ditto.
+ (sse5_phadduwq): Ditto.
+ (sse5_phaddudq): Ditto.
+ (sse5_phsubbw): Ditto.
+ (sse5_phsubwd): Ditto.
+ (sse5_phsubdq): Ditto.
+ (sse5_pperm): Ditto.
+ (sse5_pperm_sign_v16qi_v8hi): New insns for pack/unpack with SSE5.
+ (sse5_pperm_zero_v16qi_v8hi): Ditto.
+ (sse5_pperm_sign_v8hi_v4si): Ditto.
+ (sse5_pperm_zero_v8hi_v4si): Ditto.
+ (sse5_pperm_sign_v4si_v2di): Ditto.
+ (sse5_pperm_sign_v4si_v2di): Ditto.
+ (sse5_pperm_pack_v2di_v4si): Ditto.
+ (sse5_pperm_pack_v4si_v8hi): Ditto.
+ (sse5_pperm_pack_v8hi_v16qi): Ditto.
+ (sse5_perm<mode>): New SSE5 intrinsic insn.
+ (rotl<mode>3): Ditto.
+ (sse5_rotl<mode>3): Ditto.
+ (sse5_ashl<mode>3): Ditto.
+ (sse5_lshl<mode>3): Ditto.
+ (sse5_frcz<mode>2): Ditto.
+ (sse5s_frcz<mode>2): Ditto.
+ (sse5_cvtph2ps): Ditto.
+ (sse5_cvtps2ph): Ditto.
+ (sse5_vmmaskcmp<mode>3): Ditto.
+ (sse5_com_tf<mode>3): Ditto.
+ (sse5_maskcmp<mode>3): Ditto.
+ (sse5_maskcmp_uns<mode>3): Ditto.
+ (sse5_maskcmp_uns2<mode>3): Ditto.
+ (sse5_pcom_tf<mode>3): Ditto.
+
+ * config/i386/predicates.md (const_0_to_31_operand): New predicate
+ to match 0..31.
+ (sse5_comparison_float_operator): New predicate to match the
+ comparison operators supported by the SSE5 com instruction.
+ (ix86_comparison_int_operator): New predicate to match just the
+ signed int comparisons.
+ (ix86_comparison_uns_operator): New predicate to match just the
+ unsigned int comparisons.
+
+ * doc/invoke.texi (-msse5): Add documentation.
+ (-mfused-madd): Ditto.
+
+ * doc/extend.texi (x86 intrinsics): Document new SSE5 intrinsics.
+
+ * config.gcc (i[34567]86-*-*): Include bmmintrin.h and
+ mmintrin-common.h.
+ (x86_64-*-*): Ditto.
+
+ * config/i386/cpuid.h (bit_SSE5): Define SSE5 bit.
+
+ * config/i386/bmmintrin.h: New file, provide common x86 compiler
+ intrinisics for SSE5.
+
+ * config/i386/smmintrin.h: Move instructions shared with SSE5 to
+ mmintrin-common.h.
+
+ * config/i386/mmintrin-common.h: New file, to contain common
+ instructions between SSE4.1 and SSE5.
+
+ * config/i386/netware.c (gen_stdcall_or_fastcall_decoration): Use
+ FOREACH_FUNCTION_ARGS to iterate over the argument list.
+ (gen_regparm_prefix): Ditto.
+
+ * config/i386/winnt.c (gen_stdcall_or_fastcall_suffix): Use
+ FOREACH_FUNCTION_ARGS to iterate over the argument list. Use
+ prototype_p to determine if a function is prototyped.
+
+2007-09-12 Janis Johnson <janis187@us.ibm.com>
+
+ * config/dfp-bit.c (dfp_conversion_exception): New function.
+ (DFP_TO_DFP) Add new variants to use direct conversions in decNumber.
+ (DFP_TO_INT): Ditto.
+ (INT_TO_DFP): Ditto.
+ * config/dfp-bit.h (DEC_FLOAT_FROM_INT, DEC_FLOAT_TO_INT): New.
+
+2007-09-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/32338
+ * config/ia64/ia64.c (ia64_expand_epilogue): Emit blockage
+ before sp restoration even when total_size is 0, but
+ frame_pointer_needed.
+
+2007-09-12 Bob Wilson <bob.wilson@acm.org>
+
+ * config/xtensa/xtensa.c (machine_function): Add vararg_a7_copy.
+ (xtensa_copy_incoming_a7): Use start_sequence instead of
+ push_to_sequence. Stash insns in vararg_a7_copy for builtin_saveregs.
+ (xtensa_builtin_saveregs): Place code from vararg_a7_copy at the start
+ of the saveregs sequence.
+
+2007-09-12 Richard Sandiford <richard@codesourcery.com>
+
+ * c-tree.h (grokfield): Add a "tree *" argument.
+ * c-decl.c (grokdeclarator): Take a pointer to the decl's attributes.
+ Chain nested decl attributes to it. Don't call decl_attributes here.
+ (groktypename): Pass grokdeclarator a pointer to the attribute list.
+ (start_decl, grokparm, push_parm_decl, start_function): Likewise.
+ (grokfield): Take a pointer to the decl's attributes and pass
+ it to grokdeclarator.
+ * c-parser.c (c_parser_struct_declaration): Update the calls to
+ grokfield. Call decl_attributes for anonymous struct and union
+ fields.
+
+2007-09-12 Jan Hubicka <jh@suse.cz>
+
+ * c-objc-common.h (LANG_HOOKS_CALLGRAPH_EXPAND_FUNCTION): Kill.
+
+2007-09-12 Ira Rosen <irar@il.ibm.com>
+
+ PR tree-optimization/32377
+ * tree-vect-analyze.c (vect_analyze_data_ref_dependence): Distinguish
+ between positive and negative dependence distance using DDR_REVERSED_P.
+
+2007-09-12 Dorit Nuzman <dorit@il.ibm.com>
+
+ PR tree-optimization/33373
+ * tree-vect-analyze (vect_determine_vectorization_factor): Call
+ TREE_INT_CST_LOW when comparing TYPE_SIZE_UNIT.
+
+2007-09-12 Jan Hubicka <jh@suse.cz>
+
+ PR target/33393
+ * i386.md (floatsisf2_mixed_memory, floatsisf2_sse_memory): Disable for
+ !SSE_MATH
+
+2007-09-12 Christian Bruel <christian.bruel@st.com>
+
+ * sh.h (SH_DBX_REGISTER_NUMBER): Added fpscr, fixed sr/gbr regs.
+ * linux-unwind.h (SH_DWARF_FRAME_GBR): fixed.
+
+2007-09-12 Ira Rosen <irar@il.ibm.com>
+
+ * tree-vect-transform.c (vect_get_slp_defs): Don't build a vector
+ for oprnd1 if not required.
+ (vectorizable_operation): Use scalar operand in SLP in case of
+ shift with scalar argument.
+
+2007-09-12 Ira Rosen <irar@il.ibm.com>
+
+ * params.def (PARAM_MIN_VECT_LOOP_BOUND): Change default and minimum
+ to 1.
+
+2007-09-11 James E. Wilson <wilson@specifix.com>
+
+ * defaults.h (DWARF2_UNWIND_INFO): Don't define if
+ TARGET_UNWIND_INFO is defined.
+ * config/ia64/ia64.h (INCOMING_RETURN_ADDR_RTX): Delete undef
+ after definition.
+
+2007-09-12 Kaz Kojima <kkojima@gcc.gnu.org>
+
+ * config/sh/sh.c (calc_live_regs): Use
+ current_function_saves_all_registers instead of
+ current_function_has_nonlocal_label.
+ (sh_allocate_initial_value): Likewise.
+ (sh_get_pr_initial_val): Likewise.
+ * config/sh/sh.h (SHMEDIA_REGS_STACK_ADJUST): Likewise.
+ * config/sh/sh.md (load_ra): Likewise.
+
+2007-09-12 Hans-Peter Nilsson <hp@axis.com>
+
+ * config/cris/t-linux (LIMITS_H_TEST): Only define if not inhibit_libc.
+
+ PR target/33360
+ * config/cris/cris.c (cris_expand_pic_call_address): Fix typo in
+ GET_CODE (x) == CONST_INT to CONST_INT_P (x) transformation.
+
+2007-09-12 Sa Liu <saliu@de.ibm.com>
+
+ * config/spu/spu.c (spu_emit_branch_or_set): Handle NaN values as
+ operands to DFmode GE or LE compares.
+
+2007-09-12 Bernd Schmidt <bernd.schmidt@analog.com>
+
+ * config/bfin/bfin.h (enum reg_class, REG_CLASS_CONTENTS,
+ REG_CLASS_NAMES): Add P0REGS.
+ (REGNO_REG_CLASS): Return it where appropriate.
+ (REG_CLASS_FROM_CONSTRAINT): Add 'qA'.
+ (CLASS_LIKELY_SPILLED_P): P0REGS is likely_spilled.
+ * doc/md.texi (Blackfin family): Document 'q' constraints.
+
+2007-09-11 Steve Kenton <skenton@ou.edu>
+
+ * pa/linux-unwind.h: Guard with inhibit_libc.
+ * pa/hpux-unwind.h: Likewise.
+
+2007-09-11 David Daney <ddaney@avtrex.com>
+
+ * doc/invoke.texi: Document new MIPS -mllsc and -mno-llsc options.
+ * doc/install.texi: Document new --with-llsc and --without-llsc
+ options.
+ * config.gcc: Handle --with-llsc and --without-llsc configure options.
+ * config/mips/mips.md (sync, memory_barrier): Wrap sync instrunction
+ in %| and %- operand codes. Depend on GENERATE_SYNC instead of
+ ISA_HAS_SYNC.
+ (sync_compare_and_swap<mode>, sync_add<mode>, sync_sub<mode>,
+ sync_old_add<mode>, sync_old_sub<mode>, sync_new_add<mode>,
+ sync_new_sub<mode>, sync_<optab><mode>, sync_old_<optab><mode>,
+ sync_new_<optab><mode>, sync_nand<mode>, sync_old_nand<mode>,
+ sync_new_nand<mode>, sync_lock_test_and_set<mode>): Depend on
+ GENERATE_LL_SC instead of ISA_HAS_LL_SC.
+ * config/mips/mips.opt (mllsc): New option.
+ * config/mips/mips.c (mips_llsc): Define variable.
+ (mips_handle_option): Handle mllsc option.
+ (override_options): Set mips_print_operand_punct for '|' and '-'.
+ (print_operand): Add new %| and %- operand codes.
+ * config/mips/mips.h (mips_llsc_setting): New enum type.
+ (mips_llsc): Declare.
+ (OPTION_DEFAULT_SPECS): Add llsc handling.
+ (GENERATE_SYNC): New macro.
+ (GENERATE_LL_SC): New macro.
+ (MIPS_COMPARE_AND_SWAP, MIPS_SYNC_OP, MIPS_SYNC_OLD_OP,
+ MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND,
+ MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE): Wrap instructions
+ in %| and %- operand codes.
+
+2007-09-11 Eric Botcazou <ebotcazou@adacore.com>
+
+ * tree-ssa-structalias.c (push_fields_onto_fieldstack): Deal with
+ TYPE_NONALIASED_COMPONENT like with DECL_NONADDRESSABLE_P.
+
+2007-09-11 Jason Merrill <jason@redhat.com>
+
+ PR middle-end/27945
+ * stor-layout.c (layout_decl): Do pack variable size fields.
+
+2007-09-11 Maxim Kuvyrkov <maxim@codesourcery.com>
+
+ * config/m68k/predicates.md (movsi_const0_operand,
+ non_symbolic_call_operand): New predicates.
+
+ * config/m68k/constraints.md: (Cs, Ci, C0, Cj, CQ, CW, CZ, CS, Ap, Ac):
+ New constraints.
+ * doc/md.texi (Constraints for Particular Machines: Motorola 680x0):
+ Document constraints N, O, P, R, S, T, Q, U, W, Cs, Ci, C0, Cj, CQ,
+ CW, CZ, CS, Ap and Ac.
+
+ * config/m68k/m68k.md (UNSPEC_IB): New constant.
+ (constraints.md): New include.
+ (cpu, type, type1, opx, opy, opx_type, opy_type, size, opx_access,
+ opx_mem, opy_mem, op_mem, guess, split): New attributes.
+ (movdf_internal): Name pattern. Fix to use alternatives. Add split.
+ Specify attributes.
+ (pushdi): Add split.
+ (tstsi_internal): Name pattern. Fix to use alternatives. Specify
+ attributes. Split tstsi_internal_68020_cf from it.
+ (tstsi_internal_68020_cf): New pattern.
+ (tsthi_internal, tstqi_internal): Name pattern. Specify attributes.
+ (tst<mode>_cf): Specify attributea.
+ (cmpsi_cf): Name pattern. Specify attributes.
+ (cmp<mode>_68881, cmp<mode>_cf): Specify type attribute.
+ (pushexthisi_const): Fix to use alternatives. Specify
+ attributes.
+ (movsi_const0): Split movsi_const0_68000_10 and movsi_const0_68040_60
+ from it. Fix to use alternatives. Specify attributes.
+ (movsi_const0_68040_10, movsi_const0_68040_60): New patterns.
+ (movsi_cf, movstrictqi_cf): Fix to use alternatives. Specify
+ attributes.
+ (movsf_cf_soft): Specify attributes.
+ (movdf_cf_soft): Add split.
+ (pushasi, zero_extendhisi2_cf, zero_extendqisi2_cfv4,
+ cfv4_extendhisi2, 68k_extendhisi2, extendqihi2, cfv4_extendqisi2,
+ 68k_extendqisi2, truncdfsf2_cf): Specify attributes.
+ (truncdfsf2_68881): Name pattern. Specify attributes.
+ (floatsi<mode>2_cf, floathi<mode>2_68881, floathi<mode>2_cf,
+ floatqi<mode>2_68881, floatqi<mode>2_cf, ftrunc<mode>2_cf,
+ fix<mode>qi2_cf, fix<mode>hi2_cf, fix<mode>si2_cf, adddi_dishl32):
+ Specify attributes.
+ (addsi3_5200): Fix to use alternatives. Specify attributes.
+ Add splits.
+ (add<mode>3_cf, subdi_dishl32): Specify attributes.
+ (subsi3): Add alternative for subq.l. Specify attributes.
+ (sub<mode>3_cf, mulhi3, mulhisi3): Specify attributes.
+ (mulhisisi3_s, mulsi3_68020, mulsi3_cf): Name pattern. Specify
+ attributes.
+ (umulhisi3): Specify attributes.
+ (mulhisisi3_z): Name pattern. Specify attributes.
+ (fmul<mode>3_cf, div<mode>3_cf, negsi2_internal, negsi2_5200,
+ sqrt<mode>2_68881, clzsi2, one_cmplsi2_5200, subreghi1ashrdi_const32,
+ subregsi1ashrdi_const32, ashrsi3, subreg1lshrdi_const32, lshrsi3,
+ bsetmemqi): Specify attributes.
+ (bsetmemqi_ext): Name pattern. Specify attributes.
+ (bclrmemqi): Specify attributes.
+ (bclrmemqi_ext, scc, sls): Name pattern. Specify attributes.
+ (beq, bne, bgt, bgtu, blt, bltu, bge, bgeu, ble, bleu): Specify
+ attributes.
+ (beq2, bne2, bgt2, bgtu2, blt2, bltu2, bge2, bgeu2, ble2, bleu2): Name
+ pattern. Specify attributes.
+ (jump): Specify attributes.
+ (tablejump_internal): Name pattern. Specify attributes.
+ (call_value): Split into non_symbolic_call_value,
+ symbolic_call_value_jsr, symbolic_call_value_bsr. Fix to use
+ alternatives. Specify attributes.
+ (non_symbolic_call_value, symbolic_call_value_jsr,
+ symbolic_call_value_bsr): New patterns.
+ (nop, return, unlink, indirect_jump): Specify attributes.
+ (trap): Fix condition. Specify attributes.
+ (ib): New pattern.
+
+ * config/m68k/m68k.c (m68k_symbolic_call_var): New variable.
+ (override_options): Initialize it. Initialize m68k_sched_cpu.
+ (CONST_METHOD): Rename to M68K_CONST_METHOD, move to m68k.h.
+ (const_method): Make global, rename to m68k_const_method.
+ (const_int_cost, output_move_const_into_data_reg): Update.
+ (output_move_double): Parametrize to emit rtl code, rename to
+ handle_move_double.
+ (output_reg_adjust, emit_reg_adjust, output_compadr, output_movsi,
+ emit_movsi): New static functions.
+ (output_move_double): New function with semantics of old
+ output_move_double.
+ (m68k_emit_move_double): New function.
+ (m68k_sched_cpu): New variable.
+ (attr_op_type): New enum.
+ (sched_guess_p): New variable.
+ (sched_address_type, sched_operand_type, sched_attr_op_type):
+ New static functions.
+ (m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
+ m68k_sched_attr_size, m68k_sched_attr_op_mem): New functions.
+ (sched_branch_type): New static variable.
+ (m68k_sched_branch_type): New function.
+ * config/m68k/m68k.h (M68K_SYMBOLIC_CALL): New enum.
+ (m68k_symbolic_call_var): Declare.
+ (M68K_CONST_METHOD): Rename from CONST_METHOD. Move here from m68k.c.
+ (m68k_const_method, m68k_emit_move_double, m68k_sched_cpu,
+ m68k_sched_attr_opx_type, m68k_sched_attr_opy_type,
+ m68k_sched_attr_size, m68k_sched_attr_op_mem, m68k_sched_branch_type):
+ Declare.
+
+2007-09-11 Jakub Jelinek <jakub@redhat.com>
+
+ * builtins.def (BUILT_IN_VA_ARG_PACK_LEN): New builtin.
+ * builtins.c (expand_builtin) <case BUILT_IN_VA_ARG_PACK_LEN>: Issue
+ error if __builtin_va_arg_pack_len () wasn't optimized out during
+ inlining.
+ * tree-inline.c (copy_bb): Replace __builtin_va_arg_pack_len ()
+ with the number of inline's anonymous arguments.
+ * doc/extend.texi: Document __builtin_va_arg_pack_len ().
+
+2007-09-11 Zdenek Dvorak <ook@ucw.cz>
+
+ * fold-const.c (extract_muldiv_1): Do not simplify
+ var * c * c to var.
+
+2007-09-11 Jan Hubicka <jh@suse.cz>
+
+ * i386.h (ix86_tune_indices): Add X86_TUNE_INTER_UNIT_CONVERSIONS.
+ (TARGET_INTER_UNIT_CONVERSIONS): New.
+ * i386.md (floatsi expanders): Remove redundant check for SImode
+ source; offload to memory when asked for.
+ (floatsisf2_mixed, floatsisf2_sse, floatsidf2_mixed, floatsidf2_sse
+ floatdisf2_mixed, floatsisf2_sse, floatsidf2_mixed, floatsidf2_sse):
+ Update conditions;
+ (floatsisf2_mixed_memory, floatsisf2_sse_memory,
+ floatsidf2_mixed_memory, floatsidf2_sse_memory
+ floatdisf2_mixed_memory, floatsisf2_sse_memory,
+ floatsidf2_mixed_memory, floatsidf2_sse_memory): New.
+
+2007-09-11 Jan Hubicka <jh@suse.cz>
+
+ * toplev.c (process_options): all frontends now do unit-at-a-time.
+ * cgraphunit.c: update comments.
+ (cgraph_expand_function): call passmanager dirrectly; emit thunks.
+ * c-decl.c (finish_function): use cgraph_add_new_function.
+ * function.c (expand_function_end): We are always unit-at-a-time.
+
+2007-09-11 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.c (mips_set_mips16_mode): Use separate anchor
+ settings for MIPS16.
+ (mips_use_anchors_for_symbol_p): Use default_use_anchors_for_symbol_p.
+
+2007-09-11 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.c (mips_symbol_insns_1): Allow LEAs of
+ SYMBOL_FORCE_TO_MEM constants.
+ (mips_rtx_costs): Give a cost of 1 to force_to_mem_operands.
+ (mips16_rewrite_pool_refs_info): New structure.
+ (mips16_rewrite_pool_constant): New function, split out from...
+ (mips16_rewrite_pool_refs): ...here. Take a pointer to a
+ mips16_rewrite_pool_refs_info structure rather than a pointer
+ to a constant pool. Force force_to_mem_operands into memory.
+ (mips16_lay_out_constants): Update call to mips16_rewrite_pool_refs.
+ * config/mips/predicates.md (force_to_mem_operand): New predicate.
+ * config/mips/constraints.md (kf): New constraint.
+ * config/mips/mips.md (*movdi_64bit_mips16): Add a d <- kf alternative.
+ (*movsi_mips16): Likewise.
+
+2007-09-11 Richard Sandiford <richard@codesourcery.com>
+ Nigel Stephens <nigel@mips.com>
+ David Ung <davidu@mips.com>
+
+ * config/mips/mips.h (CONSTANT_POOL_COST): Move to...
+ * config/mips/mips.c: ...here and set to 4 for TARGET_MIPS16.
+ (mips16_constant_cost, mips_immediate_operand_p, mips_binary_cost)
+ (mips_fp_mult_cost, mips_fp_div_cost, mips_sign_extend_cost)
+ (mips_zero_extend_cost): New functions.
+ (mips_rtx_costs): Treat COMPARE constants as having zero cost.
+ Use the new functions. Tweak many cost estimates, both here
+ and in the new subroutines. Return false when the cost of the
+ operands has not been calculated. Check for *clear_upper32.
+ Check for floating-point multiply-add, reciprocal and rsqrt
+ patterns. Handle comparison and rotation codes.
+
+2007-09-11 Danny Smith <dannysmith@users.sourceforge.net>
+
+ * config/i386/cygming.h (TARGET_STRIP_NAME_ENCODING): Don't
+ override default.
+ * config/i386/i386.c (get_dllimport_decl): Don't strip
+ FASTCALL_PREFIX.
+
+2007-09-10 Janis Johnson <janis187@us.ibm.com>
+
+ PR c/30013
+ * config/dfp-bit.c: Don't skip TFmode conversions; move strto*
+ declarations to top.
+ (DFP_TO_BFP): Use for either XFmode or TFmode.
+ (BFP_TO_DFP): Use for either XFmode or TFmode; always use cast
+ of BFP_VIA_TYPE.
+ * config/dfp-bit.h: Include float.h.
+ (LONG_DOUBLE_HAS_XF_MODE, LONG_DOUBLE_HAS_TF_MODE): Define if long
+ double is one of these modes, rather than using LIBGCC_HAS_*F_MODE
+ which doesn't mean the same thing.
+ (BFP_KIND): Use 4 to mean TFmode.
+ (BFP_FMT): Specify the number of decimal digits based on the
+ number of mantissa digits.
+ (BFP_VIA_TYPE): Binary float type to use as cast for sprintf.
+ (BFP_TO_DFP, DFP_TO_BFP): Define names for TFmode variants.
+ (STR_TO_BFP): Use strtold for XFmode or TFmode.
+ (TFtype): Define if TFmode is supported.
+ * doc/libgcc.texi (Decimal float library routines): Document
+ TF conversion functions.
+
+2007-09-10 Chao-ying Fu <fu@mips.com>
+
+ * config/mips/mips.c (mips_scalar_mode_supported_p): Declare.
+ (TARGET_SCALAR_MODE_SUPPORTED_P): Define.
+ (mips_emit_compare): Process fixed-point modes.
+ (mips_pad_arg_upward): Support fixed-point types.
+ (override_options): Allow fixed-point modes in accumulators.
+ (mips_pass_by_reference): Pass DQ, UDQ, DA, and UDA modes in registers.
+ (mips_vector_mode_supported_p): Support V2HQmode, V2UHQmode, V2HAmode,
+ V2UHAmode, V4QQmode, and V4UQQmode when TARGET_DSP.
+ (mips_scalar_mode_supported_p): New function to accept fixed-point
+ modes if the width is not greater than two BITS_PER_WORD.
+ * config/mips/mips.h (SHORT_FRACT_TYPE_SIZE, FRACT_TYPE_SIZE,
+ LONG_FRACT_TYPE_SIZE, LONG_LONG_FRACT_TYPE_SIZE,
+ SHORT_ACCUM_TYPE_SIZE, ACCUM_TYPE_SIZE, LONG_ACCUM_TYPE_SIZE,
+ LONG_LONG_ACCUM_TYPE_SIZE): Define.
+ * config/mips/mips.md ("d"): Update mode attribute for fixed-point
+ modes.
+ ("IMODE"): New mode attribute.
+ (mips-fixed.md): Include.
+ * config/mips/mips-modes.def: Create VECTOR_MODES for FRACT, UFRACT,
+ ACCUM, UACCUM.
+ * config/mips/mips-fixed.md: New file.
+
+2007-09-11 Ben Elliston <bje@au.ibm.com>
+
+ * config/spu/spu.md: Formatting fixes.
+
+2007-09-10 Janis Johnson <janis187@us.ibm.com>
+
+ * config/dfp-bit.c (dfp_unary_func): Delete.
+ (dfp_unary_op): Delete.
+ (dfp_binary_op): Use decFloat functions instead of decNumber
+ functions for binary operations.
+ (d32_binary_op): Convert 32-bit operands to 64 bits for evaluation.
+ (dnn_binary_op): Call dfp_binary_op with decFloat rather than
+ DFP_C_TYPE.
+ (dfp_compare_op): Use decFloat functions insteadof decNumber
+ functions for comparisons.
+ (d32_compare_op): Convert 32-bit operands to 64 bits for evaluation.
+ (dnn_binary_op): Call dfp_compare_op with decFloat rather than
+ DFP_C_TYPE.
+ (DFP_ADD, DFP_SUB, DFP_MULTIPLE, DFP_DIVIDE): Use macros for
+ call to dxx_binary_op and decFloat function.
+ (DFP_EQ, DFP_NE, DFP_LT, DFP_GT, DFP_LE, DFP_GE): Use macros for
+ calls to dxx_binary_op and decFloat function.
+ * config/dfp-bit.h: Include decFloat header files.
+ (decFloat, DFP_BINARY_OP, DFP_COMPARE_OP, DEC_FLOAT_ADD,
+ DEC_FLOAT_SUBTRACT, DEC_FLOAT_MULTIPLY, DEC_FLOAT_DIVIDE,
+ DEC_FLOAT_COMPARE, DEC_FLOAT_IS_ZERO, DEC_FLOAT_IS_NAN,
+ DEC_FLOAT_IS_SIGNED: Define for each of 3 operand widths.
+
+2007-09-10 Harsha Jagasia <harsha.jagasia@amd.com>
+ Jan Sjodin <jan.sjodin@amd.com>
+
+ * tree-vect-analyze.c (vect_analyze_operations): Change
+ comparison of loop iterations with threshold to less than
+ or equal to instead of less than. Reduce
+ min_scalar_loop_bound by one.
+ * tree-vect-transform.c (vect_estimate_min_profitable_iters):
+ Change prologue and epilogue iterations estimate to vf/2,
+ when unknown at compile-time. Change versioning guard
+ cost to taken_branch_cost. If peeling for alignment is
+ unknown at compile-time, change peel guard costs to one
+ taken branch and one not-taken branch per peeled loop.
+ If peeling for alignment is known but number of scalar loop
+ iterations is unknown at compile-time, change peel guard
+ costs to one taken branch per peeled loop. Change the cost
+ model equation to consider vector iterations as the loop
+ iterations less the prologue and epilogue iterations.
+ Change outside vector cost check to less than or equal to
+ zero instead of equal to zero.
+ (vect_do_peeling_for_loop_bound): Reduce
+ min_scalar_loop_bound by one.
+ * tree-vectorizer.h: Add TARG_COND_TAKEN_BRANCH_COST and
+ TARG_COND_NOT_TAKEN_BRANCH_COST.
+ * config/i386/i386.h (processor_costs): Add
+ scalar_stmt_cost, scalar_load_cost, scalar_store_cost,
+ vec_stmt_cost, vec_to_scalar_cost, scalar_to_vec_cost,
+ vec_align_load_cost, vect_unalign_load_cost,
+ vec_store_cost, cond_taken_branch_cost,
+ cond_not_taken_branch_cost.
+ Define macros for x86 costs.
+ * config/i386/i386.c:
+ (size_cost): Set scalar_stmt_cost, scalar_load_cost,
+ scalar_store_cost, vec_stmt_cost, vec_to_scalar_cost,
+ scalar_to_vec_cost, vec_align_load_cost,
+ vect_unalign_load_cost, vec_store_cost,
+ cond_taken_branch_cost, cond_not_taken_branch_cost to one.
+ (i386_cost, i486_cost, pentium_cost, pentiumpro_cost,
+ geode_cost, k6_cost, athlon_cost, pentium4_cost, nocona_cost,
+ core2_cost, generic64_cost, generic32_cost): Set to default
+ untuned costs.
+ (k8_cost, amdfam10_cost): Costs for vectorization tuned.
+ (x86_builtin_vectorization_cost): New.
+
+2007-09-10 Janis Johnson <janis187@us.ibm.com>
+ Ben Elliston <bje@au.ibm.com>
+
+ * dfp.c: Include decimal128Local.h;
+ (dfp_byte_swap): Remove.
+ (encode_decimal32, decode_decimal32): Don't handle endianness.
+ (encode_decimal64, decode_decimal64): Ditto.
+ (encode_decimal128, decode_decimal128): Ditto.
+ * config/dfp-bit.c (host_to_ieee32, ieee_to_host_32): Ditto.
+ (__swap64): Remove.
+ (host_to_ieee_64, ieee_to_host_64): Don't handle endianness.
+ (__swap128): Remove
+ (host_to_ieee_128, ieee_to_host_128): Don't handle endianness.
+ * Makefile.in (DECNUM_H): Add decimal128Local.h.
+
+2007-09-10 David Daney <ddaney@avtrex.com>
+
+ * config/mips/mips.md (UNSPEC_MEMORY_BARRIER): New entry in
+ define_constants.
+ (memory_barrier): Rewrote as an insn that clobbers memory.
+
+2007-09-10 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.c (mips_global_pointer): Check
+ call_really_used_regs instead of call_used_regs.
+ (mips_save_reg_p): Likewise. Save all call-saved registers
+ if current_function_saves_all_registers. Fix indentation.
+ No longer treat $18 as a special case.
+ (compute_frame_size): Guard FPR loop with TARGET_HARD_FLOAT.
+
+2007-09-10 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.h (MIPS_ARCH_FLOAT_SPEC): New macro.
+ * config/mips/mips.c (mips_cpu_info_table): Mention it in the
+ the introductory comment.
+ (MIPS_MARCH_CONTROLS_SOFT_FLOAT): Delete.
+ (override_options): Don't test for it.
+ * config/mips/sde.h (MIPS_MARCH_CONTROLS_SOFT_FLOAT): Delete.
+ (DRIVER_SELF_SPECS): Add MIPS_ARCH_FLOAT_SPEC.
+ * config/mips/vr.h: As for config/mips/sde.h.
+
+2007-09-10 Trevor Smigiel <trevor_smigiel@playstation.sony.com>
+ Revital Eres <eres@il.ibm.com>
+
+ * target.h (struct gcc_target.sched): New field: sms_res_mii.
+ (struct ddg): Define.
+ * target-def.h (TARGET_SCHED_SMS_RES_MII): Define.
+ (TARGET_SCHED): Add TARGET_SCHED_SMS_RES_MII.
+ * config/spu/spu.c: Include ddg.h.
+ (TARGET_SCHED_SMS_RES_MII): Define.
+ (spu_sms_res_mii): New function to calculate mii.
+ * modulo-sched (res_MII): Use it.
+ * doc/tm.texi: Document TARGET_SCHED_SMS_RES_MII.
+
+2007-09-10 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * config/s390/s390.c (s390_dump_pool): Create copy of constant
+ pool entries since they might hold values that must not be shared.
+
+2007-09-10 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/33369
+ * gcc/config/i386/sse.md (ashr<mode>3): Change op2 mode to SImode.
+ Use 'N' operand constraint for op2.
+ (lshr<mode>3): Ditto.
+ (ashl<mode>3): Ditto.
+ (vec_shl_<mode>): Use const_0_to_255_mul_8_operand predicate for op2.
+ (vec_shr_<mode>): Ditto.
+ * gcc/config/i386/i386.c (ix86_expand_builtin) [IX86_BUILTIN_PSLL?128,
+ IX86_BUILTIN_PSRA*?128, IX86_BUILTIN_PSRL?128]: Convert op1 to SImode.
+
+2007-09-10 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * config/s390/s390.md ("fixuns_trunc<BFP:mode><GPR:mode>2"):
+ Change mode macro in the last real_2expN parameter to uppercase.
+
+2007-09-10 Michael Matz <matz@suse.de>
+
+ * tree-pass.h (pass_cselim): Declare new pass.
+ * passes.c (init_optimization_passes): Link in pass_cselim.
+ * tree-ssa-phiopt.c (tree_ssa_phiopt_worker): Renamed from
+ tree_ssa_phiopt; add do_store_elim parameter, handle it by calling
+ cond_store_replacement.
+ (condstoretemp): New static variable.
+ (cond_store_replacement): New function.
+ (tree_ssa_phiopt, tree_ssa_cs_elim): New wrappers around
+ tree_ssa_phiopt_worker.
+ (struct name_to_bb): New.
+ (get_non_trapping, name_to_bb_hash, name_to_bb_eq, add_or_mark_expr,
+ nt_init_block, nt_fini_block): New static functions.
+ (seen_ssa_names, nontrap_set): New static variables.
+ (gate_cselim, pass_cselim): Define new pass.
+ * common.opt (ftree-cselim): New flag.
+ * toplev.c (process_options): Set flag_tree_cselim if required.
+
+2007-09-10 Hans-Peter Nilsson <hp@axis.com>
+
+ * simplify-rtx.c (simplify_relational_operation_1): For recent
+ canonicalization, don't recurse if op1 equals both PLUS arguments.
+
+2007-09-09 David Daney <ddaney@avtrex.com>
+
+ * optabs.c (expand_sync_operation): Use plus insn if minus
+ CONST_INT_P(val).
+ (expand_sync_fetch_operation): Ditto.
+
+2007-09-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.md (*floatsisf2_mixed_vector): Use cvtdq2ps instead
+ of cvtpq2ps.
+ (*floatsisf2_sse_vector): Likewise.
+
+2007-09-09 Krister Walfridsson <cato@df.lth.se>
+
+ * config/netbsd.h (HANDLE_PRAGMA_PACK_PUSH_POP): Define to 1.
+
+2007-09-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.h (ix86_tune_indices): Rename
+ X86_USE_VECTOR_CONVERTS to X86_TUNE_USE_VECTOR_CONVERTS.
+ (TARGET_USE_VECTOR_CONVERTS): Updated.
+ * config/i386/i386.c: Likewise.
+
+2007-09-09 Sandra Loosemore <sandra@codesourcery.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * doc/invoke.texi (Overall Options): Add .sx file extension
+ as a synonym for .S.
+ * cppspec.c (known_suffixes): Likewise.
+ * gcc.c (default_compilers): Likewise.
+
+2007-09-09 Rask Ingemann Lambertsen <rask@sygehus.dk>
+
+ PR target/30315
+ * config/i386/i386.h (CANONICALIZE_COMPARISON): Delete.
+ * simplify-rtx.c (simplify_relational_operation_1): Add the
+ canonicalization from i386.h.
+ * doc/md.texi (Canonicalization of Instructions): Document it.
+
2007-09-09 Jan Hubicka <jh@suse.cz>
- Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
* i386.h (ix86_tune_indices): Add X86_USE_VECTOR_CONVERTS.
(TARGET_USE_VECTOR_CONVERTS): New.
vectorizable_assignment): Likewise.
(vect_model_simple_cost, vect_model_store_cost, vect_model_load_cost):
Declare (make extern).
- * tree-vectorizer.c (new_stmt_vec_info): Initiliaze the new field.
+ * tree-vectorizer.c (new_stmt_vec_info): Initialize the new field.
(new_loop_vec_info): Likewise.
(destroy_loop_vec_info): Free memory allocated for SLP structures.
* tree-vect-analyze.c: Include recog.h.
OSDN Git Service
