+2013-06-07 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline
+ 2013-06-10 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/alpha/alpha.c (alpha_emit_xfloating_compare): Also use
+ cmp_code to construct REG_EQUAL note.
+
+ Backport from mainline
+ 2013-06-05 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/alpha/alpha.c (alpha_emit_conditional_move): Swap all
+ GE, GT, GEU and GTU compares, modulo DImode compares with zero.
+
+ Backport from mainline
+ 2013-05-23 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/57379
+ * config/alpha/alpha.md (unspec): Add UNSPEC_XFLT_COMPARE.
+ * config/alpha/alpha.c (alpha_emit_xfloating_compare): Construct
+ REG_EQUAL note as UNSPEC_XFLT_COMPARE unspec.
+
+2013-06-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/57568
+ * config/i386/i386.md (TARGET_READ_MODIFY_WRITE peepholes): Ensure
+ that operands[2] doesn't overlap with operands[0].
+
+2013-05-22 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/57356
+ * config/i386/i386.md (*movti_internal_rex64): Emit movaps/movups
+ for non-sse2 targets. Simplify mode attribute calculation.
+
+2013-05-17 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline
+ 2013-05-16 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/driver-i386.c (host_detect_local_cpu): Determine
+ cache parameters using detect_caches_amd also for CYRIX,
+ NSC and TM2 signatures.
+
+ 2013-05-16 Uros Bizjak <ubizjak@gmail.com>
+ Dzianis Kahanovich <mahatma@eu.by>
+
+ PR target/45359
+ PR target/46396
+ * config/i386/driver-i386.c (host_detect_local_cpu): Detect
+ VIA/Centaur processors and determine their cache parameters
+ using detect_caches_amd.
+
+ 2013-05-15 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (ix86_option_override_internal): Add
+ PTA_POPCNT to corei7 entry.
+
+2013-05-14 Richard Biener <rguenther@suse.de>
+
+ PR gcov-profile/57269
+ Backport from mainline
+ 2012-06-30 Nathan Sidwell <nathan@acm.org>
+
+ * coverage.c (coverage_init): Read counts file before writing
+ graph header.
+
+2013-05-13 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/57264
+ Backport from mainline
+ 2013-01-22 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/55686
+ * config/i386/i386.md (UNSPEC_STOS): New.
+ (strset_singleop, *strsetdi_rex_1, *strsetsi_1, *strsethi_1,
+ *strsetqi_1): Add UNSPEC_STOS.
+
+2013-05-10 Joey Ye <joey.ye@arm.com>
+
+ Backport from mainline
+ 2012-11-29 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>
+
+ PR target/54974
+ * config/arm/arm.md (thumb2_pool_range, pool_range): Add comment on
+ Thumb pool ranges.
+ (thumb1_extendhisi2): Reduce Thumb pool range.
+ (arm_movdi): Likewise.
+ (thumb1_movdi_insn): Likewise.
+ (thumb1_movsi_insn): Likewise.
+ (pic_load_addr_unified): Likewise.
+ (pic_load_addr_32bit): Likewise.
+ (pic_load_addr_thumb1): Likewise.
+ (thumb1_movhf): Likewise.
+ (arm_movsf_soft_insn): Likewise.
+ (thumb1_movsf_soft_insn): Likewise.
+ (movdf_soft_insn): Likewise.
+ (thumb1_movdf_soft_insn): Likewise.
+ * config/arm/neon.md (*neon_mov<mode>): Likewise.
+ (*neon_mov<mode>): Likwise.
+ * config/arm/thumb2.md: (*thumb2_movsi_insn): Likewise.
+ (*thumb2_movhi_insn): Likewise.
+ (*thumb2_extendqisi_v6): Likewise.
+ (*thumb2_zero_extendqisi_v6): Likewise.
+ (*thumb2_zero_extendqisi2_v6): Likewise.
+ * config/arm/vfp.md: (*thumb2_movsi_vfp): Likewise.
+ (*movdi_vfp): Likewise.
+ (*movdi_vfp_cortexa8): Likewise.
+ (*thumb2_movsf_vfp): Likewise.
+ (*thumb2_movdf_vfp): Likewise.
+
+2013-05-10 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ * config/arm/t-rtems-eabi: Remove mthumb/march=armv7 multilib.
+ Add mthumb/march=armv7-a multilib.
+ Add mthumb/march=armv7-r multilib.
+ Add mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard multilib.
+
+2013-05-10 Ralf Corsépius <ralf.corsepius@rtems.org>
+
+ PR target/57237
+ * config/v850/t-rtems: Add more multilibs.
+
+2013-05-07 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Backport from trunk
+ 2013-05-03 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/57150
+ * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Use DFmode
+ to save TFmode registers and DImode to save TImode registers for
+ caller save operations.
+ (HARD_REGNO_CALL_PART_CLOBBERED): TFmode and TDmode do not need to
+ mark being partially clobbered since they only use the first
+ double word.
+
+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): TFmode
+ and TDmode only use the upper 64-bits of each VSX register.
+
+2013-05-03 Marek Polacek <polacek@redhat.com>
+
+ Backport from mainline
+ 2013-04-25 Marek Polacek <polacek@redhat.com>
+
+ PR tree-optimization/57066
+ * builtins.c (fold_builtin_logb): Return +Inf for -Inf.
+
2013-04-30 Uros Bizjak <ubizjak@gmail.com>
Backport from mainline
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