+2008-06-10 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (*btdi_rex64): Change operand 1 predicate to
+ nonmemory_operand. Add "N" operand constraint.
+ (*btsi): Ditto.
+ (*jcc_btdi_mask_rex64): New instruction and split pattern.
+ (*jcc_btsi_mask): Ditto.
+ (*jcc_btsi_mask_1): Ditto.
+
+2008-06-10 Joseph Myers <joseph@codesourcery.com>
+
+ * config/rs6000/rs6000.c (build_opaque_vector_type): Set
+ TYPE_CANONICAL for copied element type.
+
+2008-06-10 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/36473
+ * config/i386/i386.c (ix86_tune_features) [TUNE_USE_BT]:
+ Add m_CORE2 and m_GENERIC.
+ * config/i386/predicates.md (bt_comparison_operator): New predicate.
+ * config/i386/i386.md (*btdi_rex64): New instruction pattern.
+ (*btsi): Ditto.
+ (*jcc_btdi_rex64): New instruction and split pattern.
+ (*jcc_btsi): Ditto.
+ (*jcc_btsi_1): Ditto.
+ (*btsq): Fix Intel asm dialect operand order.
+ (*btrq): Ditto.
+ (*btcq): Ditto.
+
+2008-06-09 Andy Hutchinson <hutchinsonandy@aim.com>
+
+ PR middle-end/36447
+ * simplify-rtx.c (simplify_subreg): Add check for shift count
+ greater than size.
+
+2008-06-09 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * doc/md.texi: Synchronize with later constraints.md change.
+ * longlong.h (umul_ppmm): Replace the MIPS asm implementation
+ with a C implementation.
+ * config/mips/mips.c (mips_legitimize_move): Remove MFHI and
+ MFLO handling.
+ (mips_subword): Assume TImode for CONST_INTs if TARGET_64BIT.
+ (mips_split_doubleword_move): Use special MTHI and MFHI instructions
+ when moving to and from MD_REGNUM.
+ (mips_output_move): Don't handle moves from GPRs to HI_REGNUM.
+ Handle moves from LO_REGNUM to GPRs using MFLO, MACC or DMACC.
+ Handle byte and halfword moves.
+ (mips_hard_regno_mode_ok_p): Handle MD_REGS and DSP_ACC_REGS
+ separately.
+ * config/mips/constraints.md (h): Turn into NO_REGS.
+ (l, x): Update documentation.
+ * config/mips/mips.md (UNSPEC_MFHILO): Delete.
+ (UNSPEC_MFHI, UNSPEC_MTHI, UNSPEC_SET_HILO): New.
+ (UNSPEC_TLS_LDM, UNSPEC_TLS_GET_TP): Renumber.
+ (HILO): New mode iterator.
+ (MOVE128): Add TI.
+ (any_div): New code iterator.
+ (u): Extend code attribute to div and udiv.
+ (*add<mode>3_mips16, *movdi_64bit_mips16, *movsi_mips16): Use
+ d_operand in the splitters. Remove redundant CONST_INT checks.
+ (mulsi3_mult3, mul<mode>3_internal, mul<mode>3_r4000, *mul_acc_si)
+ (*macc, *msac, *msac_using_macc, *macc2, *msac2, *mul_sub_si)
+ (*muls): Remove "=h" clobbers. Adjust peephole2s and define_splits
+ accordingly, using normal moves instead of unspecs to move LO into
+ a GPR. Use d_operand and lo_operand instead of *_REG_P checks.
+ (<u>mulsidi3): Handle expansion in C code.
+ (<u>mulsidi3_32bit_internal): Rename to...
+ (<u>mulsidi3_32bit): ...this.
+ (<u>mulsidi3_32bit_r4000): Fix insn separator.
+ (*<u>mulsidi3_64bit): Rename to...
+ (<u>mulsidi3_64bit): ...this. Combine DImode "=h" and "=l" clobbers
+ into a TImode "=x" clobber. In the split, use an UNSPEC_SET_HILO
+ to set LO and HI to the multiplication result. Use a normal move
+ for MFLO and an unspec for MFHI.
+ (*<u>mulsidi3_64bit_parts): Replace with...
+ (<u>mulsidi3_64bit_hilo): ...this new instruction.
+ (<su>mulsi3_highpart): Extend to TARGET_FIX_R4000.
+ (<su>mulsi3_highpart_internal): Turn into a define_insn_and_split
+ and extend it to TARGET_FIX_R4000. Store the destination in a GPR
+ instead of HI. Split the instruction into a separate multiplication
+ and MFHI if !TARGET_FIX_R4000.
+ (<su>muldi3_highpart): Likewise.
+ (<su>mulsi3_highpart_mulhi_internal): Remove the first alternative
+ and the "=h" clobber.
+ (*<su>mulsi3_highpart_neg_mulhi_internal): Likewise.
+ (<u>mulditi3): New expander.
+ (<u>mulditi3_internal, <u>mulditi3_r4000): New patterns.
+ (madsi): Remove "=h" clobber.
+ (divmod<mode>4, udivmod<mode>4): Turn into define_insn_and_splits.
+ Force the modulus result to be a GPR and split the instruction into
+ a division followed by an MFHI after reload.
+ (<u>divmod<GPR:mode>4_hilo_<HILO:mode>): New instruction.
+ (*lea_high64): Use d_operand in the define_peephole2. Likewise
+ the MIPS16 HIGH define_split.
+ (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16): Change type
+ of acc<->gpr moves to "multi".
+ (*movdi_64bit): Replace the single "x" alternative with
+ alternatives for moving into and out of "a".
+ (*movhi_internal, *movqi_internal): Likewise. Use mips_output_move.
+ (*movsi_internal): Extend the "d<-A" alternative to "d<-a".
+ (*movdi_64bit_mips16, *movsi_mips16): Add d<-a alternatives.
+ Use d_operand in the splitters. Remove redundant CONST_INT checks.
+ (*movhi_mips16, *movqi_mips16): Likewise. Use mips_output_move.
+ (movti): New expander.
+ (*movti, *movti_mips16): New insns.
+ (mfhilo_<mode>, *mfhilo_<mode>, *mfhilo_<mode>_macc): Delete.
+ (mfhi<GPR:mode>_<HILO:mode>): New pattern.
+ (mthi<GPR:mode>_<HILO:mode>): Likewise.
+ * config/mips/predicates.md (fpr_operand): Delete.
+ (d_operand): New predicate.
+
+2008-06-09 Michael Meissner <michael.meissner@amd.com>
+
+ * config.gcc (i[34567]86-*-*): Put test in quotes to prevent
+ failure on some Bourne shells.
+ (x86_64-*-*): Ditto.
+
+2008-06-09 Kai Tietz <kai.tietz@onevision.com>
+
+ * config/i386/cygming.h (TARGET_SUBTARGET64_DEFAULT): New.
+
+2008-06-09 Eric Botcazou <ebotcazou@libertysurf.fr>
+
+ * doc/install.texi (*-*-solaris2*): Remove obsolete contents.
+ (sparc-sun-solaris2*): Likewise.
+
+2008-06-09 Arnaud Charlet <charlet@adacore.com
+
+ * doc/install.texi: Update requirements to build the Ada compiler.
+
+2008-06-08 Steven Bosscher <stevenb.gcc@gmail.com>
+
+ * df-scan.c (struct df_scan_problem_data): Remove the
+ mw_link_pool alloc pool.
+ (df_scan_free_internal): Don't free it.
+ (df_scan_alloc): Don't allocate it.
+ * df.h (struct df_link): Update comment.
+
+2008-06-08 Nathan Sidwell <nathan@codesourcery.com>
+
+ * except.h: Correct checks for when SJLJ exceptions must be used.
+
+2008-06-08 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
+
+ * doc/invoke.texi (Wenum-compare): Mention that it is enabled by
+ default.
+
2008-06-08 Joseph Myers <joseph@codesourcery.com>
PR tree-optimization/36218