-2007-09-28 Jakub Jelinek <jakub@redhat.com>
+2007-10-01 Alexandre Oliva <aoliva@redhat.com>
- PR c++/31434
- * tree.c (cp_build_qualified_type_real): Handle TYPE_PACK_EXPANSION
- qualification by creating qualified PACK_EXPANSION_PATTERN and
- then calling make_pack_expansion on it.
+ * tree-ssa-sink.c (sink_code_in_bb): Don't stop sinking after
+ sinking the last stmt in a BB.
+
+2007-10-01 Alexandre Oliva <aoliva@redhat.com>
+
+ PR middle-end/22156
+ * tree-sra.c (struct sra_elt): Add in_bitfld_block.
+ (sra_hash_tree): Handle BIT_FIELD_REFs.
+ (sra_elt_hash): Don't hash bitfld blocks.
+ (sra_elt_eq): Skip them in parent compares as well. Handle
+ BIT_FIELD_REFs.
+ (build_element_name_1): Handle BIT_FIELD_REFs.
+ (instantiate_element): Propagate nowarn from parents. Create
+ BIT_FIELD_REF for variables that are widened by scalarization.
+ Gimple-zero-initialize all bit-field variables that are not
+ part of parameters that are going to be scalarized on entry.
+ (instantiate_missing_elements_1): Return the sra_elt.
+ (canon_type_for_field): New.
+ (try_instantiate_multiple_fields): New. Infer widest possible
+ access mode from decl or member type, but clip it at word
+ size, and only widen it if a field crosses an alignment
+ boundary.
+ (instantiate_missing_elements): Use them.
+ (generate_one_element_ref): Handle BIT_FIELD_REFs.
+ (scalar_bitfield_p): New.
+ (sra_build_assignment): Optimize assignments from scalarizable
+ BIT_FIELD_REFs. Use BITS_BIG_ENDIAN to determine shift
+ counts.
+ (REPLDUP): New.
+ (sra_build_bf_assignment): New. Optimize assignments to
+ scalarizable BIT_FIELD_REFs.
+ (sra_build_elt_assignment): New. Optimize BIT_FIELD_REF
+ assignments to full variables.
+ (generate_copy_inout): Use the new macros and functions.
+ (generate_element_copy): Likewise. Handle bitfld differences.
+ (generate_element_zero): Don't recurse for blocks. Use
+ sra_build_elt_assignment.
+ (generate_one_element_init): Take elt instead of var. Use
+ sra_build_elt_assignment.
+ (generate_element_init_1): Adjust.
+ (bitfield_overlap_info): New struct.
+ (bitfield_overlaps_p): New.
+ (sra_explode_bitfield_assignment): New. Adjust widened
+ variables to account for endianness.
+ (sra_sync_for_bitfield_assignment): New.
+ (scalarize_use): Re-expand assignment to/from scalarized
+ BIT_FIELD_REFs. Explode or sync needed members for
+ BIT_FIELD_REFs accesses or assignments. Use REPLDUP.
+ (scalarize_copy): Use REPLDUP.
+ (scalarize_ldst): Move assert before dereference. Adjust EH
+ handling.
+ (dump_sra_elt_name): Handle BIT_FIELD_REFs.
+
+2007-10-01 Paolo Bonzini <bonzini@gnu.org>
+
+ * simplify-rtx.c (comparison_result, simplify_relational_operation_1):
+ Rename CR_* constants to CMP_*. Fix spacing.
+
+2007-10-01 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
+
+ PR other/33585
+ * Makefile.in (build_html_dir/gccinstall): gccinstall.texi needs
+ to be processed with the special script doc/install.texi2html.
+
+2007-09-30 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
+
+ * doc/invoke.texi (Wall): List the options enabled by Wall.
+ (Wstrict-aliasing): Add missing @option.
+
+2007-09-30 Richard Sandiford <rsandifo@nildram.co.uk>
+
+ * config/mips/mips.c (mips_split_64bit_move): Use gen_rtx_REG_offset
+ rather than gen_lowpart to change a register from DImode to DFmode.
+ (mips_cannot_change_mode_class): Only allow FPRs to change mode if
+ both FROM and TO are integer modes that are no bigger than 4 bytes.
+ (mips_mode_ok_for_mov_fmt_p): New function.
+ (mips_preferred_reload_class): Use it instead of FLOAT_MODE_P.
+ (mips_secondary_reload_class): Tweak formatting and comments.
+ Use reg_class_subset_p instead of direct comparisons with
+ classes. Only allow direct FPR<->FPR moves for modes that
+ satisfy mips_mode_ok_for_mov_fmt_p. Only allow loads and stores
+ for 4- and 8-byte types. Handle reloads in which X is an FPR.
+ * config/mips/mips.md (*movdi_gp32_fp64): Remove f<-f alternative.
+ (*movdi_64bit): Likewise.
+ (*movsi_internal): Likewise.
+ (*movhi_internal): Likewise.
+ (*movqi_internal): Likewise.
+
+2007-09-30 Diego Novillo <dnovillo@google.com>
+
+ PR 33593
+ * tree-ssa-ter.c (is_replaceable_p): Return false if STMT may
+ throw an exception.
+
+2007-09-30 Uros Bizjak <ubizjak@gmail.com>
+
+ PR tree-optimization/33597
+ * tree-vect-analyze.c (vect_build_slp_tree): Check if optab handler
+ for LSHIFT_EXPR and RSHIFT_EXPR is available for vec_mode.
+
+2007-09-28 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (ix86_expand_move): Use can_create_pseudo_p ()
+ instead of variants of (!reload_in_progress && !reload_completed).
+ (x86_expand_vector_move): Ditto.
+
+2007-09-28 Ollie Wild <aaw@google.com>
+
+ Revert
+ 2007-09-27 Ollie Wild <aaw@google.com>
+
+ * varasm.c (compare_constant): Removed call to
+ lang_hooks.expand_constant.
+ (copy_constants): Removed call to lang_hooks.expand_constant.
+ (compute_reloc_for_constant): Removed call to
+ lang_hooks.expand_constant.
+ (output_addressed_constants): Removed call to
+ lang_hooks.expand_constant.
+ (constructor_static_from_elts_p): Removed call to
+ lang_hooks.expand_constant.
+ (output_constant): Removed calls to lang_hooks.expand_constant.
+ * langhooks.h (struct lang_hooks): Removed field expand_constant.
+ * langhooks-def.h (lhd_return_tree): Removed.
+ (LANG_HOOKS_EXPAND_CONSTANT): Removed.
+ (LANG_HOOKS_INITIALIZER): Removed LANG_HOOKS_EXPAND_CONSTANT.
+ * langhooks.c (lhd_return_tree): Removed.
+
+2007-09-28 Andrew Pinski <andrew_pinski@playstation.sony.com>
+
+ PR target/33347
+ * config/spu/spu.c (spu_expand_insv): Call copy_rtx on the second
+ argument to gen_selb.
+
+2007-09-28 Chao-ying Fu <fu@mips.com>
+
+ * libgcc-std.ver: Add fixed-point routines to GCC_4.3.0 section.
+ * doc/libgcc.texi (Fixed-point fractional library routines):
+ Fix typos for neg and cmp functions.
+
+2007-09-28 Michael Matz <matz@suse.de>
+
+ PR rtl-optimization/33552
+ * function.c (match_asm_constraints_1): Check for overlap in
+ inputs and replace all occurences.
+
+2007-09-28 Richard Sandiford <rsandifo@nildram.co.uk>
+
+ * config/mips/mips.c (override_options): Fix comment typo.
2007-09-28 Jie Zhang <jie.zhang@analog.com>
2007-09-25 Michael Meissner <michael.meissner@amd.com>
- PR c/33524
+ PR target/33524
* config/i386/i386.c (ix86_expand_sse5_unpack): Change to call
gen_sse5_pperm_sign_v4si_v2di and gen_sse5_pperm_zero_v4si_v2di
for vector int32 -> int64 conversions. Don't write beyond the end
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