+2011-10-24 Dodji Seketeli <dodji@redhat.com>
+
+ * input.c (expand_location): Rewrite using
+ linemap_resolve_location and linemap_expand_location. Add a
+ comment.
+
+2011-10-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/50596
+ * tree-vect-stmts.c (vect_mark_relevant): Only use
+ FOR_EACH_IMM_USE_FAST if lhs is SSA_NAME.
+ (vectorizable_store): If is_pattern_stmt_p look through
+ VIEW_CONVERT_EXPR on lhs.
+ * tree-vect-patterns.c (check_bool_pattern, adjust_bool_pattern):
+ Use unsigned type instead of signed.
+ (vect_recog_bool_pattern): Optimize also stores into bool memory in
+ addition to casts from bool to integral types.
+ (vect_mark_pattern_stmts): If pattern_stmt already has vinfo
+ created, don't create it again.
+
+2011-10-25 Kai Tietz <ktietz@redhat.com>
+
+ * config/i386/i386.c (ix86_frame_pointer_required): Require
+ frame-pointer, if setjmp is used for 32-bit ms-abi.
+
+2011-10-24 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * builtins.c (set_builtin_user_assembler_name): Remove extra
+ newline added in October 11th, 2011 change.
+
+2011-10-24 David S. Miller <davem@davemloft.net>
+
+ * config/sparc/little-endian.opt: Delete.
+ * config.gcc: Remove references to config/sparc/little-endian.opt
+ * doc/invoke.texi: Remove documentation of -mlittl-endian on sparc.
+ * config/sparc/linux64.h: Delete references to -mlittle-endian.
+ * config/sparc/netbsd-elf.h: Likewise.
+ * config/sparc/openbsd64.h: Likewise.
+ * config/sparc/sparc.h: Likewise.
+ * config/sparc/sp64-elf.h: Likewise and delete overrides for
+ BYTES_BIG_ENDIAN and WORDS_BIG_ENDIAN.
+ * config/sparc/sparc.c (dump_target_flag_bits): Remove reference
+ to MASK_LITTLE_ENDIAN.
+ * config/sparc/sparc.opt (Mask(LITTLE_ENDIAN)): Delete.
+
+ * config/sparc/sparc.md: Only use F, G, and C constraints in FP
+ insns. Only use D, Y, and Z constraints in vector insns.
+
+ * config/sparc/sparc.md (cpu_feature, enabled): New attributes.
+ (*movsi_insn_novis3, *movsi_insn_vis3): Consolidate into one pattern
+ called *movsi_insn.
+ (*movdi_insn_sp32_v9_novis3, *movdi_insn_sp32_v9_vis3): Consolidate
+ into *movdi_insn_sp32.
+ (*movdi_insn_sp64_novis3, *movdi_insn_sp64_vis3): Consolidate into
+ one pattern called *movdi_insn_sp64.
+ (*movsf_insn_novis3, *movsf_insn_vis3, *movsf_insn_no_fpu):
+ Consolidate into one pattern called *movsf_insn.
+ (*movdf_insn_sp32_no_fpu, *movdf_insn_sp32_v9_novis3,
+ *movdf_insn_sp32_v9_vis3, *movdf_insn_sp32_v9_no_fpu): Consolidate
+ into *movdf_insn_sp32.
+ (*movdf_insn_sp64_novis3, *movdf_insn_sp64_vis3,
+ *movdf_insn_sp64_no_fpu): Consolidate into one pattern called
+ *movdf_insn_sp64.
+ (*zero_extendsidi2_insn_sp64_novis3,
+ *zero_extendsidi2_insn_sp64_vis3): Consolidate into one pattern
+ called *zero_extendsidi2_insn_sp64.
+ (*sign_extendsidi2_insn_novis3, *sign_extendsidi2_insn_vis3):
+ Consolidate into one pattern named *sign_extendsidi2_insn.
+ (*mov<VM32:mode>_insn_novis3, *mov<VM32:mode>_insn_vis3):
+ Consolidate into one pattern named *mov<VM32:mode>_insn.
+ (*mov<VM64:mode>_insn_sp64_novis3,
+ *mov<VM64:mode>_insn_sp64_novis3): Consolidate into one pattern
+ named *mov<VM64:mode>_insn_sp64.
+ (*mov<VM64:mode>_insn_sp32_novis3,
+ *mov<VM64:mode>_insn_sp32_vis3): Consolidate into one pattern
+ named *mov<VM64:mode>_insn_sp32.
+
+2011-10-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * tree-ssa-strlen.c (get_string_length): Change assertion to STPCPY.
+ (zero_length_string): Change assertion to accept strinfo without
+ length but with stmt instead.
+ Set the endptr pointer also if starting a new chain.
+ (adjust_related_strinfos): Ignore strinfos marked for delayed
+ length computation.
+ (handle_builtin_strcpy): Mark earlier strinfo elements also for
+ delayed length computation.
+
+2011-10-24 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/50820
+ Port from 4.6 branch r180379
+ * doc/invoke.texi (AVR Options): New subsubsection to explain EIND
+ handling and indirect jump/calls on devices > 128k.
+
+2011-10-24 Anatoly Sokolov <aesok@post.ru>
+ Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/49824
+ * doc/extend.texi (Declaring Attributes of Functions):
+ Document OS_main and OS_task attributes.
+ (Specifying Attributes of Variables): Move up
+ subsection "AVR Variable Attributes" as of alphabetical order.
+
+2011-10-24 Richard Guenther <rguenther@suse.de>
+
+ * tree-vect-stmts.c (vect_get_vec_def_for_operand): Convert constants
+ to vector element type.
+ (vectorizable_assignment): Bail out for non-mode-precision operations.
+ (vectorizable_shift): Likewise.
+ (vectorizable_operation): Likewise.
+ (vectorizable_type_demotion): Likewise.
+ (vectorizable_type_promotion): Likewise.
+ (vectorizable_store): Handle non-mode-precision stores.
+ (vectorizable_load): Handle non-mode-precision loads.
+ (get_vectype_for_scalar_type_and_size): Return a vector type
+ for non-mode-precision integers.
+ * tree-vect-loop.c (vectorizable_reduction): Bail out for
+ non-mode-precision reductions.
+
+2011-10-24 Julian Brown <julian@codesourcery.com>
+
+ * config/m68k/m68k.c (notice_update_cc): Tighten condition for
+ setting CC_REVERSED for FP comparisons.
+
+2011-10-24 Richard Guenther <rguenther@suse.de>
+
+ PR tree-optimization/50838
+ * tree-data-ref.c (dr_analyze_indices): Properly canonicalize
+ a MEM_REF base if we change it.
+
+2011-10-24 Bernd Schmidt <bernds@codesourcery.com>
+
+ PR bootstrap/50836
+ * rtlanal.c: Swap includes of "hard-reg-set.h" and "rtl.h".
+
+ PR rtl-optimization/50833
+ * function.c (thread_prologue_and_epilogue_insns): Expect the
+ return insn optimization only if optimize.
+
+2011-10-24 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr.c: Break long lines.
+ Define target hooks on the fly if applicable.
+ (TARGET_ASM_FUNCTION_RODATA_SECTION): Remove first definition
+ overridden later.
+ (targetm): Move definition to end of file.
+ (avr_can_eliminate): Make static on the fly.
+ (avr_frame_pointer_required_p): Ditto.
+ (avr_hard_regno_scratch_ok): Ditto.
+ (avr_builtin_setjmp_frame_value): Make static on the fly.
+ Indent according to coding rules.
+ (avr_case_values_threshold): Ditto.
+ (avr_attribute_table): Move down.
+
+2011-10-24 Ira Rosen <ira.rosen@linaro.org>
+
+ PR tree-optimization/50730
+ * tree-vect-data-refs.c (vect_analyze_data_refs): Stop basic block
+ analysis if encountered unsupported data-ref.
+
2011-10-23 David S. Miller <davem@davemloft.net>
+ * config/sparc/sparc.c (sparc_option_override): Remove -mv8plus
+ cpu adjustment.
+ * config/sparc/linux64.h (CC1_SPEC): When defaulting to 64-bit,
+ append -mcpu=v9 when -mv8plus is given.
+
+ * config/sparc/sparc.h (SECONDARY_MEMORY_NEEDED): We can move
+ between float and non-float regs when VIS3.
+ * config/sparc/sparc.c (eligible_for_restore_insn): We can't
+ use a restore when the source is a float register.
+ (sparc_split_regreg_legitimate): When VIS3 allow moves between
+ float and integer regs.
+ (sparc_register_move_cost): Adjust to account for VIS3 moves.
+ (sparc_preferred_reload_class): On 32-bit with VIS3 when moving an
+ integer reg to a class containing EXTRA_FP_REGS, constrain to
+ FP_REGS.
+ (sparc_secondary_reload): On 32-bit with VIS3 when moving between
+ float and integer regs we sometimes need a FP_REGS class
+ intermediate move to satisfy the reload. When this happens
+ specify an extra cost of 2.
+ (*movsi_insn): Rename to have "_novis3" suffix and add !VIS3
+ guard.
+ (*movdi_insn_sp32_v9): Likewise.
+ (*movdi_insn_sp64): Likewise.
+ (*movsf_insn): Likewise.
+ (*movdf_insn_sp32_v9): Likewise.
+ (*movdf_insn_sp64): Likewise.
+ (*zero_extendsidi2_insn_sp64): Likewise.
+ (*sign_extendsidi2_insn): Likewise.
+ (*movsi_insn_vis3): New insn.
+ (*movdi_insn_sp32_v9_vis3): New insn.
+ (*movdi_insn_sp64_vis3): New insn.
+ (*movsf_insn_vis3): New insn.
+ (*movdf_insn_sp32_v9_vis3): New insn.
+ (*movdf_insn_sp64_vis3): New insn.
+ (*zero_extendsidi2_insn_sp64_vis3): New insn.
+ (*sign_extendsidi2_insn_vis3): New insn.
+ (TFmode reg/reg split): Make sure both REG operands are float.
+ (*mov<VM32:mode>_insn): Add "_novis3" suffix and !VIS3 guard. Remove
+ easy constant to integer reg alternatives.
+ (*mov<VM64:mode>_insn_sp64): Likewise.
+ (*mov<VM64:mode>_insn_sp32_novis3): Likewise.
+ (*mov<VM32:mode>_insn_vis3): New insn.
+ (*mov<VM64:mode>_insn_sp64_vis3): New insn.
+ (*mov<VM64:mode>_insn_sp32_vis3): New insn.
+ (VM64 reg<-->reg split): New spliiter for 32-bit.
+
* config/sparc/sparc.c (sparc_split_regreg_legitimate): New
function.
* config/sparc/sparc-protos.h (sparc_split_regreg_legitimate):
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