; Options for the IA-32 and AMD64 ports of the compiler. ; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc. ; ; This file is part of GCC. ; ; GCC is free software; you can redistribute it and/or modify it under ; the terms of the GNU General Public License as published by the Free ; Software Foundation; either version 3, or (at your option) any later ; version. ; ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY ; WARRANTY; without even the implied warranty of MERCHANTABILITY or ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ; for more details. ; ; You should have received a copy of the GNU General Public License ; along with GCC; see the file COPYING3. If not see ; . m128bit-long-double Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) sizeof(long double) is 16 m80387 Target Report Mask(80387) Use hardware fp m96bit-long-double Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) sizeof(long double) is 12 maccumulate-outgoing-args Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Reserve space for outgoing arguments in the function prologue malign-double Target Report Mask(ALIGN_DOUBLE) Align some doubles on dword boundary malign-functions= Target RejectNegative Joined Var(ix86_align_funcs_string) Function starts are aligned to this power of 2 malign-jumps= Target RejectNegative Joined Var(ix86_align_jumps_string) Jump targets are aligned to this power of 2 malign-loops= Target RejectNegative Joined Var(ix86_align_loops_string) Loop code aligned to this power of 2 malign-stringops Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Align destination of the string operations march= Target RejectNegative Joined Var(ix86_arch_string) Generate code for given CPU masm= Target RejectNegative Joined Var(ix86_asm_string) Use given assembler dialect mbranch-cost= Target RejectNegative Joined Var(ix86_branch_cost_string) Branches are this expensive (1-5, arbitrary units) mlarge-data-threshold= Target RejectNegative Joined Var(ix86_section_threshold_string) Data greater than given threshold will go into .ldata section in x86-64 medium model mcmodel= Target RejectNegative Joined Var(ix86_cmodel_string) Use given x86-64 code model mfancy-math-387 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Generate sin, cos, sqrt for FPU mfp-ret-in-387 Target Report Mask(FLOAT_RETURNS) Return values of functions in FPU registers mfpmath= Target RejectNegative Joined Var(ix86_fpmath_string) Generate floating point mathematics using given instruction set mhard-float Target RejectNegative Mask(80387) MaskExists Use hardware fp mieee-fp Target Report Mask(IEEE_FP) Use IEEE math for fp comparisons minline-all-stringops Target Report Mask(INLINE_ALL_STRINGOPS) Inline all known string operations minline-stringops-dynamically Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Inline memset/memcpy string operations, but perform inline version only for small blocks mintel-syntax Target Undocumented ;; Deprecated mms-bitfields Target Report Mask(MS_BITFIELD_LAYOUT) Use native (MS) bitfield layout mno-align-stringops Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented mno-fancy-math-387 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented mno-push-args Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented mno-red-zone Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented momit-leaf-frame-pointer Target Report Mask(OMIT_LEAF_FRAME_POINTER) Omit the frame pointer in leaf functions mpc Target RejectNegative Report Joined Var(ix87_precision_string) Set 80387 floating-point precision (-mpc32, -mpc64, -mpc80) mpreferred-stack-boundary= Target RejectNegative Joined Var(ix86_preferred_stack_boundary_string) Attempt to keep stack aligned to this power of 2 mpush-args Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Use push instructions to save outgoing arguments mred-zone Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Use red-zone in the x86-64 code mregparm= Target RejectNegative Joined Var(ix86_regparm_string) Number of registers used to pass integer arguments mrtd Target Report Mask(RTD) Alternate calling convention msoft-float Target InverseMask(80387) Do not use hardware fp msseregparm Target RejectNegative Mask(SSEREGPARM) Use SSE register passing conventions for SF and DF mode mstackrealign Target Report Var(ix86_force_align_arg_pointer) Realign stack in prologue mstack-arg-probe Target Report Mask(STACK_PROBE) Enable stack probing mstringop-strategy= Target RejectNegative Joined Var(ix86_stringop_string) Chose strategy to generate stringop using mtls-dialect= Target RejectNegative Joined Var(ix86_tls_dialect_string) Use given thread-local storage dialect mtls-direct-seg-refs Target Report Mask(TLS_DIRECT_SEG_REFS) Use direct references against %gs when accessing tls data mtune= Target RejectNegative Joined Var(ix86_tune_string) Schedule code for given CPU mveclibabi= Target RejectNegative Joined Var(ix86_veclibabi_string) Vector library ABI to use ;; ISA support m32 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists Generate 32bit i386 code m64 Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists Generate 64bit x86-64 code mmmx Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists Support MMX built-in functions m3dnow Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists Support 3DNow! built-in functions m3dnowa Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists Support Athlon 3Dnow! built-in functions msse Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists Support MMX and SSE built-in functions and code generation msse2 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists Support MMX, SSE and SSE2 built-in functions and code generation msse3 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation mssse3 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation msse4.1 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation msse4.2 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) VarExists Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation msse4 Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) VarExists Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation mno-sse4 Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) VarExists Do not support SSE4.1 and SSE4.2 built-in functions and code generation msse4a Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation msse5 Target Report Mask(ISA_SSE5) Var(ix86_isa_flags) VarExists Support SSE5 built-in functions and code generation ;; Instruction support mabm Target Report RejectNegative Var(x86_abm) Support code generation of Advanced Bit Manipulation (ABM) instructions. mcx16 Target Report RejectNegative Var(x86_cmpxchg16b) Support code generation of cmpxchg16b instruction. mpopcnt Target Report RejectNegative Var(x86_popcnt) Support code generation of popcnt instruction. msahf Target Report RejectNegative Var(x86_sahf) Support code generation of sahf instruction in 64bit x86-64 code. mrecip Target Report RejectNegative Var(x86_recip) Generate reciprocals instead of divss and sqrtss. mfused-madd Target Report Var(x86_fused_muladd) Init(1) Enable automatic generation of fused floating point multiply-add instructions if the ISA supports such instructions. The -mfused-madd option is on by default.