1 /* Testcase to check generation of a SH2A specific instruction for
2 "BOR.B #imm3, @(disp12, Rn)". */
3 /* { dg-do assemble {target sh*-*-*}} */
4 /* { dg-options "-O1 -mbitops" } */
5 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
6 /* { dg-final { scan-assembler "bor.b"} } */
35 unsigned char IOR15:1;
36 unsigned char IOR14:1;
37 unsigned char IOR13:1;
38 unsigned char IOR12:1;
39 unsigned char IOR11:1;
40 unsigned char IOR10:1;
59 volatile unsigned char a;
61 /* Instruction generated is BOR.B #imm3, @(disp12, Rn) */
62 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1;
63 USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 | USRSTR.ICR0.BIT.BIT6;
64 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4;
65 USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 | USRSTR.ICR0.BIT.BIT3;
67 a = USRSTR.ICR0.BIT.BIT0 | USRSTR.ICR0.BIT.BIT1;
68 a = USRSTR.ICR0.BIT.BIT5 | USRSTR.ICR0.BIT.BIT7;
69 a = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT6;
71 PORT.BIT.IOR13 = PORT.BIT.IOR0 | USRSTR.ICR0.BIT.BIT7;
72 PORT.BIT.IOR15 = PORT.BIT.IOR6 | USRSTR.ICR0.BIT.BIT2;
73 PORT.BIT.IOR3 = PORT.BIT.IOR2 | USRSTR.ICR0.BIT.BIT5;
74 PORT.BIT.IOR1 = PORT.BIT.IOR13 | USRSTR.ICR0.BIT.BIT1;
76 PORT.BIT.IOR1 = PORT.BIT.IOR2 | USRSTR.ICR0.BIT.BIT1;
77 PORT.BIT.IOR11 = PORT.BIT.IOR9 | USRSTR.ICR0.BIT.BIT2;
78 PORT.BIT.IOR8 = PORT.BIT.IOR14 | USRSTR.ICR0.BIT.BIT5;
80 PORT.BIT.IOR10 |= USRSTR.ICR0.BIT.BIT1;
81 PORT.BIT.IOR1 |= USRSTR.ICR0.BIT.BIT2;
82 PORT.BIT.IOR5 |= USRSTR.ICR0.BIT.BIT5;
83 PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4;
85 /* Instruction generated on using size optimization option "-Os". */
86 a = a & USRSTR.ICR0.BIT.BIT1;
87 a = a & USRSTR.ICR0.BIT.BIT4;
88 a = a & USRSTR.ICR0.BIT.BIT0;