1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 2, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 /* Expression definitions and descriptions for all targets are in this file.
27 Some will not be used for some targets.
29 The fields in the cpp macro call "DEF_RTL_EXPR()"
30 are used to create declarations in the C source of the compiler.
34 1. The internal name of the rtx used in the C source.
35 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
36 By convention these are in UPPER_CASE.
38 2. The name of the rtx in the external ASCII format read by
39 read_rtx(), and printed by print_rtx().
40 These names are stored in rtx_name[].
41 By convention these are the internal (field 1) names in lower_case.
43 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
44 These formats are stored in rtx_format[].
45 The meaning of the formats is documented in front of this array in rtl.c
47 4. The class of the rtx. These are stored in rtx_class and are accessed
48 via the GET_RTX_CLASS macro. They are defined as follows:
51 an rtx code that can be used to represent a constant object
54 an rtx code that can be used to represent an object (e.g, REG, MEM)
56 an rtx code for a comparison (e.g, LT, GT)
58 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
60 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
62 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
64 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
66 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
68 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
70 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
72 an rtx code for something that matches in insns (e.g, MATCH_DUP)
74 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
78 All of the expressions that appear only in machine descriptions,
79 not in RTL used by the compiler itself, are at the end of the file. */
81 /* Unknown, or no such operation; the enumeration constant should have
83 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
85 /* ---------------------------------------------------------------------
86 Expressions used in constructing lists.
87 --------------------------------------------------------------------- */
89 /* a linked list of expressions */
90 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
92 /* a linked list of instructions.
93 The insns are represented in print by their uids. */
94 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
96 /* SEQUENCE appears in the result of a `gen_...' function
97 for a DEFINE_EXPAND that wants to make several insns.
98 Its elements are the bodies of the insns that should be made.
99 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
100 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
102 /* Refers to the address of its argument. This is only used in alias.c. */
103 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
105 /* ----------------------------------------------------------------------
106 Expression types used for things in the instruction chain.
108 All formats must start with "iuu" to handle the chain.
109 Each insn expression holds an rtl instruction and its semantics
110 during back-end processing.
111 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
113 ---------------------------------------------------------------------- */
115 /* An instruction that cannot jump. */
116 DEF_RTL_EXPR(INSN, "insn", "iuuBieie", RTX_INSN)
118 /* An instruction that can possibly jump.
119 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
120 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieie0", RTX_INSN)
122 /* An instruction that can possibly call a subroutine
123 but which will not change which instruction comes next
124 in the current function.
125 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
126 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
127 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieiee", RTX_INSN)
129 /* A marker that indicates that control will not flow through. */
130 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
132 /* Holds a label that is followed by instructions.
134 4: is used in jump.c for the use-count of the label.
135 5: is used in the sh backend.
136 6: is a number that is unique in the entire compilation.
137 7: is the user-given name of the label, if any. */
138 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
140 /* Say where in the code a source line starts, for symbol table's sake.
142 4: note-specific data
144 6: unique number if insn_note == note_insn_deleted_label. */
145 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
147 /* ----------------------------------------------------------------------
148 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
149 ---------------------------------------------------------------------- */
151 /* Conditionally execute code.
152 Operand 0 is the condition that if true, the code is executed.
153 Operand 1 is the code to be executed (typically a SET).
155 Semantics are that there are no side effects if the condition
156 is false. This pattern is created automatically by the if_convert
157 pass run after reload or by target-specific splitters. */
158 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
160 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
161 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
163 #ifdef USE_MAPPED_LOCATION
164 /* A string that is passed through to the assembler as input.
165 One can obviously pass comments through by using the
166 assembler comment syntax.
167 These occur in an insn all by themselves as the PATTERN.
168 They also appear inside an ASM_OPERANDS
169 as a convenient way to hold a string. */
170 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
172 /* An assembler instruction with operands.
173 1st operand is the instruction template.
174 2nd operand is the constraint for the output.
175 3rd operand is the number of the output this expression refers to.
176 When an insn stores more than one value, a separate ASM_OPERANDS
177 is made for each output; this integer distinguishes them.
178 4th is a vector of values of input operands.
179 5th is a vector of modes and constraints for the input operands.
180 Each element is an ASM_INPUT containing a constraint string
181 and whose mode indicates the mode of the input operand.
182 6th is the source line number. */
183 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
185 /* A string that is passed through to the assembler as input.
186 One can obviously pass comments through by using the
187 assembler comment syntax.
188 These occur in an insn all by themselves as the PATTERN.
189 They also appear inside an ASM_OPERANDS
190 as a convenient way to hold a string. */
191 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "ssi", RTX_EXTRA)
193 /* An assembler instruction with operands.
194 1st operand is the instruction template.
195 2nd operand is the constraint for the output.
196 3rd operand is the number of the output this expression refers to.
197 When an insn stores more than one value, a separate ASM_OPERANDS
198 is made for each output; this integer distinguishes them.
199 4th is a vector of values of input operands.
200 5th is a vector of modes and constraints for the input operands.
201 Each element is an ASM_INPUT containing a constraint string
202 and whose mode indicates the mode of the input operand.
203 6th is the name of the containing source file.
204 7th is the source line number. */
205 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
208 /* A machine-specific operation.
209 1st operand is a vector of operands being used by the operation so that
210 any needed reloads can be done.
211 2nd operand is a unique value saying which of a number of machine-specific
212 operations is to be performed.
213 (Note that the vector must be the first operand because of the way that
214 genrecog.c record positions within an insn.)
216 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
217 or inside an expression.
218 UNSPEC by itself or as a component of a PARALLEL
219 is currently considered not deletable.
221 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
222 of a PARALLEL with USE.
224 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
226 /* Similar, but a volatile operation and one which may trap. */
227 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
229 /* Vector of addresses, stored as full words. */
230 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
231 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
233 /* Vector of address differences X0 - BASE, X1 - BASE, ...
234 First operand is BASE; the vector contains the X's.
235 The machine mode of this rtx says how much space to leave
236 for each difference and is adjusted by branch shortening if
237 CASE_VECTOR_SHORTEN_MODE is defined.
238 The third and fourth operands store the target labels with the
239 minimum and maximum addresses respectively.
240 The fifth operand stores flags for use by branch shortening.
241 Set at the start of shorten_branches:
242 min_align: the minimum alignment for any of the target labels.
243 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
244 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
245 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
246 min_after_base: true iff minimum address target label is after BASE.
247 max_after_base: true iff maximum address target label is after BASE.
248 Set by the actual branch shortening process:
249 offset_unsigned: true iff offsets have to be treated as unsigned.
250 scale: scaling that is necessary to make offsets fit into the mode.
252 The third, fourth and fifth operands are only valid when
253 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
256 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
258 /* Memory prefetch, with attributes supported on some targets.
259 Operand 1 is the address of the memory to fetch.
260 Operand 2 is 1 for a write access, 0 otherwise.
261 Operand 3 is the level of temporal locality; 0 means there is no
262 temporal locality and 1, 2, and 3 are for increasing levels of temporal
265 The attributes specified by operands 2 and 3 are ignored for targets
266 whose prefetch instructions do not support them. */
267 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
269 /* ----------------------------------------------------------------------
270 At the top level of an instruction (perhaps under PARALLEL).
271 ---------------------------------------------------------------------- */
274 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
275 Operand 2 is the value stored there.
276 ALL assignment must use SET.
277 Instructions that do multiple assignments must use multiple SET,
279 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
281 /* Indicate something is used in a way that we don't want to explain.
282 For example, subroutine calls will use the register
283 in which the static chain is passed.
285 USE can not appear as an operand of other rtx except for PARALLEL.
286 USE is not deletable, as it indicates that the operand
287 is used in some unknown way. */
288 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
290 /* Indicate something is clobbered in a way that we don't want to explain.
291 For example, subroutine calls will clobber some physical registers
292 (the ones that are by convention not saved).
294 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
295 CLOBBER of a hard register appearing by itself (not within PARALLEL)
296 is considered undeletable before reload. */
297 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
299 /* Call a subroutine.
300 Operand 1 is the address to call.
301 Operand 2 is the number of arguments. */
303 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
305 /* Return from a subroutine. */
307 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
310 Operand 1 is the condition.
311 Operand 2 is the trap code.
312 For an unconditional trap, make the condition (const_int 1). */
313 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
315 /* Placeholder for _Unwind_Resume before we know if a function call
316 or a branch is needed. Operand 1 is the exception region from
317 which control is flowing. */
318 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
320 /* ----------------------------------------------------------------------
321 Primitive values for use in expressions.
322 ---------------------------------------------------------------------- */
324 /* numeric integer constant */
325 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
327 /* numeric floating point constant.
328 Operands hold the value. They are all 'w' and there may be from 2 to 6;
330 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
332 /* Describes a vector constant. */
333 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
335 /* String constant. Used for attributes in machine descriptions and
336 for special cases in DWARF2 debug output. NOT used for source-
337 language string constants. */
338 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
340 /* This is used to encapsulate an expression whose value is constant
341 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
342 recognized as a constant operand rather than by arithmetic instructions. */
344 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
346 /* program counter. Ordinary jumps are represented
347 by a SET whose first operand is (PC). */
348 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
350 /* Used in the cselib routines to describe a value. Objects of this
351 kind are only allocated in cselib.c, in an alloc pool instead of
352 in GC memory. The only operand of a VALUE is a cselib_val_struct. */
353 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
355 /* A register. The "operand" is the register number, accessed with
356 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
357 than a hardware register is being referred to. The second operand
358 holds the original register number - this will be different for a
359 pseudo register that got turned into a hard register. The third
360 operand points to a reg_attrs structure.
361 This rtx needs to have as many (or more) fields as a MEM, since we
362 can change REG rtx's into MEMs during reload. */
363 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
365 /* A scratch register. This represents a register used only within a
366 single insn. It will be turned into a REG during register allocation
367 or reload unless the constraint indicates that the register won't be
368 needed, in which case it can remain a SCRATCH. This code is
369 marked as having one operand so it can be turned into a REG. */
370 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
372 /* One word of a multi-word value.
373 The first operand is the complete value; the second says which word.
374 The WORDS_BIG_ENDIAN flag controls whether word number 0
375 (as numbered in a SUBREG) is the most or least significant word.
377 This is also used to refer to a value in a different machine mode.
378 For example, it can be used to refer to a SImode value as if it were
379 Qimode, or vice versa. Then the word number is always 0. */
380 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
382 /* This one-argument rtx is used for move instructions
383 that are guaranteed to alter only the low part of a destination.
384 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
385 has an unspecified effect on the high part of REG,
386 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
387 is guaranteed to alter only the bits of REG that are in HImode.
389 The actual instruction used is probably the same in both cases,
390 but the register constraints may be tighter when STRICT_LOW_PART
393 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
395 /* (CONCAT a b) represents the virtual concatenation of a and b
396 to make a value that has as many bits as a and b put together.
397 This is used for complex values. Normally it appears only
398 in DECL_RTLs and during RTL generation, but not in the insn chain. */
399 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
401 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
402 all An to make a value. This is an extension of CONCAT to larger
403 number of components. Like CONCAT, it should not appear in the
404 insn chain. Every element of the CONCATN is the same size. */
405 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
407 /* A memory location; operand is the address. The second operand is the
408 alias set to which this MEM belongs. We use `0' instead of `w' for this
409 field so that the field need not be specified in machine descriptions. */
410 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
412 /* Reference to an assembler label in the code for this function.
413 The operand is a CODE_LABEL found in the insn chain. */
414 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
416 /* Reference to a named label:
417 Operand 0: label name
418 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
419 Operand 2: tree from which this symbol is derived, or null.
420 This is either a DECL node, or some kind of constant. */
421 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
423 /* The condition code register is represented, in our imagination,
424 as a register holding a value that can be compared to zero.
425 In fact, the machine has already compared them and recorded the
426 results; but instructions that look at the condition code
427 pretend to be looking at the entire value and comparing it. */
428 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
430 /* ----------------------------------------------------------------------
431 Expressions for operators in an rtl pattern
432 ---------------------------------------------------------------------- */
434 /* if_then_else. This is used in representing ordinary
435 conditional jump instructions.
440 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
442 /* Comparison, produces a condition code result. */
443 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
446 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
448 /* Operand 0 minus operand 1. */
449 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
451 /* Minus operand 0. */
452 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
454 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
456 /* Operand 0 divided by operand 1. */
457 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
458 /* Remainder of operand 0 divided by operand 1. */
459 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
461 /* Unsigned divide and remainder. */
462 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
463 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
465 /* Bitwise operations. */
466 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
467 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
468 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
469 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
472 0: value to be shifted.
473 1: number of bits. */
474 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
475 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
476 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
477 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
478 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
480 /* Minimum and maximum values of two operands. We need both signed and
481 unsigned forms. (We cannot use MIN for SMIN because it conflicts
482 with a macro of the same name.) The signed variants should be used
483 with floating point. Further, if both operands are zeros, or if either
484 operand is NaN, then it is unspecified which of the two operands is
485 returned as the result. */
487 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
488 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
489 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
490 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
492 /* These unary operations are used to represent incrementation
493 and decrementation as they occur in memory addresses.
494 The amount of increment or decrement are not represented
495 because they can be understood from the machine-mode of the
496 containing MEM. These operations exist in only two cases:
497 1. pushes onto the stack.
498 2. created automatically by the life_analysis pass in flow.c. */
499 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
500 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
501 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
502 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
504 /* These binary operations are used to represent generic address
505 side-effects in memory addresses, except for simple incrementation
506 or decrementation which use the above operations. They are
507 created automatically by the life_analysis pass in flow.c.
508 The first operand is a REG which is used as the address.
509 The second operand is an expression that is assigned to the
510 register, either before (PRE_MODIFY) or after (POST_MODIFY)
511 evaluating the address.
512 Currently, the compiler can only handle second operands of the
513 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
514 the first operand of the PLUS has to be the same register as
515 the first operand of the *_MODIFY. */
516 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
517 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
519 /* Comparison operations. The ordered comparisons exist in two
520 flavors, signed and unsigned. */
521 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
522 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
523 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
524 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
525 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
526 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
527 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
528 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
529 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
530 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
532 /* Additional floating point unordered comparison flavors. */
533 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
534 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
536 /* These are equivalent to unordered or ... */
537 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
538 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
539 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
540 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
541 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
543 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
544 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
546 /* Represents the result of sign-extending the sole operand.
547 The machine modes of the operand and of the SIGN_EXTEND expression
548 determine how much sign-extension is going on. */
549 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
551 /* Similar for zero-extension (such as unsigned short to int). */
552 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
554 /* Similar but here the operand has a wider mode. */
555 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
557 /* Similar for extending floating-point values (such as SFmode to DFmode). */
558 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
559 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
561 /* Conversion of fixed point operand to floating point value. */
562 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
564 /* With fixed-point machine mode:
565 Conversion of floating point operand to fixed point value.
566 Value is defined only when the operand's value is an integer.
567 With floating-point machine mode (and operand with same mode):
568 Operand is rounded toward zero to produce an integer value
569 represented in floating point. */
570 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
572 /* Conversion of unsigned fixed point operand to floating point value. */
573 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
575 /* With fixed-point machine mode:
576 Conversion of floating point operand to *unsigned* fixed point value.
577 Value is defined only when the operand's value is an integer. */
578 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
581 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
584 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
587 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
589 /* Find first bit that is set.
590 Value is 1 + number of trailing zeros in the arg.,
592 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
594 /* Count leading zeros. */
595 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
597 /* Count trailing zeros. */
598 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
600 /* Population count (number of 1 bits). */
601 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
603 /* Population parity (number of 1 bits modulo 2). */
604 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
606 /* Reference to a signed bit-field of specified size and position.
607 Operand 0 is the memory unit (usually SImode or QImode) which
608 contains the field's first bit. Operand 1 is the width, in bits.
609 Operand 2 is the number of bits in the memory unit before the
610 first bit of this field.
611 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
612 operand 2 counts from the msb of the memory unit.
613 Otherwise, the first bit is the lsb and operand 2 counts from
614 the lsb of the memory unit.
615 This kind of expression can not appear as an lvalue in RTL. */
616 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
618 /* Similar for unsigned bit-field.
619 But note! This kind of expression _can_ appear as an lvalue. */
620 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
622 /* For RISC machines. These save memory when splitting insns. */
624 /* HIGH are the high-order bits of a constant expression. */
625 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
627 /* LO_SUM is the sum of a register and the low-order bits
628 of a constant expression. */
629 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
631 /* Describes a merge operation between two vector values.
632 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
633 that specifies where the parts of the result are taken from. Set bits
634 indicate operand 0, clear bits indicate operand 1. The parts are defined
635 by the mode of the vectors. */
636 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
638 /* Describes an operation that selects parts of a vector.
639 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
640 a CONST_INT for each of the subparts of the result vector, giving the
641 number of the source subpart that should be stored into it. */
642 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
644 /* Describes a vector concat operation. Operands 0 and 1 are the source
645 vectors, the result is a vector that is as long as operands 0 and 1
646 combined and is the concatenation of the two source vectors. */
647 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
649 /* Describes an operation that converts a small vector into a larger one by
650 duplicating the input values. The output vector mode must have the same
651 submodes as the input vector mode, and the number of output parts must be
652 an integer multiple of the number of input parts. */
653 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
655 /* Addition with signed saturation */
656 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
658 /* Addition with unsigned saturation */
659 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
661 /* Operand 0 minus operand 1, with signed saturation. */
662 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
664 /* Negation with signed saturation. */
665 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
667 /* Absolute value with signed saturation. */
668 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
670 /* Shift left with signed saturation. */
671 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
673 /* Operand 0 minus operand 1, with unsigned saturation. */
674 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
676 /* Signed saturating truncate. */
677 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
679 /* Unsigned saturating truncate. */
680 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
682 /* Information about the variable and its location. */
683 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
685 /* All expressions from this point forward appear only in machine
687 #ifdef GENERATOR_FILE
689 /* Include a secondary machine-description file at this point. */
690 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
692 /* Pattern-matching operators: */
694 /* Use the function named by the second arg (the string)
695 as a predicate; if matched, store the structure that was matched
696 in the operand table at index specified by the first arg (the integer).
697 If the second arg is the null string, the structure is just stored.
699 A third string argument indicates to the register allocator restrictions
700 on where the operand can be allocated.
702 If the target needs no restriction on any instruction this field should
705 The string is prepended by:
706 '=' to indicate the operand is only written to.
707 '+' to indicate the operand is both read and written to.
709 Each character in the string represents an allocable class for an operand.
710 'g' indicates the operand can be any valid class.
711 'i' indicates the operand can be immediate (in the instruction) data.
712 'r' indicates the operand can be in a register.
713 'm' indicates the operand can be in memory.
714 'o' a subset of the 'm' class. Those memory addressing modes that
715 can be offset at compile time (have a constant added to them).
717 Other characters indicate target dependent operand classes and
718 are described in each target's machine description.
720 For instructions with more than one operand, sets of classes can be
721 separated by a comma to indicate the appropriate multi-operand constraints.
722 There must be a 1 to 1 correspondence between these sets of classes in
723 all operands for an instruction.
725 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
727 /* Match a SCRATCH or a register. When used to generate rtl, a
728 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
729 the desired mode and the first argument is the operand number.
730 The second argument is the constraint. */
731 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
733 /* Apply a predicate, AND match recursively the operands of the rtx.
734 Operand 0 is the operand-number, as in match_operand.
735 Operand 1 is a predicate to apply (as a string, a function name).
736 Operand 2 is a vector of expressions, each of which must match
737 one subexpression of the rtx this construct is matching. */
738 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
740 /* Match a PARALLEL of arbitrary length. The predicate is applied
741 to the PARALLEL and the initial expressions in the PARALLEL are matched.
742 Operand 0 is the operand-number, as in match_operand.
743 Operand 1 is a predicate to apply to the PARALLEL.
744 Operand 2 is a vector of expressions, each of which must match the
745 corresponding element in the PARALLEL. */
746 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
748 /* Match only something equal to what is stored in the operand table
749 at the index specified by the argument. Use with MATCH_OPERAND. */
750 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
752 /* Match only something equal to what is stored in the operand table
753 at the index specified by the argument. Use with MATCH_OPERATOR. */
754 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
756 /* Match only something equal to what is stored in the operand table
757 at the index specified by the argument. Use with MATCH_PARALLEL. */
758 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
760 /* Appears only in define_predicate/define_special_predicate
761 expressions. Evaluates true only if the operand has an RTX code
762 from the set given by the argument (a comma-separated list). If the
763 second argument is present and nonempty, it is a sequence of digits
764 and/or letters which indicates the subexpression to test, using the
765 same syntax as genextract/genrecog's location strings: 0-9 for
766 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
767 the result of the one before it. */
768 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
770 /* Appears only in define_predicate/define_special_predicate
771 expressions. The argument is a C expression to be injected at this
772 point in the predicate formula. */
773 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
775 /* Insn (and related) definitions. */
777 /* Definition of the pattern for one kind of instruction.
779 0: names this instruction.
780 If the name is the null string, the instruction is in the
781 machine description just to be recognized, and will never be emitted by
782 the tree to rtl expander.
784 2: is a string which is a C expression
785 giving an additional condition for recognizing this pattern.
786 A null string means no extra condition.
787 3: is the action to execute if this pattern is matched.
788 If this assembler code template starts with a * then it is a fragment of
789 C code to run to decide on a template to use. Otherwise, it is the
791 4: optionally, a vector of attributes for this insn.
793 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
795 /* Definition of a peephole optimization.
796 1st operand: vector of insn patterns to match
797 2nd operand: C expression that must be true
798 3rd operand: template or C code to produce assembler output.
799 4: optionally, a vector of attributes for this insn.
801 This form is deprecated; use define_peephole2 instead. */
802 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
804 /* Definition of a split operation.
805 1st operand: insn pattern to match
806 2nd operand: C expression that must be true
807 3rd operand: vector of insn patterns to place into a SEQUENCE
808 4th operand: optionally, some C code to execute before generating the
809 insns. This might, for example, create some RTX's and store them in
810 elements of `recog_data.operand' for use by the vector of
812 (`operands' is an alias here for `recog_data.operand'). */
813 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
815 /* Definition of an insn and associated split.
816 This is the concatenation, with a few modifications, of a define_insn
817 and a define_split which share the same pattern.
819 0: names this instruction.
820 If the name is the null string, the instruction is in the
821 machine description just to be recognized, and will never be emitted by
822 the tree to rtl expander.
824 2: is a string which is a C expression
825 giving an additional condition for recognizing this pattern.
826 A null string means no extra condition.
827 3: is the action to execute if this pattern is matched.
828 If this assembler code template starts with a * then it is a fragment of
829 C code to run to decide on a template to use. Otherwise, it is the
831 4: C expression that must be true for split. This may start with "&&"
832 in which case the split condition is the logical and of the insn
833 condition and what follows the "&&" of this operand.
834 5: vector of insn patterns to place into a SEQUENCE
835 6: optionally, some C code to execute before generating the
836 insns. This might, for example, create some RTX's and store them in
837 elements of `recog_data.operand' for use by the vector of
839 (`operands' is an alias here for `recog_data.operand').
840 7: optionally, a vector of attributes for this insn. */
841 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
843 /* Definition of an RTL peephole operation.
844 Follows the same arguments as define_split. */
845 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
847 /* Define how to generate multiple insns for a standard insn name.
848 1st operand: the insn name.
849 2nd operand: vector of insn-patterns.
850 Use match_operand to substitute an element of `recog_data.operand'.
851 3rd operand: C expression that must be true for this to be available.
852 This may not test any operands.
853 4th operand: Extra C code to execute before generating the insns.
854 This might, for example, create some RTX's and store them in
855 elements of `recog_data.operand' for use by the vector of
857 (`operands' is an alias here for `recog_data.operand'). */
858 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
860 /* Define a requirement for delay slots.
861 1st operand: Condition involving insn attributes that, if true,
862 indicates that the insn requires the number of delay slots
864 2nd operand: Vector whose length is the three times the number of delay
866 Each entry gives three conditions, each involving attributes.
867 The first must be true for an insn to occupy that delay slot
868 location. The second is true for all insns that can be
869 annulled if the branch is true and the third is true for all
870 insns that can be annulled if the branch is false.
872 Multiple DEFINE_DELAYs may be present. They indicate differing
873 requirements for delay slots. */
874 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
876 /* Define attribute computation for `asm' instructions. */
877 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
879 /* Definition of a conditional execution meta operation. Automatically
880 generates new instances of DEFINE_INSN, selected by having attribute
881 "predicable" true. The new pattern will contain a COND_EXEC and the
882 predicate at top-level.
885 0: The predicate pattern. The top-level form should match a
886 relational operator. Operands should have only one alternative.
887 1: A C expression giving an additional condition for recognizing
888 the generated pattern.
889 2: A template or C code to produce assembler output. */
890 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
892 /* Definition of an operand predicate. The difference between
893 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
894 not warn about a match_operand with no mode if it has a predicate
895 defined with DEFINE_SPECIAL_PREDICATE.
898 0: The name of the predicate.
899 1: A boolean expression which computes whether or not the predicate
900 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
901 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
902 can calculate the set of RTX codes that can possibly match.
903 2: A C function body which must return true for the predicate to match.
904 Optional. Use this when the test is too complicated to fit into a
905 match_test expression. */
906 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
907 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
909 /* Definition of a register operand constraint. This simply maps the
910 constraint string to a register class.
913 0: The name of the constraint (often, but not always, a single letter).
914 1: A C expression which evaluates to the appropriate register class for
915 this constraint. If this is not just a constant, it should look only
916 at -m switches and the like.
917 2: A docstring for this constraint, in Texinfo syntax; not currently
918 used, in future will be incorporated into the manual's list of
919 machine-specific operand constraints. */
920 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
922 /* Definition of a non-register operand constraint. These look at the
923 operand and decide whether it fits the constraint.
925 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
926 It is appropriate for constant-only constraints, and most others.
928 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
929 to match, if it doesn't already, by converting the operand to the form
930 (mem (reg X)) where X is a base register. It is suitable for constraints
931 that describe a subset of all memory references.
933 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
934 to match, if it doesn't already, by converting the operand to the form
935 (reg X) where X is a base register. It is suitable for constraints that
936 describe a subset of all address references.
938 When in doubt, use plain DEFINE_CONSTRAINT.
941 0: The name of the constraint (often, but not always, a single letter).
942 1: A docstring for this constraint, in Texinfo syntax; not currently
943 used, in future will be incorporated into the manual's list of
944 machine-specific operand constraints.
945 2: A boolean expression which computes whether or not the constraint
946 matches. It should follow the same rules as a define_predicate
947 expression, including the bit about specifying the set of RTX codes
948 that could possibly match. MATCH_TEST subexpressions may make use of
950 `op' - the RTL object defining the operand.
951 `mode' - the mode of `op'.
952 `ival' - INTVAL(op), if op is a CONST_INT.
953 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
954 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
955 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
957 Do not use ival/hval/lval/rval if op is not the appropriate kind of
959 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
960 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
961 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
964 /* Constructions for CPU pipeline description described by NDFAs. */
966 /* (define_cpu_unit string [string]) describes cpu functional
967 units (separated by comma).
969 1st operand: Names of cpu functional units.
970 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
972 All define_reservations, define_cpu_units, and
973 define_query_cpu_units should have unique names which may not be
975 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
977 /* (define_query_cpu_unit string [string]) describes cpu functional
978 units analogously to define_cpu_unit. The reservation of such
979 units can be queried for automaton state. */
980 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
982 /* (exclusion_set string string) means that each CPU functional unit
983 in the first string can not be reserved simultaneously with any
984 unit whose name is in the second string and vise versa. CPU units
985 in the string are separated by commas. For example, it is useful
986 for description CPU with fully pipelined floating point functional
987 unit which can execute simultaneously only single floating point
988 insns or only double floating point insns. All CPU functional
989 units in a set should belong to the same automaton. */
990 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
992 /* (presence_set string string) means that each CPU functional unit in
993 the first string can not be reserved unless at least one of pattern
994 of units whose names are in the second string is reserved. This is
995 an asymmetric relation. CPU units or unit patterns in the strings
996 are separated by commas. Pattern is one unit name or unit names
997 separated by white-spaces.
999 For example, it is useful for description that slot1 is reserved
1000 after slot0 reservation for a VLIW processor. We could describe it
1001 by the following construction
1003 (presence_set "slot1" "slot0")
1005 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1006 this case we could write
1008 (presence_set "slot1" "slot0 b0")
1010 All CPU functional units in a set should belong to the same
1012 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1014 /* (final_presence_set string string) is analogous to `presence_set'.
1015 The difference between them is when checking is done. When an
1016 instruction is issued in given automaton state reflecting all
1017 current and planned unit reservations, the automaton state is
1018 changed. The first state is a source state, the second one is a
1019 result state. Checking for `presence_set' is done on the source
1020 state reservation, checking for `final_presence_set' is done on the
1021 result reservation. This construction is useful to describe a
1022 reservation which is actually two subsequent reservations. For
1025 (presence_set "slot1" "slot0")
1027 the following insn will be never issued (because slot1 requires
1028 slot0 which is absent in the source state).
1030 (define_reservation "insn_and_nop" "slot0 + slot1")
1032 but it can be issued if we use analogous `final_presence_set'. */
1033 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1035 /* (absence_set string string) means that each CPU functional unit in
1036 the first string can be reserved only if each pattern of units
1037 whose names are in the second string is not reserved. This is an
1038 asymmetric relation (actually exclusion set is analogous to this
1039 one but it is symmetric). CPU units or unit patterns in the string
1040 are separated by commas. Pattern is one unit name or unit names
1041 separated by white-spaces.
1043 For example, it is useful for description that slot0 can not be
1044 reserved after slot1 or slot2 reservation for a VLIW processor. We
1045 could describe it by the following construction
1047 (absence_set "slot2" "slot0, slot1")
1049 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1050 slot1 and unit b1 are reserved . In this case we could write
1052 (absence_set "slot2" "slot0 b0, slot1 b1")
1054 All CPU functional units in a set should to belong the same
1056 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1058 /* (final_absence_set string string) is analogous to `absence_set' but
1059 checking is done on the result (state) reservation. See comments
1060 for `final_presence_set'. */
1061 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1063 /* (define_bypass number out_insn_names in_insn_names) names bypass
1064 with given latency (the first number) from insns given by the first
1065 string (see define_insn_reservation) into insns given by the second
1066 string. Insn names in the strings are separated by commas. The
1067 third operand is optional name of function which is additional
1068 guard for the bypass. The function will get the two insns as
1069 parameters. If the function returns zero the bypass will be
1070 ignored for this case. Additional guard is necessary to recognize
1071 complicated bypasses, e.g. when consumer is load address. */
1072 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1074 /* (define_automaton string) describes names of automata generated and
1075 used for pipeline hazards recognition. The names are separated by
1076 comma. Actually it is possibly to generate the single automaton
1077 but unfortunately it can be very large. If we use more one
1078 automata, the summary size of the automata usually is less than the
1079 single one. The automaton name is used in define_cpu_unit and
1080 define_query_cpu_unit. All automata should have unique names. */
1081 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1083 /* (automata_option string) describes option for generation of
1084 automata. Currently there are the following options:
1086 o "no-minimization" which makes no minimization of automata. This
1087 is only worth to do when we are debugging the description and
1088 need to look more accurately at reservations of states.
1090 o "time" which means printing additional time statistics about
1091 generation of automata.
1093 o "v" which means generation of file describing the result
1094 automata. The file has suffix `.dfa' and can be used for the
1095 description verification and debugging.
1097 o "w" which means generation of warning instead of error for
1098 non-critical errors.
1100 o "ndfa" which makes nondeterministic finite state automata.
1102 o "progress" which means output of a progress bar showing how many
1103 states were generated so far for automaton being processed. */
1104 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1106 /* (define_reservation string string) names reservation (the first
1107 string) of cpu functional units (the 2nd string). Sometimes unit
1108 reservations for different insns contain common parts. In such
1109 case, you can describe common part and use its name (the 1st
1110 parameter) in regular expression in define_insn_reservation. All
1111 define_reservations, define_cpu_units, and define_query_cpu_units
1112 should have unique names which may not be "nothing". */
1113 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1115 /* (define_insn_reservation name default_latency condition regexpr)
1116 describes reservation of cpu functional units (the 3nd operand) for
1117 instruction which is selected by the condition (the 2nd parameter).
1118 The first parameter is used for output of debugging information.
1119 The reservations are described by a regular expression according
1120 the following syntax:
1122 regexp = regexp "," oneof
1125 oneof = oneof "|" allof
1128 allof = allof "+" repeat
1131 repeat = element "*" number
1134 element = cpu_function_unit_name
1140 1. "," is used for describing start of the next cycle in
1143 2. "|" is used for describing the reservation described by the
1144 first regular expression *or* the reservation described by the
1145 second regular expression *or* etc.
1147 3. "+" is used for describing the reservation described by the
1148 first regular expression *and* the reservation described by the
1149 second regular expression *and* etc.
1151 4. "*" is used for convenience and simply means sequence in
1152 which the regular expression are repeated NUMBER times with
1153 cycle advancing (see ",").
1155 5. cpu functional unit name which means its reservation.
1157 6. reservation name -- see define_reservation.
1159 7. string "nothing" means no units reservation. */
1161 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1163 /* Expressions used for insn attributes. */
1165 /* Definition of an insn attribute.
1166 1st operand: name of the attribute
1167 2nd operand: comma-separated list of possible attribute values
1168 3rd operand: expression for the default value of the attribute. */
1169 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1171 /* Marker for the name of an attribute. */
1172 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1174 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1175 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1178 (set_attr "name" "value") is equivalent to
1179 (set (attr "name") (const_string "value")) */
1180 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1182 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1183 specify that attribute values are to be assigned according to the
1184 alternative matched.
1186 The following three expressions are equivalent:
1188 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1189 (eq_attrq "alternative" "2") (const_string "a2")]
1190 (const_string "a3")))
1191 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1192 (const_string "a3")])
1193 (set_attr "att" "a1,a2,a3")
1195 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1197 /* A conditional expression true if the value of the specified attribute of
1198 the current insn equals the specified value. The first operand is the
1199 attribute name and the second is the comparison value. */
1200 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1202 /* A special case of the above representing a set of alternatives. The first
1203 operand is bitmap of the set, the second one is the default value. */
1204 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1206 /* A conditional expression which is true if the specified flag is
1207 true for the insn being scheduled in reorg.
1209 genattr.c defines the following flags which can be tested by
1210 (attr_flag "foo") expressions in eligible_for_delay.
1212 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1214 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1216 /* General conditional. The first operand is a vector composed of pairs of
1217 expressions. The first element of each pair is evaluated, in turn.
1218 The value of the conditional is the second expression of the first pair
1219 whose first expression evaluates nonzero. If none of the expressions is
1220 true, the second operand will be used as the value of the conditional. */
1221 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1223 #endif /* GENERATOR_FILE */
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