1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
50 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
59 "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
64 /* ---------------------------------------------------------------------
65 Expressions (and "meta" expressions) used for structuring the
66 rtl representation of a program.
67 --------------------------------------------------------------------- */
69 /* an expression code name unknown to the reader */
70 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
72 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
74 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
79 DEF_RTL_EXPR(INCLUDE, "include", "s", 'x')
81 /* ---------------------------------------------------------------------
82 Expressions used in constructing lists.
83 --------------------------------------------------------------------- */
85 /* a linked list of expressions */
86 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
88 /* a linked list of instructions.
89 The insns are represented in print by their uids. */
90 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
92 /* ----------------------------------------------------------------------
93 Expression types for machine descriptions.
94 These do not appear in actual rtl code in the compiler.
95 ---------------------------------------------------------------------- */
97 /* Appears only in machine descriptions.
98 Means use the function named by the second arg (the string)
99 as a predicate; if matched, store the structure that was matched
100 in the operand table at index specified by the first arg (the integer).
101 If the second arg is the null string, the structure is just stored.
103 A third string argument indicates to the register allocator restrictions
104 on where the operand can be allocated.
106 If the target needs no restriction on any instruction this field should
109 The string is prepended by:
110 '=' to indicate the operand is only written to.
111 '+' to indicate the operand is both read and written to.
113 Each character in the string represents an allocable class for an operand.
114 'g' indicates the operand can be any valid class.
115 'i' indicates the operand can be immediate (in the instruction) data.
116 'r' indicates the operand can be in a register.
117 'm' indicates the operand can be in memory.
118 'o' a subset of the 'm' class. Those memory addressing modes that
119 can be offset at compile time (have a constant added to them).
121 Other characters indicate target dependent operand classes and
122 are described in each target's machine description.
124 For instructions with more than one operand, sets of classes can be
125 separated by a comma to indicate the appropriate multi-operand constraints.
126 There must be a 1 to 1 correspondence between these sets of classes in
127 all operands for an instruction.
129 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
131 /* Appears only in machine descriptions.
132 Means match a SCRATCH or a register. When used to generate rtl, a
133 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
134 the desired mode and the first argument is the operand number.
135 The second argument is the constraint. */
136 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
138 /* Appears only in machine descriptions.
139 Means match only something equal to what is stored in the operand table
140 at the index specified by the argument. */
141 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
143 /* Appears only in machine descriptions.
144 Means apply a predicate, AND match recursively the operands of the rtx.
145 Operand 0 is the operand-number, as in match_operand.
146 Operand 1 is a predicate to apply (as a string, a function name).
147 Operand 2 is a vector of expressions, each of which must match
148 one subexpression of the rtx this construct is matching. */
149 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
151 /* Appears only in machine descriptions.
152 Means to match a PARALLEL of arbitrary length. The predicate is applied
153 to the PARALLEL and the initial expressions in the PARALLEL are matched.
154 Operand 0 is the operand-number, as in match_operand.
155 Operand 1 is a predicate to apply to the PARALLEL.
156 Operand 2 is a vector of expressions, each of which must match the
157 corresponding element in the PARALLEL. */
158 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
160 /* Appears only in machine descriptions.
161 Means match only something equal to what is stored in the operand table
162 at the index specified by the argument. For MATCH_OPERATOR. */
163 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
165 /* Appears only in machine descriptions.
166 Means match only something equal to what is stored in the operand table
167 at the index specified by the argument. For MATCH_PARALLEL. */
168 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
170 /* Appears only in machine descriptions.
171 Operand 0 is the operand number, as in match_operand.
172 Operand 1 is the predicate to apply to the insn. */
173 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
175 /* Appears only in machine descriptions.
176 Defines the pattern for one kind of instruction.
178 0: names this instruction.
179 If the name is the null string, the instruction is in the
180 machine description just to be recognized, and will never be emitted by
181 the tree to rtl expander.
183 2: is a string which is a C expression
184 giving an additional condition for recognizing this pattern.
185 A null string means no extra condition.
186 3: is the action to execute if this pattern is matched.
187 If this assembler code template starts with a * then it is a fragment of
188 C code to run to decide on a template to use. Otherwise, it is the
190 4: optionally, a vector of attributes for this insn.
192 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x')
194 /* Definition of a peephole optimization.
195 1st operand: vector of insn patterns to match
196 2nd operand: C expression that must be true
197 3rd operand: template or C code to produce assembler output.
198 4: optionally, a vector of attributes for this insn.
200 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x')
202 /* Definition of a split operation.
203 1st operand: insn pattern to match
204 2nd operand: C expression that must be true
205 3rd operand: vector of insn patterns to place into a SEQUENCE
206 4th operand: optionally, some C code to execute before generating the
207 insns. This might, for example, create some RTX's and store them in
208 elements of `recog_data.operand' for use by the vector of
210 (`operands' is an alias here for `recog_data.operand'). */
211 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
213 /* Definition of an insn and associated split.
214 This is the concatenation, with a few modifications, of a define_insn
215 and a define_split which share the same pattern.
217 0: names this instruction.
218 If the name is the null string, the instruction is in the
219 machine description just to be recognized, and will never be emitted by
220 the tree to rtl expander.
222 2: is a string which is a C expression
223 giving an additional condition for recognizing this pattern.
224 A null string means no extra condition.
225 3: is the action to execute if this pattern is matched.
226 If this assembler code template starts with a * then it is a fragment of
227 C code to run to decide on a template to use. Otherwise, it is the
229 4: C expression that must be true for split. This may start with "&&"
230 in which case the split condition is the logical and of the insn
231 condition and what follows the "&&" of this operand.
232 5: vector of insn patterns to place into a SEQUENCE
233 6: optionally, some C code to execute before generating the
234 insns. This might, for example, create some RTX's and store them in
235 elements of `recog_data.operand' for use by the vector of
237 (`operands' is an alias here for `recog_data.operand').
238 7: optionally, a vector of attributes for this insn. */
239 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x')
241 /* Definition of an RTL peephole operation.
242 Follows the same arguments as define_split. */
243 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
245 /* Definition of a combiner pattern.
246 Operands not defined yet. */
247 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
249 /* Define how to generate multiple insns for a standard insn name.
250 1st operand: the insn name.
251 2nd operand: vector of insn-patterns.
252 Use match_operand to substitute an element of `recog_data.operand'.
253 3rd operand: C expression that must be true for this to be available.
254 This may not test any operands.
255 4th operand: Extra C code to execute before generating the insns.
256 This might, for example, create some RTX's and store them in
257 elements of `recog_data.operand' for use by the vector of
259 (`operands' is an alias here for `recog_data.operand'). */
260 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
262 /* Define a requirement for delay slots.
263 1st operand: Condition involving insn attributes that, if true,
264 indicates that the insn requires the number of delay slots
266 2nd operand: Vector whose length is the three times the number of delay
268 Each entry gives three conditions, each involving attributes.
269 The first must be true for an insn to occupy that delay slot
270 location. The second is true for all insns that can be
271 annulled if the branch is true and the third is true for all
272 insns that can be annulled if the branch is false.
274 Multiple DEFINE_DELAYs may be present. They indicate differing
275 requirements for delay slots. */
276 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
278 /* Define a set of insns that requires a function unit. This means that
279 these insns produce their result after a delay and that there may be
280 restrictions on the number of insns of this type that can be scheduled
283 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
284 Each gives a set of operations and associated delays. The first three
285 operands must be the same for each operation for the same function unit.
287 All delays are specified in cycles.
289 1st operand: Name of function unit (mostly for documentation)
290 2nd operand: Number of identical function units in CPU
291 3rd operand: Total number of simultaneous insns that can execute on this
292 function unit; 0 if unlimited.
293 4th operand: Condition involving insn attribute, that, if true, specifies
294 those insns that this expression applies to.
295 5th operand: Constant delay after which insn result will be
297 6th operand: Delay until next insn can be scheduled on the function unit
298 executing this operation. The meaning depends on whether or
299 not the next operand is supplied.
300 7th operand: If this operand is not specified, the 6th operand gives the
301 number of cycles after the instruction matching the 4th
302 operand begins using the function unit until a subsequent
303 insn can begin. A value of zero should be used for a
304 unit with no issue constraints. If only one operation can
305 be executed a time and the unit is busy for the entire time,
306 the 3rd operand should be specified as 1, the 6th operand
307 should be specified as 0, and the 7th operand should not
310 If this operand is specified, it is a list of attribute
311 expressions. If an insn for which any of these expressions
312 is true is currently executing on the function unit, the
313 issue delay will be given by the 6th operand. Otherwise,
314 the insn can be immediately scheduled (subject to the limit
315 on the number of simultaneous operations executing on the
317 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
319 /* Define attribute computation for `asm' instructions. */
320 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
322 /* Definition of a conditional execution meta operation. Automatically
323 generates new instances of DEFINE_INSN, selected by having attribute
324 "predicable" true. The new pattern will contain a COND_EXEC and the
325 predicate at top-level.
328 0: The predicate pattern. The top-level form should match a
329 relational operator. Operands should have only one alternative.
330 1: A C expression giving an additional condition for recognizing
331 the generated pattern.
332 2: A template or C code to produce assembler output. */
333 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
335 /* SEQUENCE appears in the result of a `gen_...' function
336 for a DEFINE_EXPAND that wants to make several insns.
337 Its elements are the bodies of the insns that should be made.
338 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
339 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
341 /* Refers to the address of its argument. This is only used in alias.c. */
342 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
344 /* ----------------------------------------------------------------------
345 Constructions for CPU pipeline description described by NDFAs.
346 These do not appear in actual rtl code in the compiler.
347 ---------------------------------------------------------------------- */
349 /* (define_cpu_unit string [string]) describes cpu functional
350 units (separated by comma).
352 1st operand: Names of cpu functional units.
353 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
355 All define_reservations, define_cpu_units, and
356 define_query_cpu_units should have unique names which may not be
358 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x')
360 /* (define_query_cpu_unit string [string]) describes cpu functional
361 units analogously to define_cpu_unit. The reservation of such
362 units can be queried for automaton state. */
363 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x')
365 /* (exclusion_set string string) means that each CPU functional unit
366 in the first string can not be reserved simultaneously with any
367 unit whose name is in the second string and vise versa. CPU units
368 in the string are separated by commas. For example, it is useful
369 for description CPU with fully pipelined floating point functional
370 unit which can execute simultaneously only single floating point
371 insns or only double floating point insns. All CPU functional
372 units in a set should belong to the same automaton. */
373 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x')
375 /* (presence_set string string) means that each CPU functional unit in
376 the first string can not be reserved unless at least one of pattern
377 of units whose names are in the second string is reserved. This is
378 an asymmetric relation. CPU units or unit patterns in the strings
379 are separated by commas. Pattern is one unit name or unit names
380 separated by white-spaces.
382 For example, it is useful for description that slot1 is reserved
383 after slot0 reservation for a VLIW processor. We could describe it
384 by the following construction
386 (presence_set "slot1" "slot0")
388 Or slot1 is reserved only after slot0 and unit b0 reservation. In
389 this case we could write
391 (presence_set "slot1" "slot0 b0")
393 All CPU functional units in a set should belong to the same
395 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x')
397 /* (final_presence_set string string) is analogous to `presence_set'.
398 The difference between them is when checking is done. When an
399 instruction is issued in given automaton state reflecting all
400 current and planned unit reservations, the automaton state is
401 changed. The first state is a source state, the second one is a
402 result state. Checking for `presence_set' is done on the source
403 state reservation, checking for `final_presence_set' is done on the
404 result reservation. This construction is useful to describe a
405 reservation which is actually two subsequent reservations. For
408 (presence_set "slot1" "slot0")
410 the following insn will be never issued (because slot1 requires
411 slot0 which is absent in the source state).
413 (define_reservation "insn_and_nop" "slot0 + slot1")
415 but it can be issued if we use analogous `final_presence_set'. */
416 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", 'x')
418 /* (absence_set string string) means that each CPU functional unit in
419 the first string can be reserved only if each pattern of units
420 whose names are in the second string is not reserved. This is an
421 asymmetric relation (actually exclusion set is analogous to this
422 one but it is symmetric). CPU units or unit patterns in the string
423 are separated by commas. Pattern is one unit name or unit names
424 separated by white-spaces.
426 For example, it is useful for description that slot0 can not be
427 reserved after slot1 or slot2 reservation for a VLIW processor. We
428 could describe it by the following construction
430 (absence_set "slot2" "slot0, slot1")
432 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
433 slot1 and unit b1 are reserved . In this case we could write
435 (absence_set "slot2" "slot0 b0, slot1 b1")
437 All CPU functional units in a set should to belong the same
439 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x')
441 /* (final_absence_set string string) is analogous to `absence_set' but
442 checking is done on the result (state) reservation. See comments
443 for `final_presence_set'. */
444 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", 'x')
446 /* (define_bypass number out_insn_names in_insn_names) names bypass
447 with given latency (the first number) from insns given by the first
448 string (see define_insn_reservation) into insns given by the second
449 string. Insn names in the strings are separated by commas. The
450 third operand is optional name of function which is additional
451 guard for the bypass. The function will get the two insns as
452 parameters. If the function returns zero the bypass will be
453 ignored for this case. Additional guard is necessary to recognize
454 complicated bypasses, e.g. when consumer is load address. */
455 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", 'x')
457 /* (define_automaton string) describes names of automata generated and
458 used for pipeline hazards recognition. The names are separated by
459 comma. Actually it is possibly to generate the single automaton
460 but unfortunately it can be very large. If we use more one
461 automata, the summary size of the automata usually is less than the
462 single one. The automaton name is used in define_cpu_unit and
463 define_query_cpu_unit. All automata should have unique names. */
464 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", 'x')
466 /* (automata_option string) describes option for generation of
467 automata. Currently there are the following options:
469 o "no-minimization" which makes no minimization of automata. This
470 is only worth to do when we are debugging the description and
471 need to look more accurately at reservations of states.
473 o "time" which means printing additional time statistics about
474 generation of automata.
476 o "v" which means generation of file describing the result
477 automata. The file has suffix `.dfa' and can be used for the
478 description verification and debugging.
480 o "w" which means generation of warning instead of error for
483 o "ndfa" which makes nondeterministic finite state automata. */
484 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", 'x')
486 /* (define_reservation string string) names reservation (the first
487 string) of cpu functional units (the 2nd string). Sometimes unit
488 reservations for different insns contain common parts. In such
489 case, you can describe common part and use its name (the 1st
490 parameter) in regular expression in define_insn_reservation. All
491 define_reservations, define_cpu_units, and define_query_cpu_units
492 should have unique names which may not be "nothing". */
493 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", 'x')
495 /* (define_insn_reservation name default_latency condition regexpr)
496 describes reservation of cpu functional units (the 3nd operand) for
497 instruction which is selected by the condition (the 2nd parameter).
498 The first parameter is used for output of debugging information.
499 The reservations are described by a regular expression according
500 the following syntax:
502 regexp = regexp "," oneof
505 oneof = oneof "|" allof
508 allof = allof "+" repeat
511 repeat = element "*" number
514 element = cpu_function_unit_name
520 1. "," is used for describing start of the next cycle in
523 2. "|" is used for describing the reservation described by the
524 first regular expression *or* the reservation described by the
525 second regular expression *or* etc.
527 3. "+" is used for describing the reservation described by the
528 first regular expression *and* the reservation described by the
529 second regular expression *and* etc.
531 4. "*" is used for convinience and simply means sequence in
532 which the regular expression are repeated NUMBER times with
533 cycle advancing (see ",").
535 5. cpu functional unit name which means its reservation.
537 6. reservation name -- see define_reservation.
539 7. string "nothing" means no units reservation. */
541 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", 'x')
543 /* ----------------------------------------------------------------------
544 Expressions used for insn attributes. These also do not appear in
545 actual rtl code in the compiler.
546 ---------------------------------------------------------------------- */
548 /* Definition of an insn attribute.
549 1st operand: name of the attribute
550 2nd operand: comma-separated list of possible attribute values
551 3rd operand: expression for the default value of the attribute. */
552 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
554 /* Marker for the name of an attribute. */
555 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
557 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
558 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
561 (set_attr "name" "value") is equivalent to
562 (set (attr "name") (const_string "value")) */
563 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
565 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
566 specify that attribute values are to be assigned according to the
569 The following three expressions are equivalent:
571 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
572 (eq_attrq "alternative" "2") (const_string "a2")]
573 (const_string "a3")))
574 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
575 (const_string "a3")])
576 (set_attr "att" "a1,a2,a3")
578 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
580 /* A conditional expression true if the value of the specified attribute of
581 the current insn equals the specified value. The first operand is the
582 attribute name and the second is the comparison value. */
583 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
585 /* A conditional expression which is true if the specified flag is
586 true for the insn being scheduled in reorg.
588 genattr.c defines the following flags which can be tested by
589 (attr_flag "foo") expressions in eligible_for_delay.
591 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
593 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
595 /* ----------------------------------------------------------------------
596 Expression types used for things in the instruction chain.
598 All formats must start with "iuu" to handle the chain.
599 Each insn expression holds an rtl instruction and its semantics
600 during back-end processing.
601 See macros's in "rtl.h" for the meaning of each rtx->fld[].
603 ---------------------------------------------------------------------- */
605 /* An instruction that cannot jump. */
606 DEF_RTL_EXPR(INSN, "insn", "iuuBteiee", 'i')
608 /* An instruction that can possibly jump.
609 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
610 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBteiee0", 'i')
612 /* An instruction that can possibly call a subroutine
613 but which will not change which instruction comes next
614 in the current function.
615 Field ( rtx->fld[9] ) is CALL_INSN_FUNCTION_USAGE.
616 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
617 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBteieee", 'i')
619 /* A marker that indicates that control will not flow through. */
620 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", 'x')
622 /* Holds a label that is followed by instructions.
624 5: is used in jump.c for the use-count of the label.
625 6: is used in flow.c to point to the chain of label_ref's to this label.
626 7: is a number that is unique in the entire compilation.
627 8: is the user-given name of the label, if any. */
628 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", 'x')
630 /* Say where in the code a source line starts, for symbol table's sake.
632 5: filename, if line number > 0, note-specific data otherwise.
633 6: line number if > 0, enum note_insn otherwise.
634 7: unique number if line number == note_insn_deleted_label.
635 8-9: padding so that notes and insns are the same size, and thus
636 allocated from the same page ordering. */
637 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni00", 'x')
639 /* ----------------------------------------------------------------------
640 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
641 ---------------------------------------------------------------------- */
643 /* Conditionally execute code.
644 Operand 0 is the condition that if true, the code is executed.
645 Operand 1 is the code to be executed (typically a SET).
647 Semantics are that there are no side effects if the condition
648 is false. This pattern is created automatically by the if_convert
649 pass run after reload or by target-specific splitters. */
650 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
652 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
653 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
655 /* A string that is passed through to the assembler as input.
656 One can obviously pass comments through by using the
657 assembler comment syntax.
658 These occur in an insn all by themselves as the PATTERN.
659 They also appear inside an ASM_OPERANDS
660 as a convenient way to hold a string. */
661 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
663 /* An assembler instruction with operands.
664 1st operand is the instruction template.
665 2nd operand is the constraint for the output.
666 3rd operand is the number of the output this expression refers to.
667 When an insn stores more than one value, a separate ASM_OPERANDS
668 is made for each output; this integer distinguishes them.
669 4th is a vector of values of input operands.
670 5th is a vector of modes and constraints for the input operands.
671 Each element is an ASM_INPUT containing a constraint string
672 and whose mode indicates the mode of the input operand.
673 6th is the name of the containing source file.
674 7th is the source line number. */
675 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
677 /* A machine-specific operation.
678 1st operand is a vector of operands being used by the operation so that
679 any needed reloads can be done.
680 2nd operand is a unique value saying which of a number of machine-specific
681 operations is to be performed.
682 (Note that the vector must be the first operand because of the way that
683 genrecog.c record positions within an insn.)
684 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
685 or inside an expression. */
686 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
688 /* Similar, but a volatile operation and one which may trap. */
689 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
691 /* Vector of addresses, stored as full words. */
692 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
693 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
695 /* Vector of address differences X0 - BASE, X1 - BASE, ...
696 First operand is BASE; the vector contains the X's.
697 The machine mode of this rtx says how much space to leave
698 for each difference and is adjusted by branch shortening if
699 CASE_VECTOR_SHORTEN_MODE is defined.
700 The third and fourth operands store the target labels with the
701 minimum and maximum addresses respectively.
702 The fifth operand stores flags for use by branch shortening.
703 Set at the start of shorten_branches:
704 min_align: the minimum alignment for any of the target labels.
705 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
706 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
707 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
708 min_after_base: true iff minimum address target label is after BASE.
709 max_after_base: true iff maximum address target label is after BASE.
710 Set by the actual branch shortening process:
711 offset_unsigned: true iff offsets have to be treated as unsigned.
712 scale: scaling that is necessary to make offsets fit into the mode.
714 The third, fourth and fifth operands are only valid when
715 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
718 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
720 /* Memory prefetch, with attributes supported on some targets.
721 Operand 1 is the address of the memory to fetch.
722 Operand 2 is 1 for a write access, 0 otherwise.
723 Operand 3 is the level of temporal locality; 0 means there is no
724 temporal locality and 1, 2, and 3 are for increasing levels of temporal
727 The attributes specified by operands 2 and 3 are ignored for targets
728 whose prefetch instructions do not support them. */
729 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x')
731 /* ----------------------------------------------------------------------
732 At the top level of an instruction (perhaps under PARALLEL).
733 ---------------------------------------------------------------------- */
736 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
737 Operand 2 is the value stored there.
738 ALL assignment must use SET.
739 Instructions that do multiple assignments must use multiple SET,
741 DEF_RTL_EXPR(SET, "set", "ee", 'x')
743 /* Indicate something is used in a way that we don't want to explain.
744 For example, subroutine calls will use the register
745 in which the static chain is passed. */
746 DEF_RTL_EXPR(USE, "use", "e", 'x')
748 /* Indicate something is clobbered in a way that we don't want to explain.
749 For example, subroutine calls will clobber some physical registers
750 (the ones that are by convention not saved). */
751 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
753 /* Call a subroutine.
754 Operand 1 is the address to call.
755 Operand 2 is the number of arguments. */
757 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
759 /* Return from a subroutine. */
761 DEF_RTL_EXPR(RETURN, "return", "", 'x')
764 Operand 1 is the condition.
765 Operand 2 is the trap code.
766 For an unconditional trap, make the condition (const_int 1). */
767 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
769 /* Placeholder for _Unwind_Resume before we know if a function call
770 or a branch is needed. Operand 1 is the exception region from
771 which control is flowing. */
772 DEF_RTL_EXPR(RESX, "resx", "i", 'x')
774 /* ----------------------------------------------------------------------
775 Primitive values for use in expressions.
776 ---------------------------------------------------------------------- */
778 /* numeric integer constant */
779 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
781 /* numeric floating point constant.
782 Operand 0 ('0') is a chain of all CONST_DOUBLEs in use in the
784 Remaining operands hold the actual value. They are all 'w' and
785 there may be from 1 to 4; see rtl.c. */
786 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
788 /* Describes a vector constant. */
789 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x')
791 /* String constant. Used only for attributes right now. */
792 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
794 /* This is used to encapsulate an expression whose value is constant
795 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
796 recognized as a constant operand rather than by arithmetic instructions. */
798 DEF_RTL_EXPR(CONST, "const", "e", 'o')
800 /* program counter. Ordinary jumps are represented
801 by a SET whose first operand is (PC). */
802 DEF_RTL_EXPR(PC, "pc", "", 'o')
804 /* Used in the cselib routines to describe a value. */
805 DEF_RTL_EXPR(VALUE, "value", "0", 'o')
807 /* A register. The "operand" is the register number, accessed with
808 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
809 than a hardware register is being referred to. The second operand
810 holds the original register number - this will be different for a
811 pseudo register that got turned into a hard register.
812 This rtx needs to have as many (or more) fields as a MEM, since we
813 can change REG rtx's into MEMs during reload. */
814 DEF_RTL_EXPR(REG, "reg", "i00", 'o')
816 /* A scratch register. This represents a register used only within a
817 single insn. It will be turned into a REG during register allocation
818 or reload unless the constraint indicates that the register won't be
819 needed, in which case it can remain a SCRATCH. This code is
820 marked as having one operand so it can be turned into a REG. */
821 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
823 /* One word of a multi-word value.
824 The first operand is the complete value; the second says which word.
825 The WORDS_BIG_ENDIAN flag controls whether word number 0
826 (as numbered in a SUBREG) is the most or least significant word.
828 This is also used to refer to a value in a different machine mode.
829 For example, it can be used to refer to a SImode value as if it were
830 Qimode, or vice versa. Then the word number is always 0. */
831 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
833 /* This one-argument rtx is used for move instructions
834 that are guaranteed to alter only the low part of a destination.
835 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
836 has an unspecified effect on the high part of REG,
837 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
838 is guaranteed to alter only the bits of REG that are in HImode.
840 The actual instruction used is probably the same in both cases,
841 but the register constraints may be tighter when STRICT_LOW_PART
844 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
846 /* (CONCAT a b) represents the virtual concatenation of a and b
847 to make a value that has as many bits as a and b put together.
848 This is used for complex values. Normally it appears only
849 in DECL_RTLs and during RTL generation, but not in the insn chain. */
850 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
852 /* A memory location; operand is the address. The second operand is the
853 alias set to which this MEM belongs. We use `0' instead of `w' for this
854 field so that the field need not be specified in machine descriptions. */
855 DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
857 /* Reference to an assembler label in the code for this function.
858 The operand is a CODE_LABEL found in the insn chain.
859 The unprinted fields 1 and 2 are used in flow.c for the
860 LABEL_NEXTREF and CONTAINING_INSN. */
861 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
863 /* Reference to a named label: the string that is the first operand,
864 with `_' added implicitly in front.
865 Exception: if the first character explicitly given is `*',
866 to give it to the assembler, remove the `*' and do not add `_'. */
867 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
869 /* The condition code register is represented, in our imagination,
870 as a register holding a value that can be compared to zero.
871 In fact, the machine has already compared them and recorded the
872 results; but instructions that look at the condition code
873 pretend to be looking at the entire value and comparing it. */
874 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
876 /* Reference to the address of a register. Removed by purge_addressof after
877 CSE has elided as many as possible.
878 1st operand: the register we may need the address of.
879 2nd operand: the original pseudo regno we were generated for.
880 3rd operand: the decl for the object in the register, for
883 DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
885 /* =====================================================================
886 A QUEUED expression really points to a member of the queue of instructions
887 to be output later for postincrement/postdecrement.
888 QUEUED expressions never become part of instructions.
889 When a QUEUED expression would be put into an instruction,
890 instead either the incremented variable or a copy of its previous
894 0. the variable to be incremented (a REG rtx).
895 1. the incrementing instruction, or 0 if it hasn't been output yet.
896 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
897 3. the body to use for the incrementing instruction
898 4. the next QUEUED expression in the queue.
899 ====================================================================== */
901 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
903 /* ----------------------------------------------------------------------
904 Expressions for operators in an rtl pattern
905 ---------------------------------------------------------------------- */
907 /* if_then_else. This is used in representing ordinary
908 conditional jump instructions.
913 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
915 /* General conditional. The first operand is a vector composed of pairs of
916 expressions. The first element of each pair is evaluated, in turn.
917 The value of the conditional is the second expression of the first pair
918 whose first expression evaluates nonzero. If none of the expressions is
919 true, the second operand will be used as the value of the conditional.
921 This should be replaced with use of IF_THEN_ELSE. */
922 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
924 /* Comparison, produces a condition code result. */
925 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
928 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
930 /* Operand 0 minus operand 1. */
931 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
933 /* Minus operand 0. */
934 DEF_RTL_EXPR(NEG, "neg", "e", '1')
936 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
938 /* Operand 0 divided by operand 1. */
939 DEF_RTL_EXPR(DIV, "div", "ee", '2')
940 /* Remainder of operand 0 divided by operand 1. */
941 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
943 /* Unsigned divide and remainder. */
944 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
945 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
947 /* Bitwise operations. */
948 DEF_RTL_EXPR(AND, "and", "ee", 'c')
950 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
952 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
954 DEF_RTL_EXPR(NOT, "not", "e", '1')
957 0: value to be shifted.
958 1: number of bits. */
959 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
960 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
961 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
962 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
963 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
965 /* Minimum and maximum values of two operands. We need both signed and
966 unsigned forms. (We cannot use MIN for SMIN because it conflicts
967 with a macro of the same name.) */
969 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
970 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
971 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
972 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
974 /* These unary operations are used to represent incrementation
975 and decrementation as they occur in memory addresses.
976 The amount of increment or decrement are not represented
977 because they can be understood from the machine-mode of the
978 containing MEM. These operations exist in only two cases:
979 1. pushes onto the stack.
980 2. created automatically by the life_analysis pass in flow.c. */
981 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
982 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
983 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
984 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
986 /* These binary operations are used to represent generic address
987 side-effects in memory addresses, except for simple incrementation
988 or decrementation which use the above operations. They are
989 created automatically by the life_analysis pass in flow.c.
990 The first operand is a REG which is used as the address.
991 The second operand is an expression that is assigned to the
992 register, either before (PRE_MODIFY) or after (POST_MODIFY)
993 evaluating the address.
994 Currently, the compiler can only handle second operands of the
995 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
996 the first operand of the PLUS has to be the same register as
997 the first operand of the *_MODIFY. */
998 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
999 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
1001 /* Comparison operations. The ordered comparisons exist in two
1002 flavors, signed and unsigned. */
1003 DEF_RTL_EXPR(NE, "ne", "ee", '<')
1004 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
1005 DEF_RTL_EXPR(GE, "ge", "ee", '<')
1006 DEF_RTL_EXPR(GT, "gt", "ee", '<')
1007 DEF_RTL_EXPR(LE, "le", "ee", '<')
1008 DEF_RTL_EXPR(LT, "lt", "ee", '<')
1009 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
1010 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
1011 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
1012 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
1014 /* Additional floating point unordered comparison flavors. */
1015 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
1016 DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
1018 /* These are equivalent to unordered or ... */
1019 DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
1020 DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
1021 DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
1022 DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
1023 DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
1025 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
1026 DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
1028 /* Represents the result of sign-extending the sole operand.
1029 The machine modes of the operand and of the SIGN_EXTEND expression
1030 determine how much sign-extension is going on. */
1031 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
1033 /* Similar for zero-extension (such as unsigned short to int). */
1034 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
1036 /* Similar but here the operand has a wider mode. */
1037 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
1039 /* Similar for extending floating-point values (such as SFmode to DFmode). */
1040 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
1041 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
1043 /* Conversion of fixed point operand to floating point value. */
1044 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
1046 /* With fixed-point machine mode:
1047 Conversion of floating point operand to fixed point value.
1048 Value is defined only when the operand's value is an integer.
1049 With floating-point machine mode (and operand with same mode):
1050 Operand is rounded toward zero to produce an integer value
1051 represented in floating point. */
1052 DEF_RTL_EXPR(FIX, "fix", "e", '1')
1054 /* Conversion of unsigned fixed point operand to floating point value. */
1055 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
1057 /* With fixed-point machine mode:
1058 Conversion of floating point operand to *unsigned* fixed point value.
1059 Value is defined only when the operand's value is an integer. */
1060 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
1062 /* Absolute value */
1063 DEF_RTL_EXPR(ABS, "abs", "e", '1')
1066 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
1068 /* Find first bit that is set.
1069 Value is 1 + number of trailing zeros in the arg.,
1070 or 0 if arg is 0. */
1071 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
1073 /* Count leading zeros. */
1074 DEF_RTL_EXPR(CLZ, "clz", "e", '1')
1076 /* Count trailing zeros. */
1077 DEF_RTL_EXPR(CTZ, "ctz", "e", '1')
1079 /* Population count (number of 1 bits). */
1080 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", '1')
1082 /* Population parity (number of 1 bits modulo 2). */
1083 DEF_RTL_EXPR(PARITY, "parity", "e", '1')
1085 /* Reference to a signed bit-field of specified size and position.
1086 Operand 0 is the memory unit (usually SImode or QImode) which
1087 contains the field's first bit. Operand 1 is the width, in bits.
1088 Operand 2 is the number of bits in the memory unit before the
1089 first bit of this field.
1090 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
1091 operand 2 counts from the msb of the memory unit.
1092 Otherwise, the first bit is the lsb and operand 2 counts from
1093 the lsb of the memory unit. */
1094 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
1096 /* Similar for unsigned bit-field. */
1097 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
1099 /* For RISC machines. These save memory when splitting insns. */
1101 /* HIGH are the high-order bits of a constant expression. */
1102 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
1104 /* LO_SUM is the sum of a register and the low-order bits
1105 of a constant expression. */
1106 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
1108 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
1109 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
1110 the registers that can be substituted within this range. Operand 3 is the
1111 number of calls in the range. Operand 4 is the number of insns in the
1112 range. Operand 5 is the unique range number for this range. Operand 6 is
1113 the basic block # of the start of the live range. Operand 7 is the basic
1114 block # of the end of the live range. Operand 8 is the loop depth. Operand
1115 9 is a bitmap of the registers live at the start of the range. Operand 10
1116 is a bitmap of the registers live at the end of the range. Operand 11 is
1117 marker number for the start of the range. Operand 12 is the marker number
1118 for the end of the range. */
1119 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
1121 /* Registers that can be substituted within the range. Operand 0 is the
1122 original pseudo register number. Operand 1 will be filled in with the
1123 pseudo register the value is copied for the duration of the range. Operand
1124 2 is the number of references within the range to the register. Operand 3
1125 is the number of sets or clobbers of the register in the range. Operand 4
1126 is the number of deaths the register has. Operand 5 is the copy flags that
1127 give the status of whether a copy is needed from the original register to
1128 the new register at the beginning of the range, or whether a copy from the
1129 new register back to the original at the end of the range. Operand 6 is the
1130 live length. Operand 7 is the number of calls that this register is live
1131 across. Operand 8 is the symbol node of the variable if the register is a
1132 user variable. Operand 9 is the block node that the variable is declared
1133 in if the register is a user variable. */
1134 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
1136 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
1137 the different ranges a variable is in where it is copied to a different
1138 pseudo register. Operand 1 is the block that the variable is declared in.
1139 Operand 2 is the number of distinct ranges. */
1140 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
1142 /* Information about the registers that are live at the current point. Operand
1143 0 is the live bitmap. Operand 1 is the original block number. */
1144 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
1146 /* A unary `__builtin_constant_p' expression. These are only emitted
1147 during RTL generation, and then only if optimize > 0. They are
1148 eliminated by the first CSE pass. */
1149 DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
1151 /* A placeholder for a CALL_INSN which may be turned into a normal call,
1152 a sibling (tail) call or tail recursion.
1154 Immediately after RTL generation, this placeholder will be replaced
1155 by the insns to perform the call, sibcall or tail recursion.
1157 This RTX has 4 operands. The first three are lists of instructions to
1158 perform the call as a normal call, sibling call and tail recursion
1159 respectively. The latter two lists may be NULL, the first may never
1162 The last operand is the tail recursion CODE_LABEL, which may be NULL if no
1163 potential tail recursive calls were found.
1165 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
1166 after we select a call method.
1168 This method of tail-call elimination is intended to be replaced by
1169 tree-based optimizations once front-end conversions are complete. */
1170 DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
1172 /* Describes a merge operation between two vector values.
1173 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
1174 that specifies where the parts of the result are taken from. Set bits
1175 indicate operand 0, clear bits indicate operand 1. The parts are defined
1176 by the mode of the vectors. */
1177 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", '3')
1179 /* Describes an operation that selects parts of a vector.
1180 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
1181 a CONST_INT for each of the subparts of the result vector, giving the
1182 number of the source subpart that should be stored into it. */
1183 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", '2')
1185 /* Describes a vector concat operation. Operands 0 and 1 are the source
1186 vectors, the result is a vector that is as long as operands 0 and 1
1187 combined and is the concatenation of the two source vectors. */
1188 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", '2')
1190 /* Describes an operation that converts a small vector into a larger one by
1191 duplicating the input values. The output vector mode must have the same
1192 submodes as the input vector mode, and the number of output parts must be
1193 an integer multiple of the number of input parts. */
1194 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", '1')
1196 /* Addition with signed saturation */
1197 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
1199 /* Addition with unsigned saturation */
1200 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
1202 /* Operand 0 minus operand 1, with signed saturation. */
1203 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
1205 /* Operand 0 minus operand 1, with unsigned saturation. */
1206 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
1208 /* Signed saturating truncate. */
1209 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
1211 /* Unsigned saturating truncate. */
1212 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
1214 /* The SSA phi operator.
1216 The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT
1217 containing the block number of the predecessor through which control
1218 has passed when the register at element 2N is used.
1220 Note that PHI may only appear at the beginning of a basic block.
1222 ??? There may be multiple PHI insns, but they are all evaluated
1223 in parallel. This probably ought to be changed to use a real
1224 PARALLEL, as that would be less confusing and more in the spirit
1225 of canonical RTL. It is, however, easier to manipulate this way. */
1226 DEF_RTL_EXPR(PHI, "phi", "E", 'x')
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