1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999
5 Free Software Foundation, Inc.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
50 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
63 /* ---------------------------------------------------------------------
64 Expressions (and "meta" expressions) used for structuring the
65 rtl representation of a program.
66 --------------------------------------------------------------------- */
68 /* an expression code name unknown to the reader */
69 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
71 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
73 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
75 /* ---------------------------------------------------------------------
76 Expressions used in constructing lists.
77 --------------------------------------------------------------------- */
79 /* a linked list of expressions */
80 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
82 /* a linked list of instructions.
83 The insns are represented in print by their uids. */
84 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
86 /* ----------------------------------------------------------------------
87 Expression types for machine descriptions.
88 These do not appear in actual rtl code in the compiler.
89 ---------------------------------------------------------------------- */
91 /* Appears only in machine descriptions.
92 Means use the function named by the second arg (the string)
93 as a predicate; if matched, store the structure that was matched
94 in the operand table at index specified by the first arg (the integer).
95 If the second arg is the null string, the structure is just stored.
97 A third string argument indicates to the register allocator restrictions
98 on where the operand can be allocated.
100 If the target needs no restriction on any instruction this field should
103 The string is prepended by:
104 '=' to indicate the operand is only written to.
105 '+' to indicate the operand is both read and written to.
107 Each character in the string represents an allocable class for an operand.
108 'g' indicates the operand can be any valid class.
109 'i' indicates the operand can be immediate (in the instruction) data.
110 'r' indicates the operand can be in a register.
111 'm' indicates the operand can be in memory.
112 'o' a subset of the 'm' class. Those memory addressing modes that
113 can be offset at compile time (have a constant added to them).
115 Other characters indicate target dependent operand classes and
116 are described in each target's machine description.
118 For instructions with more than one operand, sets of classes can be
119 separated by a comma to indicate the appropriate multi-operand constraints.
120 There must be a 1 to 1 correspondence between these sets of classes in
121 all operands for an instruction.
123 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
125 /* Appears only in machine descriptions.
126 Means match a SCRATCH or a register. When used to generate rtl, a
127 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
128 the desired mode and the first argument is the operand number.
129 The second argument is the constraint. */
130 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
132 /* Appears only in machine descriptions.
133 Means match only something equal to what is stored in the operand table
134 at the index specified by the argument. */
135 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
137 /* Appears only in machine descriptions.
138 Means apply a predicate, AND match recursively the operands of the rtx.
139 Operand 0 is the operand-number, as in match_operand.
140 Operand 1 is a predicate to apply (as a string, a function name).
141 Operand 2 is a vector of expressions, each of which must match
142 one subexpression of the rtx this construct is matching. */
143 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
145 /* Appears only in machine descriptions.
146 Means to match a PARALLEL of arbitrary length. The predicate is applied
147 to the PARALLEL and the initial expressions in the PARALLEL are matched.
148 Operand 0 is the operand-number, as in match_operand.
149 Operand 1 is a predicate to apply to the PARALLEL.
150 Operand 2 is a vector of expressions, each of which must match the
151 corresponding element in the PARALLEL. */
152 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
154 /* Appears only in machine descriptions.
155 Means match only something equal to what is stored in the operand table
156 at the index specified by the argument. For MATCH_OPERATOR. */
157 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
159 /* Appears only in machine descriptions.
160 Means match only something equal to what is stored in the operand table
161 at the index specified by the argument. For MATCH_PARALLEL. */
162 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
164 /* Appears only in machine descriptions.
165 Operand 0 is the operand number, as in match_operand.
166 Operand 1 is the predicate to apply to the insn. */
167 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
169 /* Appears only in machine descriptions.
170 Defines the pattern for one kind of instruction.
172 0: names this instruction.
173 If the name is the null string, the instruction is in the
174 machine description just to be recognized, and will never be emitted by
175 the tree to rtl expander.
177 2: is a string which is a C expression
178 giving an additional condition for recognizing this pattern.
179 A null string means no extra condition.
180 3: is the action to execute if this pattern is matched.
181 If this assembler code template starts with a * then it is a fragment of
182 C code to run to decide on a template to use. Otherwise, it is the
184 4: optionally, a vector of attributes for this insn.
186 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
188 /* Definition of a peephole optimization.
189 1st operand: vector of insn patterns to match
190 2nd operand: C expression that must be true
191 3rd operand: template or C code to produce assembler output.
192 4: optionally, a vector of attributes for this insn.
194 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
196 /* Definition of a split operation.
197 1st operand: insn pattern to match
198 2nd operand: C expression that must be true
199 3rd operand: vector of insn patterns to place into a SEQUENCE
200 4th operand: optionally, some C code to execute before generating the
201 insns. This might, for example, create some RTX's and store them in
202 elements of `recog_operand' for use by the vector of insn-patterns.
203 (`operands' is an alias here for `recog_operand'). */
204 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
206 /* Definition of an RTL peephole operation.
207 Follows the same arguments as define_split. */
208 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
210 /* Definition of a combiner pattern.
211 Operands not defined yet. */
212 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
214 /* Define how to generate multiple insns for a standard insn name.
215 1st operand: the insn name.
216 2nd operand: vector of insn-patterns.
217 Use match_operand to substitute an element of `recog_operand'.
218 3rd operand: C expression that must be true for this to be available.
219 This may not test any operands.
220 4th operand: Extra C code to execute before generating the insns.
221 This might, for example, create some RTX's and store them in
222 elements of `recog_operand' for use by the vector of insn-patterns.
223 (`operands' is an alias here for `recog_operand'). */
224 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
226 /* Define a requirement for delay slots.
227 1st operand: Condition involving insn attributes that, if true,
228 indicates that the insn requires the number of delay slots
230 2nd operand: Vector whose length is the three times the number of delay
232 Each entry gives three conditions, each involving attributes.
233 The first must be true for an insn to occupy that delay slot
234 location. The second is true for all insns that can be
235 annulled if the branch is true and the third is true for all
236 insns that can be annulled if the branch is false.
238 Multiple DEFINE_DELAYs may be present. They indicate differing
239 requirements for delay slots. */
240 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
242 /* Define a set of insns that requires a function unit. This means that
243 these insns produce their result after a delay and that there may be
244 restrictions on the number of insns of this type that can be scheduled
247 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
248 Each gives a set of operations and associated delays. The first three
249 operands must be the same for each operation for the same function unit.
251 All delays are specified in cycles.
253 1st operand: Name of function unit (mostly for documentation)
254 2nd operand: Number of identical function units in CPU
255 3rd operand: Total number of simultaneous insns that can execute on this
256 function unit; 0 if unlimited.
257 4th operand: Condition involving insn attribute, that, if true, specifies
258 those insns that this expression applies to.
259 5th operand: Constant delay after which insn result will be
261 6th operand: Delay until next insn can be scheduled on the function unit
262 executing this operation. The meaning depends on whether or
263 not the next operand is supplied.
264 7th operand: If this operand is not specified, the 6th operand gives the
265 number of cycles after the instruction matching the 4th
266 operand begins using the function unit until a subsequent
267 insn can begin. A value of zero should be used for a
268 unit with no issue constraints. If only one operation can
269 be executed a time and the unit is busy for the entire time,
270 the 3rd operand should be specified as 1, the 6th operand
271 should be specified as 0, and the 7th operand should not
274 If this operand is specified, it is a list of attribute
275 expressions. If an insn for which any of these expressions
276 is true is currently executing on the function unit, the
277 issue delay will be given by the 6th operand. Otherwise,
278 the insn can be immediately scheduled (subject to the limit
279 on the number of simultaneous operations executing on the
281 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
283 /* Define attribute computation for `asm' instructions. */
284 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
286 /* SEQUENCE appears in the result of a `gen_...' function
287 for a DEFINE_EXPAND that wants to make several insns.
288 Its elements are the bodies of the insns that should be made.
289 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
290 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
292 /* Refers to the address of its argument. This is only used in alias.c. */
293 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
295 /* ----------------------------------------------------------------------
296 Expressions used for insn attributes. These also do not appear in
297 actual rtl code in the compiler.
298 ---------------------------------------------------------------------- */
300 /* Definition of an insn attribute.
301 1st operand: name of the attribute
302 2nd operand: comma-separated list of possible attribute values
303 3rd operand: expression for the default value of the attribute. */
304 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
306 /* Marker for the name of an attribute. */
307 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
309 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
310 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
313 (set_attr "name" "value") is equivalent to
314 (set (attr "name") (const_string "value")) */
315 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
317 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
318 specify that attribute values are to be assigned according to the
321 The following three expressions are equivalent:
323 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
324 (eq_attrq "alternative" "2") (const_string "a2")]
325 (const_string "a3")))
326 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
327 (const_string "a3")])
328 (set_attr "att" "a1,a2,a3")
330 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
332 /* A conditional expression true if the value of the specified attribute of
333 the current insn equals the specified value. The first operand is the
334 attribute name and the second is the comparison value. */
335 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
337 /* A conditional expression which is true if the specified flag is
338 true for the insn being scheduled in reorg.
340 genattr.c defines the following flags which can be tested by
341 (attr_flag "foo") expressions in eligible_for_delay.
343 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
345 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
347 /* ----------------------------------------------------------------------
348 Expression types used for things in the instruction chain.
350 All formats must start with "iuu" to handle the chain.
351 Each insn expression holds an rtl instruction and its semantics
352 during back-end processing.
353 See macros's in "rtl.h" for the meaning of each rtx->fld[].
355 ---------------------------------------------------------------------- */
357 /* An instruction that cannot jump. */
358 DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
360 /* An instruction that can possibly jump.
361 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
362 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
364 /* An instruction that can possibly call a subroutine
365 but which will not change which instruction comes next
366 in the current function.
367 Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
368 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
369 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
371 /* A marker that indicates that control will not flow through. */
372 DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
374 /* Holds a label that is followed by instructions.
376 3: is a number that is unique in the entire compilation.
377 4: is the user-given name of the label, if any.
378 5: is used in jump.c for the use-count of the label.
379 6: is used in flow.c to point to the chain of label_ref's to this label.
380 7: is the alternate label name. */
381 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuis00s", 'x')
383 /* Say where in the code a source line starts, for symbol table's sake.
384 Contains a filename and a line number. Line numbers <= 0 are special:
385 0 is used in a dummy placed at the front of every function
386 just so there will never be a need to delete the first insn;
387 -1 indicates a dummy; insns to be deleted by flow analysis and combining
388 are really changed to NOTEs with a number of -1.
389 -2 means beginning of a name binding contour; output N_LBRAC.
390 -3 means end of a contour; output N_RBRAC. */
391 DEF_RTL_EXPR(NOTE, "note", "iuu0n", 'x')
393 /* ----------------------------------------------------------------------
394 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
395 ---------------------------------------------------------------------- */
397 /* Several operations to be done in parallel. */
398 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
400 /* A string that is passed through to the assembler as input.
401 One can obviously pass comments through by using the
402 assembler comment syntax.
403 These occur in an insn all by themselves as the PATTERN.
404 They also appear inside an ASM_OPERANDS
405 as a convenient way to hold a string. */
406 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
408 /* An assembler instruction with operands.
409 1st operand is the instruction template.
410 2nd operand is the constraint for the output.
411 3rd operand is the number of the output this expression refers to.
412 When an insn stores more than one value, a separate ASM_OPERANDS
413 is made for each output; this integer distinguishes them.
414 4th is a vector of values of input operands.
415 5th is a vector of modes and constraints for the input operands.
416 Each element is an ASM_INPUT containing a constraint string
417 and whose mode indicates the mode of the input operand.
418 6th is the name of the containing source file.
419 7th is the source line number. */
420 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
422 /* A machine-specific operation.
423 1st operand is a vector of operands being used by the operation so that
424 any needed reloads can be done.
425 2nd operand is a unique value saying which of a number of machine-specific
426 operations is to be performed.
427 (Note that the vector must be the first operand because of the way that
428 genrecog.c record positions within an insn.)
429 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
430 or inside an expression. */
431 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
433 /* Similar, but a volatile operation and one which may trap. */
434 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
436 /* Vector of addresses, stored as full words. */
437 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
438 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
440 /* Vector of address differences X0 - BASE, X1 - BASE, ...
441 First operand is BASE; the vector contains the X's.
442 The machine mode of this rtx says how much space to leave
443 for each difference and is adjusted by branch shortening if
444 CASE_VECTOR_SHORTEN_MODE is defined.
445 The third and fourth operands store the target labels with the
446 minimum and maximum addresses respectively.
447 The fifth operand stores flags for use by branch shortening.
448 Set at the start of shorten_branches:
449 min_align: the minimum alignment for any of the target labels.
450 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
451 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
452 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
453 min_after_base: true iff minimum address target label is after BASE.
454 max_after_base: true iff maximum address target label is after BASE.
455 Set by the actual branch shortening process:
456 offset_unsigned: true iff offsets have to be treated as unsigned.
457 scale: scaling that is necessary to make offsets fit into the mode.
459 The third, fourth and fifth operands are only valid when
460 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
463 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
465 /* ----------------------------------------------------------------------
466 At the top level of an instruction (perhaps under PARALLEL).
467 ---------------------------------------------------------------------- */
470 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
471 Operand 2 is the value stored there.
472 ALL assignment must use SET.
473 Instructions that do multiple assignments must use multiple SET,
475 DEF_RTL_EXPR(SET, "set", "ee", 'x')
477 /* Indicate something is used in a way that we don't want to explain.
478 For example, subroutine calls will use the register
479 in which the static chain is passed. */
480 DEF_RTL_EXPR(USE, "use", "e", 'x')
482 /* Indicate something is clobbered in a way that we don't want to explain.
483 For example, subroutine calls will clobber some physical registers
484 (the ones that are by convention not saved). */
485 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
487 /* Call a subroutine.
488 Operand 1 is the address to call.
489 Operand 2 is the number of arguments. */
491 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
493 /* Return from a subroutine. */
495 DEF_RTL_EXPR(RETURN, "return", "", 'x')
498 Operand 1 is the condition.
499 Operand 2 is the trap code.
500 For an unconditional trap, make the condition (const_int 1). */
501 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
503 /* ----------------------------------------------------------------------
504 Primitive values for use in expressions.
505 ---------------------------------------------------------------------- */
507 /* numeric integer constant */
508 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
510 /* numeric floating point constant.
511 Operand 0 ('e') is the MEM that stores this constant in memory, or
512 various other things (see comments at immed_double_const in
514 Operand 1 ('0') is a chain of all CONST_DOUBLEs in use in the
516 Remaining operands hold the actual value. They are all 'w' and
517 there may be from 1 to 4; see rtl.c. */
518 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
520 /* String constant. Used only for attributes right now. */
521 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
523 /* This is used to encapsulate an expression whose value is constant
524 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
525 recognized as a constant operand rather than by arithmetic instructions. */
527 DEF_RTL_EXPR(CONST, "const", "e", 'o')
529 /* program counter. Ordinary jumps are represented
530 by a SET whose first operand is (PC). */
531 DEF_RTL_EXPR(PC, "pc", "", 'o')
533 /* A register. The "operand" is the register number, accessed with
534 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
535 than a hardware register is being referred to. The second operand
536 doesn't really exist. Unfortunately, however, the compiler
537 implicitly assumes that a REG can be transformed in place into a
538 MEM, and therefore that a REG is at least as big as a MEM. To
539 avoid this memory overhead, which is likely to be substantial,
540 search for uses of PUT_CODE that turn REGs into MEMs, and fix them
541 somehow. Then, the trailing `0' can be removed here. */
542 DEF_RTL_EXPR(REG, "reg", "i0", 'o')
544 /* A scratch register. This represents a register used only within a
545 single insn. It will be turned into a REG during register allocation
546 or reload unless the constraint indicates that the register won't be
547 needed, in which case it can remain a SCRATCH. This code is
548 marked as having one operand so it can be turned into a REG. */
549 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
551 /* One word of a multi-word value.
552 The first operand is the complete value; the second says which word.
553 The WORDS_BIG_ENDIAN flag controls whether word number 0
554 (as numbered in a SUBREG) is the most or least significant word.
556 This is also used to refer to a value in a different machine mode.
557 For example, it can be used to refer to a SImode value as if it were
558 Qimode, or vice versa. Then the word number is always 0. */
559 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
561 /* This one-argument rtx is used for move instructions
562 that are guaranteed to alter only the low part of a destination.
563 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
564 has an unspecified effect on the high part of REG,
565 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
566 is guaranteed to alter only the bits of REG that are in HImode.
568 The actual instruction used is probably the same in both cases,
569 but the register constraints may be tighter when STRICT_LOW_PART
572 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
574 /* (CONCAT a b) represents the virtual concatenation of a and b
575 to make a value that has as many bits as a and b put together.
576 This is used for complex values. Normally it appears only
577 in DECL_RTLs and during RTL generation, but not in the insn chain. */
578 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
580 /* A memory location; operand is the address. Can be nested inside a
581 VOLATILE. The second operand is the alias set to which this MEM
582 belongs. We use `0' instead of `i' for this field so that the
583 field need not be specified in machine descriptions. */
584 DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
586 /* Reference to an assembler label in the code for this function.
587 The operand is a CODE_LABEL found in the insn chain.
588 The unprinted fields 1 and 2 are used in flow.c for the
589 LABEL_NEXTREF and CONTAINING_INSN. */
590 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
592 /* Reference to a named label: the string that is the first operand,
593 with `_' added implicitly in front.
594 Exception: if the first character explicitly given is `*',
595 to give it to the assembler, remove the `*' and do not add `_'. */
596 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
598 /* The condition code register is represented, in our imagination,
599 as a register holding a value that can be compared to zero.
600 In fact, the machine has already compared them and recorded the
601 results; but instructions that look at the condition code
602 pretend to be looking at the entire value and comparing it. */
603 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
605 /* Reference to the address of a register. Removed by purge_addressof after
606 CSE has elided as many as possible.
607 1st operand: the register we may need the address of.
608 2nd operand: the original pseudo regno we were generated for.
609 3rd operand: the decl for the object in the register, for
612 DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
614 /* =====================================================================
615 A QUEUED expression really points to a member of the queue of instructions
616 to be output later for postincrement/postdecrement.
617 QUEUED expressions never become part of instructions.
618 When a QUEUED expression would be put into an instruction,
619 instead either the incremented variable or a copy of its previous
623 0. the variable to be incremented (a REG rtx).
624 1. the incrementing instruction, or 0 if it hasn't been output yet.
625 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
626 3. the body to use for the incrementing instruction
627 4. the next QUEUED expression in the queue.
628 ====================================================================== */
630 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
632 /* ----------------------------------------------------------------------
633 Expressions for operators in an rtl pattern
634 ---------------------------------------------------------------------- */
636 /* if_then_else. This is used in representing ordinary
637 conditional jump instructions.
642 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
644 /* General conditional. The first operand is a vector composed of pairs of
645 expressions. The first element of each pair is evaluated, in turn.
646 The value of the conditional is the second expression of the first pair
647 whose first expression evaluates non-zero. If none of the expressions is
648 true, the second operand will be used as the value of the conditional.
650 This should be replaced with use of IF_THEN_ELSE. */
651 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
653 /* Comparison, produces a condition code result. */
654 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
657 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
659 /* Operand 0 minus operand 1. */
660 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
662 /* Minus operand 0. */
663 DEF_RTL_EXPR(NEG, "neg", "e", '1')
665 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
667 /* Operand 0 divided by operand 1. */
668 DEF_RTL_EXPR(DIV, "div", "ee", '2')
669 /* Remainder of operand 0 divided by operand 1. */
670 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
672 /* Unsigned divide and remainder. */
673 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
674 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
676 /* Bitwise operations. */
677 DEF_RTL_EXPR(AND, "and", "ee", 'c')
679 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
681 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
683 DEF_RTL_EXPR(NOT, "not", "e", '1')
686 0: value to be shifted.
687 1: number of bits. */
688 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2')
689 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2')
691 /* Right shift operations, for machines where these are not the same
692 as left shifting with a negative argument. */
694 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2')
695 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2')
696 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2')
698 /* Minimum and maximum values of two operands. We need both signed and
699 unsigned forms. (We cannot use MIN for SMIN because it conflicts
700 with a macro of the same name.) */
702 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
703 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
704 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
705 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
707 /* These unary operations are used to represent incrementation
708 and decrementation as they occur in memory addresses.
709 The amount of increment or decrement are not represented
710 because they can be understood from the machine-mode of the
711 containing MEM. These operations exist in only two cases:
712 1. pushes onto the stack.
713 2. created automatically by the life_analysis pass in flow.c. */
714 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'x')
715 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'x')
716 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'x')
717 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'x')
719 /* These binary operations are used to represent generic address
720 side-effects in memory addresses, except for simple incrementation
721 or decrementation which use the above operations. They are
722 created automatically by the life_analysis pass in flow.c.
723 (Note that these operators are currently placeholders.) */
724 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'x')
725 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'x')
727 /* Comparison operations. The ordered comparisons exist in two
728 flavors, signed and unsigned. */
729 DEF_RTL_EXPR(NE, "ne", "ee", '<')
730 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
731 DEF_RTL_EXPR(GE, "ge", "ee", '<')
732 DEF_RTL_EXPR(GT, "gt", "ee", '<')
733 DEF_RTL_EXPR(LE, "le", "ee", '<')
734 DEF_RTL_EXPR(LT, "lt", "ee", '<')
735 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
736 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
737 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
738 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
740 /* Additional floating point unordered comparision flavors. */
741 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
742 DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
744 /* These are equivalent to unordered or ... */
745 DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
746 DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
747 DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
748 DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
749 DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
751 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
752 DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
754 /* Represents the result of sign-extending the sole operand.
755 The machine modes of the operand and of the SIGN_EXTEND expression
756 determine how much sign-extension is going on. */
757 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
759 /* Similar for zero-extension (such as unsigned short to int). */
760 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
762 /* Similar but here the operand has a wider mode. */
763 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
765 /* Similar for extending floating-point values (such as SFmode to DFmode). */
766 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
767 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
769 /* Conversion of fixed point operand to floating point value. */
770 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
772 /* With fixed-point machine mode:
773 Conversion of floating point operand to fixed point value.
774 Value is defined only when the operand's value is an integer.
775 With floating-point machine mode (and operand with same mode):
776 Operand is rounded toward zero to produce an integer value
777 represented in floating point. */
778 DEF_RTL_EXPR(FIX, "fix", "e", '1')
780 /* Conversion of unsigned fixed point operand to floating point value. */
781 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
783 /* With fixed-point machine mode:
784 Conversion of floating point operand to *unsigned* fixed point value.
785 Value is defined only when the operand's value is an integer. */
786 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
789 DEF_RTL_EXPR(ABS, "abs", "e", '1')
792 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
794 /* Find first bit that is set.
795 Value is 1 + number of trailing zeros in the arg.,
797 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
799 /* Reference to a signed bit-field of specified size and position.
800 Operand 0 is the memory unit (usually SImode or QImode) which
801 contains the field's first bit. Operand 1 is the width, in bits.
802 Operand 2 is the number of bits in the memory unit before the
803 first bit of this field.
804 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
805 operand 2 counts from the msb of the memory unit.
806 Otherwise, the first bit is the lsb and operand 2 counts from
807 the lsb of the memory unit. */
808 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
810 /* Similar for unsigned bit-field. */
811 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
813 /* For RISC machines. These save memory when splitting insns. */
815 /* HIGH are the high-order bits of a constant expression. */
816 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
818 /* LO_SUM is the sum of a register and the low-order bits
819 of a constant expression. */
820 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
822 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_START insn.
823 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
824 the registers that can be substituted within this range. Operand 3 is the
825 number of calls in the range. Operand 4 is the number of insns in the
826 range. Operand 5 is the unique range number for this range. Operand 6 is
827 the basic block # of the start of the live range. Operand 7 is the basic
828 block # of the end of the live range. Operand 8 is the loop depth. Operand
829 9 is a bitmap of the registers live at the start of the range. Operand 10
830 is a bitmap of the registers live at the end of the range. Operand 11 is
831 marker number for the start of the range. Operand 12 is the marker number
832 for the end of the range. */
833 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
835 /* Registers that can be substituted within the range. Operand 0 is the
836 original pseudo register number. Operand 1 will be filled in with the
837 pseudo register the value is copied for the duration of the range. Operand
838 2 is the number of references within the range to the register. Operand 3
839 is the number of sets or clobbers of the register in the range. Operand 4
840 is the number of deaths the register has. Operand 5 is the copy flags that
841 give the status of whether a copy is needed from the original register to
842 the new register at the beginning of the range, or whether a copy from the
843 new register back to the original at the end of the range. Operand 6 is the
844 live length. Operand 7 is the number of calls that this register is live
845 across. Operand 8 is the symbol node of the variable if the register is a
846 user variable. Operand 9 is the block node that the variable is declared
847 in if the register is a user variable. */
848 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
850 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
851 the different ranges a variable is in where it is copied to a different
852 pseudo register. Operand 1 is the block that the variable is declared in.
853 Operand 2 is the number of distinct ranges. */
854 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
856 /* Information about the registers that are live at the current point. Operand
857 0 is the live bitmap. Operand 1 is the original block number. */
858 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
860 /* A unary `__builtin_constant_p' expression. These are only emitted
861 during RTL generation, and then only if optimize > 0. They are
862 eliminated by the first CSE pass. */
863 DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
865 /* A placeholder for a CALL_INSN which may be turned into a normal call,
866 a sibling (tail) call or tail recursion.
868 Immediately after RTL generation, this placeholder will be replaced
869 by the insns to perform the call, sibcall or tail recursion.
871 This RTX has 4 operands. The first three are lists of instructions to
872 perform the call as a normal call, sibling call and tail recursion
873 respectively. The latter two lists may be NULL, the first may never
876 The last operand is the tail recursion CODE_LABEL, which may be NULL if no
877 potential tail recursive calls were found.
879 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
880 after we select a call method. */
881 DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
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