1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
79 /* ---------------------------------------------------------------------
80 Expressions (and "meta" expressions) used for structuring the
81 rtl representation of a program.
82 --------------------------------------------------------------------- */
84 /* an expression code name unknown to the reader */
85 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
89 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
91 /* ---------------------------------------------------------------------
92 Expressions used in constructing lists.
93 --------------------------------------------------------------------- */
95 /* a linked list of expressions */
96 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
98 /* a linked list of instructions.
99 The insns are represented in print by their uids. */
100 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
102 /* ----------------------------------------------------------------------
103 Expression types for machine descriptions.
104 These do not appear in actual rtl code in the compiler.
105 ---------------------------------------------------------------------- */
107 /* Appears only in machine descriptions.
108 Means use the function named by the second arg (the string)
109 as a predicate; if matched, store the structure that was matched
110 in the operand table at index specified by the first arg (the integer).
111 If the second arg is the null string, the structure is just stored.
113 A third string argument indicates to the register allocator restrictions
114 on where the operand can be allocated.
116 If the target needs no restriction on any instruction this field should
119 The string is prepended by:
120 '=' to indicate the operand is only written to.
121 '+' to indicate the operand is both read and written to.
123 Each character in the string represents an allocable class for an operand.
124 'g' indicates the operand can be any valid class.
125 'i' indicates the operand can be immediate (in the instruction) data.
126 'r' indicates the operand can be in a register.
127 'm' indicates the operand can be in memory.
128 'o' a subset of the 'm' class. Those memory addressing modes that
129 can be offset at compile time (have a constant added to them).
131 Other characters indicate target dependent operand classes and
132 are described in each target's machine description.
134 For instructions with more than one operand, sets of classes can be
135 separated by a comma to indicate the appropriate multi-operand constraints.
136 There must be a 1 to 1 correspondence between these sets of classes in
137 all operands for an instruction.
139 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
141 /* Appears only in machine descriptions.
142 Means match a SCRATCH or a register. When used to generate rtl, a
143 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
144 the desired mode and the first argument is the operand number.
145 The second argument is the constraint. */
146 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
148 /* Appears only in machine descriptions.
149 Means match only something equal to what is stored in the operand table
150 at the index specified by the argument. */
151 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
153 /* Appears only in machine descriptions.
154 Means apply a predicate, AND match recursively the operands of the rtx.
155 Operand 0 is the operand-number, as in match_operand.
156 Operand 1 is a predicate to apply (as a string, a function name).
157 Operand 2 is a vector of expressions, each of which must match
158 one subexpression of the rtx this construct is matching. */
159 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
161 /* Appears only in machine descriptions.
162 Means to match a PARALLEL of arbitrary length. The predicate is applied
163 to the PARALLEL and the initial expressions in the PARALLEL are matched.
164 Operand 0 is the operand-number, as in match_operand.
165 Operand 1 is a predicate to apply to the PARALLEL.
166 Operand 2 is a vector of expressions, each of which must match the
167 corresponding element in the PARALLEL. */
168 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
170 /* Appears only in machine descriptions.
171 Means match only something equal to what is stored in the operand table
172 at the index specified by the argument. For MATCH_OPERATOR. */
173 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
175 /* Appears only in machine descriptions.
176 Means match only something equal to what is stored in the operand table
177 at the index specified by the argument. For MATCH_PARALLEL. */
178 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
180 /* Appears only in define_predicate/define_special predicate
181 expressions in a machine description. Evaluates true only if the
182 operand has an RTX code from the set given by the argument (a
183 comma-separated list). */
184 DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH)
186 /* Appears only in define_predicate/define_special_predicate expressions
187 in a machine description. The argument is a C expression to be injected
188 at this point in the predicate formula. */
189 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
191 /* Appears only in machine descriptions.
192 Defines the pattern for one kind of instruction.
194 0: names this instruction.
195 If the name is the null string, the instruction is in the
196 machine description just to be recognized, and will never be emitted by
197 the tree to rtl expander.
199 2: is a string which is a C expression
200 giving an additional condition for recognizing this pattern.
201 A null string means no extra condition.
202 3: is the action to execute if this pattern is matched.
203 If this assembler code template starts with a * then it is a fragment of
204 C code to run to decide on a template to use. Otherwise, it is the
206 4: optionally, a vector of attributes for this insn.
208 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
210 /* Definition of a peephole optimization.
211 1st operand: vector of insn patterns to match
212 2nd operand: C expression that must be true
213 3rd operand: template or C code to produce assembler output.
214 4: optionally, a vector of attributes for this insn.
216 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
218 /* Definition of a split operation.
219 1st operand: insn pattern to match
220 2nd operand: C expression that must be true
221 3rd operand: vector of insn patterns to place into a SEQUENCE
222 4th operand: optionally, some C code to execute before generating the
223 insns. This might, for example, create some RTX's and store them in
224 elements of `recog_data.operand' for use by the vector of
226 (`operands' is an alias here for `recog_data.operand'). */
227 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
229 /* Definition of an insn and associated split.
230 This is the concatenation, with a few modifications, of a define_insn
231 and a define_split which share the same pattern.
233 0: names this instruction.
234 If the name is the null string, the instruction is in the
235 machine description just to be recognized, and will never be emitted by
236 the tree to rtl expander.
238 2: is a string which is a C expression
239 giving an additional condition for recognizing this pattern.
240 A null string means no extra condition.
241 3: is the action to execute if this pattern is matched.
242 If this assembler code template starts with a * then it is a fragment of
243 C code to run to decide on a template to use. Otherwise, it is the
245 4: C expression that must be true for split. This may start with "&&"
246 in which case the split condition is the logical and of the insn
247 condition and what follows the "&&" of this operand.
248 5: vector of insn patterns to place into a SEQUENCE
249 6: optionally, some C code to execute before generating the
250 insns. This might, for example, create some RTX's and store them in
251 elements of `recog_data.operand' for use by the vector of
253 (`operands' is an alias here for `recog_data.operand').
254 7: optionally, a vector of attributes for this insn. */
255 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
257 /* Definition of an RTL peephole operation.
258 Follows the same arguments as define_split. */
259 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
261 /* Define how to generate multiple insns for a standard insn name.
262 1st operand: the insn name.
263 2nd operand: vector of insn-patterns.
264 Use match_operand to substitute an element of `recog_data.operand'.
265 3rd operand: C expression that must be true for this to be available.
266 This may not test any operands.
267 4th operand: Extra C code to execute before generating the insns.
268 This might, for example, create some RTX's and store them in
269 elements of `recog_data.operand' for use by the vector of
271 (`operands' is an alias here for `recog_data.operand'). */
272 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
274 /* Define a requirement for delay slots.
275 1st operand: Condition involving insn attributes that, if true,
276 indicates that the insn requires the number of delay slots
278 2nd operand: Vector whose length is the three times the number of delay
280 Each entry gives three conditions, each involving attributes.
281 The first must be true for an insn to occupy that delay slot
282 location. The second is true for all insns that can be
283 annulled if the branch is true and the third is true for all
284 insns that can be annulled if the branch is false.
286 Multiple DEFINE_DELAYs may be present. They indicate differing
287 requirements for delay slots. */
288 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
290 /* Define attribute computation for `asm' instructions. */
291 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
293 /* Definition of a conditional execution meta operation. Automatically
294 generates new instances of DEFINE_INSN, selected by having attribute
295 "predicable" true. The new pattern will contain a COND_EXEC and the
296 predicate at top-level.
299 0: The predicate pattern. The top-level form should match a
300 relational operator. Operands should have only one alternative.
301 1: A C expression giving an additional condition for recognizing
302 the generated pattern.
303 2: A template or C code to produce assembler output. */
304 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
306 /* Definition of an operand predicate. The difference between
307 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
308 not warn about a match_operand with no mode if it has a predicate
309 defined with DEFINE_SPECIAL_PREDICATE.
312 0: The name of the predicate.
313 1: A boolean expression which computes whether or not the predicate
314 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
315 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
316 can calculate the set of RTX codes that can possibly match.
317 2: A C function body which must return true for the predicate to match.
318 Optional. Use this when the test is too complicated to fit into a
319 match_test expression. */
320 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
321 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
323 /* SEQUENCE appears in the result of a `gen_...' function
324 for a DEFINE_EXPAND that wants to make several insns.
325 Its elements are the bodies of the insns that should be made.
326 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
327 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
329 /* Refers to the address of its argument. This is only used in alias.c. */
330 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
332 /* ----------------------------------------------------------------------
333 Constructions for CPU pipeline description described by NDFAs.
334 These do not appear in actual rtl code in the compiler.
335 ---------------------------------------------------------------------- */
337 /* (define_cpu_unit string [string]) describes cpu functional
338 units (separated by comma).
340 1st operand: Names of cpu functional units.
341 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
343 All define_reservations, define_cpu_units, and
344 define_query_cpu_units should have unique names which may not be
346 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
348 /* (define_query_cpu_unit string [string]) describes cpu functional
349 units analogously to define_cpu_unit. The reservation of such
350 units can be queried for automaton state. */
351 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
353 /* (exclusion_set string string) means that each CPU functional unit
354 in the first string can not be reserved simultaneously with any
355 unit whose name is in the second string and vise versa. CPU units
356 in the string are separated by commas. For example, it is useful
357 for description CPU with fully pipelined floating point functional
358 unit which can execute simultaneously only single floating point
359 insns or only double floating point insns. All CPU functional
360 units in a set should belong to the same automaton. */
361 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
363 /* (presence_set string string) means that each CPU functional unit in
364 the first string can not be reserved unless at least one of pattern
365 of units whose names are in the second string is reserved. This is
366 an asymmetric relation. CPU units or unit patterns in the strings
367 are separated by commas. Pattern is one unit name or unit names
368 separated by white-spaces.
370 For example, it is useful for description that slot1 is reserved
371 after slot0 reservation for a VLIW processor. We could describe it
372 by the following construction
374 (presence_set "slot1" "slot0")
376 Or slot1 is reserved only after slot0 and unit b0 reservation. In
377 this case we could write
379 (presence_set "slot1" "slot0 b0")
381 All CPU functional units in a set should belong to the same
383 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
385 /* (final_presence_set string string) is analogous to `presence_set'.
386 The difference between them is when checking is done. When an
387 instruction is issued in given automaton state reflecting all
388 current and planned unit reservations, the automaton state is
389 changed. The first state is a source state, the second one is a
390 result state. Checking for `presence_set' is done on the source
391 state reservation, checking for `final_presence_set' is done on the
392 result reservation. This construction is useful to describe a
393 reservation which is actually two subsequent reservations. For
396 (presence_set "slot1" "slot0")
398 the following insn will be never issued (because slot1 requires
399 slot0 which is absent in the source state).
401 (define_reservation "insn_and_nop" "slot0 + slot1")
403 but it can be issued if we use analogous `final_presence_set'. */
404 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
406 /* (absence_set string string) means that each CPU functional unit in
407 the first string can be reserved only if each pattern of units
408 whose names are in the second string is not reserved. This is an
409 asymmetric relation (actually exclusion set is analogous to this
410 one but it is symmetric). CPU units or unit patterns in the string
411 are separated by commas. Pattern is one unit name or unit names
412 separated by white-spaces.
414 For example, it is useful for description that slot0 can not be
415 reserved after slot1 or slot2 reservation for a VLIW processor. We
416 could describe it by the following construction
418 (absence_set "slot2" "slot0, slot1")
420 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
421 slot1 and unit b1 are reserved . In this case we could write
423 (absence_set "slot2" "slot0 b0, slot1 b1")
425 All CPU functional units in a set should to belong the same
427 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
429 /* (final_absence_set string string) is analogous to `absence_set' but
430 checking is done on the result (state) reservation. See comments
431 for `final_presence_set'. */
432 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
434 /* (define_bypass number out_insn_names in_insn_names) names bypass
435 with given latency (the first number) from insns given by the first
436 string (see define_insn_reservation) into insns given by the second
437 string. Insn names in the strings are separated by commas. The
438 third operand is optional name of function which is additional
439 guard for the bypass. The function will get the two insns as
440 parameters. If the function returns zero the bypass will be
441 ignored for this case. Additional guard is necessary to recognize
442 complicated bypasses, e.g. when consumer is load address. */
443 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
445 /* (define_automaton string) describes names of automata generated and
446 used for pipeline hazards recognition. The names are separated by
447 comma. Actually it is possibly to generate the single automaton
448 but unfortunately it can be very large. If we use more one
449 automata, the summary size of the automata usually is less than the
450 single one. The automaton name is used in define_cpu_unit and
451 define_query_cpu_unit. All automata should have unique names. */
452 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
454 /* (automata_option string) describes option for generation of
455 automata. Currently there are the following options:
457 o "no-minimization" which makes no minimization of automata. This
458 is only worth to do when we are debugging the description and
459 need to look more accurately at reservations of states.
461 o "time" which means printing additional time statistics about
462 generation of automata.
464 o "v" which means generation of file describing the result
465 automata. The file has suffix `.dfa' and can be used for the
466 description verification and debugging.
468 o "w" which means generation of warning instead of error for
471 o "ndfa" which makes nondeterministic finite state automata.
473 o "progress" which means output of a progress bar showing how many
474 states were generated so far for automaton being processed. */
475 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
477 /* (define_reservation string string) names reservation (the first
478 string) of cpu functional units (the 2nd string). Sometimes unit
479 reservations for different insns contain common parts. In such
480 case, you can describe common part and use its name (the 1st
481 parameter) in regular expression in define_insn_reservation. All
482 define_reservations, define_cpu_units, and define_query_cpu_units
483 should have unique names which may not be "nothing". */
484 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
486 /* (define_insn_reservation name default_latency condition regexpr)
487 describes reservation of cpu functional units (the 3nd operand) for
488 instruction which is selected by the condition (the 2nd parameter).
489 The first parameter is used for output of debugging information.
490 The reservations are described by a regular expression according
491 the following syntax:
493 regexp = regexp "," oneof
496 oneof = oneof "|" allof
499 allof = allof "+" repeat
502 repeat = element "*" number
505 element = cpu_function_unit_name
511 1. "," is used for describing start of the next cycle in
514 2. "|" is used for describing the reservation described by the
515 first regular expression *or* the reservation described by the
516 second regular expression *or* etc.
518 3. "+" is used for describing the reservation described by the
519 first regular expression *and* the reservation described by the
520 second regular expression *and* etc.
522 4. "*" is used for convenience and simply means sequence in
523 which the regular expression are repeated NUMBER times with
524 cycle advancing (see ",").
526 5. cpu functional unit name which means its reservation.
528 6. reservation name -- see define_reservation.
530 7. string "nothing" means no units reservation. */
532 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
534 /* ----------------------------------------------------------------------
535 Expressions used for insn attributes. These also do not appear in
536 actual rtl code in the compiler.
537 ---------------------------------------------------------------------- */
539 /* Definition of an insn attribute.
540 1st operand: name of the attribute
541 2nd operand: comma-separated list of possible attribute values
542 3rd operand: expression for the default value of the attribute. */
543 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
545 /* Marker for the name of an attribute. */
546 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
548 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
549 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
552 (set_attr "name" "value") is equivalent to
553 (set (attr "name") (const_string "value")) */
554 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
556 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
557 specify that attribute values are to be assigned according to the
560 The following three expressions are equivalent:
562 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
563 (eq_attrq "alternative" "2") (const_string "a2")]
564 (const_string "a3")))
565 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
566 (const_string "a3")])
567 (set_attr "att" "a1,a2,a3")
569 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
571 /* A conditional expression true if the value of the specified attribute of
572 the current insn equals the specified value. The first operand is the
573 attribute name and the second is the comparison value. */
574 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
576 /* A special case of the above representing a set of alternatives. The first
577 operand is bitmap of the set, the second one is the default value. */
578 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
580 /* A conditional expression which is true if the specified flag is
581 true for the insn being scheduled in reorg.
583 genattr.c defines the following flags which can be tested by
584 (attr_flag "foo") expressions in eligible_for_delay.
586 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
588 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
590 /* ----------------------------------------------------------------------
591 Expression types used for things in the instruction chain.
593 All formats must start with "iuu" to handle the chain.
594 Each insn expression holds an rtl instruction and its semantics
595 during back-end processing.
596 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
598 ---------------------------------------------------------------------- */
600 /* An instruction that cannot jump. */
601 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
603 /* An instruction that can possibly jump.
604 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
605 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
607 /* An instruction that can possibly call a subroutine
608 but which will not change which instruction comes next
609 in the current function.
610 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
611 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
612 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
614 /* A marker that indicates that control will not flow through. */
615 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
617 /* Holds a label that is followed by instructions.
619 4: is used in jump.c for the use-count of the label.
620 5: is used in flow.c to point to the chain of label_ref's to this label.
621 6: is a number that is unique in the entire compilation.
622 7: is the user-given name of the label, if any. */
623 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
625 #ifdef USE_MAPPED_LOCATION
626 /* Say where in the code a source line starts, for symbol table's sake.
628 4: unused if line number > 0, note-specific data otherwise.
629 5: line number if > 0, enum note_insn otherwise.
630 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
632 /* Say where in the code a source line starts, for symbol table's sake.
634 4: filename, if line number > 0, note-specific data otherwise.
635 5: line number if > 0, enum note_insn otherwise.
636 6: unique number if line number == note_insn_deleted_label. */
638 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
640 /* ----------------------------------------------------------------------
641 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
642 ---------------------------------------------------------------------- */
644 /* Conditionally execute code.
645 Operand 0 is the condition that if true, the code is executed.
646 Operand 1 is the code to be executed (typically a SET).
648 Semantics are that there are no side effects if the condition
649 is false. This pattern is created automatically by the if_convert
650 pass run after reload or by target-specific splitters. */
651 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
653 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
654 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
656 /* A string that is passed through to the assembler as input.
657 One can obviously pass comments through by using the
658 assembler comment syntax.
659 These occur in an insn all by themselves as the PATTERN.
660 They also appear inside an ASM_OPERANDS
661 as a convenient way to hold a string. */
662 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
664 #ifdef USE_MAPPED_LOCATION
665 /* An assembler instruction with operands.
666 1st operand is the instruction template.
667 2nd operand is the constraint for the output.
668 3rd operand is the number of the output this expression refers to.
669 When an insn stores more than one value, a separate ASM_OPERANDS
670 is made for each output; this integer distinguishes them.
671 4th is a vector of values of input operands.
672 5th is a vector of modes and constraints for the input operands.
673 Each element is an ASM_INPUT containing a constraint string
674 and whose mode indicates the mode of the input operand.
675 6th is the source line number. */
676 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
678 /* An assembler instruction with operands.
679 1st operand is the instruction template.
680 2nd operand is the constraint for the output.
681 3rd operand is the number of the output this expression refers to.
682 When an insn stores more than one value, a separate ASM_OPERANDS
683 is made for each output; this integer distinguishes them.
684 4th is a vector of values of input operands.
685 5th is a vector of modes and constraints for the input operands.
686 Each element is an ASM_INPUT containing a constraint string
687 and whose mode indicates the mode of the input operand.
688 6th is the name of the containing source file.
689 7th is the source line number. */
690 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
693 /* A machine-specific operation.
694 1st operand is a vector of operands being used by the operation so that
695 any needed reloads can be done.
696 2nd operand is a unique value saying which of a number of machine-specific
697 operations is to be performed.
698 (Note that the vector must be the first operand because of the way that
699 genrecog.c record positions within an insn.)
700 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
701 or inside an expression. */
702 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
704 /* Similar, but a volatile operation and one which may trap. */
705 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
707 /* Vector of addresses, stored as full words. */
708 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
709 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
711 /* Vector of address differences X0 - BASE, X1 - BASE, ...
712 First operand is BASE; the vector contains the X's.
713 The machine mode of this rtx says how much space to leave
714 for each difference and is adjusted by branch shortening if
715 CASE_VECTOR_SHORTEN_MODE is defined.
716 The third and fourth operands store the target labels with the
717 minimum and maximum addresses respectively.
718 The fifth operand stores flags for use by branch shortening.
719 Set at the start of shorten_branches:
720 min_align: the minimum alignment for any of the target labels.
721 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
722 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
723 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
724 min_after_base: true iff minimum address target label is after BASE.
725 max_after_base: true iff maximum address target label is after BASE.
726 Set by the actual branch shortening process:
727 offset_unsigned: true iff offsets have to be treated as unsigned.
728 scale: scaling that is necessary to make offsets fit into the mode.
730 The third, fourth and fifth operands are only valid when
731 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
734 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
736 /* Memory prefetch, with attributes supported on some targets.
737 Operand 1 is the address of the memory to fetch.
738 Operand 2 is 1 for a write access, 0 otherwise.
739 Operand 3 is the level of temporal locality; 0 means there is no
740 temporal locality and 1, 2, and 3 are for increasing levels of temporal
743 The attributes specified by operands 2 and 3 are ignored for targets
744 whose prefetch instructions do not support them. */
745 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
747 /* ----------------------------------------------------------------------
748 At the top level of an instruction (perhaps under PARALLEL).
749 ---------------------------------------------------------------------- */
752 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
753 Operand 2 is the value stored there.
754 ALL assignment must use SET.
755 Instructions that do multiple assignments must use multiple SET,
757 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
759 /* Indicate something is used in a way that we don't want to explain.
760 For example, subroutine calls will use the register
761 in which the static chain is passed. */
762 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
764 /* Indicate something is clobbered in a way that we don't want to explain.
765 For example, subroutine calls will clobber some physical registers
766 (the ones that are by convention not saved). */
767 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
769 /* Call a subroutine.
770 Operand 1 is the address to call.
771 Operand 2 is the number of arguments. */
773 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
775 /* Return from a subroutine. */
777 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
780 Operand 1 is the condition.
781 Operand 2 is the trap code.
782 For an unconditional trap, make the condition (const_int 1). */
783 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
785 /* Placeholder for _Unwind_Resume before we know if a function call
786 or a branch is needed. Operand 1 is the exception region from
787 which control is flowing. */
788 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
790 /* ----------------------------------------------------------------------
791 Primitive values for use in expressions.
792 ---------------------------------------------------------------------- */
794 /* numeric integer constant */
795 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
797 /* numeric floating point constant.
798 Operands hold the value. They are all 'w' and there may be from 2 to 6;
800 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
802 /* Describes a vector constant. */
803 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA)
805 /* String constant. Used only for attributes right now. */
806 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
808 /* This is used to encapsulate an expression whose value is constant
809 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
810 recognized as a constant operand rather than by arithmetic instructions. */
812 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
814 /* program counter. Ordinary jumps are represented
815 by a SET whose first operand is (PC). */
816 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
818 /* Used in the cselib routines to describe a value. */
819 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
821 /* A register. The "operand" is the register number, accessed with
822 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
823 than a hardware register is being referred to. The second operand
824 holds the original register number - this will be different for a
825 pseudo register that got turned into a hard register.
826 This rtx needs to have as many (or more) fields as a MEM, since we
827 can change REG rtx's into MEMs during reload. */
828 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
830 /* A scratch register. This represents a register used only within a
831 single insn. It will be turned into a REG during register allocation
832 or reload unless the constraint indicates that the register won't be
833 needed, in which case it can remain a SCRATCH. This code is
834 marked as having one operand so it can be turned into a REG. */
835 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
837 /* One word of a multi-word value.
838 The first operand is the complete value; the second says which word.
839 The WORDS_BIG_ENDIAN flag controls whether word number 0
840 (as numbered in a SUBREG) is the most or least significant word.
842 This is also used to refer to a value in a different machine mode.
843 For example, it can be used to refer to a SImode value as if it were
844 Qimode, or vice versa. Then the word number is always 0. */
845 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
847 /* This one-argument rtx is used for move instructions
848 that are guaranteed to alter only the low part of a destination.
849 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
850 has an unspecified effect on the high part of REG,
851 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
852 is guaranteed to alter only the bits of REG that are in HImode.
854 The actual instruction used is probably the same in both cases,
855 but the register constraints may be tighter when STRICT_LOW_PART
858 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
860 /* (CONCAT a b) represents the virtual concatenation of a and b
861 to make a value that has as many bits as a and b put together.
862 This is used for complex values. Normally it appears only
863 in DECL_RTLs and during RTL generation, but not in the insn chain. */
864 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
866 /* A memory location; operand is the address. The second operand is the
867 alias set to which this MEM belongs. We use `0' instead of `w' for this
868 field so that the field need not be specified in machine descriptions. */
869 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
871 /* Reference to an assembler label in the code for this function.
872 The operand is a CODE_LABEL found in the insn chain.
873 The unprinted fields 1 and 2 are used in flow.c for the
874 LABEL_NEXTREF and CONTAINING_INSN. */
875 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", RTX_CONST_OBJ)
877 /* Reference to a named label:
878 Operand 0: label name
879 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
880 Operand 2: tree from which this symbol is derived, or null.
881 This is either a DECL node, or some kind of constant. */
882 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
884 /* The condition code register is represented, in our imagination,
885 as a register holding a value that can be compared to zero.
886 In fact, the machine has already compared them and recorded the
887 results; but instructions that look at the condition code
888 pretend to be looking at the entire value and comparing it. */
889 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
891 /* ----------------------------------------------------------------------
892 Expressions for operators in an rtl pattern
893 ---------------------------------------------------------------------- */
895 /* if_then_else. This is used in representing ordinary
896 conditional jump instructions.
901 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
903 /* General conditional. The first operand is a vector composed of pairs of
904 expressions. The first element of each pair is evaluated, in turn.
905 The value of the conditional is the second expression of the first pair
906 whose first expression evaluates nonzero. If none of the expressions is
907 true, the second operand will be used as the value of the conditional.
909 This should be replaced with use of IF_THEN_ELSE. */
910 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
912 /* Comparison, produces a condition code result. */
913 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
916 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
918 /* Operand 0 minus operand 1. */
919 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
921 /* Minus operand 0. */
922 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
924 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
926 /* Operand 0 divided by operand 1. */
927 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
928 /* Remainder of operand 0 divided by operand 1. */
929 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
931 /* Unsigned divide and remainder. */
932 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
933 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
935 /* Bitwise operations. */
936 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
938 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
940 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
942 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
945 0: value to be shifted.
946 1: number of bits. */
947 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
948 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
949 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
950 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
951 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
953 /* Minimum and maximum values of two operands. We need both signed and
954 unsigned forms. (We cannot use MIN for SMIN because it conflicts
955 with a macro of the same name.) */
957 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
958 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
959 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
960 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
962 /* These unary operations are used to represent incrementation
963 and decrementation as they occur in memory addresses.
964 The amount of increment or decrement are not represented
965 because they can be understood from the machine-mode of the
966 containing MEM. These operations exist in only two cases:
967 1. pushes onto the stack.
968 2. created automatically by the life_analysis pass in flow.c. */
969 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
970 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
971 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
972 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
974 /* These binary operations are used to represent generic address
975 side-effects in memory addresses, except for simple incrementation
976 or decrementation which use the above operations. They are
977 created automatically by the life_analysis pass in flow.c.
978 The first operand is a REG which is used as the address.
979 The second operand is an expression that is assigned to the
980 register, either before (PRE_MODIFY) or after (POST_MODIFY)
981 evaluating the address.
982 Currently, the compiler can only handle second operands of the
983 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
984 the first operand of the PLUS has to be the same register as
985 the first operand of the *_MODIFY. */
986 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
987 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
989 /* Comparison operations. The ordered comparisons exist in two
990 flavors, signed and unsigned. */
991 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
992 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
993 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
994 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
995 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
996 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
997 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
998 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
999 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
1000 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
1002 /* Additional floating point unordered comparison flavors. */
1003 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
1004 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
1006 /* These are equivalent to unordered or ... */
1007 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
1008 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
1009 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
1010 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
1011 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
1013 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
1014 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
1016 /* Represents the result of sign-extending the sole operand.
1017 The machine modes of the operand and of the SIGN_EXTEND expression
1018 determine how much sign-extension is going on. */
1019 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
1021 /* Similar for zero-extension (such as unsigned short to int). */
1022 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
1024 /* Similar but here the operand has a wider mode. */
1025 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
1027 /* Similar for extending floating-point values (such as SFmode to DFmode). */
1028 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
1029 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
1031 /* Conversion of fixed point operand to floating point value. */
1032 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
1034 /* With fixed-point machine mode:
1035 Conversion of floating point operand to fixed point value.
1036 Value is defined only when the operand's value is an integer.
1037 With floating-point machine mode (and operand with same mode):
1038 Operand is rounded toward zero to produce an integer value
1039 represented in floating point. */
1040 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
1042 /* Conversion of unsigned fixed point operand to floating point value. */
1043 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
1045 /* With fixed-point machine mode:
1046 Conversion of floating point operand to *unsigned* fixed point value.
1047 Value is defined only when the operand's value is an integer. */
1048 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
1050 /* Absolute value */
1051 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
1054 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
1056 /* Find first bit that is set.
1057 Value is 1 + number of trailing zeros in the arg.,
1058 or 0 if arg is 0. */
1059 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
1061 /* Count leading zeros. */
1062 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
1064 /* Count trailing zeros. */
1065 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
1067 /* Population count (number of 1 bits). */
1068 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
1070 /* Population parity (number of 1 bits modulo 2). */
1071 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
1073 /* Reference to a signed bit-field of specified size and position.
1074 Operand 0 is the memory unit (usually SImode or QImode) which
1075 contains the field's first bit. Operand 1 is the width, in bits.
1076 Operand 2 is the number of bits in the memory unit before the
1077 first bit of this field.
1078 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
1079 operand 2 counts from the msb of the memory unit.
1080 Otherwise, the first bit is the lsb and operand 2 counts from
1081 the lsb of the memory unit. */
1082 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
1084 /* Similar for unsigned bit-field. */
1085 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
1087 /* For RISC machines. These save memory when splitting insns. */
1089 /* HIGH are the high-order bits of a constant expression. */
1090 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
1092 /* LO_SUM is the sum of a register and the low-order bits
1093 of a constant expression. */
1094 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
1096 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
1097 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
1098 the registers that can be substituted within this range. Operand 3 is the
1099 number of calls in the range. Operand 4 is the number of insns in the
1100 range. Operand 5 is the unique range number for this range. Operand 6 is
1101 the basic block # of the start of the live range. Operand 7 is the basic
1102 block # of the end of the live range. Operand 8 is the loop depth. Operand
1103 9 is a bitmap of the registers live at the start of the range. Operand 10
1104 is a bitmap of the registers live at the end of the range. Operand 11 is
1105 marker number for the start of the range. Operand 12 is the marker number
1106 for the end of the range. */
1107 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", RTX_EXTRA)
1109 /* Registers that can be substituted within the range. Operand 0 is the
1110 original pseudo register number. Operand 1 will be filled in with the
1111 pseudo register the value is copied for the duration of the range. Operand
1112 2 is the number of references within the range to the register. Operand 3
1113 is the number of sets or clobbers of the register in the range. Operand 4
1114 is the number of deaths the register has. Operand 5 is the copy flags that
1115 give the status of whether a copy is needed from the original register to
1116 the new register at the beginning of the range, or whether a copy from the
1117 new register back to the original at the end of the range. Operand 6 is the
1118 live length. Operand 7 is the number of calls that this register is live
1119 across. Operand 8 is the symbol node of the variable if the register is a
1120 user variable. Operand 9 is the block node that the variable is declared
1121 in if the register is a user variable. */
1122 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", RTX_EXTRA)
1124 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
1125 the different ranges a variable is in where it is copied to a different
1126 pseudo register. Operand 1 is the block that the variable is declared in.
1127 Operand 2 is the number of distinct ranges. */
1128 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", RTX_EXTRA)
1130 /* Information about the registers that are live at the current point. Operand
1131 0 is the live bitmap. Operand 1 is the original block number. */
1132 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", RTX_EXTRA)
1134 /* Describes a merge operation between two vector values.
1135 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
1136 that specifies where the parts of the result are taken from. Set bits
1137 indicate operand 0, clear bits indicate operand 1. The parts are defined
1138 by the mode of the vectors. */
1139 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
1141 /* Describes an operation that selects parts of a vector.
1142 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
1143 a CONST_INT for each of the subparts of the result vector, giving the
1144 number of the source subpart that should be stored into it. */
1145 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
1147 /* Describes a vector concat operation. Operands 0 and 1 are the source
1148 vectors, the result is a vector that is as long as operands 0 and 1
1149 combined and is the concatenation of the two source vectors. */
1150 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
1152 /* Describes an operation that converts a small vector into a larger one by
1153 duplicating the input values. The output vector mode must have the same
1154 submodes as the input vector mode, and the number of output parts must be
1155 an integer multiple of the number of input parts. */
1156 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
1158 /* Addition with signed saturation */
1159 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
1161 /* Addition with unsigned saturation */
1162 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
1164 /* Operand 0 minus operand 1, with signed saturation. */
1165 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
1167 /* Operand 0 minus operand 1, with unsigned saturation. */
1168 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
1170 /* Signed saturating truncate. */
1171 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
1173 /* Unsigned saturating truncate. */
1174 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
1176 /* Information about the variable and its location. */
1177 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
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