1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* ---------------------------------------------------------------------
85 Expressions used in constructing lists.
86 --------------------------------------------------------------------- */
88 /* a linked list of expressions */
89 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
91 /* a linked list of instructions.
92 The insns are represented in print by their uids. */
93 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
95 /* SEQUENCE appears in the result of a `gen_...' function
96 for a DEFINE_EXPAND that wants to make several insns.
97 Its elements are the bodies of the insns that should be made.
98 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
99 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
101 /* Refers to the address of its argument. This is only used in alias.c. */
102 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
104 /* ----------------------------------------------------------------------
105 Expression types used for things in the instruction chain.
107 All formats must start with "iuu" to handle the chain.
108 Each insn expression holds an rtl instruction and its semantics
109 during back-end processing.
110 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
112 ---------------------------------------------------------------------- */
114 /* An instruction that cannot jump. */
115 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
117 /* An instruction that can possibly jump.
118 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
119 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
121 /* An instruction that can possibly call a subroutine
122 but which will not change which instruction comes next
123 in the current function.
124 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
125 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
126 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
128 /* A marker that indicates that control will not flow through. */
129 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
131 /* Holds a label that is followed by instructions.
133 4: is used in jump.c for the use-count of the label.
134 5: is used in flow.c to point to the chain of label_ref's to this label.
135 6: is a number that is unique in the entire compilation.
136 7: is the user-given name of the label, if any. */
137 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
139 #ifdef USE_MAPPED_LOCATION
140 /* Say where in the code a source line starts, for symbol table's sake.
142 4: unused if line number > 0, note-specific data otherwise.
143 5: line number if > 0, enum note_insn otherwise.
144 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
146 /* Say where in the code a source line starts, for symbol table's sake.
148 4: filename, if line number > 0, note-specific data otherwise.
149 5: line number if > 0, enum note_insn otherwise.
150 6: unique number if line number == note_insn_deleted_label. */
152 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
154 /* ----------------------------------------------------------------------
155 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
156 ---------------------------------------------------------------------- */
158 /* Conditionally execute code.
159 Operand 0 is the condition that if true, the code is executed.
160 Operand 1 is the code to be executed (typically a SET).
162 Semantics are that there are no side effects if the condition
163 is false. This pattern is created automatically by the if_convert
164 pass run after reload or by target-specific splitters. */
165 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
167 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
168 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
170 /* A string that is passed through to the assembler as input.
171 One can obviously pass comments through by using the
172 assembler comment syntax.
173 These occur in an insn all by themselves as the PATTERN.
174 They also appear inside an ASM_OPERANDS
175 as a convenient way to hold a string. */
176 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
178 #ifdef USE_MAPPED_LOCATION
179 /* An assembler instruction with operands.
180 1st operand is the instruction template.
181 2nd operand is the constraint for the output.
182 3rd operand is the number of the output this expression refers to.
183 When an insn stores more than one value, a separate ASM_OPERANDS
184 is made for each output; this integer distinguishes them.
185 4th is a vector of values of input operands.
186 5th is a vector of modes and constraints for the input operands.
187 Each element is an ASM_INPUT containing a constraint string
188 and whose mode indicates the mode of the input operand.
189 6th is the source line number. */
190 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
192 /* An assembler instruction with operands.
193 1st operand is the instruction template.
194 2nd operand is the constraint for the output.
195 3rd operand is the number of the output this expression refers to.
196 When an insn stores more than one value, a separate ASM_OPERANDS
197 is made for each output; this integer distinguishes them.
198 4th is a vector of values of input operands.
199 5th is a vector of modes and constraints for the input operands.
200 Each element is an ASM_INPUT containing a constraint string
201 and whose mode indicates the mode of the input operand.
202 6th is the name of the containing source file.
203 7th is the source line number. */
204 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
207 /* A machine-specific operation.
208 1st operand is a vector of operands being used by the operation so that
209 any needed reloads can be done.
210 2nd operand is a unique value saying which of a number of machine-specific
211 operations is to be performed.
212 (Note that the vector must be the first operand because of the way that
213 genrecog.c record positions within an insn.)
214 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
215 or inside an expression. */
216 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
218 /* Similar, but a volatile operation and one which may trap. */
219 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
221 /* Vector of addresses, stored as full words. */
222 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
223 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
225 /* Vector of address differences X0 - BASE, X1 - BASE, ...
226 First operand is BASE; the vector contains the X's.
227 The machine mode of this rtx says how much space to leave
228 for each difference and is adjusted by branch shortening if
229 CASE_VECTOR_SHORTEN_MODE is defined.
230 The third and fourth operands store the target labels with the
231 minimum and maximum addresses respectively.
232 The fifth operand stores flags for use by branch shortening.
233 Set at the start of shorten_branches:
234 min_align: the minimum alignment for any of the target labels.
235 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
236 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
237 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
238 min_after_base: true iff minimum address target label is after BASE.
239 max_after_base: true iff maximum address target label is after BASE.
240 Set by the actual branch shortening process:
241 offset_unsigned: true iff offsets have to be treated as unsigned.
242 scale: scaling that is necessary to make offsets fit into the mode.
244 The third, fourth and fifth operands are only valid when
245 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
248 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
250 /* Memory prefetch, with attributes supported on some targets.
251 Operand 1 is the address of the memory to fetch.
252 Operand 2 is 1 for a write access, 0 otherwise.
253 Operand 3 is the level of temporal locality; 0 means there is no
254 temporal locality and 1, 2, and 3 are for increasing levels of temporal
257 The attributes specified by operands 2 and 3 are ignored for targets
258 whose prefetch instructions do not support them. */
259 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
261 /* ----------------------------------------------------------------------
262 At the top level of an instruction (perhaps under PARALLEL).
263 ---------------------------------------------------------------------- */
266 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
267 Operand 2 is the value stored there.
268 ALL assignment must use SET.
269 Instructions that do multiple assignments must use multiple SET,
271 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
273 /* Indicate something is used in a way that we don't want to explain.
274 For example, subroutine calls will use the register
275 in which the static chain is passed. */
276 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
278 /* Indicate something is clobbered in a way that we don't want to explain.
279 For example, subroutine calls will clobber some physical registers
280 (the ones that are by convention not saved). */
281 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
283 /* Call a subroutine.
284 Operand 1 is the address to call.
285 Operand 2 is the number of arguments. */
287 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
289 /* Return from a subroutine. */
291 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
294 Operand 1 is the condition.
295 Operand 2 is the trap code.
296 For an unconditional trap, make the condition (const_int 1). */
297 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
299 /* Placeholder for _Unwind_Resume before we know if a function call
300 or a branch is needed. Operand 1 is the exception region from
301 which control is flowing. */
302 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
304 /* ----------------------------------------------------------------------
305 Primitive values for use in expressions.
306 ---------------------------------------------------------------------- */
308 /* numeric integer constant */
309 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
311 /* numeric floating point constant.
312 Operands hold the value. They are all 'w' and there may be from 2 to 6;
314 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
316 /* Describes a vector constant. */
317 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA)
319 /* String constant. Used for attributes in machine descriptions and
320 for special cases in DWARF2 debug output. NOT used for source-
321 language string constants. */
322 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
324 /* This is used to encapsulate an expression whose value is constant
325 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
326 recognized as a constant operand rather than by arithmetic instructions. */
328 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
330 /* program counter. Ordinary jumps are represented
331 by a SET whose first operand is (PC). */
332 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
334 /* Used in the cselib routines to describe a value. */
335 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
337 /* A register. The "operand" is the register number, accessed with
338 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
339 than a hardware register is being referred to. The second operand
340 holds the original register number - this will be different for a
341 pseudo register that got turned into a hard register. The third
342 operand points to a reg_attrs structure.
343 This rtx needs to have as many (or more) fields as a MEM, since we
344 can change REG rtx's into MEMs during reload. */
345 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
347 /* A scratch register. This represents a register used only within a
348 single insn. It will be turned into a REG during register allocation
349 or reload unless the constraint indicates that the register won't be
350 needed, in which case it can remain a SCRATCH. This code is
351 marked as having one operand so it can be turned into a REG. */
352 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
354 /* One word of a multi-word value.
355 The first operand is the complete value; the second says which word.
356 The WORDS_BIG_ENDIAN flag controls whether word number 0
357 (as numbered in a SUBREG) is the most or least significant word.
359 This is also used to refer to a value in a different machine mode.
360 For example, it can be used to refer to a SImode value as if it were
361 Qimode, or vice versa. Then the word number is always 0. */
362 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
364 /* This one-argument rtx is used for move instructions
365 that are guaranteed to alter only the low part of a destination.
366 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
367 has an unspecified effect on the high part of REG,
368 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
369 is guaranteed to alter only the bits of REG that are in HImode.
371 The actual instruction used is probably the same in both cases,
372 but the register constraints may be tighter when STRICT_LOW_PART
375 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
377 /* (CONCAT a b) represents the virtual concatenation of a and b
378 to make a value that has as many bits as a and b put together.
379 This is used for complex values. Normally it appears only
380 in DECL_RTLs and during RTL generation, but not in the insn chain. */
381 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
383 /* A memory location; operand is the address. The second operand is the
384 alias set to which this MEM belongs. We use `0' instead of `w' for this
385 field so that the field need not be specified in machine descriptions. */
386 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
388 /* Reference to an assembler label in the code for this function.
389 The operand is a CODE_LABEL found in the insn chain.
390 The unprinted fields 1 and 2 are used in flow.c for the
391 LABEL_NEXTREF and CONTAINING_INSN. */
392 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", RTX_CONST_OBJ)
394 /* Reference to a named label:
395 Operand 0: label name
396 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
397 Operand 2: tree from which this symbol is derived, or null.
398 This is either a DECL node, or some kind of constant. */
399 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
401 /* The condition code register is represented, in our imagination,
402 as a register holding a value that can be compared to zero.
403 In fact, the machine has already compared them and recorded the
404 results; but instructions that look at the condition code
405 pretend to be looking at the entire value and comparing it. */
406 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
408 /* ----------------------------------------------------------------------
409 Expressions for operators in an rtl pattern
410 ---------------------------------------------------------------------- */
412 /* if_then_else. This is used in representing ordinary
413 conditional jump instructions.
418 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
420 /* Comparison, produces a condition code result. */
421 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
424 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
426 /* Operand 0 minus operand 1. */
427 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
429 /* Minus operand 0. */
430 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
432 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
434 /* Operand 0 divided by operand 1. */
435 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
436 /* Remainder of operand 0 divided by operand 1. */
437 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
439 /* Unsigned divide and remainder. */
440 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
441 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
443 /* Bitwise operations. */
444 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
446 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
448 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
450 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
453 0: value to be shifted.
454 1: number of bits. */
455 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
456 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
457 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
458 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
459 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
461 /* Minimum and maximum values of two operands. We need both signed and
462 unsigned forms. (We cannot use MIN for SMIN because it conflicts
463 with a macro of the same name.) */
465 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
466 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
467 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
468 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
470 /* These unary operations are used to represent incrementation
471 and decrementation as they occur in memory addresses.
472 The amount of increment or decrement are not represented
473 because they can be understood from the machine-mode of the
474 containing MEM. These operations exist in only two cases:
475 1. pushes onto the stack.
476 2. created automatically by the life_analysis pass in flow.c. */
477 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
478 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
479 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
480 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
482 /* These binary operations are used to represent generic address
483 side-effects in memory addresses, except for simple incrementation
484 or decrementation which use the above operations. They are
485 created automatically by the life_analysis pass in flow.c.
486 The first operand is a REG which is used as the address.
487 The second operand is an expression that is assigned to the
488 register, either before (PRE_MODIFY) or after (POST_MODIFY)
489 evaluating the address.
490 Currently, the compiler can only handle second operands of the
491 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
492 the first operand of the PLUS has to be the same register as
493 the first operand of the *_MODIFY. */
494 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
495 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
497 /* Comparison operations. The ordered comparisons exist in two
498 flavors, signed and unsigned. */
499 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
500 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
501 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
502 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
503 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
504 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
505 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
506 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
507 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
508 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
510 /* Additional floating point unordered comparison flavors. */
511 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
512 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
514 /* These are equivalent to unordered or ... */
515 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
516 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
517 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
518 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
519 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
521 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
522 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
524 /* Represents the result of sign-extending the sole operand.
525 The machine modes of the operand and of the SIGN_EXTEND expression
526 determine how much sign-extension is going on. */
527 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
529 /* Similar for zero-extension (such as unsigned short to int). */
530 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
532 /* Similar but here the operand has a wider mode. */
533 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
535 /* Similar for extending floating-point values (such as SFmode to DFmode). */
536 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
537 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
539 /* Conversion of fixed point operand to floating point value. */
540 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
542 /* With fixed-point machine mode:
543 Conversion of floating point operand to fixed point value.
544 Value is defined only when the operand's value is an integer.
545 With floating-point machine mode (and operand with same mode):
546 Operand is rounded toward zero to produce an integer value
547 represented in floating point. */
548 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
550 /* Conversion of unsigned fixed point operand to floating point value. */
551 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
553 /* With fixed-point machine mode:
554 Conversion of floating point operand to *unsigned* fixed point value.
555 Value is defined only when the operand's value is an integer. */
556 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
559 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
562 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
564 /* Find first bit that is set.
565 Value is 1 + number of trailing zeros in the arg.,
567 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
569 /* Count leading zeros. */
570 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
572 /* Count trailing zeros. */
573 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
575 /* Population count (number of 1 bits). */
576 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
578 /* Population parity (number of 1 bits modulo 2). */
579 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
581 /* Reference to a signed bit-field of specified size and position.
582 Operand 0 is the memory unit (usually SImode or QImode) which
583 contains the field's first bit. Operand 1 is the width, in bits.
584 Operand 2 is the number of bits in the memory unit before the
585 first bit of this field.
586 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
587 operand 2 counts from the msb of the memory unit.
588 Otherwise, the first bit is the lsb and operand 2 counts from
589 the lsb of the memory unit. */
590 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
592 /* Similar for unsigned bit-field. */
593 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
595 /* For RISC machines. These save memory when splitting insns. */
597 /* HIGH are the high-order bits of a constant expression. */
598 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
600 /* LO_SUM is the sum of a register and the low-order bits
601 of a constant expression. */
602 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
604 /* Describes a merge operation between two vector values.
605 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
606 that specifies where the parts of the result are taken from. Set bits
607 indicate operand 0, clear bits indicate operand 1. The parts are defined
608 by the mode of the vectors. */
609 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
611 /* Describes an operation that selects parts of a vector.
612 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
613 a CONST_INT for each of the subparts of the result vector, giving the
614 number of the source subpart that should be stored into it. */
615 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
617 /* Describes a vector concat operation. Operands 0 and 1 are the source
618 vectors, the result is a vector that is as long as operands 0 and 1
619 combined and is the concatenation of the two source vectors. */
620 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
622 /* Describes an operation that converts a small vector into a larger one by
623 duplicating the input values. The output vector mode must have the same
624 submodes as the input vector mode, and the number of output parts must be
625 an integer multiple of the number of input parts. */
626 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
628 /* Addition with signed saturation */
629 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
631 /* Addition with unsigned saturation */
632 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
634 /* Operand 0 minus operand 1, with signed saturation. */
635 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
637 /* Operand 0 minus operand 1, with unsigned saturation. */
638 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
640 /* Signed saturating truncate. */
641 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
643 /* Unsigned saturating truncate. */
644 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
646 /* Information about the variable and its location. */
647 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
649 /* All expressions from this point forward appear only in machine
651 #ifdef GENERATOR_FILE
653 /* Include a secondary machine-description file at this point. */
654 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
656 /* Pattern-matching operators: */
658 /* Use the function named by the second arg (the string)
659 as a predicate; if matched, store the structure that was matched
660 in the operand table at index specified by the first arg (the integer).
661 If the second arg is the null string, the structure is just stored.
663 A third string argument indicates to the register allocator restrictions
664 on where the operand can be allocated.
666 If the target needs no restriction on any instruction this field should
669 The string is prepended by:
670 '=' to indicate the operand is only written to.
671 '+' to indicate the operand is both read and written to.
673 Each character in the string represents an allocable class for an operand.
674 'g' indicates the operand can be any valid class.
675 'i' indicates the operand can be immediate (in the instruction) data.
676 'r' indicates the operand can be in a register.
677 'm' indicates the operand can be in memory.
678 'o' a subset of the 'm' class. Those memory addressing modes that
679 can be offset at compile time (have a constant added to them).
681 Other characters indicate target dependent operand classes and
682 are described in each target's machine description.
684 For instructions with more than one operand, sets of classes can be
685 separated by a comma to indicate the appropriate multi-operand constraints.
686 There must be a 1 to 1 correspondence between these sets of classes in
687 all operands for an instruction.
689 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
691 /* Match a SCRATCH or a register. When used to generate rtl, a
692 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
693 the desired mode and the first argument is the operand number.
694 The second argument is the constraint. */
695 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
697 /* Apply a predicate, AND match recursively the operands of the rtx.
698 Operand 0 is the operand-number, as in match_operand.
699 Operand 1 is a predicate to apply (as a string, a function name).
700 Operand 2 is a vector of expressions, each of which must match
701 one subexpression of the rtx this construct is matching. */
702 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
704 /* Match a PARALLEL of arbitrary length. The predicate is applied
705 to the PARALLEL and the initial expressions in the PARALLEL are matched.
706 Operand 0 is the operand-number, as in match_operand.
707 Operand 1 is a predicate to apply to the PARALLEL.
708 Operand 2 is a vector of expressions, each of which must match the
709 corresponding element in the PARALLEL. */
710 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
712 /* Match only something equal to what is stored in the operand table
713 at the index specified by the argument. Use with MATCH_OPERAND. */
714 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
716 /* Match only something equal to what is stored in the operand table
717 at the index specified by the argument. Use with MATCH_OPERATOR. */
718 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
720 /* Match only something equal to what is stored in the operand table
721 at the index specified by the argument. Use with MATCH_PARALLEL. */
722 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
724 /* Appears only in define_predicate/define_special_predicate
725 expressions. Evaluates true only if the operand has an RTX code
726 from the set given by the argument (a comma-separated list). */
727 DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH)
729 /* Appears only in define_predicate/define_special_predicate
730 expressions. The argument is a C expression to be injected at this
731 point in the predicate formula. */
732 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
734 /* Insn (and related) definitions. */
736 /* Definition of the pattern for one kind of instruction.
738 0: names this instruction.
739 If the name is the null string, the instruction is in the
740 machine description just to be recognized, and will never be emitted by
741 the tree to rtl expander.
743 2: is a string which is a C expression
744 giving an additional condition for recognizing this pattern.
745 A null string means no extra condition.
746 3: is the action to execute if this pattern is matched.
747 If this assembler code template starts with a * then it is a fragment of
748 C code to run to decide on a template to use. Otherwise, it is the
750 4: optionally, a vector of attributes for this insn.
752 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
754 /* Definition of a peephole optimization.
755 1st operand: vector of insn patterns to match
756 2nd operand: C expression that must be true
757 3rd operand: template or C code to produce assembler output.
758 4: optionally, a vector of attributes for this insn.
760 This form is deprecated; use define_peephole2 instead. */
761 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
763 /* Definition of a split operation.
764 1st operand: insn pattern to match
765 2nd operand: C expression that must be true
766 3rd operand: vector of insn patterns to place into a SEQUENCE
767 4th operand: optionally, some C code to execute before generating the
768 insns. This might, for example, create some RTX's and store them in
769 elements of `recog_data.operand' for use by the vector of
771 (`operands' is an alias here for `recog_data.operand'). */
772 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
774 /* Definition of an insn and associated split.
775 This is the concatenation, with a few modifications, of a define_insn
776 and a define_split which share the same pattern.
778 0: names this instruction.
779 If the name is the null string, the instruction is in the
780 machine description just to be recognized, and will never be emitted by
781 the tree to rtl expander.
783 2: is a string which is a C expression
784 giving an additional condition for recognizing this pattern.
785 A null string means no extra condition.
786 3: is the action to execute if this pattern is matched.
787 If this assembler code template starts with a * then it is a fragment of
788 C code to run to decide on a template to use. Otherwise, it is the
790 4: C expression that must be true for split. This may start with "&&"
791 in which case the split condition is the logical and of the insn
792 condition and what follows the "&&" of this operand.
793 5: vector of insn patterns to place into a SEQUENCE
794 6: optionally, some C code to execute before generating the
795 insns. This might, for example, create some RTX's and store them in
796 elements of `recog_data.operand' for use by the vector of
798 (`operands' is an alias here for `recog_data.operand').
799 7: optionally, a vector of attributes for this insn. */
800 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
802 /* Definition of an RTL peephole operation.
803 Follows the same arguments as define_split. */
804 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
806 /* Define how to generate multiple insns for a standard insn name.
807 1st operand: the insn name.
808 2nd operand: vector of insn-patterns.
809 Use match_operand to substitute an element of `recog_data.operand'.
810 3rd operand: C expression that must be true for this to be available.
811 This may not test any operands.
812 4th operand: Extra C code to execute before generating the insns.
813 This might, for example, create some RTX's and store them in
814 elements of `recog_data.operand' for use by the vector of
816 (`operands' is an alias here for `recog_data.operand'). */
817 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
819 /* Define a requirement for delay slots.
820 1st operand: Condition involving insn attributes that, if true,
821 indicates that the insn requires the number of delay slots
823 2nd operand: Vector whose length is the three times the number of delay
825 Each entry gives three conditions, each involving attributes.
826 The first must be true for an insn to occupy that delay slot
827 location. The second is true for all insns that can be
828 annulled if the branch is true and the third is true for all
829 insns that can be annulled if the branch is false.
831 Multiple DEFINE_DELAYs may be present. They indicate differing
832 requirements for delay slots. */
833 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
835 /* Define attribute computation for `asm' instructions. */
836 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
838 /* Definition of a conditional execution meta operation. Automatically
839 generates new instances of DEFINE_INSN, selected by having attribute
840 "predicable" true. The new pattern will contain a COND_EXEC and the
841 predicate at top-level.
844 0: The predicate pattern. The top-level form should match a
845 relational operator. Operands should have only one alternative.
846 1: A C expression giving an additional condition for recognizing
847 the generated pattern.
848 2: A template or C code to produce assembler output. */
849 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
851 /* Definition of an operand predicate. The difference between
852 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
853 not warn about a match_operand with no mode if it has a predicate
854 defined with DEFINE_SPECIAL_PREDICATE.
857 0: The name of the predicate.
858 1: A boolean expression which computes whether or not the predicate
859 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
860 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
861 can calculate the set of RTX codes that can possibly match.
862 2: A C function body which must return true for the predicate to match.
863 Optional. Use this when the test is too complicated to fit into a
864 match_test expression. */
865 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
866 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
868 /* Constructions for CPU pipeline description described by NDFAs. */
870 /* (define_cpu_unit string [string]) describes cpu functional
871 units (separated by comma).
873 1st operand: Names of cpu functional units.
874 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
876 All define_reservations, define_cpu_units, and
877 define_query_cpu_units should have unique names which may not be
879 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
881 /* (define_query_cpu_unit string [string]) describes cpu functional
882 units analogously to define_cpu_unit. The reservation of such
883 units can be queried for automaton state. */
884 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
886 /* (exclusion_set string string) means that each CPU functional unit
887 in the first string can not be reserved simultaneously with any
888 unit whose name is in the second string and vise versa. CPU units
889 in the string are separated by commas. For example, it is useful
890 for description CPU with fully pipelined floating point functional
891 unit which can execute simultaneously only single floating point
892 insns or only double floating point insns. All CPU functional
893 units in a set should belong to the same automaton. */
894 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
896 /* (presence_set string string) means that each CPU functional unit in
897 the first string can not be reserved unless at least one of pattern
898 of units whose names are in the second string is reserved. This is
899 an asymmetric relation. CPU units or unit patterns in the strings
900 are separated by commas. Pattern is one unit name or unit names
901 separated by white-spaces.
903 For example, it is useful for description that slot1 is reserved
904 after slot0 reservation for a VLIW processor. We could describe it
905 by the following construction
907 (presence_set "slot1" "slot0")
909 Or slot1 is reserved only after slot0 and unit b0 reservation. In
910 this case we could write
912 (presence_set "slot1" "slot0 b0")
914 All CPU functional units in a set should belong to the same
916 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
918 /* (final_presence_set string string) is analogous to `presence_set'.
919 The difference between them is when checking is done. When an
920 instruction is issued in given automaton state reflecting all
921 current and planned unit reservations, the automaton state is
922 changed. The first state is a source state, the second one is a
923 result state. Checking for `presence_set' is done on the source
924 state reservation, checking for `final_presence_set' is done on the
925 result reservation. This construction is useful to describe a
926 reservation which is actually two subsequent reservations. For
929 (presence_set "slot1" "slot0")
931 the following insn will be never issued (because slot1 requires
932 slot0 which is absent in the source state).
934 (define_reservation "insn_and_nop" "slot0 + slot1")
936 but it can be issued if we use analogous `final_presence_set'. */
937 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
939 /* (absence_set string string) means that each CPU functional unit in
940 the first string can be reserved only if each pattern of units
941 whose names are in the second string is not reserved. This is an
942 asymmetric relation (actually exclusion set is analogous to this
943 one but it is symmetric). CPU units or unit patterns in the string
944 are separated by commas. Pattern is one unit name or unit names
945 separated by white-spaces.
947 For example, it is useful for description that slot0 can not be
948 reserved after slot1 or slot2 reservation for a VLIW processor. We
949 could describe it by the following construction
951 (absence_set "slot2" "slot0, slot1")
953 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
954 slot1 and unit b1 are reserved . In this case we could write
956 (absence_set "slot2" "slot0 b0, slot1 b1")
958 All CPU functional units in a set should to belong the same
960 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
962 /* (final_absence_set string string) is analogous to `absence_set' but
963 checking is done on the result (state) reservation. See comments
964 for `final_presence_set'. */
965 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
967 /* (define_bypass number out_insn_names in_insn_names) names bypass
968 with given latency (the first number) from insns given by the first
969 string (see define_insn_reservation) into insns given by the second
970 string. Insn names in the strings are separated by commas. The
971 third operand is optional name of function which is additional
972 guard for the bypass. The function will get the two insns as
973 parameters. If the function returns zero the bypass will be
974 ignored for this case. Additional guard is necessary to recognize
975 complicated bypasses, e.g. when consumer is load address. */
976 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
978 /* (define_automaton string) describes names of automata generated and
979 used for pipeline hazards recognition. The names are separated by
980 comma. Actually it is possibly to generate the single automaton
981 but unfortunately it can be very large. If we use more one
982 automata, the summary size of the automata usually is less than the
983 single one. The automaton name is used in define_cpu_unit and
984 define_query_cpu_unit. All automata should have unique names. */
985 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
987 /* (automata_option string) describes option for generation of
988 automata. Currently there are the following options:
990 o "no-minimization" which makes no minimization of automata. This
991 is only worth to do when we are debugging the description and
992 need to look more accurately at reservations of states.
994 o "time" which means printing additional time statistics about
995 generation of automata.
997 o "v" which means generation of file describing the result
998 automata. The file has suffix `.dfa' and can be used for the
999 description verification and debugging.
1001 o "w" which means generation of warning instead of error for
1002 non-critical errors.
1004 o "ndfa" which makes nondeterministic finite state automata.
1006 o "progress" which means output of a progress bar showing how many
1007 states were generated so far for automaton being processed. */
1008 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1010 /* (define_reservation string string) names reservation (the first
1011 string) of cpu functional units (the 2nd string). Sometimes unit
1012 reservations for different insns contain common parts. In such
1013 case, you can describe common part and use its name (the 1st
1014 parameter) in regular expression in define_insn_reservation. All
1015 define_reservations, define_cpu_units, and define_query_cpu_units
1016 should have unique names which may not be "nothing". */
1017 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1019 /* (define_insn_reservation name default_latency condition regexpr)
1020 describes reservation of cpu functional units (the 3nd operand) for
1021 instruction which is selected by the condition (the 2nd parameter).
1022 The first parameter is used for output of debugging information.
1023 The reservations are described by a regular expression according
1024 the following syntax:
1026 regexp = regexp "," oneof
1029 oneof = oneof "|" allof
1032 allof = allof "+" repeat
1035 repeat = element "*" number
1038 element = cpu_function_unit_name
1044 1. "," is used for describing start of the next cycle in
1047 2. "|" is used for describing the reservation described by the
1048 first regular expression *or* the reservation described by the
1049 second regular expression *or* etc.
1051 3. "+" is used for describing the reservation described by the
1052 first regular expression *and* the reservation described by the
1053 second regular expression *and* etc.
1055 4. "*" is used for convenience and simply means sequence in
1056 which the regular expression are repeated NUMBER times with
1057 cycle advancing (see ",").
1059 5. cpu functional unit name which means its reservation.
1061 6. reservation name -- see define_reservation.
1063 7. string "nothing" means no units reservation. */
1065 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1067 /* Expressions used for insn attributes. */
1069 /* Definition of an insn attribute.
1070 1st operand: name of the attribute
1071 2nd operand: comma-separated list of possible attribute values
1072 3rd operand: expression for the default value of the attribute. */
1073 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1075 /* Marker for the name of an attribute. */
1076 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1078 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1079 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1082 (set_attr "name" "value") is equivalent to
1083 (set (attr "name") (const_string "value")) */
1084 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1086 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1087 specify that attribute values are to be assigned according to the
1088 alternative matched.
1090 The following three expressions are equivalent:
1092 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1093 (eq_attrq "alternative" "2") (const_string "a2")]
1094 (const_string "a3")))
1095 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1096 (const_string "a3")])
1097 (set_attr "att" "a1,a2,a3")
1099 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1101 /* A conditional expression true if the value of the specified attribute of
1102 the current insn equals the specified value. The first operand is the
1103 attribute name and the second is the comparison value. */
1104 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1106 /* A special case of the above representing a set of alternatives. The first
1107 operand is bitmap of the set, the second one is the default value. */
1108 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1110 /* A conditional expression which is true if the specified flag is
1111 true for the insn being scheduled in reorg.
1113 genattr.c defines the following flags which can be tested by
1114 (attr_flag "foo") expressions in eligible_for_delay.
1116 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1118 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1120 /* General conditional. The first operand is a vector composed of pairs of
1121 expressions. The first element of each pair is evaluated, in turn.
1122 The value of the conditional is the second expression of the first pair
1123 whose first expression evaluates nonzero. If none of the expressions is
1124 true, the second operand will be used as the value of the conditional. */
1125 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1127 #endif /* GENERATOR_FILE */
OSDN Git Service
