1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
5 2005, 2006, 2007, 2008, 2009
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* Used in the cselib routines to describe a value. Objects of this
85 kind are only allocated in cselib.c, in an alloc pool instead of in
86 GC memory. The only operand of a VALUE is a cselib_val_struct.
87 var-tracking requires this to have a distinct integral value from
88 DECL codes in trees. */
89 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
91 /* ---------------------------------------------------------------------
92 Expressions used in constructing lists.
93 --------------------------------------------------------------------- */
95 /* a linked list of expressions */
96 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
98 /* a linked list of instructions.
99 The insns are represented in print by their uids. */
100 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
102 /* SEQUENCE appears in the result of a `gen_...' function
103 for a DEFINE_EXPAND that wants to make several insns.
104 Its elements are the bodies of the insns that should be made.
105 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
106 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
108 /* Refers to the address of its argument. This is only used in alias.c. */
109 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
111 /* ----------------------------------------------------------------------
112 Expression types used for things in the instruction chain.
114 All formats must start with "iuu" to handle the chain.
115 Each insn expression holds an rtl instruction and its semantics
116 during back-end processing.
117 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
119 ---------------------------------------------------------------------- */
121 /* An annotation for variable assignment tracking. */
122 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBieie", RTX_INSN)
124 /* An instruction that cannot jump. */
125 DEF_RTL_EXPR(INSN, "insn", "iuuBieie", RTX_INSN)
127 /* An instruction that can possibly jump.
128 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
129 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieie0", RTX_INSN)
131 /* An instruction that can possibly call a subroutine
132 but which will not change which instruction comes next
133 in the current function.
134 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
135 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
136 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieiee", RTX_INSN)
138 /* A marker that indicates that control will not flow through. */
139 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
141 /* Holds a label that is followed by instructions.
143 4: is used in jump.c for the use-count of the label.
144 5: is used in the sh backend.
145 6: is a number that is unique in the entire compilation.
146 7: is the user-given name of the label, if any. */
147 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
149 /* Say where in the code a source line starts, for symbol table's sake.
151 4: note-specific data
153 6: unique number if insn_note == note_insn_deleted_label. */
154 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
156 /* ----------------------------------------------------------------------
157 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
158 ---------------------------------------------------------------------- */
160 /* Conditionally execute code.
161 Operand 0 is the condition that if true, the code is executed.
162 Operand 1 is the code to be executed (typically a SET).
164 Semantics are that there are no side effects if the condition
165 is false. This pattern is created automatically by the if_convert
166 pass run after reload or by target-specific splitters. */
167 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
169 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
170 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
172 /* A string that is passed through to the assembler as input.
173 One can obviously pass comments through by using the
174 assembler comment syntax.
175 These occur in an insn all by themselves as the PATTERN.
176 They also appear inside an ASM_OPERANDS
177 as a convenient way to hold a string. */
178 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
180 /* An assembler instruction with operands.
181 1st operand is the instruction template.
182 2nd operand is the constraint for the output.
183 3rd operand is the number of the output this expression refers to.
184 When an insn stores more than one value, a separate ASM_OPERANDS
185 is made for each output; this integer distinguishes them.
186 4th is a vector of values of input operands.
187 5th is a vector of modes and constraints for the input operands.
188 Each element is an ASM_INPUT containing a constraint string
189 and whose mode indicates the mode of the input operand.
190 6th is a vector of labels that may be branched to by the asm.
191 7th is the source line number. */
192 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
194 /* A machine-specific operation.
195 1st operand is a vector of operands being used by the operation so that
196 any needed reloads can be done.
197 2nd operand is a unique value saying which of a number of machine-specific
198 operations is to be performed.
199 (Note that the vector must be the first operand because of the way that
200 genrecog.c record positions within an insn.)
202 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
203 or inside an expression.
204 UNSPEC by itself or as a component of a PARALLEL
205 is currently considered not deletable.
207 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
208 of a PARALLEL with USE.
210 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
212 /* Similar, but a volatile operation and one which may trap. */
213 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
215 /* Vector of addresses, stored as full words. */
216 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
217 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
219 /* Vector of address differences X0 - BASE, X1 - BASE, ...
220 First operand is BASE; the vector contains the X's.
221 The machine mode of this rtx says how much space to leave
222 for each difference and is adjusted by branch shortening if
223 CASE_VECTOR_SHORTEN_MODE is defined.
224 The third and fourth operands store the target labels with the
225 minimum and maximum addresses respectively.
226 The fifth operand stores flags for use by branch shortening.
227 Set at the start of shorten_branches:
228 min_align: the minimum alignment for any of the target labels.
229 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
230 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
231 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
232 min_after_base: true iff minimum address target label is after BASE.
233 max_after_base: true iff maximum address target label is after BASE.
234 Set by the actual branch shortening process:
235 offset_unsigned: true iff offsets have to be treated as unsigned.
236 scale: scaling that is necessary to make offsets fit into the mode.
238 The third, fourth and fifth operands are only valid when
239 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
242 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
244 /* Memory prefetch, with attributes supported on some targets.
245 Operand 1 is the address of the memory to fetch.
246 Operand 2 is 1 for a write access, 0 otherwise.
247 Operand 3 is the level of temporal locality; 0 means there is no
248 temporal locality and 1, 2, and 3 are for increasing levels of temporal
251 The attributes specified by operands 2 and 3 are ignored for targets
252 whose prefetch instructions do not support them. */
253 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
255 /* ----------------------------------------------------------------------
256 At the top level of an instruction (perhaps under PARALLEL).
257 ---------------------------------------------------------------------- */
260 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
261 Operand 2 is the value stored there.
262 ALL assignment must use SET.
263 Instructions that do multiple assignments must use multiple SET,
265 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
267 /* Indicate something is used in a way that we don't want to explain.
268 For example, subroutine calls will use the register
269 in which the static chain is passed.
271 USE can not appear as an operand of other rtx except for PARALLEL.
272 USE is not deletable, as it indicates that the operand
273 is used in some unknown way. */
274 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
276 /* Indicate something is clobbered in a way that we don't want to explain.
277 For example, subroutine calls will clobber some physical registers
278 (the ones that are by convention not saved).
280 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
281 CLOBBER of a hard register appearing by itself (not within PARALLEL)
282 is considered undeletable before reload. */
283 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
285 /* Call a subroutine.
286 Operand 1 is the address to call.
287 Operand 2 is the number of arguments. */
289 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
291 /* Return from a subroutine. */
293 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
295 /* Special for EH return from subroutine. */
297 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
300 Operand 1 is the condition.
301 Operand 2 is the trap code.
302 For an unconditional trap, make the condition (const_int 1). */
303 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
305 /* ----------------------------------------------------------------------
306 Primitive values for use in expressions.
307 ---------------------------------------------------------------------- */
309 /* numeric integer constant */
310 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
312 /* fixed-point constant */
313 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
315 /* numeric floating point constant.
316 Operands hold the value. They are all 'w' and there may be from 2 to 6;
318 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
320 /* Describes a vector constant. */
321 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
323 /* String constant. Used for attributes in machine descriptions and
324 for special cases in DWARF2 debug output. NOT used for source-
325 language string constants. */
326 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
328 /* This is used to encapsulate an expression whose value is constant
329 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
330 recognized as a constant operand rather than by arithmetic instructions. */
332 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
334 /* program counter. Ordinary jumps are represented
335 by a SET whose first operand is (PC). */
336 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
338 /* A register. The "operand" is the register number, accessed with
339 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
340 than a hardware register is being referred to. The second operand
341 holds the original register number - this will be different for a
342 pseudo register that got turned into a hard register. The third
343 operand points to a reg_attrs structure.
344 This rtx needs to have as many (or more) fields as a MEM, since we
345 can change REG rtx's into MEMs during reload. */
346 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
348 /* A scratch register. This represents a register used only within a
349 single insn. It will be turned into a REG during register allocation
350 or reload unless the constraint indicates that the register won't be
351 needed, in which case it can remain a SCRATCH. This code is
352 marked as having one operand so it can be turned into a REG. */
353 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
355 /* A reference to a part of another value. The first operand is the
356 complete value and the second is the byte offset of the selected part. */
357 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
359 /* This one-argument rtx is used for move instructions
360 that are guaranteed to alter only the low part of a destination.
361 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
362 has an unspecified effect on the high part of REG,
363 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
364 is guaranteed to alter only the bits of REG that are in HImode.
366 The actual instruction used is probably the same in both cases,
367 but the register constraints may be tighter when STRICT_LOW_PART
370 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
372 /* (CONCAT a b) represents the virtual concatenation of a and b
373 to make a value that has as many bits as a and b put together.
374 This is used for complex values. Normally it appears only
375 in DECL_RTLs and during RTL generation, but not in the insn chain. */
376 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
378 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
379 all An to make a value. This is an extension of CONCAT to larger
380 number of components. Like CONCAT, it should not appear in the
381 insn chain. Every element of the CONCATN is the same size. */
382 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
384 /* A memory location; operand is the address. The second operand is the
385 alias set to which this MEM belongs. We use `0' instead of `w' for this
386 field so that the field need not be specified in machine descriptions. */
387 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
389 /* Reference to an assembler label in the code for this function.
390 The operand is a CODE_LABEL found in the insn chain. */
391 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
393 /* Reference to a named label:
394 Operand 0: label name
395 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
396 Operand 2: tree from which this symbol is derived, or null.
397 This is either a DECL node, or some kind of constant. */
398 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
400 /* The condition code register is represented, in our imagination,
401 as a register holding a value that can be compared to zero.
402 In fact, the machine has already compared them and recorded the
403 results; but instructions that look at the condition code
404 pretend to be looking at the entire value and comparing it. */
405 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
407 /* ----------------------------------------------------------------------
408 Expressions for operators in an rtl pattern
409 ---------------------------------------------------------------------- */
411 /* if_then_else. This is used in representing ordinary
412 conditional jump instructions.
417 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
419 /* Comparison, produces a condition code result. */
420 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
423 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
425 /* Operand 0 minus operand 1. */
426 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
428 /* Minus operand 0. */
429 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
431 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
433 /* Multiplication with signed saturation */
434 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
435 /* Multiplication with unsigned saturation */
436 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
438 /* Operand 0 divided by operand 1. */
439 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
440 /* Division with signed saturation */
441 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
442 /* Division with unsigned saturation */
443 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
445 /* Remainder of operand 0 divided by operand 1. */
446 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
448 /* Unsigned divide and remainder. */
449 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
450 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
452 /* Bitwise operations. */
453 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
454 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
455 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
456 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
459 0: value to be shifted.
460 1: number of bits. */
461 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
462 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
463 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
464 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
465 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
467 /* Minimum and maximum values of two operands. We need both signed and
468 unsigned forms. (We cannot use MIN for SMIN because it conflicts
469 with a macro of the same name.) The signed variants should be used
470 with floating point. Further, if both operands are zeros, or if either
471 operand is NaN, then it is unspecified which of the two operands is
472 returned as the result. */
474 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
475 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
476 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
477 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
479 /* These unary operations are used to represent incrementation
480 and decrementation as they occur in memory addresses.
481 The amount of increment or decrement are not represented
482 because they can be understood from the machine-mode of the
483 containing MEM. These operations exist in only two cases:
484 1. pushes onto the stack.
485 2. created automatically by the life_analysis pass in flow.c. */
486 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
487 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
488 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
489 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
491 /* These binary operations are used to represent generic address
492 side-effects in memory addresses, except for simple incrementation
493 or decrementation which use the above operations. They are
494 created automatically by the life_analysis pass in flow.c.
495 The first operand is a REG which is used as the address.
496 The second operand is an expression that is assigned to the
497 register, either before (PRE_MODIFY) or after (POST_MODIFY)
498 evaluating the address.
499 Currently, the compiler can only handle second operands of the
500 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
501 the first operand of the PLUS has to be the same register as
502 the first operand of the *_MODIFY. */
503 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
504 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
506 /* Comparison operations. The ordered comparisons exist in two
507 flavors, signed and unsigned. */
508 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
509 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
510 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
511 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
512 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
513 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
514 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
515 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
516 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
517 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
519 /* Additional floating point unordered comparison flavors. */
520 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
521 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
523 /* These are equivalent to unordered or ... */
524 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
525 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
526 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
527 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
528 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
530 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
531 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
533 /* Represents the result of sign-extending the sole operand.
534 The machine modes of the operand and of the SIGN_EXTEND expression
535 determine how much sign-extension is going on. */
536 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
538 /* Similar for zero-extension (such as unsigned short to int). */
539 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
541 /* Similar but here the operand has a wider mode. */
542 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
544 /* Similar for extending floating-point values (such as SFmode to DFmode). */
545 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
546 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
548 /* Conversion of fixed point operand to floating point value. */
549 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
551 /* With fixed-point machine mode:
552 Conversion of floating point operand to fixed point value.
553 Value is defined only when the operand's value is an integer.
554 With floating-point machine mode (and operand with same mode):
555 Operand is rounded toward zero to produce an integer value
556 represented in floating point. */
557 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
559 /* Conversion of unsigned fixed point operand to floating point value. */
560 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
562 /* With fixed-point machine mode:
563 Conversion of floating point operand to *unsigned* fixed point value.
564 Value is defined only when the operand's value is an integer. */
565 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
567 /* Conversions involving fractional fixed-point types without saturation,
569 fractional to fractional (of different precision),
570 signed integer to fractional,
571 fractional to signed integer,
572 floating point to fractional,
573 fractional to floating point.
574 NOTE: fractional can be either signed or unsigned for conversions. */
575 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
577 /* Conversions involving fractional fixed-point types and unsigned integer
578 without saturation, including:
579 unsigned integer to fractional,
580 fractional to unsigned integer.
581 NOTE: fractional can be either signed or unsigned for conversions. */
582 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
584 /* Conversions involving fractional fixed-point types with saturation,
586 fractional to fractional (of different precision),
587 signed integer to fractional,
588 floating point to fractional.
589 NOTE: fractional can be either signed or unsigned for conversions. */
590 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
592 /* Conversions involving fractional fixed-point types and unsigned integer
593 with saturation, including:
594 unsigned integer to fractional.
595 NOTE: fractional can be either signed or unsigned for conversions. */
596 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
599 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
602 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
605 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
607 /* Find first bit that is set.
608 Value is 1 + number of trailing zeros in the arg.,
610 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
612 /* Count leading zeros. */
613 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
615 /* Count trailing zeros. */
616 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
618 /* Population count (number of 1 bits). */
619 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
621 /* Population parity (number of 1 bits modulo 2). */
622 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
624 /* Reference to a signed bit-field of specified size and position.
625 Operand 0 is the memory unit (usually SImode or QImode) which
626 contains the field's first bit. Operand 1 is the width, in bits.
627 Operand 2 is the number of bits in the memory unit before the
628 first bit of this field.
629 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
630 operand 2 counts from the msb of the memory unit.
631 Otherwise, the first bit is the lsb and operand 2 counts from
632 the lsb of the memory unit.
633 This kind of expression can not appear as an lvalue in RTL. */
634 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
636 /* Similar for unsigned bit-field.
637 But note! This kind of expression _can_ appear as an lvalue. */
638 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
640 /* For RISC machines. These save memory when splitting insns. */
642 /* HIGH are the high-order bits of a constant expression. */
643 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
645 /* LO_SUM is the sum of a register and the low-order bits
646 of a constant expression. */
647 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
649 /* Describes a merge operation between two vector values.
650 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
651 that specifies where the parts of the result are taken from. Set bits
652 indicate operand 0, clear bits indicate operand 1. The parts are defined
653 by the mode of the vectors. */
654 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
656 /* Describes an operation that selects parts of a vector.
657 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
658 a CONST_INT for each of the subparts of the result vector, giving the
659 number of the source subpart that should be stored into it. */
660 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
662 /* Describes a vector concat operation. Operands 0 and 1 are the source
663 vectors, the result is a vector that is as long as operands 0 and 1
664 combined and is the concatenation of the two source vectors. */
665 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
667 /* Describes an operation that converts a small vector into a larger one by
668 duplicating the input values. The output vector mode must have the same
669 submodes as the input vector mode, and the number of output parts must be
670 an integer multiple of the number of input parts. */
671 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
673 /* Addition with signed saturation */
674 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
676 /* Addition with unsigned saturation */
677 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
679 /* Operand 0 minus operand 1, with signed saturation. */
680 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
682 /* Negation with signed saturation. */
683 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
684 /* Negation with unsigned saturation. */
685 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
687 /* Absolute value with signed saturation. */
688 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
690 /* Shift left with signed saturation. */
691 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
693 /* Shift left with unsigned saturation. */
694 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
696 /* Operand 0 minus operand 1, with unsigned saturation. */
697 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
699 /* Signed saturating truncate. */
700 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
702 /* Unsigned saturating truncate. */
703 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
705 /* Information about the variable and its location. */
706 /* Changed 'te' to 'tei'; the 'i' field is for recording
707 initialization status of variables. */
708 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
710 /* All expressions from this point forward appear only in machine
712 #ifdef GENERATOR_FILE
714 /* Include a secondary machine-description file at this point. */
715 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
717 /* Pattern-matching operators: */
719 /* Use the function named by the second arg (the string)
720 as a predicate; if matched, store the structure that was matched
721 in the operand table at index specified by the first arg (the integer).
722 If the second arg is the null string, the structure is just stored.
724 A third string argument indicates to the register allocator restrictions
725 on where the operand can be allocated.
727 If the target needs no restriction on any instruction this field should
730 The string is prepended by:
731 '=' to indicate the operand is only written to.
732 '+' to indicate the operand is both read and written to.
734 Each character in the string represents an allocable class for an operand.
735 'g' indicates the operand can be any valid class.
736 'i' indicates the operand can be immediate (in the instruction) data.
737 'r' indicates the operand can be in a register.
738 'm' indicates the operand can be in memory.
739 'o' a subset of the 'm' class. Those memory addressing modes that
740 can be offset at compile time (have a constant added to them).
742 Other characters indicate target dependent operand classes and
743 are described in each target's machine description.
745 For instructions with more than one operand, sets of classes can be
746 separated by a comma to indicate the appropriate multi-operand constraints.
747 There must be a 1 to 1 correspondence between these sets of classes in
748 all operands for an instruction.
750 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
752 /* Match a SCRATCH or a register. When used to generate rtl, a
753 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
754 the desired mode and the first argument is the operand number.
755 The second argument is the constraint. */
756 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
758 /* Apply a predicate, AND match recursively the operands of the rtx.
759 Operand 0 is the operand-number, as in match_operand.
760 Operand 1 is a predicate to apply (as a string, a function name).
761 Operand 2 is a vector of expressions, each of which must match
762 one subexpression of the rtx this construct is matching. */
763 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
765 /* Match a PARALLEL of arbitrary length. The predicate is applied
766 to the PARALLEL and the initial expressions in the PARALLEL are matched.
767 Operand 0 is the operand-number, as in match_operand.
768 Operand 1 is a predicate to apply to the PARALLEL.
769 Operand 2 is a vector of expressions, each of which must match the
770 corresponding element in the PARALLEL. */
771 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
773 /* Match only something equal to what is stored in the operand table
774 at the index specified by the argument. Use with MATCH_OPERAND. */
775 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
777 /* Match only something equal to what is stored in the operand table
778 at the index specified by the argument. Use with MATCH_OPERATOR. */
779 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
781 /* Match only something equal to what is stored in the operand table
782 at the index specified by the argument. Use with MATCH_PARALLEL. */
783 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
785 /* Appears only in define_predicate/define_special_predicate
786 expressions. Evaluates true only if the operand has an RTX code
787 from the set given by the argument (a comma-separated list). If the
788 second argument is present and nonempty, it is a sequence of digits
789 and/or letters which indicates the subexpression to test, using the
790 same syntax as genextract/genrecog's location strings: 0-9 for
791 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
792 the result of the one before it. */
793 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
795 /* Appears only in define_predicate/define_special_predicate
796 expressions. The argument is a C expression to be injected at this
797 point in the predicate formula. */
798 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
800 /* Insn (and related) definitions. */
802 /* Definition of the pattern for one kind of instruction.
804 0: names this instruction.
805 If the name is the null string, the instruction is in the
806 machine description just to be recognized, and will never be emitted by
807 the tree to rtl expander.
809 2: is a string which is a C expression
810 giving an additional condition for recognizing this pattern.
811 A null string means no extra condition.
812 3: is the action to execute if this pattern is matched.
813 If this assembler code template starts with a * then it is a fragment of
814 C code to run to decide on a template to use. Otherwise, it is the
816 4: optionally, a vector of attributes for this insn.
818 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
820 /* Definition of a peephole optimization.
821 1st operand: vector of insn patterns to match
822 2nd operand: C expression that must be true
823 3rd operand: template or C code to produce assembler output.
824 4: optionally, a vector of attributes for this insn.
826 This form is deprecated; use define_peephole2 instead. */
827 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
829 /* Definition of a split operation.
830 1st operand: insn pattern to match
831 2nd operand: C expression that must be true
832 3rd operand: vector of insn patterns to place into a SEQUENCE
833 4th operand: optionally, some C code to execute before generating the
834 insns. This might, for example, create some RTX's and store them in
835 elements of `recog_data.operand' for use by the vector of
837 (`operands' is an alias here for `recog_data.operand'). */
838 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
840 /* Definition of an insn and associated split.
841 This is the concatenation, with a few modifications, of a define_insn
842 and a define_split which share the same pattern.
844 0: names this instruction.
845 If the name is the null string, the instruction is in the
846 machine description just to be recognized, and will never be emitted by
847 the tree to rtl expander.
849 2: is a string which is a C expression
850 giving an additional condition for recognizing this pattern.
851 A null string means no extra condition.
852 3: is the action to execute if this pattern is matched.
853 If this assembler code template starts with a * then it is a fragment of
854 C code to run to decide on a template to use. Otherwise, it is the
856 4: C expression that must be true for split. This may start with "&&"
857 in which case the split condition is the logical and of the insn
858 condition and what follows the "&&" of this operand.
859 5: vector of insn patterns to place into a SEQUENCE
860 6: optionally, some C code to execute before generating the
861 insns. This might, for example, create some RTX's and store them in
862 elements of `recog_data.operand' for use by the vector of
864 (`operands' is an alias here for `recog_data.operand').
865 7: optionally, a vector of attributes for this insn. */
866 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
868 /* Definition of an RTL peephole operation.
869 Follows the same arguments as define_split. */
870 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
872 /* Define how to generate multiple insns for a standard insn name.
873 1st operand: the insn name.
874 2nd operand: vector of insn-patterns.
875 Use match_operand to substitute an element of `recog_data.operand'.
876 3rd operand: C expression that must be true for this to be available.
877 This may not test any operands.
878 4th operand: Extra C code to execute before generating the insns.
879 This might, for example, create some RTX's and store them in
880 elements of `recog_data.operand' for use by the vector of
882 (`operands' is an alias here for `recog_data.operand'). */
883 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
885 /* Define a requirement for delay slots.
886 1st operand: Condition involving insn attributes that, if true,
887 indicates that the insn requires the number of delay slots
889 2nd operand: Vector whose length is the three times the number of delay
891 Each entry gives three conditions, each involving attributes.
892 The first must be true for an insn to occupy that delay slot
893 location. The second is true for all insns that can be
894 annulled if the branch is true and the third is true for all
895 insns that can be annulled if the branch is false.
897 Multiple DEFINE_DELAYs may be present. They indicate differing
898 requirements for delay slots. */
899 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
901 /* Define attribute computation for `asm' instructions. */
902 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
904 /* Definition of a conditional execution meta operation. Automatically
905 generates new instances of DEFINE_INSN, selected by having attribute
906 "predicable" true. The new pattern will contain a COND_EXEC and the
907 predicate at top-level.
910 0: The predicate pattern. The top-level form should match a
911 relational operator. Operands should have only one alternative.
912 1: A C expression giving an additional condition for recognizing
913 the generated pattern.
914 2: A template or C code to produce assembler output. */
915 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
917 /* Definition of an operand predicate. The difference between
918 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
919 not warn about a match_operand with no mode if it has a predicate
920 defined with DEFINE_SPECIAL_PREDICATE.
923 0: The name of the predicate.
924 1: A boolean expression which computes whether or not the predicate
925 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
926 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
927 can calculate the set of RTX codes that can possibly match.
928 2: A C function body which must return true for the predicate to match.
929 Optional. Use this when the test is too complicated to fit into a
930 match_test expression. */
931 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
932 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
934 /* Definition of a register operand constraint. This simply maps the
935 constraint string to a register class.
938 0: The name of the constraint (often, but not always, a single letter).
939 1: A C expression which evaluates to the appropriate register class for
940 this constraint. If this is not just a constant, it should look only
941 at -m switches and the like.
942 2: A docstring for this constraint, in Texinfo syntax; not currently
943 used, in future will be incorporated into the manual's list of
944 machine-specific operand constraints. */
945 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
947 /* Definition of a non-register operand constraint. These look at the
948 operand and decide whether it fits the constraint.
950 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
951 It is appropriate for constant-only constraints, and most others.
953 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
954 to match, if it doesn't already, by converting the operand to the form
955 (mem (reg X)) where X is a base register. It is suitable for constraints
956 that describe a subset of all memory references.
958 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
959 to match, if it doesn't already, by converting the operand to the form
960 (reg X) where X is a base register. It is suitable for constraints that
961 describe a subset of all address references.
963 When in doubt, use plain DEFINE_CONSTRAINT.
966 0: The name of the constraint (often, but not always, a single letter).
967 1: A docstring for this constraint, in Texinfo syntax; not currently
968 used, in future will be incorporated into the manual's list of
969 machine-specific operand constraints.
970 2: A boolean expression which computes whether or not the constraint
971 matches. It should follow the same rules as a define_predicate
972 expression, including the bit about specifying the set of RTX codes
973 that could possibly match. MATCH_TEST subexpressions may make use of
975 `op' - the RTL object defining the operand.
976 `mode' - the mode of `op'.
977 `ival' - INTVAL(op), if op is a CONST_INT.
978 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
979 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
980 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
982 Do not use ival/hval/lval/rval if op is not the appropriate kind of
984 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
985 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
986 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
989 /* Constructions for CPU pipeline description described by NDFAs. */
991 /* (define_cpu_unit string [string]) describes cpu functional
992 units (separated by comma).
994 1st operand: Names of cpu functional units.
995 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
997 All define_reservations, define_cpu_units, and
998 define_query_cpu_units should have unique names which may not be
1000 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1002 /* (define_query_cpu_unit string [string]) describes cpu functional
1003 units analogously to define_cpu_unit. The reservation of such
1004 units can be queried for automaton state. */
1005 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1007 /* (exclusion_set string string) means that each CPU functional unit
1008 in the first string can not be reserved simultaneously with any
1009 unit whose name is in the second string and vise versa. CPU units
1010 in the string are separated by commas. For example, it is useful
1011 for description CPU with fully pipelined floating point functional
1012 unit which can execute simultaneously only single floating point
1013 insns or only double floating point insns. All CPU functional
1014 units in a set should belong to the same automaton. */
1015 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1017 /* (presence_set string string) means that each CPU functional unit in
1018 the first string can not be reserved unless at least one of pattern
1019 of units whose names are in the second string is reserved. This is
1020 an asymmetric relation. CPU units or unit patterns in the strings
1021 are separated by commas. Pattern is one unit name or unit names
1022 separated by white-spaces.
1024 For example, it is useful for description that slot1 is reserved
1025 after slot0 reservation for a VLIW processor. We could describe it
1026 by the following construction
1028 (presence_set "slot1" "slot0")
1030 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1031 this case we could write
1033 (presence_set "slot1" "slot0 b0")
1035 All CPU functional units in a set should belong to the same
1037 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1039 /* (final_presence_set string string) is analogous to `presence_set'.
1040 The difference between them is when checking is done. When an
1041 instruction is issued in given automaton state reflecting all
1042 current and planned unit reservations, the automaton state is
1043 changed. The first state is a source state, the second one is a
1044 result state. Checking for `presence_set' is done on the source
1045 state reservation, checking for `final_presence_set' is done on the
1046 result reservation. This construction is useful to describe a
1047 reservation which is actually two subsequent reservations. For
1050 (presence_set "slot1" "slot0")
1052 the following insn will be never issued (because slot1 requires
1053 slot0 which is absent in the source state).
1055 (define_reservation "insn_and_nop" "slot0 + slot1")
1057 but it can be issued if we use analogous `final_presence_set'. */
1058 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1060 /* (absence_set string string) means that each CPU functional unit in
1061 the first string can be reserved only if each pattern of units
1062 whose names are in the second string is not reserved. This is an
1063 asymmetric relation (actually exclusion set is analogous to this
1064 one but it is symmetric). CPU units or unit patterns in the string
1065 are separated by commas. Pattern is one unit name or unit names
1066 separated by white-spaces.
1068 For example, it is useful for description that slot0 can not be
1069 reserved after slot1 or slot2 reservation for a VLIW processor. We
1070 could describe it by the following construction
1072 (absence_set "slot2" "slot0, slot1")
1074 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1075 slot1 and unit b1 are reserved . In this case we could write
1077 (absence_set "slot2" "slot0 b0, slot1 b1")
1079 All CPU functional units in a set should to belong the same
1081 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1083 /* (final_absence_set string string) is analogous to `absence_set' but
1084 checking is done on the result (state) reservation. See comments
1085 for `final_presence_set'. */
1086 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1088 /* (define_bypass number out_insn_names in_insn_names) names bypass
1089 with given latency (the first number) from insns given by the first
1090 string (see define_insn_reservation) into insns given by the second
1091 string. Insn names in the strings are separated by commas. The
1092 third operand is optional name of function which is additional
1093 guard for the bypass. The function will get the two insns as
1094 parameters. If the function returns zero the bypass will be
1095 ignored for this case. Additional guard is necessary to recognize
1096 complicated bypasses, e.g. when consumer is load address. If there
1097 are more one bypass with the same output and input insns, the
1098 chosen bypass is the first bypass with a guard in description whose
1099 guard function returns nonzero. If there is no such bypass, then
1100 bypass without the guard function is chosen. */
1101 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1103 /* (define_automaton string) describes names of automata generated and
1104 used for pipeline hazards recognition. The names are separated by
1105 comma. Actually it is possibly to generate the single automaton
1106 but unfortunately it can be very large. If we use more one
1107 automata, the summary size of the automata usually is less than the
1108 single one. The automaton name is used in define_cpu_unit and
1109 define_query_cpu_unit. All automata should have unique names. */
1110 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1112 /* (automata_option string) describes option for generation of
1113 automata. Currently there are the following options:
1115 o "no-minimization" which makes no minimization of automata. This
1116 is only worth to do when we are debugging the description and
1117 need to look more accurately at reservations of states.
1119 o "time" which means printing additional time statistics about
1120 generation of automata.
1122 o "v" which means generation of file describing the result
1123 automata. The file has suffix `.dfa' and can be used for the
1124 description verification and debugging.
1126 o "w" which means generation of warning instead of error for
1127 non-critical errors.
1129 o "ndfa" which makes nondeterministic finite state automata.
1131 o "progress" which means output of a progress bar showing how many
1132 states were generated so far for automaton being processed. */
1133 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1135 /* (define_reservation string string) names reservation (the first
1136 string) of cpu functional units (the 2nd string). Sometimes unit
1137 reservations for different insns contain common parts. In such
1138 case, you can describe common part and use its name (the 1st
1139 parameter) in regular expression in define_insn_reservation. All
1140 define_reservations, define_cpu_units, and define_query_cpu_units
1141 should have unique names which may not be "nothing". */
1142 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1144 /* (define_insn_reservation name default_latency condition regexpr)
1145 describes reservation of cpu functional units (the 3nd operand) for
1146 instruction which is selected by the condition (the 2nd parameter).
1147 The first parameter is used for output of debugging information.
1148 The reservations are described by a regular expression according
1149 the following syntax:
1151 regexp = regexp "," oneof
1154 oneof = oneof "|" allof
1157 allof = allof "+" repeat
1160 repeat = element "*" number
1163 element = cpu_function_unit_name
1169 1. "," is used for describing start of the next cycle in
1172 2. "|" is used for describing the reservation described by the
1173 first regular expression *or* the reservation described by the
1174 second regular expression *or* etc.
1176 3. "+" is used for describing the reservation described by the
1177 first regular expression *and* the reservation described by the
1178 second regular expression *and* etc.
1180 4. "*" is used for convenience and simply means sequence in
1181 which the regular expression are repeated NUMBER times with
1182 cycle advancing (see ",").
1184 5. cpu functional unit name which means its reservation.
1186 6. reservation name -- see define_reservation.
1188 7. string "nothing" means no units reservation. */
1190 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1192 /* Expressions used for insn attributes. */
1194 /* Definition of an insn attribute.
1195 1st operand: name of the attribute
1196 2nd operand: comma-separated list of possible attribute values
1197 3rd operand: expression for the default value of the attribute. */
1198 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1200 /* Marker for the name of an attribute. */
1201 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1203 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1204 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1207 (set_attr "name" "value") is equivalent to
1208 (set (attr "name") (const_string "value")) */
1209 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1211 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1212 specify that attribute values are to be assigned according to the
1213 alternative matched.
1215 The following three expressions are equivalent:
1217 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1218 (eq_attrq "alternative" "2") (const_string "a2")]
1219 (const_string "a3")))
1220 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1221 (const_string "a3")])
1222 (set_attr "att" "a1,a2,a3")
1224 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1226 /* A conditional expression true if the value of the specified attribute of
1227 the current insn equals the specified value. The first operand is the
1228 attribute name and the second is the comparison value. */
1229 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1231 /* A special case of the above representing a set of alternatives. The first
1232 operand is bitmap of the set, the second one is the default value. */
1233 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1235 /* A conditional expression which is true if the specified flag is
1236 true for the insn being scheduled in reorg.
1238 genattr.c defines the following flags which can be tested by
1239 (attr_flag "foo") expressions in eligible_for_delay.
1241 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1243 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1245 /* General conditional. The first operand is a vector composed of pairs of
1246 expressions. The first element of each pair is evaluated, in turn.
1247 The value of the conditional is the second expression of the first pair
1248 whose first expression evaluates nonzero. If none of the expressions is
1249 true, the second operand will be used as the value of the conditional. */
1250 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1252 #endif /* GENERATOR_FILE */
OSDN Git Service
