1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
124 int reg_equiv_init_size;
126 /* Vector to remember old contents of reg_renumber before spilling. */
127 static short *reg_old_renumber;
129 /* During reload_as_needed, element N contains the last pseudo regno reloaded
130 into hard register N. If that pseudo reg occupied more than one register,
131 reg_reloaded_contents points to that pseudo for each spill register in
132 use; all of these must remain set for an inheritance to occur. */
133 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
135 /* During reload_as_needed, element N contains the insn for which
136 hard register N was last used. Its contents are significant only
137 when reg_reloaded_valid is set for this register. */
138 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
140 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
141 static HARD_REG_SET reg_reloaded_valid;
142 /* Indicate if the register was dead at the end of the reload.
143 This is only valid if reg_reloaded_contents is set and valid. */
144 static HARD_REG_SET reg_reloaded_dead;
146 /* Indicate whether the register's current value is one that is not
147 safe to retain across a call, even for registers that are normally
149 static HARD_REG_SET reg_reloaded_call_part_clobbered;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 static struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 static char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 static char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 /* List of insn_chain instructions, one for every insn that reload needs to
288 struct insn_chain *reload_insn_chain;
290 /* List of all insns needing reloads. */
291 static struct insn_chain *insns_need_reload;
293 /* This structure is used to record information about register eliminations.
294 Each array entry describes one possible way of eliminating a register
295 in favor of another. If there is more than one way of eliminating a
296 particular register, the most preferred should be specified first. */
300 int from; /* Register number to be eliminated. */
301 int to; /* Register number used as replacement. */
302 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
303 int can_eliminate; /* Nonzero if this elimination can be done. */
304 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
305 insns made by reload. */
306 HOST_WIDE_INT offset; /* Current offset between the two regs. */
307 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
308 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
309 rtx from_rtx; /* REG rtx for the register to be eliminated.
310 We cannot simply compare the number since
311 we might then spuriously replace a hard
312 register corresponding to a pseudo
313 assigned to the reg to be eliminated. */
314 rtx to_rtx; /* REG rtx for the replacement. */
317 static struct elim_table *reg_eliminate = 0;
319 /* This is an intermediate structure to initialize the table. It has
320 exactly the members provided by ELIMINABLE_REGS. */
321 static const struct elim_table_1
325 } reg_eliminate_1[] =
327 /* If a set of eliminable registers was specified, define the table from it.
328 Otherwise, default to the normal case of the frame pointer being
329 replaced by the stack pointer. */
331 #ifdef ELIMINABLE_REGS
334 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
337 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
339 /* Record the number of pending eliminations that have an offset not equal
340 to their initial offset. If nonzero, we use a new copy of each
341 replacement result in any insns encountered. */
342 int num_not_at_initial_offset;
344 /* Count the number of registers that we may be able to eliminate. */
345 static int num_eliminable;
346 /* And the number of registers that are equivalent to a constant that
347 can be eliminated to frame_pointer / arg_pointer + constant. */
348 static int num_eliminable_invariants;
350 /* For each label, we record the offset of each elimination. If we reach
351 a label by more than one path and an offset differs, we cannot do the
352 elimination. This information is indexed by the difference of the
353 number of the label and the first label number. We can't offset the
354 pointer itself as this can cause problems on machines with segmented
355 memory. The first table is an array of flags that records whether we
356 have yet encountered a label and the second table is an array of arrays,
357 one entry in the latter array for each elimination. */
359 static int first_label_num;
360 static char *offsets_known_at;
361 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
363 /* Number of labels in the current function. */
365 static int num_labels;
367 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
368 static void maybe_fix_stack_asms (void);
369 static void copy_reloads (struct insn_chain *);
370 static void calculate_needs_all_insns (int);
371 static int find_reg (struct insn_chain *, int);
372 static void find_reload_regs (struct insn_chain *);
373 static void select_reload_regs (void);
374 static void delete_caller_save_insns (void);
376 static void spill_failure (rtx, enum reg_class);
377 static void count_spilled_pseudo (int, int, int);
378 static void delete_dead_insn (rtx);
379 static void alter_reg (int, int);
380 static void set_label_offsets (rtx, rtx, int);
381 static void check_eliminable_occurrences (rtx);
382 static void elimination_effects (rtx, enum machine_mode);
383 static int eliminate_regs_in_insn (rtx, int);
384 static void update_eliminable_offsets (void);
385 static void mark_not_eliminable (rtx, rtx, void *);
386 static void set_initial_elim_offsets (void);
387 static bool verify_initial_elim_offsets (void);
388 static void set_initial_label_offsets (void);
389 static void set_offsets_for_label (rtx);
390 static void init_elim_table (void);
391 static void update_eliminables (HARD_REG_SET *);
392 static void spill_hard_reg (unsigned int, int);
393 static int finish_spills (int);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
698 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
699 reg_old_renumber = xcalloc (max_regno, sizeof (short));
700 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
701 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
702 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
704 CLEAR_HARD_REG_SET (bad_spill_regs_global);
706 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
707 to. Also find all paradoxical subregs and find largest such for
710 num_eliminable_invariants = 0;
711 for (insn = first; insn; insn = NEXT_INSN (insn))
713 rtx set = single_set (insn);
715 /* We may introduce USEs that we want to remove at the end, so
716 we'll mark them with QImode. Make sure there are no
717 previously-marked insns left by say regmove. */
718 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
719 && GET_MODE (insn) != VOIDmode)
720 PUT_MODE (insn, VOIDmode);
723 scan_paradoxical_subregs (PATTERN (insn));
725 if (set != 0 && REG_P (SET_DEST (set)))
727 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
733 i = REGNO (SET_DEST (set));
736 if (i <= LAST_VIRTUAL_REGISTER)
739 if (! function_invariant_p (x)
741 /* A function invariant is often CONSTANT_P but may
742 include a register. We promise to only pass
743 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
745 && LEGITIMATE_PIC_OPERAND_P (x)))
747 /* It can happen that a REG_EQUIV note contains a MEM
748 that is not a legitimate memory operand. As later
749 stages of reload assume that all addresses found
750 in the reg_equiv_* arrays were originally legitimate,
751 we ignore such REG_EQUIV notes. */
752 if (memory_operand (x, VOIDmode))
754 /* Always unshare the equivalence, so we can
755 substitute into this insn without touching the
757 reg_equiv_memory_loc[i] = copy_rtx (x);
759 else if (function_invariant_p (x))
761 if (GET_CODE (x) == PLUS)
763 /* This is PLUS of frame pointer and a constant,
764 and might be shared. Unshare it. */
765 reg_equiv_constant[i] = copy_rtx (x);
766 num_eliminable_invariants++;
768 else if (x == frame_pointer_rtx
769 || x == arg_pointer_rtx)
771 reg_equiv_constant[i] = x;
772 num_eliminable_invariants++;
774 else if (LEGITIMATE_CONSTANT_P (x))
775 reg_equiv_constant[i] = x;
778 reg_equiv_memory_loc[i]
779 = force_const_mem (GET_MODE (SET_DEST (set)), x);
780 if (! reg_equiv_memory_loc[i])
781 reg_equiv_init[i] = NULL_RTX;
786 reg_equiv_init[i] = NULL_RTX;
791 reg_equiv_init[i] = NULL_RTX;
796 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
797 if (reg_equiv_init[i])
799 fprintf (dump_file, "init_insns for %u: ", i);
800 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
801 fprintf (dump_file, "\n");
806 first_label_num = get_first_label_num ();
807 num_labels = max_label_num () - first_label_num;
809 /* Allocate the tables used to store offset information at labels. */
810 /* We used to use alloca here, but the size of what it would try to
811 allocate would occasionally cause it to exceed the stack limit and
812 cause a core dump. */
813 offsets_known_at = xmalloc (num_labels);
814 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
816 /* Alter each pseudo-reg rtx to contain its hard reg number.
817 Assign stack slots to the pseudos that lack hard regs or equivalents.
818 Do not touch virtual registers. */
820 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
823 /* If we have some registers we think can be eliminated, scan all insns to
824 see if there is an insn that sets one of these registers to something
825 other than itself plus a constant. If so, the register cannot be
826 eliminated. Doing this scan here eliminates an extra pass through the
827 main reload loop in the most common case where register elimination
829 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
831 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
833 maybe_fix_stack_asms ();
835 insns_need_reload = 0;
836 something_needs_elimination = 0;
838 /* Initialize to -1, which means take the first spill register. */
841 /* Spill any hard regs that we know we can't eliminate. */
842 CLEAR_HARD_REG_SET (used_spill_regs);
843 /* There can be multiple ways to eliminate a register;
844 they should be listed adjacently.
845 Elimination for any register fails only if all possible ways fail. */
846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
849 int can_eliminate = 0;
852 can_eliminate |= ep->can_eliminate;
855 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
857 spill_hard_reg (from, 1);
860 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
861 if (frame_pointer_needed)
862 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
864 finish_spills (global);
866 /* From now on, we may need to generate moves differently. We may also
867 allow modifications of insns which cause them to not be recognized.
868 Any such modifications will be cleaned up during reload itself. */
869 reload_in_progress = 1;
871 /* This loop scans the entire function each go-round
872 and repeats until one repetition spills no additional hard regs. */
875 int something_changed;
878 HOST_WIDE_INT starting_frame_size;
880 /* Round size of stack frame to stack_alignment_needed. This must be done
881 here because the stack size may be a part of the offset computation
882 for register elimination, and there might have been new stack slots
883 created in the last iteration of this loop. */
884 if (cfun->stack_alignment_needed)
885 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
887 starting_frame_size = get_frame_size ();
889 set_initial_elim_offsets ();
890 set_initial_label_offsets ();
892 /* For each pseudo register that has an equivalent location defined,
893 try to eliminate any eliminable registers (such as the frame pointer)
894 assuming initial offsets for the replacement register, which
897 If the resulting location is directly addressable, substitute
898 the MEM we just got directly for the old REG.
900 If it is not addressable but is a constant or the sum of a hard reg
901 and constant, it is probably not addressable because the constant is
902 out of range, in that case record the address; we will generate
903 hairy code to compute the address in a register each time it is
904 needed. Similarly if it is a hard register, but one that is not
905 valid as an address register.
907 If the location is not addressable, but does not have one of the
908 above forms, assign a stack slot. We have to do this to avoid the
909 potential of producing lots of reloads if, e.g., a location involves
910 a pseudo that didn't get a hard register and has an equivalent memory
911 location that also involves a pseudo that didn't get a hard register.
913 Perhaps at some point we will improve reload_when_needed handling
914 so this problem goes away. But that's very hairy. */
916 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
917 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
919 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
921 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
923 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
924 else if (CONSTANT_P (XEXP (x, 0))
925 || (REG_P (XEXP (x, 0))
926 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
927 || (GET_CODE (XEXP (x, 0)) == PLUS
928 && REG_P (XEXP (XEXP (x, 0), 0))
929 && (REGNO (XEXP (XEXP (x, 0), 0))
930 < FIRST_PSEUDO_REGISTER)
931 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
932 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
935 /* Make a new stack slot. Then indicate that something
936 changed so we go back and recompute offsets for
937 eliminable registers because the allocation of memory
938 below might change some offset. reg_equiv_{mem,address}
939 will be set up for this pseudo on the next pass around
941 reg_equiv_memory_loc[i] = 0;
942 reg_equiv_init[i] = 0;
947 if (caller_save_needed)
950 /* If we allocated another stack slot, redo elimination bookkeeping. */
951 if (starting_frame_size != get_frame_size ())
954 if (caller_save_needed)
956 save_call_clobbered_regs ();
957 /* That might have allocated new insn_chain structures. */
958 reload_firstobj = obstack_alloc (&reload_obstack, 0);
961 calculate_needs_all_insns (global);
963 CLEAR_REG_SET (&spilled_pseudos);
966 something_changed = 0;
968 /* If we allocated any new memory locations, make another pass
969 since it might have changed elimination offsets. */
970 if (starting_frame_size != get_frame_size ())
971 something_changed = 1;
973 /* Even if the frame size remained the same, we might still have
974 changed elimination offsets, e.g. if find_reloads called
975 force_const_mem requiring the back end to allocate a constant
976 pool base register that needs to be saved on the stack. */
977 else if (!verify_initial_elim_offsets ())
978 something_changed = 1;
981 HARD_REG_SET to_spill;
982 CLEAR_HARD_REG_SET (to_spill);
983 update_eliminables (&to_spill);
984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
985 if (TEST_HARD_REG_BIT (to_spill, i))
987 spill_hard_reg (i, 1);
990 /* Regardless of the state of spills, if we previously had
991 a register that we thought we could eliminate, but now can
992 not eliminate, we must run another pass.
994 Consider pseudos which have an entry in reg_equiv_* which
995 reference an eliminable register. We must make another pass
996 to update reg_equiv_* so that we do not substitute in the
997 old value from when we thought the elimination could be
999 something_changed = 1;
1003 select_reload_regs ();
1007 if (insns_need_reload != 0 || did_spill)
1008 something_changed |= finish_spills (global);
1010 if (! something_changed)
1013 if (caller_save_needed)
1014 delete_caller_save_insns ();
1016 obstack_free (&reload_obstack, reload_firstobj);
1019 /* If global-alloc was run, notify it of any register eliminations we have
1022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1023 if (ep->can_eliminate)
1024 mark_elimination (ep->from, ep->to);
1026 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1027 If that insn didn't set the register (i.e., it copied the register to
1028 memory), just delete that insn instead of the equivalencing insn plus
1029 anything now dead. If we call delete_dead_insn on that insn, we may
1030 delete the insn that actually sets the register if the register dies
1031 there and that is incorrect. */
1033 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1035 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1038 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1040 rtx equiv_insn = XEXP (list, 0);
1042 /* If we already deleted the insn or if it may trap, we can't
1043 delete it. The latter case shouldn't happen, but can
1044 if an insn has a variable address, gets a REG_EH_REGION
1045 note added to it, and then gets converted into an load
1046 from a constant address. */
1047 if (NOTE_P (equiv_insn)
1048 || can_throw_internal (equiv_insn))
1050 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1051 delete_dead_insn (equiv_insn);
1053 SET_INSN_DELETED (equiv_insn);
1058 /* Use the reload registers where necessary
1059 by generating move instructions to move the must-be-register
1060 values into or out of the reload registers. */
1062 if (insns_need_reload != 0 || something_needs_elimination
1063 || something_needs_operands_changed)
1065 HOST_WIDE_INT old_frame_size = get_frame_size ();
1067 reload_as_needed (global);
1069 gcc_assert (old_frame_size == get_frame_size ());
1071 gcc_assert (verify_initial_elim_offsets ());
1074 /* If we were able to eliminate the frame pointer, show that it is no
1075 longer live at the start of any basic block. If it ls live by
1076 virtue of being in a pseudo, that pseudo will be marked live
1077 and hence the frame pointer will be known to be live via that
1080 if (! frame_pointer_needed)
1082 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1083 HARD_FRAME_POINTER_REGNUM);
1085 /* Come here (with failure set nonzero) if we can't get enough spill
1089 CLEAR_REG_SET (&spilled_pseudos);
1090 reload_in_progress = 0;
1092 /* Now eliminate all pseudo regs by modifying them into
1093 their equivalent memory references.
1094 The REG-rtx's for the pseudos are modified in place,
1095 so all insns that used to refer to them now refer to memory.
1097 For a reg that has a reg_equiv_address, all those insns
1098 were changed by reloading so that no insns refer to it any longer;
1099 but the DECL_RTL of a variable decl may refer to it,
1100 and if so this causes the debugging info to mention the variable. */
1102 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1106 if (reg_equiv_mem[i])
1107 addr = XEXP (reg_equiv_mem[i], 0);
1109 if (reg_equiv_address[i])
1110 addr = reg_equiv_address[i];
1114 if (reg_renumber[i] < 0)
1116 rtx reg = regno_reg_rtx[i];
1118 REG_USERVAR_P (reg) = 0;
1119 PUT_CODE (reg, MEM);
1120 XEXP (reg, 0) = addr;
1121 if (reg_equiv_memory_loc[i])
1122 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1125 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1126 MEM_ATTRS (reg) = 0;
1129 else if (reg_equiv_mem[i])
1130 XEXP (reg_equiv_mem[i], 0) = addr;
1134 /* We must set reload_completed now since the cleanup_subreg_operands call
1135 below will re-recognize each insn and reload may have generated insns
1136 which are only valid during and after reload. */
1137 reload_completed = 1;
1139 /* Make a pass over all the insns and delete all USEs which we inserted
1140 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1141 notes. Delete all CLOBBER insns, except those that refer to the return
1142 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1143 from misarranging variable-array code, and simplify (subreg (reg))
1144 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1145 are no longer useful or accurate. Strip and regenerate REG_INC notes
1146 that may have been moved around. */
1148 for (insn = first; insn; insn = NEXT_INSN (insn))
1154 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1155 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1157 if ((GET_CODE (PATTERN (insn)) == USE
1158 /* We mark with QImode USEs introduced by reload itself. */
1159 && (GET_MODE (insn) == QImode
1160 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1161 || (GET_CODE (PATTERN (insn)) == CLOBBER
1162 && (!MEM_P (XEXP (PATTERN (insn), 0))
1163 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1164 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1165 && XEXP (XEXP (PATTERN (insn), 0), 0)
1166 != stack_pointer_rtx))
1167 && (!REG_P (XEXP (PATTERN (insn), 0))
1168 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1174 /* Some CLOBBERs may survive until here and still reference unassigned
1175 pseudos with const equivalent, which may in turn cause ICE in later
1176 passes if the reference remains in place. */
1177 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1178 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1179 VOIDmode, PATTERN (insn));
1181 /* Discard obvious no-ops, even without -O. This optimization
1182 is fast and doesn't interfere with debugging. */
1183 if (NONJUMP_INSN_P (insn)
1184 && GET_CODE (PATTERN (insn)) == SET
1185 && REG_P (SET_SRC (PATTERN (insn)))
1186 && REG_P (SET_DEST (PATTERN (insn)))
1187 && (REGNO (SET_SRC (PATTERN (insn)))
1188 == REGNO (SET_DEST (PATTERN (insn)))))
1194 pnote = ®_NOTES (insn);
1197 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1198 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1199 || REG_NOTE_KIND (*pnote) == REG_INC
1200 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1201 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1202 *pnote = XEXP (*pnote, 1);
1204 pnote = &XEXP (*pnote, 1);
1208 add_auto_inc_notes (insn, PATTERN (insn));
1211 /* And simplify (subreg (reg)) if it appears as an operand. */
1212 cleanup_subreg_operands (insn);
1215 /* If we are doing stack checking, give a warning if this function's
1216 frame size is larger than we expect. */
1217 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1219 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1220 static int verbose_warned = 0;
1222 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1223 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1224 size += UNITS_PER_WORD;
1226 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1228 warning (0, "frame size too large for reliable stack checking");
1229 if (! verbose_warned)
1231 warning (0, "try reducing the number of local variables");
1237 /* Indicate that we no longer have known memory locations or constants. */
1238 if (reg_equiv_constant)
1239 free (reg_equiv_constant);
1240 reg_equiv_constant = 0;
1241 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1242 reg_equiv_memory_loc = 0;
1244 if (offsets_known_at)
1245 free (offsets_known_at);
1249 free (reg_equiv_mem);
1251 free (reg_equiv_address);
1252 free (reg_max_ref_width);
1253 free (reg_old_renumber);
1254 free (pseudo_previous_regs);
1255 free (pseudo_forbidden_regs);
1257 CLEAR_HARD_REG_SET (used_spill_regs);
1258 for (i = 0; i < n_spills; i++)
1259 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1261 /* Free all the insn_chain structures at once. */
1262 obstack_free (&reload_obstack, reload_startobj);
1263 unused_insn_chains = 0;
1264 fixup_abnormal_edges ();
1266 /* Replacing pseudos with their memory equivalents might have
1267 created shared rtx. Subsequent passes would get confused
1268 by this, so unshare everything here. */
1269 unshare_all_rtl_again (first);
1271 #ifdef STACK_BOUNDARY
1272 /* init_emit has set the alignment of the hard frame pointer
1273 to STACK_BOUNDARY. It is very likely no longer valid if
1274 the hard frame pointer was used for register allocation. */
1275 if (!frame_pointer_needed)
1276 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1282 /* Yet another special case. Unfortunately, reg-stack forces people to
1283 write incorrect clobbers in asm statements. These clobbers must not
1284 cause the register to appear in bad_spill_regs, otherwise we'll call
1285 fatal_insn later. We clear the corresponding regnos in the live
1286 register sets to avoid this.
1287 The whole thing is rather sick, I'm afraid. */
1290 maybe_fix_stack_asms (void)
1293 const char *constraints[MAX_RECOG_OPERANDS];
1294 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1295 struct insn_chain *chain;
1297 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1300 HARD_REG_SET clobbered, allowed;
1303 if (! INSN_P (chain->insn)
1304 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1306 pat = PATTERN (chain->insn);
1307 if (GET_CODE (pat) != PARALLEL)
1310 CLEAR_HARD_REG_SET (clobbered);
1311 CLEAR_HARD_REG_SET (allowed);
1313 /* First, make a mask of all stack regs that are clobbered. */
1314 for (i = 0; i < XVECLEN (pat, 0); i++)
1316 rtx t = XVECEXP (pat, 0, i);
1317 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1318 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1321 /* Get the operand values and constraints out of the insn. */
1322 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1323 constraints, operand_mode);
1325 /* For every operand, see what registers are allowed. */
1326 for (i = 0; i < noperands; i++)
1328 const char *p = constraints[i];
1329 /* For every alternative, we compute the class of registers allowed
1330 for reloading in CLS, and merge its contents into the reg set
1332 int cls = (int) NO_REGS;
1338 if (c == '\0' || c == ',' || c == '#')
1340 /* End of one alternative - mark the regs in the current
1341 class, and reset the class. */
1342 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1348 } while (c != '\0' && c != ',');
1356 case '=': case '+': case '*': case '%': case '?': case '!':
1357 case '0': case '1': case '2': case '3': case '4': case 'm':
1358 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1359 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1360 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1365 cls = (int) reg_class_subunion[cls]
1366 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1371 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1375 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1376 cls = (int) reg_class_subunion[cls]
1377 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1379 cls = (int) reg_class_subunion[cls]
1380 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1382 p += CONSTRAINT_LEN (c, p);
1385 /* Those of the registers which are clobbered, but allowed by the
1386 constraints, must be usable as reload registers. So clear them
1387 out of the life information. */
1388 AND_HARD_REG_SET (allowed, clobbered);
1389 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1390 if (TEST_HARD_REG_BIT (allowed, i))
1392 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1393 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1400 /* Copy the global variables n_reloads and rld into the corresponding elts
1403 copy_reloads (struct insn_chain *chain)
1405 chain->n_reloads = n_reloads;
1406 chain->rld = obstack_alloc (&reload_obstack,
1407 n_reloads * sizeof (struct reload));
1408 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1409 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1412 /* Walk the chain of insns, and determine for each whether it needs reloads
1413 and/or eliminations. Build the corresponding insns_need_reload list, and
1414 set something_needs_elimination as appropriate. */
1416 calculate_needs_all_insns (int global)
1418 struct insn_chain **pprev_reload = &insns_need_reload;
1419 struct insn_chain *chain, *next = 0;
1421 something_needs_elimination = 0;
1423 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1424 for (chain = reload_insn_chain; chain != 0; chain = next)
1426 rtx insn = chain->insn;
1430 /* Clear out the shortcuts. */
1431 chain->n_reloads = 0;
1432 chain->need_elim = 0;
1433 chain->need_reload = 0;
1434 chain->need_operand_change = 0;
1436 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1437 include REG_LABEL), we need to see what effects this has on the
1438 known offsets at labels. */
1440 if (LABEL_P (insn) || JUMP_P (insn)
1441 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1442 set_label_offsets (insn, insn, 0);
1446 rtx old_body = PATTERN (insn);
1447 int old_code = INSN_CODE (insn);
1448 rtx old_notes = REG_NOTES (insn);
1449 int did_elimination = 0;
1450 int operands_changed = 0;
1451 rtx set = single_set (insn);
1453 /* Skip insns that only set an equivalence. */
1454 if (set && REG_P (SET_DEST (set))
1455 && reg_renumber[REGNO (SET_DEST (set))] < 0
1456 && reg_equiv_constant[REGNO (SET_DEST (set))])
1459 /* If needed, eliminate any eliminable registers. */
1460 if (num_eliminable || num_eliminable_invariants)
1461 did_elimination = eliminate_regs_in_insn (insn, 0);
1463 /* Analyze the instruction. */
1464 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1465 global, spill_reg_order);
1467 /* If a no-op set needs more than one reload, this is likely
1468 to be something that needs input address reloads. We
1469 can't get rid of this cleanly later, and it is of no use
1470 anyway, so discard it now.
1471 We only do this when expensive_optimizations is enabled,
1472 since this complements reload inheritance / output
1473 reload deletion, and it can make debugging harder. */
1474 if (flag_expensive_optimizations && n_reloads > 1)
1476 rtx set = single_set (insn);
1478 && SET_SRC (set) == SET_DEST (set)
1479 && REG_P (SET_SRC (set))
1480 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1483 /* Delete it from the reload chain. */
1485 chain->prev->next = next;
1487 reload_insn_chain = next;
1489 next->prev = chain->prev;
1490 chain->next = unused_insn_chains;
1491 unused_insn_chains = chain;
1496 update_eliminable_offsets ();
1498 /* Remember for later shortcuts which insns had any reloads or
1499 register eliminations. */
1500 chain->need_elim = did_elimination;
1501 chain->need_reload = n_reloads > 0;
1502 chain->need_operand_change = operands_changed;
1504 /* Discard any register replacements done. */
1505 if (did_elimination)
1507 obstack_free (&reload_obstack, reload_insn_firstobj);
1508 PATTERN (insn) = old_body;
1509 INSN_CODE (insn) = old_code;
1510 REG_NOTES (insn) = old_notes;
1511 something_needs_elimination = 1;
1514 something_needs_operands_changed |= operands_changed;
1518 copy_reloads (chain);
1519 *pprev_reload = chain;
1520 pprev_reload = &chain->next_need_reload;
1527 /* Comparison function for qsort to decide which of two reloads
1528 should be handled first. *P1 and *P2 are the reload numbers. */
1531 reload_reg_class_lower (const void *r1p, const void *r2p)
1533 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1536 /* Consider required reloads before optional ones. */
1537 t = rld[r1].optional - rld[r2].optional;
1541 /* Count all solitary classes before non-solitary ones. */
1542 t = ((reg_class_size[(int) rld[r2].class] == 1)
1543 - (reg_class_size[(int) rld[r1].class] == 1));
1547 /* Aside from solitaires, consider all multi-reg groups first. */
1548 t = rld[r2].nregs - rld[r1].nregs;
1552 /* Consider reloads in order of increasing reg-class number. */
1553 t = (int) rld[r1].class - (int) rld[r2].class;
1557 /* If reloads are equally urgent, sort by reload number,
1558 so that the results of qsort leave nothing to chance. */
1562 /* The cost of spilling each hard reg. */
1563 static int spill_cost[FIRST_PSEUDO_REGISTER];
1565 /* When spilling multiple hard registers, we use SPILL_COST for the first
1566 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1567 only the first hard reg for a multi-reg pseudo. */
1568 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1570 /* Update the spill cost arrays, considering that pseudo REG is live. */
1573 count_pseudo (int reg)
1575 int freq = REG_FREQ (reg);
1576 int r = reg_renumber[reg];
1579 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1580 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1583 SET_REGNO_REG_SET (&pseudos_counted, reg);
1585 gcc_assert (r >= 0);
1587 spill_add_cost[r] += freq;
1589 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1591 spill_cost[r + nregs] += freq;
1594 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1595 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1598 order_regs_for_reload (struct insn_chain *chain)
1601 HARD_REG_SET used_by_pseudos;
1602 HARD_REG_SET used_by_pseudos2;
1603 reg_set_iterator rsi;
1605 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1607 memset (spill_cost, 0, sizeof spill_cost);
1608 memset (spill_add_cost, 0, sizeof spill_add_cost);
1610 /* Count number of uses of each hard reg by pseudo regs allocated to it
1611 and then order them by decreasing use. First exclude hard registers
1612 that are live in or across this insn. */
1614 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1615 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1616 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1617 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1619 /* Now find out which pseudos are allocated to it, and update
1621 CLEAR_REG_SET (&pseudos_counted);
1623 EXECUTE_IF_SET_IN_REG_SET
1624 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1628 EXECUTE_IF_SET_IN_REG_SET
1629 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1633 CLEAR_REG_SET (&pseudos_counted);
1636 /* Vector of reload-numbers showing the order in which the reloads should
1638 static short reload_order[MAX_RELOADS];
1640 /* This is used to keep track of the spill regs used in one insn. */
1641 static HARD_REG_SET used_spill_regs_local;
1643 /* We decided to spill hard register SPILLED, which has a size of
1644 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1645 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1646 update SPILL_COST/SPILL_ADD_COST. */
1649 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1651 int r = reg_renumber[reg];
1652 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1654 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1655 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1658 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1660 spill_add_cost[r] -= REG_FREQ (reg);
1662 spill_cost[r + nregs] -= REG_FREQ (reg);
1665 /* Find reload register to use for reload number ORDER. */
1668 find_reg (struct insn_chain *chain, int order)
1670 int rnum = reload_order[order];
1671 struct reload *rl = rld + rnum;
1672 int best_cost = INT_MAX;
1676 HARD_REG_SET not_usable;
1677 HARD_REG_SET used_by_other_reload;
1678 reg_set_iterator rsi;
1680 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1681 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1682 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1684 CLEAR_HARD_REG_SET (used_by_other_reload);
1685 for (k = 0; k < order; k++)
1687 int other = reload_order[k];
1689 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1690 for (j = 0; j < rld[other].nregs; j++)
1691 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1696 unsigned int regno = i;
1698 if (! TEST_HARD_REG_BIT (not_usable, regno)
1699 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1700 && HARD_REGNO_MODE_OK (regno, rl->mode))
1702 int this_cost = spill_cost[regno];
1704 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1706 for (j = 1; j < this_nregs; j++)
1708 this_cost += spill_add_cost[regno + j];
1709 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1710 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1715 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1717 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1719 if (this_cost < best_cost
1720 /* Among registers with equal cost, prefer caller-saved ones, or
1721 use REG_ALLOC_ORDER if it is defined. */
1722 || (this_cost == best_cost
1723 #ifdef REG_ALLOC_ORDER
1724 && (inv_reg_alloc_order[regno]
1725 < inv_reg_alloc_order[best_reg])
1727 && call_used_regs[regno]
1728 && ! call_used_regs[best_reg]
1733 best_cost = this_cost;
1741 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1743 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1744 rl->regno = best_reg;
1746 EXECUTE_IF_SET_IN_REG_SET
1747 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1749 count_spilled_pseudo (best_reg, rl->nregs, j);
1752 EXECUTE_IF_SET_IN_REG_SET
1753 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1755 count_spilled_pseudo (best_reg, rl->nregs, j);
1758 for (i = 0; i < rl->nregs; i++)
1760 gcc_assert (spill_cost[best_reg + i] == 0);
1761 gcc_assert (spill_add_cost[best_reg + i] == 0);
1762 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1767 /* Find more reload regs to satisfy the remaining need of an insn, which
1769 Do it by ascending class number, since otherwise a reg
1770 might be spilled for a big class and might fail to count
1771 for a smaller class even though it belongs to that class. */
1774 find_reload_regs (struct insn_chain *chain)
1778 /* In order to be certain of getting the registers we need,
1779 we must sort the reloads into order of increasing register class.
1780 Then our grabbing of reload registers will parallel the process
1781 that provided the reload registers. */
1782 for (i = 0; i < chain->n_reloads; i++)
1784 /* Show whether this reload already has a hard reg. */
1785 if (chain->rld[i].reg_rtx)
1787 int regno = REGNO (chain->rld[i].reg_rtx);
1788 chain->rld[i].regno = regno;
1790 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1793 chain->rld[i].regno = -1;
1794 reload_order[i] = i;
1797 n_reloads = chain->n_reloads;
1798 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1800 CLEAR_HARD_REG_SET (used_spill_regs_local);
1803 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1805 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1807 /* Compute the order of preference for hard registers to spill. */
1809 order_regs_for_reload (chain);
1811 for (i = 0; i < n_reloads; i++)
1813 int r = reload_order[i];
1815 /* Ignore reloads that got marked inoperative. */
1816 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1817 && ! rld[r].optional
1818 && rld[r].regno == -1)
1819 if (! find_reg (chain, i))
1821 spill_failure (chain->insn, rld[r].class);
1827 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1828 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1830 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1834 select_reload_regs (void)
1836 struct insn_chain *chain;
1838 /* Try to satisfy the needs for each insn. */
1839 for (chain = insns_need_reload; chain != 0;
1840 chain = chain->next_need_reload)
1841 find_reload_regs (chain);
1844 /* Delete all insns that were inserted by emit_caller_save_insns during
1847 delete_caller_save_insns (void)
1849 struct insn_chain *c = reload_insn_chain;
1853 while (c != 0 && c->is_caller_save_insn)
1855 struct insn_chain *next = c->next;
1858 if (c == reload_insn_chain)
1859 reload_insn_chain = next;
1863 next->prev = c->prev;
1865 c->prev->next = next;
1866 c->next = unused_insn_chains;
1867 unused_insn_chains = c;
1875 /* Handle the failure to find a register to spill.
1876 INSN should be one of the insns which needed this particular spill reg. */
1879 spill_failure (rtx insn, enum reg_class class)
1881 if (asm_noperands (PATTERN (insn)) >= 0)
1882 error_for_asm (insn, "can't find a register in class %qs while "
1883 "reloading %<asm%>",
1884 reg_class_names[class]);
1887 error ("unable to find a register to spill in class %qs",
1888 reg_class_names[class]);
1889 fatal_insn ("this is the insn:", insn);
1893 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1894 data that is dead in INSN. */
1897 delete_dead_insn (rtx insn)
1899 rtx prev = prev_real_insn (insn);
1902 /* If the previous insn sets a register that dies in our insn, delete it
1904 if (prev && GET_CODE (PATTERN (prev)) == SET
1905 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1906 && reg_mentioned_p (prev_dest, PATTERN (insn))
1907 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1908 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1909 delete_dead_insn (prev);
1911 SET_INSN_DELETED (insn);
1914 /* Modify the home of pseudo-reg I.
1915 The new home is present in reg_renumber[I].
1917 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1918 or it may be -1, meaning there is none or it is not relevant.
1919 This is used so that all pseudos spilled from a given hard reg
1920 can share one stack slot. */
1923 alter_reg (int i, int from_reg)
1925 /* When outputting an inline function, this can happen
1926 for a reg that isn't actually used. */
1927 if (regno_reg_rtx[i] == 0)
1930 /* If the reg got changed to a MEM at rtl-generation time,
1932 if (!REG_P (regno_reg_rtx[i]))
1935 /* Modify the reg-rtx to contain the new hard reg
1936 number or else to contain its pseudo reg number. */
1937 REGNO (regno_reg_rtx[i])
1938 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1940 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1941 allocate a stack slot for it. */
1943 if (reg_renumber[i] < 0
1944 && REG_N_REFS (i) > 0
1945 && reg_equiv_constant[i] == 0
1946 && reg_equiv_memory_loc[i] == 0)
1949 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1950 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1953 /* Each pseudo reg has an inherent size which comes from its own mode,
1954 and a total size which provides room for paradoxical subregs
1955 which refer to the pseudo reg in wider modes.
1957 We can use a slot already allocated if it provides both
1958 enough inherent space and enough total space.
1959 Otherwise, we allocate a new slot, making sure that it has no less
1960 inherent space, and no less total space, then the previous slot. */
1963 /* No known place to spill from => no slot to reuse. */
1964 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1965 inherent_size == total_size ? 0 : -1);
1966 if (BYTES_BIG_ENDIAN)
1967 /* Cancel the big-endian correction done in assign_stack_local.
1968 Get the address of the beginning of the slot.
1969 This is so we can do a big-endian correction unconditionally
1971 adjust = inherent_size - total_size;
1973 /* Nothing can alias this slot except this pseudo. */
1974 set_mem_alias_set (x, new_alias_set ());
1977 /* Reuse a stack slot if possible. */
1978 else if (spill_stack_slot[from_reg] != 0
1979 && spill_stack_slot_width[from_reg] >= total_size
1980 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1982 x = spill_stack_slot[from_reg];
1984 /* Allocate a bigger slot. */
1987 /* Compute maximum size needed, both for inherent size
1988 and for total size. */
1989 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1992 if (spill_stack_slot[from_reg])
1994 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1996 mode = GET_MODE (spill_stack_slot[from_reg]);
1997 if (spill_stack_slot_width[from_reg] > total_size)
1998 total_size = spill_stack_slot_width[from_reg];
2001 /* Make a slot with that size. */
2002 x = assign_stack_local (mode, total_size,
2003 inherent_size == total_size ? 0 : -1);
2006 /* All pseudos mapped to this slot can alias each other. */
2007 if (spill_stack_slot[from_reg])
2008 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2010 set_mem_alias_set (x, new_alias_set ());
2012 if (BYTES_BIG_ENDIAN)
2014 /* Cancel the big-endian correction done in assign_stack_local.
2015 Get the address of the beginning of the slot.
2016 This is so we can do a big-endian correction unconditionally
2018 adjust = GET_MODE_SIZE (mode) - total_size;
2021 = adjust_address_nv (x, mode_for_size (total_size
2027 spill_stack_slot[from_reg] = stack_slot;
2028 spill_stack_slot_width[from_reg] = total_size;
2031 /* On a big endian machine, the "address" of the slot
2032 is the address of the low part that fits its inherent mode. */
2033 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2034 adjust += (total_size - inherent_size);
2036 /* If we have any adjustment to make, or if the stack slot is the
2037 wrong mode, make a new stack slot. */
2038 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2040 /* If we have a decl for the original register, set it for the
2041 memory. If this is a shared MEM, make a copy. */
2042 if (REG_EXPR (regno_reg_rtx[i])
2043 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2045 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2047 /* We can do this only for the DECLs home pseudo, not for
2048 any copies of it, since otherwise when the stack slot
2049 is reused, nonoverlapping_memrefs_p might think they
2051 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2053 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2056 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2060 /* Save the stack slot for later. */
2061 reg_equiv_memory_loc[i] = x;
2065 /* Mark the slots in regs_ever_live for the hard regs
2066 used by pseudo-reg number REGNO. */
2069 mark_home_live (int regno)
2073 i = reg_renumber[regno];
2076 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2078 regs_ever_live[i++] = 1;
2081 /* This function handles the tracking of elimination offsets around branches.
2083 X is a piece of RTL being scanned.
2085 INSN is the insn that it came from, if any.
2087 INITIAL_P is nonzero if we are to set the offset to be the initial
2088 offset and zero if we are setting the offset of the label to be the
2092 set_label_offsets (rtx x, rtx insn, int initial_p)
2094 enum rtx_code code = GET_CODE (x);
2097 struct elim_table *p;
2102 if (LABEL_REF_NONLOCAL_P (x))
2107 /* ... fall through ... */
2110 /* If we know nothing about this label, set the desired offsets. Note
2111 that this sets the offset at a label to be the offset before a label
2112 if we don't know anything about the label. This is not correct for
2113 the label after a BARRIER, but is the best guess we can make. If
2114 we guessed wrong, we will suppress an elimination that might have
2115 been possible had we been able to guess correctly. */
2117 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2119 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2120 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2121 = (initial_p ? reg_eliminate[i].initial_offset
2122 : reg_eliminate[i].offset);
2123 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2126 /* Otherwise, if this is the definition of a label and it is
2127 preceded by a BARRIER, set our offsets to the known offset of
2131 && (tem = prev_nonnote_insn (insn)) != 0
2133 set_offsets_for_label (insn);
2135 /* If neither of the above cases is true, compare each offset
2136 with those previously recorded and suppress any eliminations
2137 where the offsets disagree. */
2139 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2140 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2141 != (initial_p ? reg_eliminate[i].initial_offset
2142 : reg_eliminate[i].offset))
2143 reg_eliminate[i].can_eliminate = 0;
2148 set_label_offsets (PATTERN (insn), insn, initial_p);
2150 /* ... fall through ... */
2154 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2155 and hence must have all eliminations at their initial offsets. */
2156 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2157 if (REG_NOTE_KIND (tem) == REG_LABEL)
2158 set_label_offsets (XEXP (tem, 0), insn, 1);
2164 /* Each of the labels in the parallel or address vector must be
2165 at their initial offsets. We want the first field for PARALLEL
2166 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2168 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2169 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2174 /* We only care about setting PC. If the source is not RETURN,
2175 IF_THEN_ELSE, or a label, disable any eliminations not at
2176 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2177 isn't one of those possibilities. For branches to a label,
2178 call ourselves recursively.
2180 Note that this can disable elimination unnecessarily when we have
2181 a non-local goto since it will look like a non-constant jump to
2182 someplace in the current function. This isn't a significant
2183 problem since such jumps will normally be when all elimination
2184 pairs are back to their initial offsets. */
2186 if (SET_DEST (x) != pc_rtx)
2189 switch (GET_CODE (SET_SRC (x)))
2196 set_label_offsets (SET_SRC (x), insn, initial_p);
2200 tem = XEXP (SET_SRC (x), 1);
2201 if (GET_CODE (tem) == LABEL_REF)
2202 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2203 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2206 tem = XEXP (SET_SRC (x), 2);
2207 if (GET_CODE (tem) == LABEL_REF)
2208 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2209 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2217 /* If we reach here, all eliminations must be at their initial
2218 offset because we are doing a jump to a variable address. */
2219 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2220 if (p->offset != p->initial_offset)
2221 p->can_eliminate = 0;
2229 /* Scan X and replace any eliminable registers (such as fp) with a
2230 replacement (such as sp), plus an offset.
2232 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2233 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2234 MEM, we are allowed to replace a sum of a register and the constant zero
2235 with the register, which we cannot do outside a MEM. In addition, we need
2236 to record the fact that a register is referenced outside a MEM.
2238 If INSN is an insn, it is the insn containing X. If we replace a REG
2239 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2240 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2241 the REG is being modified.
2243 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2244 That's used when we eliminate in expressions stored in notes.
2245 This means, do not set ref_outside_mem even if the reference
2248 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2249 replacements done assuming all offsets are at their initial values. If
2250 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2251 encounter, return the actual location so that find_reloads will do
2252 the proper thing. */
2255 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2257 enum rtx_code code = GET_CODE (x);
2258 struct elim_table *ep;
2265 if (! current_function_decl)
2287 /* First handle the case where we encounter a bare register that
2288 is eliminable. Replace it with a PLUS. */
2289 if (regno < FIRST_PSEUDO_REGISTER)
2291 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2293 if (ep->from_rtx == x && ep->can_eliminate)
2294 return plus_constant (ep->to_rtx, ep->previous_offset);
2297 else if (reg_renumber && reg_renumber[regno] < 0
2298 && reg_equiv_constant && reg_equiv_constant[regno]
2299 && ! CONSTANT_P (reg_equiv_constant[regno]))
2300 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2304 /* You might think handling MINUS in a manner similar to PLUS is a
2305 good idea. It is not. It has been tried multiple times and every
2306 time the change has had to have been reverted.
2308 Other parts of reload know a PLUS is special (gen_reload for example)
2309 and require special code to handle code a reloaded PLUS operand.
2311 Also consider backends where the flags register is clobbered by a
2312 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2313 lea instruction comes to mind). If we try to reload a MINUS, we
2314 may kill the flags register that was holding a useful value.
2316 So, please before trying to handle MINUS, consider reload as a
2317 whole instead of this little section as well as the backend issues. */
2319 /* If this is the sum of an eliminable register and a constant, rework
2321 if (REG_P (XEXP (x, 0))
2322 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2323 && CONSTANT_P (XEXP (x, 1)))
2325 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2327 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2329 /* The only time we want to replace a PLUS with a REG (this
2330 occurs when the constant operand of the PLUS is the negative
2331 of the offset) is when we are inside a MEM. We won't want
2332 to do so at other times because that would change the
2333 structure of the insn in a way that reload can't handle.
2334 We special-case the commonest situation in
2335 eliminate_regs_in_insn, so just replace a PLUS with a
2336 PLUS here, unless inside a MEM. */
2337 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2338 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2341 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2342 plus_constant (XEXP (x, 1),
2343 ep->previous_offset));
2346 /* If the register is not eliminable, we are done since the other
2347 operand is a constant. */
2351 /* If this is part of an address, we want to bring any constant to the
2352 outermost PLUS. We will do this by doing register replacement in
2353 our operands and seeing if a constant shows up in one of them.
2355 Note that there is no risk of modifying the structure of the insn,
2356 since we only get called for its operands, thus we are either
2357 modifying the address inside a MEM, or something like an address
2358 operand of a load-address insn. */
2361 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2362 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2364 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2366 /* If one side is a PLUS and the other side is a pseudo that
2367 didn't get a hard register but has a reg_equiv_constant,
2368 we must replace the constant here since it may no longer
2369 be in the position of any operand. */
2370 if (GET_CODE (new0) == PLUS && REG_P (new1)
2371 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2372 && reg_renumber[REGNO (new1)] < 0
2373 && reg_equiv_constant != 0
2374 && reg_equiv_constant[REGNO (new1)] != 0)
2375 new1 = reg_equiv_constant[REGNO (new1)];
2376 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2377 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2378 && reg_renumber[REGNO (new0)] < 0
2379 && reg_equiv_constant[REGNO (new0)] != 0)
2380 new0 = reg_equiv_constant[REGNO (new0)];
2382 new = form_sum (new0, new1);
2384 /* As above, if we are not inside a MEM we do not want to
2385 turn a PLUS into something else. We might try to do so here
2386 for an addition of 0 if we aren't optimizing. */
2387 if (! mem_mode && GET_CODE (new) != PLUS)
2388 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2396 /* If this is the product of an eliminable register and a
2397 constant, apply the distribute law and move the constant out
2398 so that we have (plus (mult ..) ..). This is needed in order
2399 to keep load-address insns valid. This case is pathological.
2400 We ignore the possibility of overflow here. */
2401 if (REG_P (XEXP (x, 0))
2402 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2403 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2406 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2409 /* Refs inside notes don't count for this purpose. */
2410 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2411 || GET_CODE (insn) == INSN_LIST)))
2412 ep->ref_outside_mem = 1;
2415 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2416 ep->previous_offset * INTVAL (XEXP (x, 1)));
2419 /* ... fall through ... */
2423 /* See comments before PLUS about handling MINUS. */
2425 case DIV: case UDIV:
2426 case MOD: case UMOD:
2427 case AND: case IOR: case XOR:
2428 case ROTATERT: case ROTATE:
2429 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2431 case GE: case GT: case GEU: case GTU:
2432 case LE: case LT: case LEU: case LTU:
2434 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2436 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2438 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2439 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2444 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2447 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2448 if (new != XEXP (x, 0))
2450 /* If this is a REG_DEAD note, it is not valid anymore.
2451 Using the eliminated version could result in creating a
2452 REG_DEAD note for the stack or frame pointer. */
2453 if (GET_MODE (x) == REG_DEAD)
2455 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2458 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2462 /* ... fall through ... */
2465 /* Now do eliminations in the rest of the chain. If this was
2466 an EXPR_LIST, this might result in allocating more memory than is
2467 strictly needed, but it simplifies the code. */
2470 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2471 if (new != XEXP (x, 1))
2473 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2481 case STRICT_LOW_PART:
2483 case SIGN_EXTEND: case ZERO_EXTEND:
2484 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2485 case FLOAT: case FIX:
2486 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2494 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2495 if (new != XEXP (x, 0))
2496 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2500 /* Similar to above processing, but preserve SUBREG_BYTE.
2501 Convert (subreg (mem)) to (mem) if not paradoxical.
2502 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2503 pseudo didn't get a hard reg, we must replace this with the
2504 eliminated version of the memory location because push_reload
2505 may do the replacement in certain circumstances. */
2506 if (REG_P (SUBREG_REG (x))
2507 && (GET_MODE_SIZE (GET_MODE (x))
2508 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2509 && reg_equiv_memory_loc != 0
2510 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2512 new = SUBREG_REG (x);
2515 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2517 if (new != SUBREG_REG (x))
2519 int x_size = GET_MODE_SIZE (GET_MODE (x));
2520 int new_size = GET_MODE_SIZE (GET_MODE (new));
2523 && ((x_size < new_size
2524 #ifdef WORD_REGISTER_OPERATIONS
2525 /* On these machines, combine can create rtl of the form
2526 (set (subreg:m1 (reg:m2 R) 0) ...)
2527 where m1 < m2, and expects something interesting to
2528 happen to the entire word. Moreover, it will use the
2529 (reg:m2 R) later, expecting all bits to be preserved.
2530 So if the number of words is the same, preserve the
2531 subreg so that push_reload can see it. */
2532 && ! ((x_size - 1) / UNITS_PER_WORD
2533 == (new_size -1 ) / UNITS_PER_WORD)
2536 || x_size == new_size)
2538 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2540 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2546 /* Our only special processing is to pass the mode of the MEM to our
2547 recursive call and copy the flags. While we are here, handle this
2548 case more efficiently. */
2550 replace_equiv_address_nv (x,
2551 eliminate_regs (XEXP (x, 0),
2552 GET_MODE (x), insn));
2555 /* Handle insn_list USE that a call to a pure function may generate. */
2556 new = eliminate_regs (XEXP (x, 0), 0, insn);
2557 if (new != XEXP (x, 0))
2558 return gen_rtx_USE (GET_MODE (x), new);
2570 /* Process each of our operands recursively. If any have changed, make a
2572 fmt = GET_RTX_FORMAT (code);
2573 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2577 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2578 if (new != XEXP (x, i) && ! copied)
2580 rtx new_x = rtx_alloc (code);
2581 memcpy (new_x, x, RTX_SIZE (code));
2587 else if (*fmt == 'E')
2590 for (j = 0; j < XVECLEN (x, i); j++)
2592 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2593 if (new != XVECEXP (x, i, j) && ! copied_vec)
2595 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2599 rtx new_x = rtx_alloc (code);
2600 memcpy (new_x, x, RTX_SIZE (code));
2604 XVEC (x, i) = new_v;
2607 XVECEXP (x, i, j) = new;
2615 /* Scan rtx X for modifications of elimination target registers. Update
2616 the table of eliminables to reflect the changed state. MEM_MODE is
2617 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2620 elimination_effects (rtx x, enum machine_mode mem_mode)
2622 enum rtx_code code = GET_CODE (x);
2623 struct elim_table *ep;
2647 /* First handle the case where we encounter a bare register that
2648 is eliminable. Replace it with a PLUS. */
2649 if (regno < FIRST_PSEUDO_REGISTER)
2651 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2653 if (ep->from_rtx == x && ep->can_eliminate)
2656 ep->ref_outside_mem = 1;
2661 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2662 && reg_equiv_constant[regno]
2663 && ! function_invariant_p (reg_equiv_constant[regno]))
2664 elimination_effects (reg_equiv_constant[regno], mem_mode);
2673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2674 if (ep->to_rtx == XEXP (x, 0))
2676 int size = GET_MODE_SIZE (mem_mode);
2678 /* If more bytes than MEM_MODE are pushed, account for them. */
2679 #ifdef PUSH_ROUNDING
2680 if (ep->to_rtx == stack_pointer_rtx)
2681 size = PUSH_ROUNDING (size);
2683 if (code == PRE_DEC || code == POST_DEC)
2685 else if (code == PRE_INC || code == POST_INC)
2687 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2688 && GET_CODE (XEXP (x, 1)) == PLUS
2689 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2690 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2691 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2694 /* These two aren't unary operators. */
2695 if (code == POST_MODIFY || code == PRE_MODIFY)
2698 /* Fall through to generic unary operation case. */
2699 case STRICT_LOW_PART:
2701 case SIGN_EXTEND: case ZERO_EXTEND:
2702 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2703 case FLOAT: case FIX:
2704 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2712 elimination_effects (XEXP (x, 0), mem_mode);
2716 if (REG_P (SUBREG_REG (x))
2717 && (GET_MODE_SIZE (GET_MODE (x))
2718 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2719 && reg_equiv_memory_loc != 0
2720 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2723 elimination_effects (SUBREG_REG (x), mem_mode);
2727 /* If using a register that is the source of an eliminate we still
2728 think can be performed, note it cannot be performed since we don't
2729 know how this register is used. */
2730 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2731 if (ep->from_rtx == XEXP (x, 0))
2732 ep->can_eliminate = 0;
2734 elimination_effects (XEXP (x, 0), mem_mode);
2738 /* If clobbering a register that is the replacement register for an
2739 elimination we still think can be performed, note that it cannot
2740 be performed. Otherwise, we need not be concerned about it. */
2741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2742 if (ep->to_rtx == XEXP (x, 0))
2743 ep->can_eliminate = 0;
2745 elimination_effects (XEXP (x, 0), mem_mode);
2749 /* Check for setting a register that we know about. */
2750 if (REG_P (SET_DEST (x)))
2752 /* See if this is setting the replacement register for an
2755 If DEST is the hard frame pointer, we do nothing because we
2756 assume that all assignments to the frame pointer are for
2757 non-local gotos and are being done at a time when they are valid
2758 and do not disturb anything else. Some machines want to
2759 eliminate a fake argument pointer (or even a fake frame pointer)
2760 with either the real frame or the stack pointer. Assignments to
2761 the hard frame pointer must not prevent this elimination. */
2763 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2765 if (ep->to_rtx == SET_DEST (x)
2766 && SET_DEST (x) != hard_frame_pointer_rtx)
2768 /* If it is being incremented, adjust the offset. Otherwise,
2769 this elimination can't be done. */
2770 rtx src = SET_SRC (x);
2772 if (GET_CODE (src) == PLUS
2773 && XEXP (src, 0) == SET_DEST (x)
2774 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2775 ep->offset -= INTVAL (XEXP (src, 1));
2777 ep->can_eliminate = 0;
2781 elimination_effects (SET_DEST (x), 0);
2782 elimination_effects (SET_SRC (x), 0);
2786 /* Our only special processing is to pass the mode of the MEM to our
2788 elimination_effects (XEXP (x, 0), GET_MODE (x));
2795 fmt = GET_RTX_FORMAT (code);
2796 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2799 elimination_effects (XEXP (x, i), mem_mode);
2800 else if (*fmt == 'E')
2801 for (j = 0; j < XVECLEN (x, i); j++)
2802 elimination_effects (XVECEXP (x, i, j), mem_mode);
2806 /* Descend through rtx X and verify that no references to eliminable registers
2807 remain. If any do remain, mark the involved register as not
2811 check_eliminable_occurrences (rtx x)
2820 code = GET_CODE (x);
2822 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2824 struct elim_table *ep;
2826 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2827 if (ep->from_rtx == x)
2828 ep->can_eliminate = 0;
2832 fmt = GET_RTX_FORMAT (code);
2833 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2836 check_eliminable_occurrences (XEXP (x, i));
2837 else if (*fmt == 'E')
2840 for (j = 0; j < XVECLEN (x, i); j++)
2841 check_eliminable_occurrences (XVECEXP (x, i, j));
2846 /* Scan INSN and eliminate all eliminable registers in it.
2848 If REPLACE is nonzero, do the replacement destructively. Also
2849 delete the insn as dead it if it is setting an eliminable register.
2851 If REPLACE is zero, do all our allocations in reload_obstack.
2853 If no eliminations were done and this insn doesn't require any elimination
2854 processing (these are not identical conditions: it might be updating sp,
2855 but not referencing fp; this needs to be seen during reload_as_needed so
2856 that the offset between fp and sp can be taken into consideration), zero
2857 is returned. Otherwise, 1 is returned. */
2860 eliminate_regs_in_insn (rtx insn, int replace)
2862 int icode = recog_memoized (insn);
2863 rtx old_body = PATTERN (insn);
2864 int insn_is_asm = asm_noperands (old_body) >= 0;
2865 rtx old_set = single_set (insn);
2869 rtx substed_operand[MAX_RECOG_OPERANDS];
2870 rtx orig_operand[MAX_RECOG_OPERANDS];
2871 struct elim_table *ep;
2874 if (! insn_is_asm && icode < 0)
2876 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2877 || GET_CODE (PATTERN (insn)) == CLOBBER
2878 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2879 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2880 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2884 if (old_set != 0 && REG_P (SET_DEST (old_set))
2885 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2887 /* Check for setting an eliminable register. */
2888 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2889 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2891 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2892 /* If this is setting the frame pointer register to the
2893 hardware frame pointer register and this is an elimination
2894 that will be done (tested above), this insn is really
2895 adjusting the frame pointer downward to compensate for
2896 the adjustment done before a nonlocal goto. */
2897 if (ep->from == FRAME_POINTER_REGNUM
2898 && ep->to == HARD_FRAME_POINTER_REGNUM)
2900 rtx base = SET_SRC (old_set);
2901 rtx base_insn = insn;
2902 HOST_WIDE_INT offset = 0;
2904 while (base != ep->to_rtx)
2906 rtx prev_insn, prev_set;
2908 if (GET_CODE (base) == PLUS
2909 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2911 offset += INTVAL (XEXP (base, 1));
2912 base = XEXP (base, 0);
2914 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2915 && (prev_set = single_set (prev_insn)) != 0
2916 && rtx_equal_p (SET_DEST (prev_set), base))
2918 base = SET_SRC (prev_set);
2919 base_insn = prev_insn;
2925 if (base == ep->to_rtx)
2928 = plus_constant (ep->to_rtx, offset - ep->offset);
2930 new_body = old_body;
2933 new_body = copy_insn (old_body);
2934 if (REG_NOTES (insn))
2935 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2937 PATTERN (insn) = new_body;
2938 old_set = single_set (insn);
2940 /* First see if this insn remains valid when we
2941 make the change. If not, keep the INSN_CODE
2942 the same and let reload fit it up. */
2943 validate_change (insn, &SET_SRC (old_set), src, 1);
2944 validate_change (insn, &SET_DEST (old_set),
2946 if (! apply_change_group ())
2948 SET_SRC (old_set) = src;
2949 SET_DEST (old_set) = ep->to_rtx;
2958 /* In this case this insn isn't serving a useful purpose. We
2959 will delete it in reload_as_needed once we know that this
2960 elimination is, in fact, being done.
2962 If REPLACE isn't set, we can't delete this insn, but needn't
2963 process it since it won't be used unless something changes. */
2966 delete_dead_insn (insn);
2974 /* We allow one special case which happens to work on all machines we
2975 currently support: a single set with the source or a REG_EQUAL
2976 note being a PLUS of an eliminable register and a constant. */
2978 if (old_set && REG_P (SET_DEST (old_set)))
2980 /* First see if the source is of the form (plus (reg) CST). */
2981 if (GET_CODE (SET_SRC (old_set)) == PLUS
2982 && REG_P (XEXP (SET_SRC (old_set), 0))
2983 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2984 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2985 plus_src = SET_SRC (old_set);
2986 else if (REG_P (SET_SRC (old_set)))
2988 /* Otherwise, see if we have a REG_EQUAL note of the form
2989 (plus (reg) CST). */
2991 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2993 if (REG_NOTE_KIND (links) == REG_EQUAL
2994 && GET_CODE (XEXP (links, 0)) == PLUS
2995 && REG_P (XEXP (XEXP (links, 0), 0))
2996 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2997 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2999 plus_src = XEXP (links, 0);
3007 rtx reg = XEXP (plus_src, 0);
3008 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3010 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3011 if (ep->from_rtx == reg && ep->can_eliminate)
3013 offset += ep->offset;
3018 /* We assume here that if we need a PARALLEL with
3019 CLOBBERs for this assignment, we can do with the
3020 MATCH_SCRATCHes that add_clobbers allocates.
3021 There's not much we can do if that doesn't work. */
3022 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3026 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3029 rtvec vec = rtvec_alloc (num_clobbers + 1);
3031 vec->elem[0] = PATTERN (insn);
3032 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3033 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3035 gcc_assert (INSN_CODE (insn) >= 0);
3037 /* If we have a nonzero offset, and the source is already
3038 a simple REG, the following transformation would
3039 increase the cost of the insn by replacing a simple REG
3040 with (plus (reg sp) CST). So try only when plus_src
3041 comes from old_set proper, not REG_NOTES. */
3042 else if (SET_SRC (old_set) == plus_src)
3044 new_body = old_body;
3047 new_body = copy_insn (old_body);
3048 if (REG_NOTES (insn))
3049 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3051 PATTERN (insn) = new_body;
3052 old_set = single_set (insn);
3054 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3055 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3061 /* This can't have an effect on elimination offsets, so skip right
3067 /* Determine the effects of this insn on elimination offsets. */
3068 elimination_effects (old_body, 0);
3070 /* Eliminate all eliminable registers occurring in operands that
3071 can be handled by reload. */
3072 extract_insn (insn);
3073 for (i = 0; i < recog_data.n_operands; i++)
3075 orig_operand[i] = recog_data.operand[i];
3076 substed_operand[i] = recog_data.operand[i];
3078 /* For an asm statement, every operand is eliminable. */
3079 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3081 /* Check for setting a register that we know about. */
3082 if (recog_data.operand_type[i] != OP_IN
3083 && REG_P (orig_operand[i]))
3085 /* If we are assigning to a register that can be eliminated, it
3086 must be as part of a PARALLEL, since the code above handles
3087 single SETs. We must indicate that we can no longer
3088 eliminate this reg. */
3089 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3091 if (ep->from_rtx == orig_operand[i])
3092 ep->can_eliminate = 0;
3095 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3096 replace ? insn : NULL_RTX);
3097 if (substed_operand[i] != orig_operand[i])
3099 /* Terminate the search in check_eliminable_occurrences at
3101 *recog_data.operand_loc[i] = 0;
3103 /* If an output operand changed from a REG to a MEM and INSN is an
3104 insn, write a CLOBBER insn. */
3105 if (recog_data.operand_type[i] != OP_IN
3106 && REG_P (orig_operand[i])
3107 && MEM_P (substed_operand[i])
3109 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3114 for (i = 0; i < recog_data.n_dups; i++)
3115 *recog_data.dup_loc[i]
3116 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3118 /* If any eliminable remain, they aren't eliminable anymore. */
3119 check_eliminable_occurrences (old_body);
3121 /* Substitute the operands; the new values are in the substed_operand
3123 for (i = 0; i < recog_data.n_operands; i++)
3124 *recog_data.operand_loc[i] = substed_operand[i];
3125 for (i = 0; i < recog_data.n_dups; i++)
3126 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3128 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3129 re-recognize the insn. We do this in case we had a simple addition
3130 but now can do this as a load-address. This saves an insn in this
3132 If re-recognition fails, the old insn code number will still be used,
3133 and some register operands may have changed into PLUS expressions.
3134 These will be handled by find_reloads by loading them into a register
3139 /* If we aren't replacing things permanently and we changed something,
3140 make another copy to ensure that all the RTL is new. Otherwise
3141 things can go wrong if find_reload swaps commutative operands
3142 and one is inside RTL that has been copied while the other is not. */
3143 new_body = old_body;
3146 new_body = copy_insn (old_body);
3147 if (REG_NOTES (insn))
3148 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3150 PATTERN (insn) = new_body;
3152 /* If we had a move insn but now we don't, rerecognize it. This will
3153 cause spurious re-recognition if the old move had a PARALLEL since
3154 the new one still will, but we can't call single_set without
3155 having put NEW_BODY into the insn and the re-recognition won't
3156 hurt in this rare case. */
3157 /* ??? Why this huge if statement - why don't we just rerecognize the
3161 && ((REG_P (SET_SRC (old_set))
3162 && (GET_CODE (new_body) != SET
3163 || !REG_P (SET_SRC (new_body))))
3164 /* If this was a load from or store to memory, compare
3165 the MEM in recog_data.operand to the one in the insn.
3166 If they are not equal, then rerecognize the insn. */
3168 && ((MEM_P (SET_SRC (old_set))
3169 && SET_SRC (old_set) != recog_data.operand[1])
3170 || (MEM_P (SET_DEST (old_set))
3171 && SET_DEST (old_set) != recog_data.operand[0])))
3172 /* If this was an add insn before, rerecognize. */
3173 || GET_CODE (SET_SRC (old_set)) == PLUS))
3175 int new_icode = recog (PATTERN (insn), insn, 0);
3177 INSN_CODE (insn) = icode;
3181 /* Restore the old body. If there were any changes to it, we made a copy
3182 of it while the changes were still in place, so we'll correctly return
3183 a modified insn below. */
3186 /* Restore the old body. */
3187 for (i = 0; i < recog_data.n_operands; i++)
3188 *recog_data.operand_loc[i] = orig_operand[i];
3189 for (i = 0; i < recog_data.n_dups; i++)
3190 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3193 /* Update all elimination pairs to reflect the status after the current
3194 insn. The changes we make were determined by the earlier call to
3195 elimination_effects.
3197 We also detect cases where register elimination cannot be done,
3198 namely, if a register would be both changed and referenced outside a MEM
3199 in the resulting insn since such an insn is often undefined and, even if
3200 not, we cannot know what meaning will be given to it. Note that it is
3201 valid to have a register used in an address in an insn that changes it
3202 (presumably with a pre- or post-increment or decrement).
3204 If anything changes, return nonzero. */
3206 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3208 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3209 ep->can_eliminate = 0;
3211 ep->ref_outside_mem = 0;
3213 if (ep->previous_offset != ep->offset)
3218 /* If we changed something, perform elimination in REG_NOTES. This is
3219 needed even when REPLACE is zero because a REG_DEAD note might refer
3220 to a register that we eliminate and could cause a different number
3221 of spill registers to be needed in the final reload pass than in
3223 if (val && REG_NOTES (insn) != 0)
3224 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3229 /* Loop through all elimination pairs.
3230 Recalculate the number not at initial offset.
3232 Compute the maximum offset (minimum offset if the stack does not
3233 grow downward) for each elimination pair. */
3236 update_eliminable_offsets (void)
3238 struct elim_table *ep;
3240 num_not_at_initial_offset = 0;
3241 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3243 ep->previous_offset = ep->offset;
3244 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3245 num_not_at_initial_offset++;
3249 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3250 replacement we currently believe is valid, mark it as not eliminable if X
3251 modifies DEST in any way other than by adding a constant integer to it.
3253 If DEST is the frame pointer, we do nothing because we assume that
3254 all assignments to the hard frame pointer are nonlocal gotos and are being
3255 done at a time when they are valid and do not disturb anything else.
3256 Some machines want to eliminate a fake argument pointer with either the
3257 frame or stack pointer. Assignments to the hard frame pointer must not
3258 prevent this elimination.
3260 Called via note_stores from reload before starting its passes to scan
3261 the insns of the function. */
3264 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3268 /* A SUBREG of a hard register here is just changing its mode. We should
3269 not see a SUBREG of an eliminable hard register, but check just in
3271 if (GET_CODE (dest) == SUBREG)
3272 dest = SUBREG_REG (dest);
3274 if (dest == hard_frame_pointer_rtx)
3277 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3278 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3279 && (GET_CODE (x) != SET
3280 || GET_CODE (SET_SRC (x)) != PLUS
3281 || XEXP (SET_SRC (x), 0) != dest
3282 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3284 reg_eliminate[i].can_eliminate_previous
3285 = reg_eliminate[i].can_eliminate = 0;
3290 /* Verify that the initial elimination offsets did not change since the
3291 last call to set_initial_elim_offsets. This is used to catch cases
3292 where something illegal happened during reload_as_needed that could
3293 cause incorrect code to be generated if we did not check for it. */
3296 verify_initial_elim_offsets (void)
3300 if (!num_eliminable)
3303 #ifdef ELIMINABLE_REGS
3305 struct elim_table *ep;
3307 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3309 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3310 if (t != ep->initial_offset)
3315 INITIAL_FRAME_POINTER_OFFSET (t);
3316 if (t != reg_eliminate[0].initial_offset)
3323 /* Reset all offsets on eliminable registers to their initial values. */
3326 set_initial_elim_offsets (void)
3328 struct elim_table *ep = reg_eliminate;
3330 #ifdef ELIMINABLE_REGS
3331 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3333 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3334 ep->previous_offset = ep->offset = ep->initial_offset;
3337 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3338 ep->previous_offset = ep->offset = ep->initial_offset;
3341 num_not_at_initial_offset = 0;
3344 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3347 set_initial_eh_label_offset (rtx label)
3349 set_label_offsets (label, NULL_RTX, 1);
3352 /* Initialize the known label offsets.
3353 Set a known offset for each forced label to be at the initial offset
3354 of each elimination. We do this because we assume that all
3355 computed jumps occur from a location where each elimination is
3356 at its initial offset.
3357 For all other labels, show that we don't know the offsets. */
3360 set_initial_label_offsets (void)
3363 memset (offsets_known_at, 0, num_labels);
3365 for (x = forced_labels; x; x = XEXP (x, 1))
3367 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3369 for_each_eh_label (set_initial_eh_label_offset);
3372 /* Set all elimination offsets to the known values for the code label given
3376 set_offsets_for_label (rtx insn)
3379 int label_nr = CODE_LABEL_NUMBER (insn);
3380 struct elim_table *ep;
3382 num_not_at_initial_offset = 0;
3383 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3385 ep->offset = ep->previous_offset
3386 = offsets_at[label_nr - first_label_num][i];
3387 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3388 num_not_at_initial_offset++;
3392 /* See if anything that happened changes which eliminations are valid.
3393 For example, on the SPARC, whether or not the frame pointer can
3394 be eliminated can depend on what registers have been used. We need
3395 not check some conditions again (such as flag_omit_frame_pointer)
3396 since they can't have changed. */
3399 update_eliminables (HARD_REG_SET *pset)
3401 int previous_frame_pointer_needed = frame_pointer_needed;
3402 struct elim_table *ep;
3404 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3405 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3406 #ifdef ELIMINABLE_REGS
3407 || ! CAN_ELIMINATE (ep->from, ep->to)
3410 ep->can_eliminate = 0;
3412 /* Look for the case where we have discovered that we can't replace
3413 register A with register B and that means that we will now be
3414 trying to replace register A with register C. This means we can
3415 no longer replace register C with register B and we need to disable
3416 such an elimination, if it exists. This occurs often with A == ap,
3417 B == sp, and C == fp. */
3419 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3421 struct elim_table *op;
3424 if (! ep->can_eliminate && ep->can_eliminate_previous)
3426 /* Find the current elimination for ep->from, if there is a
3428 for (op = reg_eliminate;
3429 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3430 if (op->from == ep->from && op->can_eliminate)
3436 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3438 for (op = reg_eliminate;
3439 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3440 if (op->from == new_to && op->to == ep->to)
3441 op->can_eliminate = 0;
3445 /* See if any registers that we thought we could eliminate the previous
3446 time are no longer eliminable. If so, something has changed and we
3447 must spill the register. Also, recompute the number of eliminable
3448 registers and see if the frame pointer is needed; it is if there is
3449 no elimination of the frame pointer that we can perform. */
3451 frame_pointer_needed = 1;
3452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3454 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3455 && ep->to != HARD_FRAME_POINTER_REGNUM)
3456 frame_pointer_needed = 0;
3458 if (! ep->can_eliminate && ep->can_eliminate_previous)
3460 ep->can_eliminate_previous = 0;
3461 SET_HARD_REG_BIT (*pset, ep->from);
3466 /* If we didn't need a frame pointer last time, but we do now, spill
3467 the hard frame pointer. */
3468 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3469 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3472 /* Initialize the table of registers to eliminate. */
3475 init_elim_table (void)
3477 struct elim_table *ep;
3478 #ifdef ELIMINABLE_REGS
3479 const struct elim_table_1 *ep1;
3483 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3485 /* Does this function require a frame pointer? */
3487 frame_pointer_needed = (! flag_omit_frame_pointer
3488 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3489 and restore sp for alloca. So we can't eliminate
3490 the frame pointer in that case. At some point,
3491 we should improve this by emitting the
3492 sp-adjusting insns for this case. */
3493 || (current_function_calls_alloca
3494 && EXIT_IGNORE_STACK)
3495 || FRAME_POINTER_REQUIRED);
3499 #ifdef ELIMINABLE_REGS
3500 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3501 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3503 ep->from = ep1->from;
3505 ep->can_eliminate = ep->can_eliminate_previous
3506 = (CAN_ELIMINATE (ep->from, ep->to)
3507 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3510 reg_eliminate[0].from = reg_eliminate_1[0].from;
3511 reg_eliminate[0].to = reg_eliminate_1[0].to;
3512 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3513 = ! frame_pointer_needed;
3516 /* Count the number of eliminable registers and build the FROM and TO
3517 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3518 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3519 We depend on this. */
3520 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3522 num_eliminable += ep->can_eliminate;
3523 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3524 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3528 /* Kick all pseudos out of hard register REGNO.
3530 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3531 because we found we can't eliminate some register. In the case, no pseudos
3532 are allowed to be in the register, even if they are only in a block that
3533 doesn't require spill registers, unlike the case when we are spilling this
3534 hard reg to produce another spill register.
3536 Return nonzero if any pseudos needed to be kicked out. */
3539 spill_hard_reg (unsigned int regno, int cant_eliminate)
3545 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3546 regs_ever_live[regno] = 1;
3549 /* Spill every pseudo reg that was allocated to this reg
3550 or to something that overlaps this reg. */
3552 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3553 if (reg_renumber[i] >= 0
3554 && (unsigned int) reg_renumber[i] <= regno
3555 && ((unsigned int) reg_renumber[i]
3556 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3557 [PSEUDO_REGNO_MODE (i)]
3559 SET_REGNO_REG_SET (&spilled_pseudos, i);
3562 /* After find_reload_regs has been run for all insn that need reloads,
3563 and/or spill_hard_regs was called, this function is used to actually
3564 spill pseudo registers and try to reallocate them. It also sets up the
3565 spill_regs array for use by choose_reload_regs. */
3568 finish_spills (int global)
3570 struct insn_chain *chain;
3571 int something_changed = 0;
3573 reg_set_iterator rsi;
3575 /* Build the spill_regs array for the function. */
3576 /* If there are some registers still to eliminate and one of the spill regs
3577 wasn't ever used before, additional stack space may have to be
3578 allocated to store this register. Thus, we may have changed the offset
3579 between the stack and frame pointers, so mark that something has changed.
3581 One might think that we need only set VAL to 1 if this is a call-used
3582 register. However, the set of registers that must be saved by the
3583 prologue is not identical to the call-used set. For example, the
3584 register used by the call insn for the return PC is a call-used register,
3585 but must be saved by the prologue. */
3588 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3589 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3591 spill_reg_order[i] = n_spills;
3592 spill_regs[n_spills++] = i;
3593 if (num_eliminable && ! regs_ever_live[i])
3594 something_changed = 1;
3595 regs_ever_live[i] = 1;
3598 spill_reg_order[i] = -1;
3600 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3602 /* Record the current hard register the pseudo is allocated to in
3603 pseudo_previous_regs so we avoid reallocating it to the same
3604 hard reg in a later pass. */
3605 gcc_assert (reg_renumber[i] >= 0);
3607 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3608 /* Mark it as no longer having a hard register home. */
3609 reg_renumber[i] = -1;
3610 /* We will need to scan everything again. */
3611 something_changed = 1;
3614 /* Retry global register allocation if possible. */
3617 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3618 /* For every insn that needs reloads, set the registers used as spill
3619 regs in pseudo_forbidden_regs for every pseudo live across the
3621 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3623 EXECUTE_IF_SET_IN_REG_SET
3624 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3626 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3627 chain->used_spill_regs);
3629 EXECUTE_IF_SET_IN_REG_SET
3630 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3632 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3633 chain->used_spill_regs);
3637 /* Retry allocating the spilled pseudos. For each reg, merge the
3638 various reg sets that indicate which hard regs can't be used,
3639 and call retry_global_alloc.
3640 We change spill_pseudos here to only contain pseudos that did not
3641 get a new hard register. */
3642 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3643 if (reg_old_renumber[i] != reg_renumber[i])
3645 HARD_REG_SET forbidden;
3646 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3647 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3648 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3649 retry_global_alloc (i, forbidden);
3650 if (reg_renumber[i] >= 0)
3651 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3655 /* Fix up the register information in the insn chain.
3656 This involves deleting those of the spilled pseudos which did not get
3657 a new hard register home from the live_{before,after} sets. */
3658 for (chain = reload_insn_chain; chain; chain = chain->next)
3660 HARD_REG_SET used_by_pseudos;
3661 HARD_REG_SET used_by_pseudos2;
3663 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3664 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3666 /* Mark any unallocated hard regs as available for spills. That
3667 makes inheritance work somewhat better. */
3668 if (chain->need_reload)
3670 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3671 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3672 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3674 /* Save the old value for the sanity test below. */
3675 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3677 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3678 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3679 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3680 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3682 /* Make sure we only enlarge the set. */
3683 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3689 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3690 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3692 int regno = reg_renumber[i];
3693 if (reg_old_renumber[i] == regno)
3696 alter_reg (i, reg_old_renumber[i]);
3697 reg_old_renumber[i] = regno;
3701 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3703 fprintf (dump_file, " Register %d now in %d.\n\n",
3704 i, reg_renumber[i]);
3708 return something_changed;
3711 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3714 scan_paradoxical_subregs (rtx x)
3718 enum rtx_code code = GET_CODE (x);
3728 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3736 if (REG_P (SUBREG_REG (x))
3737 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3738 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3739 = GET_MODE_SIZE (GET_MODE (x));
3746 fmt = GET_RTX_FORMAT (code);
3747 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3750 scan_paradoxical_subregs (XEXP (x, i));
3751 else if (fmt[i] == 'E')
3754 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3755 scan_paradoxical_subregs (XVECEXP (x, i, j));
3760 /* Reload pseudo-registers into hard regs around each insn as needed.
3761 Additional register load insns are output before the insn that needs it
3762 and perhaps store insns after insns that modify the reloaded pseudo reg.
3764 reg_last_reload_reg and reg_reloaded_contents keep track of
3765 which registers are already available in reload registers.
3766 We update these for the reloads that we perform,
3767 as the insns are scanned. */
3770 reload_as_needed (int live_known)
3772 struct insn_chain *chain;
3773 #if defined (AUTO_INC_DEC)
3778 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3779 memset (spill_reg_store, 0, sizeof spill_reg_store);
3780 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3781 reg_has_output_reload = xmalloc (max_regno);
3782 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3783 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3785 set_initial_elim_offsets ();
3787 for (chain = reload_insn_chain; chain; chain = chain->next)
3790 rtx insn = chain->insn;
3791 rtx old_next = NEXT_INSN (insn);
3793 /* If we pass a label, copy the offsets from the label information
3794 into the current offsets of each elimination. */
3796 set_offsets_for_label (insn);
3798 else if (INSN_P (insn))
3800 rtx oldpat = copy_rtx (PATTERN (insn));
3802 /* If this is a USE and CLOBBER of a MEM, ensure that any
3803 references to eliminable registers have been removed. */
3805 if ((GET_CODE (PATTERN (insn)) == USE
3806 || GET_CODE (PATTERN (insn)) == CLOBBER)
3807 && MEM_P (XEXP (PATTERN (insn), 0)))
3808 XEXP (XEXP (PATTERN (insn), 0), 0)
3809 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3810 GET_MODE (XEXP (PATTERN (insn), 0)),
3813 /* If we need to do register elimination processing, do so.
3814 This might delete the insn, in which case we are done. */
3815 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3817 eliminate_regs_in_insn (insn, 1);
3820 update_eliminable_offsets ();
3825 /* If need_elim is nonzero but need_reload is zero, one might think
3826 that we could simply set n_reloads to 0. However, find_reloads
3827 could have done some manipulation of the insn (such as swapping
3828 commutative operands), and these manipulations are lost during
3829 the first pass for every insn that needs register elimination.
3830 So the actions of find_reloads must be redone here. */
3832 if (! chain->need_elim && ! chain->need_reload
3833 && ! chain->need_operand_change)
3835 /* First find the pseudo regs that must be reloaded for this insn.
3836 This info is returned in the tables reload_... (see reload.h).
3837 Also modify the body of INSN by substituting RELOAD
3838 rtx's for those pseudo regs. */
3841 memset (reg_has_output_reload, 0, max_regno);
3842 CLEAR_HARD_REG_SET (reg_is_output_reload);
3844 find_reloads (insn, 1, spill_indirect_levels, live_known,
3850 rtx next = NEXT_INSN (insn);
3853 prev = PREV_INSN (insn);
3855 /* Now compute which reload regs to reload them into. Perhaps
3856 reusing reload regs from previous insns, or else output
3857 load insns to reload them. Maybe output store insns too.
3858 Record the choices of reload reg in reload_reg_rtx. */
3859 choose_reload_regs (chain);
3861 /* Merge any reloads that we didn't combine for fear of
3862 increasing the number of spill registers needed but now
3863 discover can be safely merged. */
3864 if (SMALL_REGISTER_CLASSES)
3865 merge_assigned_reloads (insn);
3867 /* Generate the insns to reload operands into or out of
3868 their reload regs. */
3869 emit_reload_insns (chain);
3871 /* Substitute the chosen reload regs from reload_reg_rtx
3872 into the insn's body (or perhaps into the bodies of other
3873 load and store insn that we just made for reloading
3874 and that we moved the structure into). */
3875 subst_reloads (insn);
3877 /* If this was an ASM, make sure that all the reload insns
3878 we have generated are valid. If not, give an error
3881 if (asm_noperands (PATTERN (insn)) >= 0)
3882 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3883 if (p != insn && INSN_P (p)
3884 && GET_CODE (PATTERN (p)) != USE
3885 && (recog_memoized (p) < 0
3886 || (extract_insn (p), ! constrain_operands (1))))
3888 error_for_asm (insn,
3889 "%<asm%> operand requires "
3890 "impossible reload");
3895 if (num_eliminable && chain->need_elim)
3896 update_eliminable_offsets ();
3898 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3899 is no longer validly lying around to save a future reload.
3900 Note that this does not detect pseudos that were reloaded
3901 for this insn in order to be stored in
3902 (obeying register constraints). That is correct; such reload
3903 registers ARE still valid. */
3904 note_stores (oldpat, forget_old_reloads_1, NULL);
3906 /* There may have been CLOBBER insns placed after INSN. So scan
3907 between INSN and NEXT and use them to forget old reloads. */
3908 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3909 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3910 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3913 /* Likewise for regs altered by auto-increment in this insn.
3914 REG_INC notes have been changed by reloading:
3915 find_reloads_address_1 records substitutions for them,
3916 which have been performed by subst_reloads above. */
3917 for (i = n_reloads - 1; i >= 0; i--)
3919 rtx in_reg = rld[i].in_reg;
3922 enum rtx_code code = GET_CODE (in_reg);
3923 /* PRE_INC / PRE_DEC will have the reload register ending up
3924 with the same value as the stack slot, but that doesn't
3925 hold true for POST_INC / POST_DEC. Either we have to
3926 convert the memory access to a true POST_INC / POST_DEC,
3927 or we can't use the reload register for inheritance. */
3928 if ((code == POST_INC || code == POST_DEC)
3929 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3930 REGNO (rld[i].reg_rtx))
3931 /* Make sure it is the inc/dec pseudo, and not
3932 some other (e.g. output operand) pseudo. */
3933 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3934 == REGNO (XEXP (in_reg, 0))))
3937 rtx reload_reg = rld[i].reg_rtx;
3938 enum machine_mode mode = GET_MODE (reload_reg);
3942 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3944 /* We really want to ignore REG_INC notes here, so
3945 use PATTERN (p) as argument to reg_set_p . */
3946 if (reg_set_p (reload_reg, PATTERN (p)))
3948 n = count_occurrences (PATTERN (p), reload_reg, 0);
3953 n = validate_replace_rtx (reload_reg,
3954 gen_rtx_fmt_e (code,
3959 /* We must also verify that the constraints
3960 are met after the replacement. */
3963 n = constrain_operands (1);
3967 /* If the constraints were not met, then
3968 undo the replacement. */
3971 validate_replace_rtx (gen_rtx_fmt_e (code,
3984 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3986 /* Mark this as having an output reload so that the
3987 REG_INC processing code below won't invalidate
3988 the reload for inheritance. */
3989 SET_HARD_REG_BIT (reg_is_output_reload,
3990 REGNO (reload_reg));
3991 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3994 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3997 else if ((code == PRE_INC || code == PRE_DEC)
3998 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3999 REGNO (rld[i].reg_rtx))
4000 /* Make sure it is the inc/dec pseudo, and not
4001 some other (e.g. output operand) pseudo. */
4002 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4003 == REGNO (XEXP (in_reg, 0))))
4005 SET_HARD_REG_BIT (reg_is_output_reload,
4006 REGNO (rld[i].reg_rtx));
4007 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4011 /* If a pseudo that got a hard register is auto-incremented,
4012 we must purge records of copying it into pseudos without
4014 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4015 if (REG_NOTE_KIND (x) == REG_INC)
4017 /* See if this pseudo reg was reloaded in this insn.
4018 If so, its last-reload info is still valid
4019 because it is based on this insn's reload. */
4020 for (i = 0; i < n_reloads; i++)
4021 if (rld[i].out == XEXP (x, 0))
4025 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4029 /* A reload reg's contents are unknown after a label. */
4031 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4033 /* Don't assume a reload reg is still good after a call insn
4034 if it is a call-used reg, or if it contains a value that will
4035 be partially clobbered by the call. */
4036 else if (CALL_P (insn))
4038 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4039 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4044 free (reg_last_reload_reg);
4045 free (reg_has_output_reload);
4048 /* Discard all record of any value reloaded from X,
4049 or reloaded in X from someplace else;
4050 unless X is an output reload reg of the current insn.
4052 X may be a hard reg (the reload reg)
4053 or it may be a pseudo reg that was reloaded from. */
4056 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4057 void *data ATTRIBUTE_UNUSED)
4062 /* note_stores does give us subregs of hard regs,
4063 subreg_regno_offset requires a hard reg. */
4064 while (GET_CODE (x) == SUBREG)
4066 /* We ignore the subreg offset when calculating the regno,
4067 because we are using the entire underlying hard register
4077 if (regno >= FIRST_PSEUDO_REGISTER)
4083 nr = hard_regno_nregs[regno][GET_MODE (x)];
4084 /* Storing into a spilled-reg invalidates its contents.
4085 This can happen if a block-local pseudo is allocated to that reg
4086 and it wasn't spilled because this block's total need is 0.
4087 Then some insn might have an optional reload and use this reg. */
4088 for (i = 0; i < nr; i++)
4089 /* But don't do this if the reg actually serves as an output
4090 reload reg in the current instruction. */
4092 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4094 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4095 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4096 spill_reg_store[regno + i] = 0;
4100 /* Since value of X has changed,
4101 forget any value previously copied from it. */
4104 /* But don't forget a copy if this is the output reload
4105 that establishes the copy's validity. */
4106 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4107 reg_last_reload_reg[regno + nr] = 0;
4110 /* The following HARD_REG_SETs indicate when each hard register is
4111 used for a reload of various parts of the current insn. */
4113 /* If reg is unavailable for all reloads. */
4114 static HARD_REG_SET reload_reg_unavailable;
4115 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4116 static HARD_REG_SET reload_reg_used;
4117 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4118 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4119 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4120 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4121 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4122 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4123 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4124 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4125 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4126 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4127 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4128 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4129 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4130 static HARD_REG_SET reload_reg_used_in_op_addr;
4131 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4132 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4133 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4134 static HARD_REG_SET reload_reg_used_in_insn;
4135 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4136 static HARD_REG_SET reload_reg_used_in_other_addr;
4138 /* If reg is in use as a reload reg for any sort of reload. */
4139 static HARD_REG_SET reload_reg_used_at_all;
4141 /* If reg is use as an inherited reload. We just mark the first register
4143 static HARD_REG_SET reload_reg_used_for_inherit;
4145 /* Records which hard regs are used in any way, either as explicit use or
4146 by being allocated to a pseudo during any point of the current insn. */
4147 static HARD_REG_SET reg_used_in_insn;
4149 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4150 TYPE. MODE is used to indicate how many consecutive regs are
4154 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4155 enum machine_mode mode)
4157 unsigned int nregs = hard_regno_nregs[regno][mode];
4160 for (i = regno; i < nregs + regno; i++)
4165 SET_HARD_REG_BIT (reload_reg_used, i);
4168 case RELOAD_FOR_INPUT_ADDRESS:
4169 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4172 case RELOAD_FOR_INPADDR_ADDRESS:
4173 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4176 case RELOAD_FOR_OUTPUT_ADDRESS:
4177 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4180 case RELOAD_FOR_OUTADDR_ADDRESS:
4181 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4184 case RELOAD_FOR_OPERAND_ADDRESS:
4185 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4188 case RELOAD_FOR_OPADDR_ADDR:
4189 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4192 case RELOAD_FOR_OTHER_ADDRESS:
4193 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4196 case RELOAD_FOR_INPUT:
4197 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4200 case RELOAD_FOR_OUTPUT:
4201 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4204 case RELOAD_FOR_INSN:
4205 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4209 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4213 /* Similarly, but show REGNO is no longer in use for a reload. */
4216 clear_reload_reg_in_use (unsigned int regno, int opnum,
4217 enum reload_type type, enum machine_mode mode)
4219 unsigned int nregs = hard_regno_nregs[regno][mode];
4220 unsigned int start_regno, end_regno, r;
4222 /* A complication is that for some reload types, inheritance might
4223 allow multiple reloads of the same types to share a reload register.
4224 We set check_opnum if we have to check only reloads with the same
4225 operand number, and check_any if we have to check all reloads. */
4226 int check_opnum = 0;
4228 HARD_REG_SET *used_in_set;
4233 used_in_set = &reload_reg_used;
4236 case RELOAD_FOR_INPUT_ADDRESS:
4237 used_in_set = &reload_reg_used_in_input_addr[opnum];
4240 case RELOAD_FOR_INPADDR_ADDRESS:
4242 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4245 case RELOAD_FOR_OUTPUT_ADDRESS:
4246 used_in_set = &reload_reg_used_in_output_addr[opnum];
4249 case RELOAD_FOR_OUTADDR_ADDRESS:
4251 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4254 case RELOAD_FOR_OPERAND_ADDRESS:
4255 used_in_set = &reload_reg_used_in_op_addr;
4258 case RELOAD_FOR_OPADDR_ADDR:
4260 used_in_set = &reload_reg_used_in_op_addr_reload;
4263 case RELOAD_FOR_OTHER_ADDRESS:
4264 used_in_set = &reload_reg_used_in_other_addr;
4268 case RELOAD_FOR_INPUT:
4269 used_in_set = &reload_reg_used_in_input[opnum];
4272 case RELOAD_FOR_OUTPUT:
4273 used_in_set = &reload_reg_used_in_output[opnum];
4276 case RELOAD_FOR_INSN:
4277 used_in_set = &reload_reg_used_in_insn;
4282 /* We resolve conflicts with remaining reloads of the same type by
4283 excluding the intervals of reload registers by them from the
4284 interval of freed reload registers. Since we only keep track of
4285 one set of interval bounds, we might have to exclude somewhat
4286 more than what would be necessary if we used a HARD_REG_SET here.
4287 But this should only happen very infrequently, so there should
4288 be no reason to worry about it. */
4290 start_regno = regno;
4291 end_regno = regno + nregs;
4292 if (check_opnum || check_any)
4294 for (i = n_reloads - 1; i >= 0; i--)
4296 if (rld[i].when_needed == type
4297 && (check_any || rld[i].opnum == opnum)
4300 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4301 unsigned int conflict_end
4303 + hard_regno_nregs[conflict_start][rld[i].mode]);
4305 /* If there is an overlap with the first to-be-freed register,
4306 adjust the interval start. */
4307 if (conflict_start <= start_regno && conflict_end > start_regno)
4308 start_regno = conflict_end;
4309 /* Otherwise, if there is a conflict with one of the other
4310 to-be-freed registers, adjust the interval end. */
4311 if (conflict_start > start_regno && conflict_start < end_regno)
4312 end_regno = conflict_start;
4317 for (r = start_regno; r < end_regno; r++)
4318 CLEAR_HARD_REG_BIT (*used_in_set, r);
4321 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4322 specified by OPNUM and TYPE. */
4325 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4329 /* In use for a RELOAD_OTHER means it's not available for anything. */
4330 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4331 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4337 /* In use for anything means we can't use it for RELOAD_OTHER. */
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4339 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4340 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4341 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4344 for (i = 0; i < reload_n_operands; i++)
4345 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4346 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4347 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4348 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4349 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4350 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4355 case RELOAD_FOR_INPUT:
4356 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4357 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4360 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4363 /* If it is used for some other input, can't use it. */
4364 for (i = 0; i < reload_n_operands; i++)
4365 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4368 /* If it is used in a later operand's address, can't use it. */
4369 for (i = opnum + 1; i < reload_n_operands; i++)
4370 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4371 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4376 case RELOAD_FOR_INPUT_ADDRESS:
4377 /* Can't use a register if it is used for an input address for this
4378 operand or used as an input in an earlier one. */
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4383 for (i = 0; i < opnum; i++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4389 case RELOAD_FOR_INPADDR_ADDRESS:
4390 /* Can't use a register if it is used for an input address
4391 for this operand or used as an input in an earlier
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4396 for (i = 0; i < opnum; i++)
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4402 case RELOAD_FOR_OUTPUT_ADDRESS:
4403 /* Can't use a register if it is used for an output address for this
4404 operand or used as an output in this or a later operand. Note
4405 that multiple output operands are emitted in reverse order, so
4406 the conflicting ones are those with lower indices. */
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4410 for (i = 0; i <= opnum; i++)
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4416 case RELOAD_FOR_OUTADDR_ADDRESS:
4417 /* Can't use a register if it is used for an output address
4418 for this operand or used as an output in this or a
4419 later operand. Note that multiple output operands are
4420 emitted in reverse order, so the conflicting ones are
4421 those with lower indices. */
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4425 for (i = 0; i <= opnum; i++)
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4431 case RELOAD_FOR_OPERAND_ADDRESS:
4432 for (i = 0; i < reload_n_operands; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4436 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4437 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4439 case RELOAD_FOR_OPADDR_ADDR:
4440 for (i = 0; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4444 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4446 case RELOAD_FOR_OUTPUT:
4447 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4448 outputs, or an operand address for this or an earlier output.
4449 Note that multiple output operands are emitted in reverse order,
4450 so the conflicting ones are those with higher indices. */
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4454 for (i = 0; i < reload_n_operands; i++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4458 for (i = opnum; i < reload_n_operands; i++)
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4460 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4465 case RELOAD_FOR_INSN:
4466 for (i = 0; i < reload_n_operands; i++)
4467 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4468 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4471 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4472 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4474 case RELOAD_FOR_OTHER_ADDRESS:
4475 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4482 /* Return 1 if the value in reload reg REGNO, as used by a reload
4483 needed for the part of the insn specified by OPNUM and TYPE,
4484 is still available in REGNO at the end of the insn.
4486 We can assume that the reload reg was already tested for availability
4487 at the time it is needed, and we should not check this again,
4488 in case the reg has already been marked in use. */
4491 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4498 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4499 its value must reach the end. */
4502 /* If this use is for part of the insn,
4503 its value reaches if no subsequent part uses the same register.
4504 Just like the above function, don't try to do this with lots
4507 case RELOAD_FOR_OTHER_ADDRESS:
4508 /* Here we check for everything else, since these don't conflict
4509 with anything else and everything comes later. */
4511 for (i = 0; i < reload_n_operands; i++)
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4513 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4516 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4520 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4521 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4522 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4523 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4525 case RELOAD_FOR_INPUT_ADDRESS:
4526 case RELOAD_FOR_INPADDR_ADDRESS:
4527 /* Similar, except that we check only for this and subsequent inputs
4528 and the address of only subsequent inputs and we do not need
4529 to check for RELOAD_OTHER objects since they are known not to
4532 for (i = opnum; i < reload_n_operands; i++)
4533 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4536 for (i = opnum + 1; i < reload_n_operands; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4538 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4541 for (i = 0; i < reload_n_operands; i++)
4542 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4550 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4551 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4552 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4554 case RELOAD_FOR_INPUT:
4555 /* Similar to input address, except we start at the next operand for
4556 both input and input address and we do not check for
4557 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4560 for (i = opnum + 1; i < reload_n_operands; i++)
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4566 /* ... fall through ... */
4568 case RELOAD_FOR_OPERAND_ADDRESS:
4569 /* Check outputs and their addresses. */
4571 for (i = 0; i < reload_n_operands; i++)
4572 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4577 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4579 case RELOAD_FOR_OPADDR_ADDR:
4580 for (i = 0; i < reload_n_operands; i++)
4581 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4582 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4583 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4586 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4587 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4588 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4590 case RELOAD_FOR_INSN:
4591 /* These conflict with other outputs with RELOAD_OTHER. So
4592 we need only check for output addresses. */
4594 opnum = reload_n_operands;
4596 /* ... fall through ... */
4598 case RELOAD_FOR_OUTPUT:
4599 case RELOAD_FOR_OUTPUT_ADDRESS:
4600 case RELOAD_FOR_OUTADDR_ADDRESS:
4601 /* We already know these can't conflict with a later output. So the
4602 only thing to check are later output addresses.
4603 Note that multiple output operands are emitted in reverse order,
4604 so the conflicting ones are those with lower indices. */
4605 for (i = 0; i < opnum; i++)
4606 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4607 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4617 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4620 This function uses the same algorithm as reload_reg_free_p above. */
4623 reloads_conflict (int r1, int r2)
4625 enum reload_type r1_type = rld[r1].when_needed;
4626 enum reload_type r2_type = rld[r2].when_needed;
4627 int r1_opnum = rld[r1].opnum;
4628 int r2_opnum = rld[r2].opnum;
4630 /* RELOAD_OTHER conflicts with everything. */
4631 if (r2_type == RELOAD_OTHER)
4634 /* Otherwise, check conflicts differently for each type. */
4638 case RELOAD_FOR_INPUT:
4639 return (r2_type == RELOAD_FOR_INSN
4640 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4641 || r2_type == RELOAD_FOR_OPADDR_ADDR
4642 || r2_type == RELOAD_FOR_INPUT
4643 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4644 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4645 && r2_opnum > r1_opnum));
4647 case RELOAD_FOR_INPUT_ADDRESS:
4648 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4649 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4651 case RELOAD_FOR_INPADDR_ADDRESS:
4652 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4653 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4655 case RELOAD_FOR_OUTPUT_ADDRESS:
4656 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4657 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4659 case RELOAD_FOR_OUTADDR_ADDRESS:
4660 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4661 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4663 case RELOAD_FOR_OPERAND_ADDRESS:
4664 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4665 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4667 case RELOAD_FOR_OPADDR_ADDR:
4668 return (r2_type == RELOAD_FOR_INPUT
4669 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4671 case RELOAD_FOR_OUTPUT:
4672 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4673 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4674 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4675 && r2_opnum >= r1_opnum));
4677 case RELOAD_FOR_INSN:
4678 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4679 || r2_type == RELOAD_FOR_INSN
4680 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4682 case RELOAD_FOR_OTHER_ADDRESS:
4683 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4693 /* Indexed by reload number, 1 if incoming value
4694 inherited from previous insns. */
4695 static char reload_inherited[MAX_RELOADS];
4697 /* For an inherited reload, this is the insn the reload was inherited from,
4698 if we know it. Otherwise, this is 0. */
4699 static rtx reload_inheritance_insn[MAX_RELOADS];
4701 /* If nonzero, this is a place to get the value of the reload,
4702 rather than using reload_in. */
4703 static rtx reload_override_in[MAX_RELOADS];
4705 /* For each reload, the hard register number of the register used,
4706 or -1 if we did not need a register for this reload. */
4707 static int reload_spill_index[MAX_RELOADS];
4709 /* Subroutine of free_for_value_p, used to check a single register.
4710 START_REGNO is the starting regno of the full reload register
4711 (possibly comprising multiple hard registers) that we are considering. */
4714 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4715 enum reload_type type, rtx value, rtx out,
4716 int reloadnum, int ignore_address_reloads)
4719 /* Set if we see an input reload that must not share its reload register
4720 with any new earlyclobber, but might otherwise share the reload
4721 register with an output or input-output reload. */
4722 int check_earlyclobber = 0;
4726 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4729 if (out == const0_rtx)
4735 /* We use some pseudo 'time' value to check if the lifetimes of the
4736 new register use would overlap with the one of a previous reload
4737 that is not read-only or uses a different value.
4738 The 'time' used doesn't have to be linear in any shape or form, just
4740 Some reload types use different 'buckets' for each operand.
4741 So there are MAX_RECOG_OPERANDS different time values for each
4743 We compute TIME1 as the time when the register for the prospective
4744 new reload ceases to be live, and TIME2 for each existing
4745 reload as the time when that the reload register of that reload
4747 Where there is little to be gained by exact lifetime calculations,
4748 we just make conservative assumptions, i.e. a longer lifetime;
4749 this is done in the 'default:' cases. */
4752 case RELOAD_FOR_OTHER_ADDRESS:
4753 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4754 time1 = copy ? 0 : 1;
4757 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4759 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4760 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4761 respectively, to the time values for these, we get distinct time
4762 values. To get distinct time values for each operand, we have to
4763 multiply opnum by at least three. We round that up to four because
4764 multiply by four is often cheaper. */
4765 case RELOAD_FOR_INPADDR_ADDRESS:
4766 time1 = opnum * 4 + 2;
4768 case RELOAD_FOR_INPUT_ADDRESS:
4769 time1 = opnum * 4 + 3;
4771 case RELOAD_FOR_INPUT:
4772 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4773 executes (inclusive). */
4774 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4776 case RELOAD_FOR_OPADDR_ADDR:
4778 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4779 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4781 case RELOAD_FOR_OPERAND_ADDRESS:
4782 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4784 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4786 case RELOAD_FOR_OUTADDR_ADDRESS:
4787 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4789 case RELOAD_FOR_OUTPUT_ADDRESS:
4790 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4793 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4796 for (i = 0; i < n_reloads; i++)
4798 rtx reg = rld[i].reg_rtx;
4799 if (reg && REG_P (reg)
4800 && ((unsigned) regno - true_regnum (reg)
4801 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4804 rtx other_input = rld[i].in;
4806 /* If the other reload loads the same input value, that
4807 will not cause a conflict only if it's loading it into
4808 the same register. */
4809 if (true_regnum (reg) != start_regno)
4810 other_input = NULL_RTX;
4811 if (! other_input || ! rtx_equal_p (other_input, value)
4812 || rld[i].out || out)
4815 switch (rld[i].when_needed)
4817 case RELOAD_FOR_OTHER_ADDRESS:
4820 case RELOAD_FOR_INPADDR_ADDRESS:
4821 /* find_reloads makes sure that a
4822 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4823 by at most one - the first -
4824 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4825 address reload is inherited, the address address reload
4826 goes away, so we can ignore this conflict. */
4827 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4828 && ignore_address_reloads
4829 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4830 Then the address address is still needed to store
4831 back the new address. */
4832 && ! rld[reloadnum].out)
4834 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4835 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4837 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4838 && ignore_address_reloads
4839 /* Unless we are reloading an auto_inc expression. */
4840 && ! rld[reloadnum].out)
4842 time2 = rld[i].opnum * 4 + 2;
4844 case RELOAD_FOR_INPUT_ADDRESS:
4845 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4846 && ignore_address_reloads
4847 && ! rld[reloadnum].out)
4849 time2 = rld[i].opnum * 4 + 3;
4851 case RELOAD_FOR_INPUT:
4852 time2 = rld[i].opnum * 4 + 4;
4853 check_earlyclobber = 1;
4855 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4856 == MAX_RECOG_OPERAND * 4 */
4857 case RELOAD_FOR_OPADDR_ADDR:
4858 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4859 && ignore_address_reloads
4860 && ! rld[reloadnum].out)
4862 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4864 case RELOAD_FOR_OPERAND_ADDRESS:
4865 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4866 check_earlyclobber = 1;
4868 case RELOAD_FOR_INSN:
4869 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4871 case RELOAD_FOR_OUTPUT:
4872 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4873 instruction is executed. */
4874 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4876 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4877 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4879 case RELOAD_FOR_OUTADDR_ADDRESS:
4880 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4881 && ignore_address_reloads
4882 && ! rld[reloadnum].out)
4884 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4886 case RELOAD_FOR_OUTPUT_ADDRESS:
4887 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4890 /* If there is no conflict in the input part, handle this
4891 like an output reload. */
4892 if (! rld[i].in || rtx_equal_p (other_input, value))
4894 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4895 /* Earlyclobbered outputs must conflict with inputs. */
4896 if (earlyclobber_operand_p (rld[i].out))
4897 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4902 /* RELOAD_OTHER might be live beyond instruction execution,
4903 but this is not obvious when we set time2 = 1. So check
4904 here if there might be a problem with the new reload
4905 clobbering the register used by the RELOAD_OTHER. */
4913 && (! rld[i].in || rld[i].out
4914 || ! rtx_equal_p (other_input, value)))
4915 || (out && rld[reloadnum].out_reg
4916 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4922 /* Earlyclobbered outputs must conflict with inputs. */
4923 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4929 /* Return 1 if the value in reload reg REGNO, as used by a reload
4930 needed for the part of the insn specified by OPNUM and TYPE,
4931 may be used to load VALUE into it.
4933 MODE is the mode in which the register is used, this is needed to
4934 determine how many hard regs to test.
4936 Other read-only reloads with the same value do not conflict
4937 unless OUT is nonzero and these other reloads have to live while
4938 output reloads live.
4939 If OUT is CONST0_RTX, this is a special case: it means that the
4940 test should not be for using register REGNO as reload register, but
4941 for copying from register REGNO into the reload register.
4943 RELOADNUM is the number of the reload we want to load this value for;
4944 a reload does not conflict with itself.
4946 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4947 reloads that load an address for the very reload we are considering.
4949 The caller has to make sure that there is no conflict with the return
4953 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4954 enum reload_type type, rtx value, rtx out, int reloadnum,
4955 int ignore_address_reloads)
4957 int nregs = hard_regno_nregs[regno][mode];
4959 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4960 value, out, reloadnum,
4961 ignore_address_reloads))
4966 /* Return nonzero if the rtx X is invariant over the current function. */
4967 /* ??? Actually, the places where we use this expect exactly what is
4968 tested here, and not everything that is function invariant. In
4969 particular, the frame pointer and arg pointer are special cased;
4970 pic_offset_table_rtx is not, and we must not spill these things to
4974 function_invariant_p (rtx x)
4978 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4980 if (GET_CODE (x) == PLUS
4981 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4982 && CONSTANT_P (XEXP (x, 1)))
4987 /* Determine whether the reload reg X overlaps any rtx'es used for
4988 overriding inheritance. Return nonzero if so. */
4991 conflicts_with_override (rtx x)
4994 for (i = 0; i < n_reloads; i++)
4995 if (reload_override_in[i]
4996 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5001 /* Give an error message saying we failed to find a reload for INSN,
5002 and clear out reload R. */
5004 failed_reload (rtx insn, int r)
5006 if (asm_noperands (PATTERN (insn)) < 0)
5007 /* It's the compiler's fault. */
5008 fatal_insn ("could not find a spill register", insn);
5010 /* It's the user's fault; the operand's mode and constraint
5011 don't match. Disable this reload so we don't crash in final. */
5012 error_for_asm (insn,
5013 "%<asm%> operand constraint incompatible with operand size");
5017 rld[r].optional = 1;
5018 rld[r].secondary_p = 1;
5021 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5022 for reload R. If it's valid, get an rtx for it. Return nonzero if
5025 set_reload_reg (int i, int r)
5028 rtx reg = spill_reg_rtx[i];
5030 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5031 spill_reg_rtx[i] = reg
5032 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5034 regno = true_regnum (reg);
5036 /* Detect when the reload reg can't hold the reload mode.
5037 This used to be one `if', but Sequent compiler can't handle that. */
5038 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5040 enum machine_mode test_mode = VOIDmode;
5042 test_mode = GET_MODE (rld[r].in);
5043 /* If rld[r].in has VOIDmode, it means we will load it
5044 in whatever mode the reload reg has: to wit, rld[r].mode.
5045 We have already tested that for validity. */
5046 /* Aside from that, we need to test that the expressions
5047 to reload from or into have modes which are valid for this
5048 reload register. Otherwise the reload insns would be invalid. */
5049 if (! (rld[r].in != 0 && test_mode != VOIDmode
5050 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5051 if (! (rld[r].out != 0
5052 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5054 /* The reg is OK. */
5057 /* Mark as in use for this insn the reload regs we use
5059 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5060 rld[r].when_needed, rld[r].mode);
5062 rld[r].reg_rtx = reg;
5063 reload_spill_index[r] = spill_regs[i];
5070 /* Find a spill register to use as a reload register for reload R.
5071 LAST_RELOAD is nonzero if this is the last reload for the insn being
5074 Set rld[R].reg_rtx to the register allocated.
5076 We return 1 if successful, or 0 if we couldn't find a spill reg and
5077 we didn't change anything. */
5080 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5085 /* If we put this reload ahead, thinking it is a group,
5086 then insist on finding a group. Otherwise we can grab a
5087 reg that some other reload needs.
5088 (That can happen when we have a 68000 DATA_OR_FP_REG
5089 which is a group of data regs or one fp reg.)
5090 We need not be so restrictive if there are no more reloads
5093 ??? Really it would be nicer to have smarter handling
5094 for that kind of reg class, where a problem like this is normal.
5095 Perhaps those classes should be avoided for reloading
5096 by use of more alternatives. */
5098 int force_group = rld[r].nregs > 1 && ! last_reload;
5100 /* If we want a single register and haven't yet found one,
5101 take any reg in the right class and not in use.
5102 If we want a consecutive group, here is where we look for it.
5104 We use two passes so we can first look for reload regs to
5105 reuse, which are already in use for other reloads in this insn,
5106 and only then use additional registers.
5107 I think that maximizing reuse is needed to make sure we don't
5108 run out of reload regs. Suppose we have three reloads, and
5109 reloads A and B can share regs. These need two regs.
5110 Suppose A and B are given different regs.
5111 That leaves none for C. */
5112 for (pass = 0; pass < 2; pass++)
5114 /* I is the index in spill_regs.
5115 We advance it round-robin between insns to use all spill regs
5116 equally, so that inherited reloads have a chance
5117 of leapfrogging each other. */
5121 for (count = 0; count < n_spills; count++)
5123 int class = (int) rld[r].class;
5129 regnum = spill_regs[i];
5131 if ((reload_reg_free_p (regnum, rld[r].opnum,
5134 /* We check reload_reg_used to make sure we
5135 don't clobber the return register. */
5136 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5137 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5138 rld[r].when_needed, rld[r].in,
5140 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5141 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5142 /* Look first for regs to share, then for unshared. But
5143 don't share regs used for inherited reloads; they are
5144 the ones we want to preserve. */
5146 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5148 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5151 int nr = hard_regno_nregs[regnum][rld[r].mode];
5152 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5153 (on 68000) got us two FP regs. If NR is 1,
5154 we would reject both of them. */
5157 /* If we need only one reg, we have already won. */
5160 /* But reject a single reg if we demand a group. */
5165 /* Otherwise check that as many consecutive regs as we need
5166 are available here. */
5169 int regno = regnum + nr - 1;
5170 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5171 && spill_reg_order[regno] >= 0
5172 && reload_reg_free_p (regno, rld[r].opnum,
5173 rld[r].when_needed)))
5182 /* If we found something on pass 1, omit pass 2. */
5183 if (count < n_spills)
5187 /* We should have found a spill register by now. */
5188 if (count >= n_spills)
5191 /* I is the index in SPILL_REG_RTX of the reload register we are to
5192 allocate. Get an rtx for it and find its register number. */
5194 return set_reload_reg (i, r);
5197 /* Initialize all the tables needed to allocate reload registers.
5198 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5199 is the array we use to restore the reg_rtx field for every reload. */
5202 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5206 for (i = 0; i < n_reloads; i++)
5207 rld[i].reg_rtx = save_reload_reg_rtx[i];
5209 memset (reload_inherited, 0, MAX_RELOADS);
5210 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5211 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5213 CLEAR_HARD_REG_SET (reload_reg_used);
5214 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5215 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5216 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5218 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5220 CLEAR_HARD_REG_SET (reg_used_in_insn);
5223 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5224 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5225 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5226 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5227 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5228 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5231 for (i = 0; i < reload_n_operands; i++)
5233 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5241 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5243 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5245 for (i = 0; i < n_reloads; i++)
5246 /* If we have already decided to use a certain register,
5247 don't use it in another way. */
5249 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5250 rld[i].when_needed, rld[i].mode);
5253 /* Assign hard reg targets for the pseudo-registers we must reload
5254 into hard regs for this insn.
5255 Also output the instructions to copy them in and out of the hard regs.
5257 For machines with register classes, we are responsible for
5258 finding a reload reg in the proper class. */
5261 choose_reload_regs (struct insn_chain *chain)
5263 rtx insn = chain->insn;
5265 unsigned int max_group_size = 1;
5266 enum reg_class group_class = NO_REGS;
5267 int pass, win, inheritance;
5269 rtx save_reload_reg_rtx[MAX_RELOADS];
5271 /* In order to be certain of getting the registers we need,
5272 we must sort the reloads into order of increasing register class.
5273 Then our grabbing of reload registers will parallel the process
5274 that provided the reload registers.
5276 Also note whether any of the reloads wants a consecutive group of regs.
5277 If so, record the maximum size of the group desired and what
5278 register class contains all the groups needed by this insn. */
5280 for (j = 0; j < n_reloads; j++)
5282 reload_order[j] = j;
5283 reload_spill_index[j] = -1;
5285 if (rld[j].nregs > 1)
5287 max_group_size = MAX (rld[j].nregs, max_group_size);
5289 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5292 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5296 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5298 /* If -O, try first with inheritance, then turning it off.
5299 If not -O, don't do inheritance.
5300 Using inheritance when not optimizing leads to paradoxes
5301 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5302 because one side of the comparison might be inherited. */
5304 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5306 choose_reload_regs_init (chain, save_reload_reg_rtx);
5308 /* Process the reloads in order of preference just found.
5309 Beyond this point, subregs can be found in reload_reg_rtx.
5311 This used to look for an existing reloaded home for all of the
5312 reloads, and only then perform any new reloads. But that could lose
5313 if the reloads were done out of reg-class order because a later
5314 reload with a looser constraint might have an old home in a register
5315 needed by an earlier reload with a tighter constraint.
5317 To solve this, we make two passes over the reloads, in the order
5318 described above. In the first pass we try to inherit a reload
5319 from a previous insn. If there is a later reload that needs a
5320 class that is a proper subset of the class being processed, we must
5321 also allocate a spill register during the first pass.
5323 Then make a second pass over the reloads to allocate any reloads
5324 that haven't been given registers yet. */
5326 for (j = 0; j < n_reloads; j++)
5328 int r = reload_order[j];
5329 rtx search_equiv = NULL_RTX;
5331 /* Ignore reloads that got marked inoperative. */
5332 if (rld[r].out == 0 && rld[r].in == 0
5333 && ! rld[r].secondary_p)
5336 /* If find_reloads chose to use reload_in or reload_out as a reload
5337 register, we don't need to chose one. Otherwise, try even if it
5338 found one since we might save an insn if we find the value lying
5340 Try also when reload_in is a pseudo without a hard reg. */
5341 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5342 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5343 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5344 && !MEM_P (rld[r].in)
5345 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5348 #if 0 /* No longer needed for correct operation.
5349 It might give better code, or might not; worth an experiment? */
5350 /* If this is an optional reload, we can't inherit from earlier insns
5351 until we are sure that any non-optional reloads have been allocated.
5352 The following code takes advantage of the fact that optional reloads
5353 are at the end of reload_order. */
5354 if (rld[r].optional != 0)
5355 for (i = 0; i < j; i++)
5356 if ((rld[reload_order[i]].out != 0
5357 || rld[reload_order[i]].in != 0
5358 || rld[reload_order[i]].secondary_p)
5359 && ! rld[reload_order[i]].optional
5360 && rld[reload_order[i]].reg_rtx == 0)
5361 allocate_reload_reg (chain, reload_order[i], 0);
5364 /* First see if this pseudo is already available as reloaded
5365 for a previous insn. We cannot try to inherit for reloads
5366 that are smaller than the maximum number of registers needed
5367 for groups unless the register we would allocate cannot be used
5370 We could check here to see if this is a secondary reload for
5371 an object that is already in a register of the desired class.
5372 This would avoid the need for the secondary reload register.
5373 But this is complex because we can't easily determine what
5374 objects might want to be loaded via this reload. So let a
5375 register be allocated here. In `emit_reload_insns' we suppress
5376 one of the loads in the case described above. */
5382 enum machine_mode mode = VOIDmode;
5386 else if (REG_P (rld[r].in))
5388 regno = REGNO (rld[r].in);
5389 mode = GET_MODE (rld[r].in);
5391 else if (REG_P (rld[r].in_reg))
5393 regno = REGNO (rld[r].in_reg);
5394 mode = GET_MODE (rld[r].in_reg);
5396 else if (GET_CODE (rld[r].in_reg) == SUBREG
5397 && REG_P (SUBREG_REG (rld[r].in_reg)))
5399 byte = SUBREG_BYTE (rld[r].in_reg);
5400 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5401 if (regno < FIRST_PSEUDO_REGISTER)
5402 regno = subreg_regno (rld[r].in_reg);
5403 mode = GET_MODE (rld[r].in_reg);
5406 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5407 || GET_CODE (rld[r].in_reg) == PRE_DEC
5408 || GET_CODE (rld[r].in_reg) == POST_INC
5409 || GET_CODE (rld[r].in_reg) == POST_DEC)
5410 && REG_P (XEXP (rld[r].in_reg, 0)))
5412 regno = REGNO (XEXP (rld[r].in_reg, 0));
5413 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5414 rld[r].out = rld[r].in;
5418 /* This won't work, since REGNO can be a pseudo reg number.
5419 Also, it takes much more hair to keep track of all the things
5420 that can invalidate an inherited reload of part of a pseudoreg. */
5421 else if (GET_CODE (rld[r].in) == SUBREG
5422 && REG_P (SUBREG_REG (rld[r].in)))
5423 regno = subreg_regno (rld[r].in);
5426 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5428 enum reg_class class = rld[r].class, last_class;
5429 rtx last_reg = reg_last_reload_reg[regno];
5430 enum machine_mode need_mode;
5432 i = REGNO (last_reg);
5433 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5434 last_class = REGNO_REG_CLASS (i);
5440 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5441 + byte * BITS_PER_UNIT,
5442 GET_MODE_CLASS (mode));
5444 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5445 >= GET_MODE_SIZE (need_mode))
5446 #ifdef CANNOT_CHANGE_MODE_CLASS
5447 /* Verify that the register in "i" can be obtained
5449 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5450 GET_MODE (last_reg),
5453 && reg_reloaded_contents[i] == regno
5454 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5455 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5456 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5457 /* Even if we can't use this register as a reload
5458 register, we might use it for reload_override_in,
5459 if copying it to the desired class is cheap
5461 || ((REGISTER_MOVE_COST (mode, last_class, class)
5462 < MEMORY_MOVE_COST (mode, class, 1))
5463 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5464 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5468 #ifdef SECONDARY_MEMORY_NEEDED
5469 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5474 && (rld[r].nregs == max_group_size
5475 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5477 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5478 rld[r].when_needed, rld[r].in,
5481 /* If a group is needed, verify that all the subsequent
5482 registers still have their values intact. */
5483 int nr = hard_regno_nregs[i][rld[r].mode];
5486 for (k = 1; k < nr; k++)
5487 if (reg_reloaded_contents[i + k] != regno
5488 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5496 last_reg = (GET_MODE (last_reg) == mode
5497 ? last_reg : gen_rtx_REG (mode, i));
5500 for (k = 0; k < nr; k++)
5501 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5504 /* We found a register that contains the
5505 value we need. If this register is the
5506 same as an `earlyclobber' operand of the
5507 current insn, just mark it as a place to
5508 reload from since we can't use it as the
5509 reload register itself. */
5511 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5512 if (reg_overlap_mentioned_for_reload_p
5513 (reg_last_reload_reg[regno],
5514 reload_earlyclobbers[i1]))
5517 if (i1 != n_earlyclobbers
5518 || ! (free_for_value_p (i, rld[r].mode,
5520 rld[r].when_needed, rld[r].in,
5522 /* Don't use it if we'd clobber a pseudo reg. */
5523 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5525 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5526 /* Don't clobber the frame pointer. */
5527 || (i == HARD_FRAME_POINTER_REGNUM
5528 && frame_pointer_needed
5530 /* Don't really use the inherited spill reg
5531 if we need it wider than we've got it. */
5532 || (GET_MODE_SIZE (rld[r].mode)
5533 > GET_MODE_SIZE (mode))
5536 /* If find_reloads chose reload_out as reload
5537 register, stay with it - that leaves the
5538 inherited register for subsequent reloads. */
5539 || (rld[r].out && rld[r].reg_rtx
5540 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5542 if (! rld[r].optional)
5544 reload_override_in[r] = last_reg;
5545 reload_inheritance_insn[r]
5546 = reg_reloaded_insn[i];
5552 /* We can use this as a reload reg. */
5553 /* Mark the register as in use for this part of
5555 mark_reload_reg_in_use (i,
5559 rld[r].reg_rtx = last_reg;
5560 reload_inherited[r] = 1;
5561 reload_inheritance_insn[r]
5562 = reg_reloaded_insn[i];
5563 reload_spill_index[r] = i;
5564 for (k = 0; k < nr; k++)
5565 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5573 /* Here's another way to see if the value is already lying around. */
5576 && ! reload_inherited[r]
5578 && (CONSTANT_P (rld[r].in)
5579 || GET_CODE (rld[r].in) == PLUS
5580 || REG_P (rld[r].in)
5581 || MEM_P (rld[r].in))
5582 && (rld[r].nregs == max_group_size
5583 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5584 search_equiv = rld[r].in;
5585 /* If this is an output reload from a simple move insn, look
5586 if an equivalence for the input is available. */
5587 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5589 rtx set = single_set (insn);
5592 && rtx_equal_p (rld[r].out, SET_DEST (set))
5593 && CONSTANT_P (SET_SRC (set)))
5594 search_equiv = SET_SRC (set);
5600 = find_equiv_reg (search_equiv, insn, rld[r].class,
5601 -1, NULL, 0, rld[r].mode);
5607 regno = REGNO (equiv);
5610 /* This must be a SUBREG of a hard register.
5611 Make a new REG since this might be used in an
5612 address and not all machines support SUBREGs
5614 gcc_assert (GET_CODE (equiv) == SUBREG);
5615 regno = subreg_regno (equiv);
5616 equiv = gen_rtx_REG (rld[r].mode, regno);
5617 /* If we choose EQUIV as the reload register, but the
5618 loop below decides to cancel the inheritance, we'll
5619 end up reloading EQUIV in rld[r].mode, not the mode
5620 it had originally. That isn't safe when EQUIV isn't
5621 available as a spill register since its value might
5622 still be live at this point. */
5623 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5624 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5629 /* If we found a spill reg, reject it unless it is free
5630 and of the desired class. */
5634 int bad_for_class = 0;
5635 int max_regno = regno + rld[r].nregs;
5637 for (i = regno; i < max_regno; i++)
5639 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5641 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5646 && ! free_for_value_p (regno, rld[r].mode,
5647 rld[r].opnum, rld[r].when_needed,
5648 rld[r].in, rld[r].out, r, 1))
5653 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5656 /* We found a register that contains the value we need.
5657 If this register is the same as an `earlyclobber' operand
5658 of the current insn, just mark it as a place to reload from
5659 since we can't use it as the reload register itself. */
5662 for (i = 0; i < n_earlyclobbers; i++)
5663 if (reg_overlap_mentioned_for_reload_p (equiv,
5664 reload_earlyclobbers[i]))
5666 if (! rld[r].optional)
5667 reload_override_in[r] = equiv;
5672 /* If the equiv register we have found is explicitly clobbered
5673 in the current insn, it depends on the reload type if we
5674 can use it, use it for reload_override_in, or not at all.
5675 In particular, we then can't use EQUIV for a
5676 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5680 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5681 switch (rld[r].when_needed)
5683 case RELOAD_FOR_OTHER_ADDRESS:
5684 case RELOAD_FOR_INPADDR_ADDRESS:
5685 case RELOAD_FOR_INPUT_ADDRESS:
5686 case RELOAD_FOR_OPADDR_ADDR:
5689 case RELOAD_FOR_INPUT:
5690 case RELOAD_FOR_OPERAND_ADDRESS:
5691 if (! rld[r].optional)
5692 reload_override_in[r] = equiv;
5698 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5699 switch (rld[r].when_needed)
5701 case RELOAD_FOR_OTHER_ADDRESS:
5702 case RELOAD_FOR_INPADDR_ADDRESS:
5703 case RELOAD_FOR_INPUT_ADDRESS:
5704 case RELOAD_FOR_OPADDR_ADDR:
5705 case RELOAD_FOR_OPERAND_ADDRESS:
5706 case RELOAD_FOR_INPUT:
5709 if (! rld[r].optional)
5710 reload_override_in[r] = equiv;
5718 /* If we found an equivalent reg, say no code need be generated
5719 to load it, and use it as our reload reg. */
5721 && (regno != HARD_FRAME_POINTER_REGNUM
5722 || !frame_pointer_needed))
5724 int nr = hard_regno_nregs[regno][rld[r].mode];
5726 rld[r].reg_rtx = equiv;
5727 reload_inherited[r] = 1;
5729 /* If reg_reloaded_valid is not set for this register,
5730 there might be a stale spill_reg_store lying around.
5731 We must clear it, since otherwise emit_reload_insns
5732 might delete the store. */
5733 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5734 spill_reg_store[regno] = NULL_RTX;
5735 /* If any of the hard registers in EQUIV are spill
5736 registers, mark them as in use for this insn. */
5737 for (k = 0; k < nr; k++)
5739 i = spill_reg_order[regno + k];
5742 mark_reload_reg_in_use (regno, rld[r].opnum,
5745 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5752 /* If we found a register to use already, or if this is an optional
5753 reload, we are done. */
5754 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5758 /* No longer needed for correct operation. Might or might
5759 not give better code on the average. Want to experiment? */
5761 /* See if there is a later reload that has a class different from our
5762 class that intersects our class or that requires less register
5763 than our reload. If so, we must allocate a register to this
5764 reload now, since that reload might inherit a previous reload
5765 and take the only available register in our class. Don't do this
5766 for optional reloads since they will force all previous reloads
5767 to be allocated. Also don't do this for reloads that have been
5770 for (i = j + 1; i < n_reloads; i++)
5772 int s = reload_order[i];
5774 if ((rld[s].in == 0 && rld[s].out == 0
5775 && ! rld[s].secondary_p)
5779 if ((rld[s].class != rld[r].class
5780 && reg_classes_intersect_p (rld[r].class,
5782 || rld[s].nregs < rld[r].nregs)
5789 allocate_reload_reg (chain, r, j == n_reloads - 1);
5793 /* Now allocate reload registers for anything non-optional that
5794 didn't get one yet. */
5795 for (j = 0; j < n_reloads; j++)
5797 int r = reload_order[j];
5799 /* Ignore reloads that got marked inoperative. */
5800 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5803 /* Skip reloads that already have a register allocated or are
5805 if (rld[r].reg_rtx != 0 || rld[r].optional)
5808 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5812 /* If that loop got all the way, we have won. */
5819 /* Loop around and try without any inheritance. */
5824 /* First undo everything done by the failed attempt
5825 to allocate with inheritance. */
5826 choose_reload_regs_init (chain, save_reload_reg_rtx);
5828 /* Some sanity tests to verify that the reloads found in the first
5829 pass are identical to the ones we have now. */
5830 gcc_assert (chain->n_reloads == n_reloads);
5832 for (i = 0; i < n_reloads; i++)
5834 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5836 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5837 for (j = 0; j < n_spills; j++)
5838 if (spill_regs[j] == chain->rld[i].regno)
5839 if (! set_reload_reg (j, i))
5840 failed_reload (chain->insn, i);
5844 /* If we thought we could inherit a reload, because it seemed that
5845 nothing else wanted the same reload register earlier in the insn,
5846 verify that assumption, now that all reloads have been assigned.
5847 Likewise for reloads where reload_override_in has been set. */
5849 /* If doing expensive optimizations, do one preliminary pass that doesn't
5850 cancel any inheritance, but removes reloads that have been needed only
5851 for reloads that we know can be inherited. */
5852 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5854 for (j = 0; j < n_reloads; j++)
5856 int r = reload_order[j];
5858 if (reload_inherited[r] && rld[r].reg_rtx)
5859 check_reg = rld[r].reg_rtx;
5860 else if (reload_override_in[r]
5861 && (REG_P (reload_override_in[r])
5862 || GET_CODE (reload_override_in[r]) == SUBREG))
5863 check_reg = reload_override_in[r];
5866 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5867 rld[r].opnum, rld[r].when_needed, rld[r].in,
5868 (reload_inherited[r]
5869 ? rld[r].out : const0_rtx),
5874 reload_inherited[r] = 0;
5875 reload_override_in[r] = 0;
5877 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5878 reload_override_in, then we do not need its related
5879 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5880 likewise for other reload types.
5881 We handle this by removing a reload when its only replacement
5882 is mentioned in reload_in of the reload we are going to inherit.
5883 A special case are auto_inc expressions; even if the input is
5884 inherited, we still need the address for the output. We can
5885 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5886 If we succeeded removing some reload and we are doing a preliminary
5887 pass just to remove such reloads, make another pass, since the
5888 removal of one reload might allow us to inherit another one. */
5890 && rld[r].out != rld[r].in
5891 && remove_address_replacements (rld[r].in) && pass)
5896 /* Now that reload_override_in is known valid,
5897 actually override reload_in. */
5898 for (j = 0; j < n_reloads; j++)
5899 if (reload_override_in[j])
5900 rld[j].in = reload_override_in[j];
5902 /* If this reload won't be done because it has been canceled or is
5903 optional and not inherited, clear reload_reg_rtx so other
5904 routines (such as subst_reloads) don't get confused. */
5905 for (j = 0; j < n_reloads; j++)
5906 if (rld[j].reg_rtx != 0
5907 && ((rld[j].optional && ! reload_inherited[j])
5908 || (rld[j].in == 0 && rld[j].out == 0
5909 && ! rld[j].secondary_p)))
5911 int regno = true_regnum (rld[j].reg_rtx);
5913 if (spill_reg_order[regno] >= 0)
5914 clear_reload_reg_in_use (regno, rld[j].opnum,
5915 rld[j].when_needed, rld[j].mode);
5917 reload_spill_index[j] = -1;
5920 /* Record which pseudos and which spill regs have output reloads. */
5921 for (j = 0; j < n_reloads; j++)
5923 int r = reload_order[j];
5925 i = reload_spill_index[r];
5927 /* I is nonneg if this reload uses a register.
5928 If rld[r].reg_rtx is 0, this is an optional reload
5929 that we opted to ignore. */
5930 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5931 && rld[r].reg_rtx != 0)
5933 int nregno = REGNO (rld[r].out_reg);
5936 if (nregno < FIRST_PSEUDO_REGISTER)
5937 nr = hard_regno_nregs[nregno][rld[r].mode];
5940 reg_has_output_reload[nregno + nr] = 1;
5944 nr = hard_regno_nregs[i][rld[r].mode];
5946 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5949 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5950 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5951 || rld[r].when_needed == RELOAD_FOR_INSN);
5956 /* Deallocate the reload register for reload R. This is called from
5957 remove_address_replacements. */
5960 deallocate_reload_reg (int r)
5964 if (! rld[r].reg_rtx)
5966 regno = true_regnum (rld[r].reg_rtx);
5968 if (spill_reg_order[regno] >= 0)
5969 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5971 reload_spill_index[r] = -1;
5974 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5975 reloads of the same item for fear that we might not have enough reload
5976 registers. However, normally they will get the same reload register
5977 and hence actually need not be loaded twice.
5979 Here we check for the most common case of this phenomenon: when we have
5980 a number of reloads for the same object, each of which were allocated
5981 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5982 reload, and is not modified in the insn itself. If we find such,
5983 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5984 This will not increase the number of spill registers needed and will
5985 prevent redundant code. */
5988 merge_assigned_reloads (rtx insn)
5992 /* Scan all the reloads looking for ones that only load values and
5993 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5994 assigned and not modified by INSN. */
5996 for (i = 0; i < n_reloads; i++)
5998 int conflicting_input = 0;
5999 int max_input_address_opnum = -1;
6000 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6002 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6003 || rld[i].out != 0 || rld[i].reg_rtx == 0
6004 || reg_set_p (rld[i].reg_rtx, insn))
6007 /* Look at all other reloads. Ensure that the only use of this
6008 reload_reg_rtx is in a reload that just loads the same value
6009 as we do. Note that any secondary reloads must be of the identical
6010 class since the values, modes, and result registers are the
6011 same, so we need not do anything with any secondary reloads. */
6013 for (j = 0; j < n_reloads; j++)
6015 if (i == j || rld[j].reg_rtx == 0
6016 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6020 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6021 && rld[j].opnum > max_input_address_opnum)
6022 max_input_address_opnum = rld[j].opnum;
6024 /* If the reload regs aren't exactly the same (e.g, different modes)
6025 or if the values are different, we can't merge this reload.
6026 But if it is an input reload, we might still merge
6027 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6029 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6030 || rld[j].out != 0 || rld[j].in == 0
6031 || ! rtx_equal_p (rld[i].in, rld[j].in))
6033 if (rld[j].when_needed != RELOAD_FOR_INPUT
6034 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6035 || rld[i].opnum > rld[j].opnum)
6036 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6038 conflicting_input = 1;
6039 if (min_conflicting_input_opnum > rld[j].opnum)
6040 min_conflicting_input_opnum = rld[j].opnum;
6044 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6045 we, in fact, found any matching reloads. */
6048 && max_input_address_opnum <= min_conflicting_input_opnum)
6050 for (j = 0; j < n_reloads; j++)
6051 if (i != j && rld[j].reg_rtx != 0
6052 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6053 && (! conflicting_input
6054 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6055 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6057 rld[i].when_needed = RELOAD_OTHER;
6059 reload_spill_index[j] = -1;
6060 transfer_replacements (i, j);
6063 /* If this is now RELOAD_OTHER, look for any reloads that load
6064 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6065 if they were for inputs, RELOAD_OTHER for outputs. Note that
6066 this test is equivalent to looking for reloads for this operand
6068 /* We must take special care when there are two or more reloads to
6069 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6070 same value or a part of it; we must not change its type if there
6071 is a conflicting input. */
6073 if (rld[i].when_needed == RELOAD_OTHER)
6074 for (j = 0; j < n_reloads; j++)
6076 && rld[j].when_needed != RELOAD_OTHER
6077 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6078 && (! conflicting_input
6079 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6080 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6081 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6087 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6088 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6089 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6091 /* Check to see if we accidentally converted two
6092 reloads that use the same reload register with
6093 different inputs to the same type. If so, the
6094 resulting code won't work. */
6096 for (k = 0; k < j; k++)
6097 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6098 || rld[k].when_needed != rld[j].when_needed
6099 || !rtx_equal_p (rld[k].reg_rtx,
6101 || rtx_equal_p (rld[k].in,
6108 /* These arrays are filled by emit_reload_insns and its subroutines. */
6109 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6110 static rtx other_input_address_reload_insns = 0;
6111 static rtx other_input_reload_insns = 0;
6112 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6113 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6114 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6115 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6116 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6117 static rtx operand_reload_insns = 0;
6118 static rtx other_operand_reload_insns = 0;
6119 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6121 /* Values to be put in spill_reg_store are put here first. */
6122 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6123 static HARD_REG_SET reg_reloaded_died;
6125 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6126 has the number J. OLD contains the value to be used as input. */
6129 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6132 rtx insn = chain->insn;
6133 rtx reloadreg = rl->reg_rtx;
6134 rtx oldequiv_reg = 0;
6137 enum machine_mode mode;
6140 /* Determine the mode to reload in.
6141 This is very tricky because we have three to choose from.
6142 There is the mode the insn operand wants (rl->inmode).
6143 There is the mode of the reload register RELOADREG.
6144 There is the intrinsic mode of the operand, which we could find
6145 by stripping some SUBREGs.
6146 It turns out that RELOADREG's mode is irrelevant:
6147 we can change that arbitrarily.
6149 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6150 then the reload reg may not support QImode moves, so use SImode.
6151 If foo is in memory due to spilling a pseudo reg, this is safe,
6152 because the QImode value is in the least significant part of a
6153 slot big enough for a SImode. If foo is some other sort of
6154 memory reference, then it is impossible to reload this case,
6155 so previous passes had better make sure this never happens.
6157 Then consider a one-word union which has SImode and one of its
6158 members is a float, being fetched as (SUBREG:SF union:SI).
6159 We must fetch that as SFmode because we could be loading into
6160 a float-only register. In this case OLD's mode is correct.
6162 Consider an immediate integer: it has VOIDmode. Here we need
6163 to get a mode from something else.
6165 In some cases, there is a fourth mode, the operand's
6166 containing mode. If the insn specifies a containing mode for
6167 this operand, it overrides all others.
6169 I am not sure whether the algorithm here is always right,
6170 but it does the right things in those cases. */
6172 mode = GET_MODE (old);
6173 if (mode == VOIDmode)
6176 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6177 /* If we need a secondary register for this operation, see if
6178 the value is already in a register in that class. Don't
6179 do this if the secondary register will be used as a scratch
6182 if (rl->secondary_in_reload >= 0
6183 && rl->secondary_in_icode == CODE_FOR_nothing
6186 = find_equiv_reg (old, insn,
6187 rld[rl->secondary_in_reload].class,
6191 /* If reloading from memory, see if there is a register
6192 that already holds the same value. If so, reload from there.
6193 We can pass 0 as the reload_reg_p argument because
6194 any other reload has either already been emitted,
6195 in which case find_equiv_reg will see the reload-insn,
6196 or has yet to be emitted, in which case it doesn't matter
6197 because we will use this equiv reg right away. */
6199 if (oldequiv == 0 && optimize
6202 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6203 && reg_renumber[REGNO (old)] < 0)))
6204 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6208 unsigned int regno = true_regnum (oldequiv);
6210 /* Don't use OLDEQUIV if any other reload changes it at an
6211 earlier stage of this insn or at this stage. */
6212 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6213 rl->in, const0_rtx, j, 0))
6216 /* If it is no cheaper to copy from OLDEQUIV into the
6217 reload register than it would be to move from memory,
6218 don't use it. Likewise, if we need a secondary register
6222 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6223 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6225 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6226 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6227 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6231 #ifdef SECONDARY_MEMORY_NEEDED
6232 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6240 /* delete_output_reload is only invoked properly if old contains
6241 the original pseudo register. Since this is replaced with a
6242 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6243 find the pseudo in RELOAD_IN_REG. */
6245 && reload_override_in[j]
6246 && REG_P (rl->in_reg))
6253 else if (REG_P (oldequiv))
6254 oldequiv_reg = oldequiv;
6255 else if (GET_CODE (oldequiv) == SUBREG)
6256 oldequiv_reg = SUBREG_REG (oldequiv);
6258 /* If we are reloading from a register that was recently stored in
6259 with an output-reload, see if we can prove there was
6260 actually no need to store the old value in it. */
6262 if (optimize && REG_P (oldequiv)
6263 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6264 && spill_reg_store[REGNO (oldequiv)]
6266 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6267 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6269 delete_output_reload (insn, j, REGNO (oldequiv));
6271 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6272 then load RELOADREG from OLDEQUIV. Note that we cannot use
6273 gen_lowpart_common since it can do the wrong thing when
6274 RELOADREG has a multi-word mode. Note that RELOADREG
6275 must always be a REG here. */
6277 if (GET_MODE (reloadreg) != mode)
6278 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6279 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6280 oldequiv = SUBREG_REG (oldequiv);
6281 if (GET_MODE (oldequiv) != VOIDmode
6282 && mode != GET_MODE (oldequiv))
6283 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6285 /* Switch to the right place to emit the reload insns. */
6286 switch (rl->when_needed)
6289 where = &other_input_reload_insns;
6291 case RELOAD_FOR_INPUT:
6292 where = &input_reload_insns[rl->opnum];
6294 case RELOAD_FOR_INPUT_ADDRESS:
6295 where = &input_address_reload_insns[rl->opnum];
6297 case RELOAD_FOR_INPADDR_ADDRESS:
6298 where = &inpaddr_address_reload_insns[rl->opnum];
6300 case RELOAD_FOR_OUTPUT_ADDRESS:
6301 where = &output_address_reload_insns[rl->opnum];
6303 case RELOAD_FOR_OUTADDR_ADDRESS:
6304 where = &outaddr_address_reload_insns[rl->opnum];
6306 case RELOAD_FOR_OPERAND_ADDRESS:
6307 where = &operand_reload_insns;
6309 case RELOAD_FOR_OPADDR_ADDR:
6310 where = &other_operand_reload_insns;
6312 case RELOAD_FOR_OTHER_ADDRESS:
6313 where = &other_input_address_reload_insns;
6319 push_to_sequence (*where);
6321 /* Auto-increment addresses must be reloaded in a special way. */
6322 if (rl->out && ! rl->out_reg)
6324 /* We are not going to bother supporting the case where a
6325 incremented register can't be copied directly from
6326 OLDEQUIV since this seems highly unlikely. */
6327 gcc_assert (rl->secondary_in_reload < 0);
6329 if (reload_inherited[j])
6330 oldequiv = reloadreg;
6332 old = XEXP (rl->in_reg, 0);
6334 if (optimize && REG_P (oldequiv)
6335 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6336 && spill_reg_store[REGNO (oldequiv)]
6338 && (dead_or_set_p (insn,
6339 spill_reg_stored_to[REGNO (oldequiv)])
6340 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6342 delete_output_reload (insn, j, REGNO (oldequiv));
6344 /* Prevent normal processing of this reload. */
6346 /* Output a special code sequence for this case. */
6347 new_spill_reg_store[REGNO (reloadreg)]
6348 = inc_for_reload (reloadreg, oldequiv, rl->out,
6352 /* If we are reloading a pseudo-register that was set by the previous
6353 insn, see if we can get rid of that pseudo-register entirely
6354 by redirecting the previous insn into our reload register. */
6356 else if (optimize && REG_P (old)
6357 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6358 && dead_or_set_p (insn, old)
6359 /* This is unsafe if some other reload
6360 uses the same reg first. */
6361 && ! conflicts_with_override (reloadreg)
6362 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6363 rl->when_needed, old, rl->out, j, 0))
6365 rtx temp = PREV_INSN (insn);
6366 while (temp && NOTE_P (temp))
6367 temp = PREV_INSN (temp);
6369 && NONJUMP_INSN_P (temp)
6370 && GET_CODE (PATTERN (temp)) == SET
6371 && SET_DEST (PATTERN (temp)) == old
6372 /* Make sure we can access insn_operand_constraint. */
6373 && asm_noperands (PATTERN (temp)) < 0
6374 /* This is unsafe if operand occurs more than once in current
6375 insn. Perhaps some occurrences aren't reloaded. */
6376 && count_occurrences (PATTERN (insn), old, 0) == 1)
6378 rtx old = SET_DEST (PATTERN (temp));
6379 /* Store into the reload register instead of the pseudo. */
6380 SET_DEST (PATTERN (temp)) = reloadreg;
6382 /* Verify that resulting insn is valid. */
6383 extract_insn (temp);
6384 if (constrain_operands (1))
6386 /* If the previous insn is an output reload, the source is
6387 a reload register, and its spill_reg_store entry will
6388 contain the previous destination. This is now
6390 if (REG_P (SET_SRC (PATTERN (temp)))
6391 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6393 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6394 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6397 /* If these are the only uses of the pseudo reg,
6398 pretend for GDB it lives in the reload reg we used. */
6399 if (REG_N_DEATHS (REGNO (old)) == 1
6400 && REG_N_SETS (REGNO (old)) == 1)
6402 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6403 alter_reg (REGNO (old), -1);
6409 SET_DEST (PATTERN (temp)) = old;
6414 /* We can't do that, so output an insn to load RELOADREG. */
6416 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6417 /* If we have a secondary reload, pick up the secondary register
6418 and icode, if any. If OLDEQUIV and OLD are different or
6419 if this is an in-out reload, recompute whether or not we
6420 still need a secondary register and what the icode should
6421 be. If we still need a secondary register and the class or
6422 icode is different, go back to reloading from OLD if using
6423 OLDEQUIV means that we got the wrong type of register. We
6424 cannot have different class or icode due to an in-out reload
6425 because we don't make such reloads when both the input and
6426 output need secondary reload registers. */
6428 if (! special && rl->secondary_in_reload >= 0)
6430 rtx second_reload_reg = 0;
6431 int secondary_reload = rl->secondary_in_reload;
6432 rtx real_oldequiv = oldequiv;
6435 enum insn_code icode;
6437 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6438 and similarly for OLD.
6439 See comments in get_secondary_reload in reload.c. */
6440 /* If it is a pseudo that cannot be replaced with its
6441 equivalent MEM, we must fall back to reload_in, which
6442 will have all the necessary substitutions registered.
6443 Likewise for a pseudo that can't be replaced with its
6444 equivalent constant.
6446 Take extra care for subregs of such pseudos. Note that
6447 we cannot use reg_equiv_mem in this case because it is
6448 not in the right mode. */
6451 if (GET_CODE (tmp) == SUBREG)
6452 tmp = SUBREG_REG (tmp);
6454 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6455 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6456 || reg_equiv_constant[REGNO (tmp)] != 0))
6458 if (! reg_equiv_mem[REGNO (tmp)]
6459 || num_not_at_initial_offset
6460 || GET_CODE (oldequiv) == SUBREG)
6461 real_oldequiv = rl->in;
6463 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6467 if (GET_CODE (tmp) == SUBREG)
6468 tmp = SUBREG_REG (tmp);
6470 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6471 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6472 || reg_equiv_constant[REGNO (tmp)] != 0))
6474 if (! reg_equiv_mem[REGNO (tmp)]
6475 || num_not_at_initial_offset
6476 || GET_CODE (old) == SUBREG)
6479 real_old = reg_equiv_mem[REGNO (tmp)];
6482 second_reload_reg = rld[secondary_reload].reg_rtx;
6483 icode = rl->secondary_in_icode;
6485 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6486 || (rl->in != 0 && rl->out != 0))
6488 enum reg_class new_class
6489 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6490 mode, real_oldequiv);
6492 if (new_class == NO_REGS)
6493 second_reload_reg = 0;
6496 enum insn_code new_icode;
6497 enum machine_mode new_mode;
6499 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6500 REGNO (second_reload_reg)))
6501 oldequiv = old, real_oldequiv = real_old;
6504 new_icode = reload_in_optab[(int) mode];
6505 if (new_icode != CODE_FOR_nothing
6506 && ((insn_data[(int) new_icode].operand[0].predicate
6507 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6509 || (insn_data[(int) new_icode].operand[1].predicate
6510 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6511 (real_oldequiv, mode)))))
6512 new_icode = CODE_FOR_nothing;
6514 if (new_icode == CODE_FOR_nothing)
6517 new_mode = insn_data[(int) new_icode].operand[2].mode;
6519 if (GET_MODE (second_reload_reg) != new_mode)
6521 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6523 oldequiv = old, real_oldequiv = real_old;
6526 = reload_adjust_reg_for_mode (second_reload_reg,
6533 /* If we still need a secondary reload register, check
6534 to see if it is being used as a scratch or intermediate
6535 register and generate code appropriately. If we need
6536 a scratch register, use REAL_OLDEQUIV since the form of
6537 the insn may depend on the actual address if it is
6540 if (second_reload_reg)
6542 if (icode != CODE_FOR_nothing)
6544 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6545 second_reload_reg));
6550 /* See if we need a scratch register to load the
6551 intermediate register (a tertiary reload). */
6552 enum insn_code tertiary_icode
6553 = rld[secondary_reload].secondary_in_icode;
6555 if (tertiary_icode != CODE_FOR_nothing)
6557 rtx third_reload_reg
6558 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6560 emit_insn ((GEN_FCN (tertiary_icode)
6561 (second_reload_reg, real_oldequiv,
6562 third_reload_reg)));
6565 gen_reload (second_reload_reg, real_oldequiv,
6569 oldequiv = second_reload_reg;
6575 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6577 rtx real_oldequiv = oldequiv;
6579 if ((REG_P (oldequiv)
6580 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6581 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6582 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6583 || (GET_CODE (oldequiv) == SUBREG
6584 && REG_P (SUBREG_REG (oldequiv))
6585 && (REGNO (SUBREG_REG (oldequiv))
6586 >= FIRST_PSEUDO_REGISTER)
6587 && ((reg_equiv_memory_loc
6588 [REGNO (SUBREG_REG (oldequiv))] != 0)
6589 || (reg_equiv_constant
6590 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6591 || (CONSTANT_P (oldequiv)
6592 && (PREFERRED_RELOAD_CLASS (oldequiv,
6593 REGNO_REG_CLASS (REGNO (reloadreg)))
6595 real_oldequiv = rl->in;
6596 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6600 if (flag_non_call_exceptions)
6601 copy_eh_notes (insn, get_insns ());
6603 /* End this sequence. */
6604 *where = get_insns ();
6607 /* Update reload_override_in so that delete_address_reloads_1
6608 can see the actual register usage. */
6610 reload_override_in[j] = oldequiv;
6613 /* Generate insns to for the output reload RL, which is for the insn described
6614 by CHAIN and has the number J. */
6616 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6619 rtx reloadreg = rl->reg_rtx;
6620 rtx insn = chain->insn;
6623 enum machine_mode mode = GET_MODE (old);
6626 if (rl->when_needed == RELOAD_OTHER)
6629 push_to_sequence (output_reload_insns[rl->opnum]);
6631 /* Determine the mode to reload in.
6632 See comments above (for input reloading). */
6634 if (mode == VOIDmode)
6636 /* VOIDmode should never happen for an output. */
6637 if (asm_noperands (PATTERN (insn)) < 0)
6638 /* It's the compiler's fault. */
6639 fatal_insn ("VOIDmode on an output", insn);
6640 error_for_asm (insn, "output operand is constant in %<asm%>");
6641 /* Prevent crash--use something we know is valid. */
6643 old = gen_rtx_REG (mode, REGNO (reloadreg));
6646 if (GET_MODE (reloadreg) != mode)
6647 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6649 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6651 /* If we need two reload regs, set RELOADREG to the intermediate
6652 one, since it will be stored into OLD. We might need a secondary
6653 register only for an input reload, so check again here. */
6655 if (rl->secondary_out_reload >= 0)
6659 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6660 && reg_equiv_mem[REGNO (old)] != 0)
6661 real_old = reg_equiv_mem[REGNO (old)];
6663 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6667 rtx second_reloadreg = reloadreg;
6668 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6670 /* See if RELOADREG is to be used as a scratch register
6671 or as an intermediate register. */
6672 if (rl->secondary_out_icode != CODE_FOR_nothing)
6674 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6675 (real_old, second_reloadreg, reloadreg)));
6680 /* See if we need both a scratch and intermediate reload
6683 int secondary_reload = rl->secondary_out_reload;
6684 enum insn_code tertiary_icode
6685 = rld[secondary_reload].secondary_out_icode;
6687 if (GET_MODE (reloadreg) != mode)
6688 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6690 if (tertiary_icode != CODE_FOR_nothing)
6693 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6696 /* Copy primary reload reg to secondary reload reg.
6697 (Note that these have been swapped above, then
6698 secondary reload reg to OLD using our insn.) */
6700 /* If REAL_OLD is a paradoxical SUBREG, remove it
6701 and try to put the opposite SUBREG on
6703 if (GET_CODE (real_old) == SUBREG
6704 && (GET_MODE_SIZE (GET_MODE (real_old))
6705 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6706 && 0 != (tem = gen_lowpart_common
6707 (GET_MODE (SUBREG_REG (real_old)),
6709 real_old = SUBREG_REG (real_old), reloadreg = tem;
6711 gen_reload (reloadreg, second_reloadreg,
6712 rl->opnum, rl->when_needed);
6713 emit_insn ((GEN_FCN (tertiary_icode)
6714 (real_old, reloadreg, third_reloadreg)));
6719 /* Copy between the reload regs here and then to
6722 gen_reload (reloadreg, second_reloadreg,
6723 rl->opnum, rl->when_needed);
6729 /* Output the last reload insn. */
6734 /* Don't output the last reload if OLD is not the dest of
6735 INSN and is in the src and is clobbered by INSN. */
6736 if (! flag_expensive_optimizations
6738 || !(set = single_set (insn))
6739 || rtx_equal_p (old, SET_DEST (set))
6740 || !reg_mentioned_p (old, SET_SRC (set))
6741 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6742 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6743 gen_reload (old, reloadreg, rl->opnum,
6747 /* Look at all insns we emitted, just to be safe. */
6748 for (p = get_insns (); p; p = NEXT_INSN (p))
6751 rtx pat = PATTERN (p);
6753 /* If this output reload doesn't come from a spill reg,
6754 clear any memory of reloaded copies of the pseudo reg.
6755 If this output reload comes from a spill reg,
6756 reg_has_output_reload will make this do nothing. */
6757 note_stores (pat, forget_old_reloads_1, NULL);
6759 if (reg_mentioned_p (rl->reg_rtx, pat))
6761 rtx set = single_set (insn);
6762 if (reload_spill_index[j] < 0
6764 && SET_SRC (set) == rl->reg_rtx)
6766 int src = REGNO (SET_SRC (set));
6768 reload_spill_index[j] = src;
6769 SET_HARD_REG_BIT (reg_is_output_reload, src);
6770 if (find_regno_note (insn, REG_DEAD, src))
6771 SET_HARD_REG_BIT (reg_reloaded_died, src);
6773 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6775 int s = rl->secondary_out_reload;
6776 set = single_set (p);
6777 /* If this reload copies only to the secondary reload
6778 register, the secondary reload does the actual
6780 if (s >= 0 && set == NULL_RTX)
6781 /* We can't tell what function the secondary reload
6782 has and where the actual store to the pseudo is
6783 made; leave new_spill_reg_store alone. */
6786 && SET_SRC (set) == rl->reg_rtx
6787 && SET_DEST (set) == rld[s].reg_rtx)
6789 /* Usually the next instruction will be the
6790 secondary reload insn; if we can confirm
6791 that it is, setting new_spill_reg_store to
6792 that insn will allow an extra optimization. */
6793 rtx s_reg = rld[s].reg_rtx;
6794 rtx next = NEXT_INSN (p);
6795 rld[s].out = rl->out;
6796 rld[s].out_reg = rl->out_reg;
6797 set = single_set (next);
6798 if (set && SET_SRC (set) == s_reg
6799 && ! new_spill_reg_store[REGNO (s_reg)])
6801 SET_HARD_REG_BIT (reg_is_output_reload,
6803 new_spill_reg_store[REGNO (s_reg)] = next;
6807 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6812 if (rl->when_needed == RELOAD_OTHER)
6814 emit_insn (other_output_reload_insns[rl->opnum]);
6815 other_output_reload_insns[rl->opnum] = get_insns ();
6818 output_reload_insns[rl->opnum] = get_insns ();
6820 if (flag_non_call_exceptions)
6821 copy_eh_notes (insn, get_insns ());
6826 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6827 and has the number J. */
6829 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6831 rtx insn = chain->insn;
6832 rtx old = (rl->in && MEM_P (rl->in)
6833 ? rl->in_reg : rl->in);
6836 /* AUTO_INC reloads need to be handled even if inherited. We got an
6837 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6838 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6839 && ! rtx_equal_p (rl->reg_rtx, old)
6840 && rl->reg_rtx != 0)
6841 emit_input_reload_insns (chain, rld + j, old, j);
6843 /* When inheriting a wider reload, we have a MEM in rl->in,
6844 e.g. inheriting a SImode output reload for
6845 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6846 if (optimize && reload_inherited[j] && rl->in
6848 && MEM_P (rl->in_reg)
6849 && reload_spill_index[j] >= 0
6850 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6851 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6853 /* If we are reloading a register that was recently stored in with an
6854 output-reload, see if we can prove there was
6855 actually no need to store the old value in it. */
6858 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6859 that there may be multiple uses of the previous output reload.
6860 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6861 && rl->when_needed == RELOAD_FOR_INPUT
6862 && (reload_inherited[j] || reload_override_in[j])
6864 && REG_P (rl->reg_rtx)
6865 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6867 /* There doesn't seem to be any reason to restrict this to pseudos
6868 and doing so loses in the case where we are copying from a
6869 register of the wrong class. */
6870 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6871 >= FIRST_PSEUDO_REGISTER)
6873 /* The insn might have already some references to stackslots
6874 replaced by MEMs, while reload_out_reg still names the
6876 && (dead_or_set_p (insn,
6877 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6878 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6880 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6883 /* Do output reloading for reload RL, which is for the insn described by
6884 CHAIN and has the number J.
6885 ??? At some point we need to support handling output reloads of
6886 JUMP_INSNs or insns that set cc0. */
6888 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6891 rtx insn = chain->insn;
6892 /* If this is an output reload that stores something that is
6893 not loaded in this same reload, see if we can eliminate a previous
6895 rtx pseudo = rl->out_reg;
6900 && ! rtx_equal_p (rl->in_reg, pseudo)
6901 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6902 && reg_last_reload_reg[REGNO (pseudo)])
6904 int pseudo_no = REGNO (pseudo);
6905 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6907 /* We don't need to test full validity of last_regno for
6908 inherit here; we only want to know if the store actually
6909 matches the pseudo. */
6910 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6911 && reg_reloaded_contents[last_regno] == pseudo_no
6912 && spill_reg_store[last_regno]
6913 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6914 delete_output_reload (insn, j, last_regno);
6919 || rl->reg_rtx == old
6920 || rl->reg_rtx == 0)
6923 /* An output operand that dies right away does need a reload,
6924 but need not be copied from it. Show the new location in the
6926 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6927 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6929 XEXP (note, 0) = rl->reg_rtx;
6932 /* Likewise for a SUBREG of an operand that dies. */
6933 else if (GET_CODE (old) == SUBREG
6934 && REG_P (SUBREG_REG (old))
6935 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6938 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6942 else if (GET_CODE (old) == SCRATCH)
6943 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6944 but we don't want to make an output reload. */
6947 /* If is a JUMP_INSN, we can't support output reloads yet. */
6948 gcc_assert (!JUMP_P (insn));
6950 emit_output_reload_insns (chain, rld + j, j);
6953 /* Reload number R reloads from or to a group of hard registers starting at
6954 register REGNO. Return true if it can be treated for inheritance purposes
6955 like a group of reloads, each one reloading a single hard register.
6956 The caller has already checked that the spill register and REGNO use
6957 the same number of registers to store the reload value. */
6960 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6962 #ifdef CANNOT_CHANGE_MODE_CLASS
6963 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6964 GET_MODE (rld[r].reg_rtx),
6965 reg_raw_mode[reload_spill_index[r]])
6966 && !REG_CANNOT_CHANGE_MODE_P (regno,
6967 GET_MODE (rld[r].reg_rtx),
6968 reg_raw_mode[regno]));
6974 /* Output insns to reload values in and out of the chosen reload regs. */
6977 emit_reload_insns (struct insn_chain *chain)
6979 rtx insn = chain->insn;
6983 CLEAR_HARD_REG_SET (reg_reloaded_died);
6985 for (j = 0; j < reload_n_operands; j++)
6986 input_reload_insns[j] = input_address_reload_insns[j]
6987 = inpaddr_address_reload_insns[j]
6988 = output_reload_insns[j] = output_address_reload_insns[j]
6989 = outaddr_address_reload_insns[j]
6990 = other_output_reload_insns[j] = 0;
6991 other_input_address_reload_insns = 0;
6992 other_input_reload_insns = 0;
6993 operand_reload_insns = 0;
6994 other_operand_reload_insns = 0;
6996 /* Dump reloads into the dump file. */
6999 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7000 debug_reload_to_stream (dump_file);
7003 /* Now output the instructions to copy the data into and out of the
7004 reload registers. Do these in the order that the reloads were reported,
7005 since reloads of base and index registers precede reloads of operands
7006 and the operands may need the base and index registers reloaded. */
7008 for (j = 0; j < n_reloads; j++)
7011 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7012 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7014 do_input_reload (chain, rld + j, j);
7015 do_output_reload (chain, rld + j, j);
7018 /* Now write all the insns we made for reloads in the order expected by
7019 the allocation functions. Prior to the insn being reloaded, we write
7020 the following reloads:
7022 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7024 RELOAD_OTHER reloads.
7026 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7027 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7028 RELOAD_FOR_INPUT reload for the operand.
7030 RELOAD_FOR_OPADDR_ADDRS reloads.
7032 RELOAD_FOR_OPERAND_ADDRESS reloads.
7034 After the insn being reloaded, we write the following:
7036 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7037 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7038 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7039 reloads for the operand. The RELOAD_OTHER output reloads are
7040 output in descending order by reload number. */
7042 emit_insn_before (other_input_address_reload_insns, insn);
7043 emit_insn_before (other_input_reload_insns, insn);
7045 for (j = 0; j < reload_n_operands; j++)
7047 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7048 emit_insn_before (input_address_reload_insns[j], insn);
7049 emit_insn_before (input_reload_insns[j], insn);
7052 emit_insn_before (other_operand_reload_insns, insn);
7053 emit_insn_before (operand_reload_insns, insn);
7055 for (j = 0; j < reload_n_operands; j++)
7057 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7058 x = emit_insn_after (output_address_reload_insns[j], x);
7059 x = emit_insn_after (output_reload_insns[j], x);
7060 emit_insn_after (other_output_reload_insns[j], x);
7063 /* For all the spill regs newly reloaded in this instruction,
7064 record what they were reloaded from, so subsequent instructions
7065 can inherit the reloads.
7067 Update spill_reg_store for the reloads of this insn.
7068 Copy the elements that were updated in the loop above. */
7070 for (j = 0; j < n_reloads; j++)
7072 int r = reload_order[j];
7073 int i = reload_spill_index[r];
7075 /* If this is a non-inherited input reload from a pseudo, we must
7076 clear any memory of a previous store to the same pseudo. Only do
7077 something if there will not be an output reload for the pseudo
7079 if (rld[r].in_reg != 0
7080 && ! (reload_inherited[r] || reload_override_in[r]))
7082 rtx reg = rld[r].in_reg;
7084 if (GET_CODE (reg) == SUBREG)
7085 reg = SUBREG_REG (reg);
7088 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7089 && ! reg_has_output_reload[REGNO (reg)])
7091 int nregno = REGNO (reg);
7093 if (reg_last_reload_reg[nregno])
7095 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7097 if (reg_reloaded_contents[last_regno] == nregno)
7098 spill_reg_store[last_regno] = 0;
7103 /* I is nonneg if this reload used a register.
7104 If rld[r].reg_rtx is 0, this is an optional reload
7105 that we opted to ignore. */
7107 if (i >= 0 && rld[r].reg_rtx != 0)
7109 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7111 int part_reaches_end = 0;
7112 int all_reaches_end = 1;
7114 /* For a multi register reload, we need to check if all or part
7115 of the value lives to the end. */
7116 for (k = 0; k < nr; k++)
7118 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7119 rld[r].when_needed))
7120 part_reaches_end = 1;
7122 all_reaches_end = 0;
7125 /* Ignore reloads that don't reach the end of the insn in
7127 if (all_reaches_end)
7129 /* First, clear out memory of what used to be in this spill reg.
7130 If consecutive registers are used, clear them all. */
7132 for (k = 0; k < nr; k++)
7134 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7135 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7138 /* Maybe the spill reg contains a copy of reload_out. */
7140 && (REG_P (rld[r].out)
7144 || REG_P (rld[r].out_reg)))
7146 rtx out = (REG_P (rld[r].out)
7150 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7151 int nregno = REGNO (out);
7152 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7153 : hard_regno_nregs[nregno]
7154 [GET_MODE (rld[r].reg_rtx)]);
7157 spill_reg_store[i] = new_spill_reg_store[i];
7158 spill_reg_stored_to[i] = out;
7159 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7161 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7163 && inherit_piecemeal_p (r, nregno));
7165 /* If NREGNO is a hard register, it may occupy more than
7166 one register. If it does, say what is in the
7167 rest of the registers assuming that both registers
7168 agree on how many words the object takes. If not,
7169 invalidate the subsequent registers. */
7171 if (nregno < FIRST_PSEUDO_REGISTER)
7172 for (k = 1; k < nnr; k++)
7173 reg_last_reload_reg[nregno + k]
7175 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7178 /* Now do the inverse operation. */
7179 for (k = 0; k < nr; k++)
7181 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7182 reg_reloaded_contents[i + k]
7183 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7186 reg_reloaded_insn[i + k] = insn;
7187 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7188 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7189 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7193 /* Maybe the spill reg contains a copy of reload_in. Only do
7194 something if there will not be an output reload for
7195 the register being reloaded. */
7196 else if (rld[r].out_reg == 0
7198 && ((REG_P (rld[r].in)
7199 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7200 && ! reg_has_output_reload[REGNO (rld[r].in)])
7201 || (REG_P (rld[r].in_reg)
7202 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7203 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7210 if (REG_P (rld[r].in)
7211 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7213 else if (REG_P (rld[r].in_reg))
7216 in = XEXP (rld[r].in_reg, 0);
7217 nregno = REGNO (in);
7219 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7220 : hard_regno_nregs[nregno]
7221 [GET_MODE (rld[r].reg_rtx)]);
7223 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7225 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7227 && inherit_piecemeal_p (r, nregno));
7229 if (nregno < FIRST_PSEUDO_REGISTER)
7230 for (k = 1; k < nnr; k++)
7231 reg_last_reload_reg[nregno + k]
7233 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7236 /* Unless we inherited this reload, show we haven't
7237 recently done a store.
7238 Previous stores of inherited auto_inc expressions
7239 also have to be discarded. */
7240 if (! reload_inherited[r]
7241 || (rld[r].out && ! rld[r].out_reg))
7242 spill_reg_store[i] = 0;
7244 for (k = 0; k < nr; k++)
7246 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7247 reg_reloaded_contents[i + k]
7248 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7251 reg_reloaded_insn[i + k] = insn;
7252 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7253 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7254 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7259 /* However, if part of the reload reaches the end, then we must
7260 invalidate the old info for the part that survives to the end. */
7261 else if (part_reaches_end)
7263 for (k = 0; k < nr; k++)
7264 if (reload_reg_reaches_end_p (i + k,
7266 rld[r].when_needed))
7267 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7271 /* The following if-statement was #if 0'd in 1.34 (or before...).
7272 It's reenabled in 1.35 because supposedly nothing else
7273 deals with this problem. */
7275 /* If a register gets output-reloaded from a non-spill register,
7276 that invalidates any previous reloaded copy of it.
7277 But forget_old_reloads_1 won't get to see it, because
7278 it thinks only about the original insn. So invalidate it here. */
7279 if (i < 0 && rld[r].out != 0
7280 && (REG_P (rld[r].out)
7281 || (MEM_P (rld[r].out)
7282 && REG_P (rld[r].out_reg))))
7284 rtx out = (REG_P (rld[r].out)
7285 ? rld[r].out : rld[r].out_reg);
7286 int nregno = REGNO (out);
7287 if (nregno >= FIRST_PSEUDO_REGISTER)
7289 rtx src_reg, store_insn = NULL_RTX;
7291 reg_last_reload_reg[nregno] = 0;
7293 /* If we can find a hard register that is stored, record
7294 the storing insn so that we may delete this insn with
7295 delete_output_reload. */
7296 src_reg = rld[r].reg_rtx;
7298 /* If this is an optional reload, try to find the source reg
7299 from an input reload. */
7302 rtx set = single_set (insn);
7303 if (set && SET_DEST (set) == rld[r].out)
7307 src_reg = SET_SRC (set);
7309 for (k = 0; k < n_reloads; k++)
7311 if (rld[k].in == src_reg)
7313 src_reg = rld[k].reg_rtx;
7320 store_insn = new_spill_reg_store[REGNO (src_reg)];
7321 if (src_reg && REG_P (src_reg)
7322 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7324 int src_regno = REGNO (src_reg);
7325 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7326 /* The place where to find a death note varies with
7327 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7328 necessarily checked exactly in the code that moves
7329 notes, so just check both locations. */
7330 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7331 if (! note && store_insn)
7332 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7335 spill_reg_store[src_regno + nr] = store_insn;
7336 spill_reg_stored_to[src_regno + nr] = out;
7337 reg_reloaded_contents[src_regno + nr] = nregno;
7338 reg_reloaded_insn[src_regno + nr] = store_insn;
7339 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7340 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7341 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7342 GET_MODE (src_reg)))
7343 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7345 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7347 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7349 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7351 reg_last_reload_reg[nregno] = src_reg;
7352 /* We have to set reg_has_output_reload here, or else
7353 forget_old_reloads_1 will clear reg_last_reload_reg
7355 reg_has_output_reload[nregno] = 1;
7360 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7362 while (num_regs-- > 0)
7363 reg_last_reload_reg[nregno + num_regs] = 0;
7367 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7370 /* Emit code to perform a reload from IN (which may be a reload register) to
7371 OUT (which may also be a reload register). IN or OUT is from operand
7372 OPNUM with reload type TYPE.
7374 Returns first insn emitted. */
7377 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7379 rtx last = get_last_insn ();
7382 /* If IN is a paradoxical SUBREG, remove it and try to put the
7383 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7384 if (GET_CODE (in) == SUBREG
7385 && (GET_MODE_SIZE (GET_MODE (in))
7386 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7387 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7388 in = SUBREG_REG (in), out = tem;
7389 else if (GET_CODE (out) == SUBREG
7390 && (GET_MODE_SIZE (GET_MODE (out))
7391 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7392 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7393 out = SUBREG_REG (out), in = tem;
7395 /* How to do this reload can get quite tricky. Normally, we are being
7396 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7397 register that didn't get a hard register. In that case we can just
7398 call emit_move_insn.
7400 We can also be asked to reload a PLUS that adds a register or a MEM to
7401 another register, constant or MEM. This can occur during frame pointer
7402 elimination and while reloading addresses. This case is handled by
7403 trying to emit a single insn to perform the add. If it is not valid,
7404 we use a two insn sequence.
7406 Finally, we could be called to handle an 'o' constraint by putting
7407 an address into a register. In that case, we first try to do this
7408 with a named pattern of "reload_load_address". If no such pattern
7409 exists, we just emit a SET insn and hope for the best (it will normally
7410 be valid on machines that use 'o').
7412 This entire process is made complex because reload will never
7413 process the insns we generate here and so we must ensure that
7414 they will fit their constraints and also by the fact that parts of
7415 IN might be being reloaded separately and replaced with spill registers.
7416 Because of this, we are, in some sense, just guessing the right approach
7417 here. The one listed above seems to work.
7419 ??? At some point, this whole thing needs to be rethought. */
7421 if (GET_CODE (in) == PLUS
7422 && (REG_P (XEXP (in, 0))
7423 || GET_CODE (XEXP (in, 0)) == SUBREG
7424 || MEM_P (XEXP (in, 0)))
7425 && (REG_P (XEXP (in, 1))
7426 || GET_CODE (XEXP (in, 1)) == SUBREG
7427 || CONSTANT_P (XEXP (in, 1))
7428 || MEM_P (XEXP (in, 1))))
7430 /* We need to compute the sum of a register or a MEM and another
7431 register, constant, or MEM, and put it into the reload
7432 register. The best possible way of doing this is if the machine
7433 has a three-operand ADD insn that accepts the required operands.
7435 The simplest approach is to try to generate such an insn and see if it
7436 is recognized and matches its constraints. If so, it can be used.
7438 It might be better not to actually emit the insn unless it is valid,
7439 but we need to pass the insn as an operand to `recog' and
7440 `extract_insn' and it is simpler to emit and then delete the insn if
7441 not valid than to dummy things up. */
7443 rtx op0, op1, tem, insn;
7446 op0 = find_replacement (&XEXP (in, 0));
7447 op1 = find_replacement (&XEXP (in, 1));
7449 /* Since constraint checking is strict, commutativity won't be
7450 checked, so we need to do that here to avoid spurious failure
7451 if the add instruction is two-address and the second operand
7452 of the add is the same as the reload reg, which is frequently
7453 the case. If the insn would be A = B + A, rearrange it so
7454 it will be A = A + B as constrain_operands expects. */
7456 if (REG_P (XEXP (in, 1))
7457 && REGNO (out) == REGNO (XEXP (in, 1)))
7458 tem = op0, op0 = op1, op1 = tem;
7460 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7461 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7463 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7464 code = recog_memoized (insn);
7468 extract_insn (insn);
7469 /* We want constrain operands to treat this insn strictly in
7470 its validity determination, i.e., the way it would after reload
7472 if (constrain_operands (1))
7476 delete_insns_since (last);
7478 /* If that failed, we must use a conservative two-insn sequence.
7480 Use a move to copy one operand into the reload register. Prefer
7481 to reload a constant, MEM or pseudo since the move patterns can
7482 handle an arbitrary operand. If OP1 is not a constant, MEM or
7483 pseudo and OP1 is not a valid operand for an add instruction, then
7486 After reloading one of the operands into the reload register, add
7487 the reload register to the output register.
7489 If there is another way to do this for a specific machine, a
7490 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7493 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7495 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7497 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7498 || (code != CODE_FOR_nothing
7499 && ! ((*insn_data[code].operand[2].predicate)
7500 (op1, insn_data[code].operand[2].mode))))
7501 tem = op0, op0 = op1, op1 = tem;
7503 gen_reload (out, op0, opnum, type);
7505 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7506 This fixes a problem on the 32K where the stack pointer cannot
7507 be used as an operand of an add insn. */
7509 if (rtx_equal_p (op0, op1))
7512 insn = emit_insn (gen_add2_insn (out, op1));
7514 /* If that failed, copy the address register to the reload register.
7515 Then add the constant to the reload register. */
7517 code = recog_memoized (insn);
7521 extract_insn (insn);
7522 /* We want constrain operands to treat this insn strictly in
7523 its validity determination, i.e., the way it would after reload
7525 if (constrain_operands (1))
7527 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7529 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7534 delete_insns_since (last);
7536 gen_reload (out, op1, opnum, type);
7537 insn = emit_insn (gen_add2_insn (out, op0));
7538 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7541 #ifdef SECONDARY_MEMORY_NEEDED
7542 /* If we need a memory location to do the move, do it that way. */
7543 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7544 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7545 && (REG_P (out) || GET_CODE (out) == SUBREG)
7546 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7547 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7548 REGNO_REG_CLASS (reg_or_subregno (out)),
7551 /* Get the memory to use and rewrite both registers to its mode. */
7552 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7554 if (GET_MODE (loc) != GET_MODE (out))
7555 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7557 if (GET_MODE (loc) != GET_MODE (in))
7558 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7560 gen_reload (loc, in, opnum, type);
7561 gen_reload (out, loc, opnum, type);
7565 /* If IN is a simple operand, use gen_move_insn. */
7566 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7567 emit_insn (gen_move_insn (out, in));
7569 #ifdef HAVE_reload_load_address
7570 else if (HAVE_reload_load_address)
7571 emit_insn (gen_reload_load_address (out, in));
7574 /* Otherwise, just write (set OUT IN) and hope for the best. */
7576 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7578 /* Return the first insn emitted.
7579 We can not just return get_last_insn, because there may have
7580 been multiple instructions emitted. Also note that gen_move_insn may
7581 emit more than one insn itself, so we can not assume that there is one
7582 insn emitted per emit_insn_before call. */
7584 return last ? NEXT_INSN (last) : get_insns ();
7587 /* Delete a previously made output-reload whose result we now believe
7588 is not needed. First we double-check.
7590 INSN is the insn now being processed.
7591 LAST_RELOAD_REG is the hard register number for which we want to delete
7592 the last output reload.
7593 J is the reload-number that originally used REG. The caller has made
7594 certain that reload J doesn't use REG any longer for input. */
7597 delete_output_reload (rtx insn, int j, int last_reload_reg)
7599 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7600 rtx reg = spill_reg_stored_to[last_reload_reg];
7603 int n_inherited = 0;
7607 /* It is possible that this reload has been only used to set another reload
7608 we eliminated earlier and thus deleted this instruction too. */
7609 if (INSN_DELETED_P (output_reload_insn))
7612 /* Get the raw pseudo-register referred to. */
7614 while (GET_CODE (reg) == SUBREG)
7615 reg = SUBREG_REG (reg);
7616 substed = reg_equiv_memory_loc[REGNO (reg)];
7618 /* This is unsafe if the operand occurs more often in the current
7619 insn than it is inherited. */
7620 for (k = n_reloads - 1; k >= 0; k--)
7622 rtx reg2 = rld[k].in;
7625 if (MEM_P (reg2) || reload_override_in[k])
7626 reg2 = rld[k].in_reg;
7628 if (rld[k].out && ! rld[k].out_reg)
7629 reg2 = XEXP (rld[k].in_reg, 0);
7631 while (GET_CODE (reg2) == SUBREG)
7632 reg2 = SUBREG_REG (reg2);
7633 if (rtx_equal_p (reg2, reg))
7635 if (reload_inherited[k] || reload_override_in[k] || k == j)
7638 reg2 = rld[k].out_reg;
7641 while (GET_CODE (reg2) == SUBREG)
7642 reg2 = XEXP (reg2, 0);
7643 if (rtx_equal_p (reg2, reg))
7650 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7652 n_occurrences += count_occurrences (PATTERN (insn),
7653 eliminate_regs (substed, 0,
7655 if (n_occurrences > n_inherited)
7658 /* If the pseudo-reg we are reloading is no longer referenced
7659 anywhere between the store into it and here,
7660 and we're within the same basic block, then the value can only
7661 pass through the reload reg and end up here.
7662 Otherwise, give up--return. */
7663 for (i1 = NEXT_INSN (output_reload_insn);
7664 i1 != insn; i1 = NEXT_INSN (i1))
7666 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7668 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7669 && reg_mentioned_p (reg, PATTERN (i1)))
7671 /* If this is USE in front of INSN, we only have to check that
7672 there are no more references than accounted for by inheritance. */
7673 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7675 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7676 i1 = NEXT_INSN (i1);
7678 if (n_occurrences <= n_inherited && i1 == insn)
7684 /* We will be deleting the insn. Remove the spill reg information. */
7685 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7687 spill_reg_store[last_reload_reg + k] = 0;
7688 spill_reg_stored_to[last_reload_reg + k] = 0;
7691 /* The caller has already checked that REG dies or is set in INSN.
7692 It has also checked that we are optimizing, and thus some
7693 inaccuracies in the debugging information are acceptable.
7694 So we could just delete output_reload_insn. But in some cases
7695 we can improve the debugging information without sacrificing
7696 optimization - maybe even improving the code: See if the pseudo
7697 reg has been completely replaced with reload regs. If so, delete
7698 the store insn and forget we had a stack slot for the pseudo. */
7699 if (rld[j].out != rld[j].in
7700 && REG_N_DEATHS (REGNO (reg)) == 1
7701 && REG_N_SETS (REGNO (reg)) == 1
7702 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7703 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7707 /* We know that it was used only between here and the beginning of
7708 the current basic block. (We also know that the last use before
7709 INSN was the output reload we are thinking of deleting, but never
7710 mind that.) Search that range; see if any ref remains. */
7711 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7713 rtx set = single_set (i2);
7715 /* Uses which just store in the pseudo don't count,
7716 since if they are the only uses, they are dead. */
7717 if (set != 0 && SET_DEST (set) == reg)
7722 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7723 && reg_mentioned_p (reg, PATTERN (i2)))
7725 /* Some other ref remains; just delete the output reload we
7727 delete_address_reloads (output_reload_insn, insn);
7728 delete_insn (output_reload_insn);
7733 /* Delete the now-dead stores into this pseudo. Note that this
7734 loop also takes care of deleting output_reload_insn. */
7735 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7737 rtx set = single_set (i2);
7739 if (set != 0 && SET_DEST (set) == reg)
7741 delete_address_reloads (i2, insn);
7749 /* For the debugging info, say the pseudo lives in this reload reg. */
7750 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7751 alter_reg (REGNO (reg), -1);
7755 delete_address_reloads (output_reload_insn, insn);
7756 delete_insn (output_reload_insn);
7760 /* We are going to delete DEAD_INSN. Recursively delete loads of
7761 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7762 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7764 delete_address_reloads (rtx dead_insn, rtx current_insn)
7766 rtx set = single_set (dead_insn);
7767 rtx set2, dst, prev, next;
7770 rtx dst = SET_DEST (set);
7772 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7774 /* If we deleted the store from a reloaded post_{in,de}c expression,
7775 we can delete the matching adds. */
7776 prev = PREV_INSN (dead_insn);
7777 next = NEXT_INSN (dead_insn);
7778 if (! prev || ! next)
7780 set = single_set (next);
7781 set2 = single_set (prev);
7783 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7784 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7785 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7787 dst = SET_DEST (set);
7788 if (! rtx_equal_p (dst, SET_DEST (set2))
7789 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7790 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7791 || (INTVAL (XEXP (SET_SRC (set), 1))
7792 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7794 delete_related_insns (prev);
7795 delete_related_insns (next);
7798 /* Subfunction of delete_address_reloads: process registers found in X. */
7800 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7802 rtx prev, set, dst, i2;
7804 enum rtx_code code = GET_CODE (x);
7808 const char *fmt = GET_RTX_FORMAT (code);
7809 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7812 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7813 else if (fmt[i] == 'E')
7815 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7816 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7823 if (spill_reg_order[REGNO (x)] < 0)
7826 /* Scan backwards for the insn that sets x. This might be a way back due
7828 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7830 code = GET_CODE (prev);
7831 if (code == CODE_LABEL || code == JUMP_INSN)
7835 if (reg_set_p (x, PATTERN (prev)))
7837 if (reg_referenced_p (x, PATTERN (prev)))
7840 if (! prev || INSN_UID (prev) < reload_first_uid)
7842 /* Check that PREV only sets the reload register. */
7843 set = single_set (prev);
7846 dst = SET_DEST (set);
7848 || ! rtx_equal_p (dst, x))
7850 if (! reg_set_p (dst, PATTERN (dead_insn)))
7852 /* Check if DST was used in a later insn -
7853 it might have been inherited. */
7854 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7860 if (reg_referenced_p (dst, PATTERN (i2)))
7862 /* If there is a reference to the register in the current insn,
7863 it might be loaded in a non-inherited reload. If no other
7864 reload uses it, that means the register is set before
7866 if (i2 == current_insn)
7868 for (j = n_reloads - 1; j >= 0; j--)
7869 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7870 || reload_override_in[j] == dst)
7872 for (j = n_reloads - 1; j >= 0; j--)
7873 if (rld[j].in && rld[j].reg_rtx == dst)
7882 /* If DST is still live at CURRENT_INSN, check if it is used for
7883 any reload. Note that even if CURRENT_INSN sets DST, we still
7884 have to check the reloads. */
7885 if (i2 == current_insn)
7887 for (j = n_reloads - 1; j >= 0; j--)
7888 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7889 || reload_override_in[j] == dst)
7891 /* ??? We can't finish the loop here, because dst might be
7892 allocated to a pseudo in this block if no reload in this
7893 block needs any of the classes containing DST - see
7894 spill_hard_reg. There is no easy way to tell this, so we
7895 have to scan till the end of the basic block. */
7897 if (reg_set_p (dst, PATTERN (i2)))
7901 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7902 reg_reloaded_contents[REGNO (dst)] = -1;
7906 /* Output reload-insns to reload VALUE into RELOADREG.
7907 VALUE is an autoincrement or autodecrement RTX whose operand
7908 is a register or memory location;
7909 so reloading involves incrementing that location.
7910 IN is either identical to VALUE, or some cheaper place to reload from.
7912 INC_AMOUNT is the number to increment or decrement by (always positive).
7913 This cannot be deduced from VALUE.
7915 Return the instruction that stores into RELOADREG. */
7918 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7920 /* REG or MEM to be copied and incremented. */
7921 rtx incloc = XEXP (value, 0);
7922 /* Nonzero if increment after copying. */
7923 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7929 rtx real_in = in == value ? XEXP (in, 0) : in;
7931 /* No hard register is equivalent to this register after
7932 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7933 we could inc/dec that register as well (maybe even using it for
7934 the source), but I'm not sure it's worth worrying about. */
7936 reg_last_reload_reg[REGNO (incloc)] = 0;
7938 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7939 inc_amount = -inc_amount;
7941 inc = GEN_INT (inc_amount);
7943 /* If this is post-increment, first copy the location to the reload reg. */
7944 if (post && real_in != reloadreg)
7945 emit_insn (gen_move_insn (reloadreg, real_in));
7949 /* See if we can directly increment INCLOC. Use a method similar to
7950 that in gen_reload. */
7952 last = get_last_insn ();
7953 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7954 gen_rtx_PLUS (GET_MODE (incloc),
7957 code = recog_memoized (add_insn);
7960 extract_insn (add_insn);
7961 if (constrain_operands (1))
7963 /* If this is a pre-increment and we have incremented the value
7964 where it lives, copy the incremented value to RELOADREG to
7965 be used as an address. */
7968 emit_insn (gen_move_insn (reloadreg, incloc));
7973 delete_insns_since (last);
7976 /* If couldn't do the increment directly, must increment in RELOADREG.
7977 The way we do this depends on whether this is pre- or post-increment.
7978 For pre-increment, copy INCLOC to the reload register, increment it
7979 there, then save back. */
7983 if (in != reloadreg)
7984 emit_insn (gen_move_insn (reloadreg, real_in));
7985 emit_insn (gen_add2_insn (reloadreg, inc));
7986 store = emit_insn (gen_move_insn (incloc, reloadreg));
7991 Because this might be a jump insn or a compare, and because RELOADREG
7992 may not be available after the insn in an input reload, we must do
7993 the incrementation before the insn being reloaded for.
7995 We have already copied IN to RELOADREG. Increment the copy in
7996 RELOADREG, save that back, then decrement RELOADREG so it has
7997 the original value. */
7999 emit_insn (gen_add2_insn (reloadreg, inc));
8000 store = emit_insn (gen_move_insn (incloc, reloadreg));
8001 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8009 add_auto_inc_notes (rtx insn, rtx x)
8011 enum rtx_code code = GET_CODE (x);
8015 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8018 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8022 /* Scan all the operand sub-expressions. */
8023 fmt = GET_RTX_FORMAT (code);
8024 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8027 add_auto_inc_notes (insn, XEXP (x, i));
8028 else if (fmt[i] == 'E')
8029 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8030 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8035 /* Copy EH notes from an insn to its reloads. */
8037 copy_eh_notes (rtx insn, rtx x)
8039 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8042 for (; x != 0; x = NEXT_INSN (x))
8044 if (may_trap_p (PATTERN (x)))
8046 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8052 /* This is used by reload pass, that does emit some instructions after
8053 abnormal calls moving basic block end, but in fact it wants to emit
8054 them on the edge. Looks for abnormal call edges, find backward the
8055 proper call and fix the damage.
8057 Similar handle instructions throwing exceptions internally. */
8059 fixup_abnormal_edges (void)
8061 bool inserted = false;
8069 /* Look for cases we are interested in - calls or instructions causing
8071 FOR_EACH_EDGE (e, ei, bb->succs)
8073 if (e->flags & EDGE_ABNORMAL_CALL)
8075 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8076 == (EDGE_ABNORMAL | EDGE_EH))
8079 if (e && !CALL_P (BB_END (bb))
8080 && !can_throw_internal (BB_END (bb)))
8082 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8084 FOR_EACH_EDGE (e, ei, bb->succs)
8085 if (e->flags & EDGE_FALLTHRU)
8087 /* Get past the new insns generated. Allow notes, as the insns may
8088 be already deleted. */
8089 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8090 && !can_throw_internal (insn)
8091 && insn != BB_HEAD (bb))
8092 insn = PREV_INSN (insn);
8093 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8096 insn = NEXT_INSN (insn);
8097 while (insn && insn != stop)
8099 next = NEXT_INSN (insn);
8104 /* Sometimes there's still the return value USE.
8105 If it's placed after a trapping call (i.e. that
8106 call is the last insn anyway), we have no fallthru
8107 edge. Simply delete this use and don't try to insert
8108 on the non-existent edge. */
8109 if (GET_CODE (PATTERN (insn)) != USE)
8111 /* We're not deleting it, we're moving it. */
8112 INSN_DELETED_P (insn) = 0;
8113 PREV_INSN (insn) = NULL_RTX;
8114 NEXT_INSN (insn) = NULL_RTX;
8116 insert_insn_on_edge (insn, e);
8123 /* We've possibly turned single trapping insn into multiple ones. */
8124 if (flag_non_call_exceptions)
8127 blocks = sbitmap_alloc (last_basic_block);
8128 sbitmap_ones (blocks);
8129 find_many_sub_basic_blocks (blocks);
8132 commit_edge_insertions ();
OSDN Git Service
